Searched refs:reg (Results 1 - 25 of 107) sorted by relevance

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/trex/src/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_dcb_82598.c120 u32 reg = 0; local
125 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
126 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
128 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
130 reg &= ~IXGBE_RMCS_ARBDIS;
132 reg |= IXGBE_RMCS_RRM;
134 reg |= IXGBE_RMCS_DFP;
136 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
143 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
146 reg |
176 u32 reg, max_credits; local
220 u32 reg; local
263 u32 fcrtl, reg; local
315 u32 reg = 0; local
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H A Dixgbe_dcb_82599.c120 u32 reg = 0; local
129 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
130 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
138 reg = 0;
140 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
142 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
148 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
150 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
153 reg |= IXGBE_RTRPT4C_LSP;
155 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
178 u32 reg, max_credits; local
224 u32 reg; local
284 u32 i, j, fcrtl, reg; local
371 u32 reg = 0; local
497 u32 reg; local
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H A Dixgbe_osdep.h127 #define IXGBE_PCI_REG(reg) rte_read32(reg)
134 #define IXGBE_PCI_REG_WRITE(reg, value) \
135 rte_write32((rte_cpu_to_le_32(value)), reg)
137 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
138 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
140 #define IXGBE_PCI_REG_ADDR(hw, reg) \
141 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
143 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
144 IXGBE_PCI_REG_ADDR((hw), (reg)
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H A Dixgbe_82598.h44 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
45 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
H A Dixgbe_82599.h55 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
56 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
H A Dixgbe_x550.c103 * @reg: register number to write
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) argument
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
116 * @reg: register number to write
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) argument
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
129 * @reg: register number to read
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) argument
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
148 * @reg
153 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) argument
176 u8 reg; local
631 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) argument
647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) argument
662 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) argument
678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) argument
961 u32 reg, high_pri_tc; local
1009 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; local
1064 u32 reg; local
1435 u32 reg; local
1458 u32 reg; local
1482 u32 idx, reg, num_qs, start_q, bitmask; local
1523 u32 i, j, reg, q, shift, vf, idx; local
2029 u16 reg; local
2116 u16 reg; local
2620 u16 reg; local
3289 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + local
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H A Dixgbe_hv_vf.c183 u32 reg; local
188 reg = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(0));
190 reg |= ((max_size + 4) | IXGBE_RXDCTL_RLPML_EN);
191 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(0), reg);
/trex/src/dpdk/drivers/net/e1000/base/
H A De1000_osdep.h98 #define E1000_PCI_REG(reg) rte_read32(reg)
100 #define E1000_PCI_REG16(reg) rte_read16(reg)
102 #define E1000_PCI_REG_WRITE(reg, value) \
103 rte_write32((rte_cpu_to_le_32(value)), reg)
105 #define E1000_PCI_REG_WRITE_RELAXED(reg, value) \
106 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
108 #define E1000_PCI_REG_WRITE16(reg, value) \
109 rte_write16((rte_cpu_to_le_16(value)), reg)
[all...]
H A De1000_osdep.c44 e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) argument
50 e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) argument
71 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) argument
80 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) argument
H A De1000_82542.c440 * @reg: e1000 register to be read
447 u32 e1000_translate_register_82542(u32 reg) argument
455 switch (reg) {
457 reg = 0x00040;
460 reg = 0x00108;
463 reg = 0x00110;
466 reg = 0x00114;
469 reg = 0x00118;
472 reg = 0x00120;
475 reg
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H A De1000_82571.c1271 u32 reg; local
1276 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1277 reg |= (1 << 22);
1278 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1281 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1282 reg |= (1 << 22);
1283 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1286 reg = E1000_READ_REG(hw, E1000_TARC(0));
1287 reg &= ~(0xF << 27); /* 30:27 */
1291 reg |
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H A De1000_80003es2lan.c995 u32 reg; local
1000 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1001 reg |= (1 << 22);
1002 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1005 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1006 reg |= (1 << 22);
1007 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1010 reg = E1000_READ_REG(hw, E1000_TARC(0));
1011 reg &= ~(0xF << 27); /* 30:27 */
1013 reg
1044 u32 reg; local
[all...]
/trex/src/dpdk/lib/librte_eal/linuxapp/kni/ethtool/igb/
H A De1000_osdep.h92 #define E1000_REGISTER(a, reg) reg
94 #define E1000_WRITE_REG(a, reg, value) ( \
95 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))
97 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
99 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
100 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
102 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
103 readl((a)->hw_addr + E1000_REGISTER(a, reg)
[all...]
/trex/src/dpdk/drivers/net/vmxnet3/
H A Dvmxnet3_ethdev.h120 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
121 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
125 #define VMXNET3_PCI_REG(reg) rte_read32(reg)
133 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
135 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
136 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
[all...]
/trex/src/dpdk/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/
H A Dixgbe_osdep.h81 #define IXGBE_WRITE_REG(a, reg, value) do {\
82 switch (reg) { \
90 reg, (u32)(value)); \
94 writel((value), ((a)->hw_addr + (reg))); \
97 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
100 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
102 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
103 writel((value), ((a)->hw_addr + (reg)
[all...]
H A Dixgbe_82598.h36 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
37 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
H A Dixgbe_82599.h50 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
51 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
/trex/src/dpdk/lib/librte_eal/linuxapp/eal/
H A Deal_pci_vfio.c94 uint32_t reg; local
99 ret = pread64(fd, &reg, sizeof(reg),
102 if (ret != sizeof(reg)) {
109 cap_offset = reg & 0xFF;
114 ret = pread64(fd, &reg, sizeof(reg),
117 if (ret != sizeof(reg)) {
124 cap_id = reg & 0xFF;
128 ret = pread64(fd, &reg, sizeo
177 uint16_t reg; local
375 struct vfio_region_info reg = { .argsz = sizeof(reg) }; local
[all...]
H A Deal_pci_uio.c77 uint16_t reg; local
80 ret = pread(dev_fd, &reg, sizeof(reg), PCI_COMMAND);
81 if (ret != sizeof(reg)) {
88 if (reg & PCI_COMMAND_MASTER)
91 reg |= PCI_COMMAND_MASTER;
93 ret = pwrite(dev_fd, &reg, sizeof(reg), PCI_COMMAND);
94 if (ret != sizeof(reg)) {
494 uintptr_t reg local
528 uintptr_t reg = p->base + offset; local
[all...]
/trex/src/dpdk/drivers/net/fm10k/base/
H A Dfm10k_osdep.h93 #define FM10K_WRITE_REG(hw, reg, val) \
94 rte_write32((val), ((hw)->hw_addr + (reg)))
96 #define FM10K_READ_REG(hw, reg) rte_read32(((hw)->hw_addr + (reg)))
100 #define FM10K_PCI_REG(reg) rte_read32(reg)
102 #define FM10K_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
105 #define FM10K_READ_PCI_WORD(hw, reg) 0
107 #define FM10K_WRITE_MBX(hw, reg, valu
[all...]
H A Dfm10k_common.c225 u32 reg; local
235 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));
237 reg & ~FM10K_TXDCTL_ENABLE);
238 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));
240 reg & ~FM10K_RXQCTL_ENABLE);
253 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));
254 if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) {
255 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));
256 if (!~reg || !(re
[all...]
/trex/src/dpdk/drivers/net/i40e/base/
H A Di40e_osdep.h157 #define I40E_PCI_REG(reg) rte_read32(reg)
158 #define I40E_PCI_REG_ADDR(a, reg) \
159 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
165 #define I40E_PCI_REG_WRITE(reg, value) \
166 rte_write32((rte_cpu_to_le_32(value)), reg)
167 #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \
168 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
173 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
[all...]
H A Di40e_diag.c58 * @reg: reg to be tested
62 u32 reg, u32 mask)
68 orig_val = rd32(hw, reg);
71 wr32(hw, reg, (pat & mask));
72 val = rd32(hw, reg);
78 wr32(hw, reg, orig_val);
79 val = rd32(hw, reg);
112 u32 reg, mask; local
118 /* set actual reg rang
61 i40e_diag_reg_pattern_test(struct i40e_hw *hw, u32 reg, u32 mask) argument
[all...]
/trex/src/dpdk/drivers/net/e1000/
H A Digb_regs.h187 igb_read_regs(struct e1000_hw *hw, const struct reg_info *reg, argument
192 for (i = 0; i < reg->count; i++) {
194 reg->base_addr + i * reg->stride);
196 return reg->count;
/trex/src/dpdk/drivers/net/cxgbe/base/
H A Dadapter.h328 #define CXGBE_PCI_REG(reg) rte_read32(reg)
345 #define CXGBE_PCI_REG_ADDR(adap, reg) \
346 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
348 #define CXGBE_READ_REG(adap, reg) \
349 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
351 #define CXGBE_READ_REG64(adap, reg) \
352 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
354 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
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