Searched refs:reg_offset (Results 1 - 10 of 10) sorted by relevance

/trex/src/dpdk/drivers/net/ixgbe/
H A Dixgbe_pf.c397 uint32_t reg_offset, vf_shift; local
402 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
405 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
407 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
409 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
411 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
414 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
416 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
/trex/src/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_mbx.c607 u32 reg_offset = (vf_number < 32) ? 0 : 1; local
616 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
622 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
630 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
/trex/src/dpdk/lib/librte_eal/linuxapp/kni/ethtool/igb/
H A Digb_regtest.h31 u16 reg_offset; member in struct:igb_reg_test
H A De1000_82575.c2241 u32 reg_val, reg_offset; local
2245 reg_offset = E1000_DTXSWC;
2249 reg_offset = E1000_TXSWC;
2255 reg_val = E1000_READ_REG(hw, reg_offset);
2267 E1000_WRITE_REG(hw, reg_offset, reg_val);
H A Digb_ethtool.c1077 (i * test->reg_offset),
1083 (i * test->reg_offset),
1090 + (i * test->reg_offset));
H A Digb_main.c6478 u32 dtxswc, reg_offset; local
6486 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
6487 dtxswc = E1000_READ_REG(hw, reg_offset);
6494 E1000_WRITE_REG(hw, reg_offset, dtxswc);
/trex/src/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c3895 int reg_offset; local
3968 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3971 val = REG_RD(sc, reg_offset);
3973 REG_WR(sc, reg_offset, val);
3985 int reg_offset; local
3998 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4001 val = REG_RD(sc, reg_offset);
4003 REG_WR(sc, reg_offset, val);
4015 int reg_offset; local
4018 reg_offset
5036 int reg_offset, reg_offset_en5; local
[all...]
H A Decore_sp.c718 uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM : local
732 reg_offset += 8 * index;
738 ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2);
/trex/src/dpdk/drivers/net/e1000/base/
H A De1000_82575.c2275 u32 reg_val, reg_offset; local
2279 reg_offset = E1000_DTXSWC;
2283 reg_offset = E1000_TXSWC;
2289 reg_val = E1000_READ_REG(hw, reg_offset);
2301 E1000_WRITE_REG(hw, reg_offset, reg_val);
/trex/src/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c10199 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset; local
10216 reg_offset = arr_idx * reg_info->stride1 +
10218 reg_offset += reg_info->base_addr;
10219 ptr_data[reg_offset >> 2] =
10220 i40e_read_rx_ctl(hw, reg_offset);
10232 reg_offset = arr_idx * reg_info->stride1 +
10234 reg_offset += reg_info->base_addr;
10235 ptr_data[reg_offset >> 2] =
10236 I40E_READ_REG(hw, reg_offset);

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