15129044dSC.J. Collier/*-
25129044dSC.J. Collier *   BSD LICENSE
35129044dSC.J. Collier *
45129044dSC.J. Collier *   Copyright(c) 2015 Cavium Networks. All rights reserved.
55129044dSC.J. Collier *   All rights reserved.
65129044dSC.J. Collier *
75129044dSC.J. Collier *   Redistribution and use in source and binary forms, with or without
85129044dSC.J. Collier *   modification, are permitted provided that the following conditions
95129044dSC.J. Collier *   are met:
105129044dSC.J. Collier *
115129044dSC.J. Collier *     * Redistributions of source code must retain the above copyright
125129044dSC.J. Collier *       notice, this list of conditions and the following disclaimer.
135129044dSC.J. Collier *     * Redistributions in binary form must reproduce the above copyright
145129044dSC.J. Collier *       notice, this list of conditions and the following disclaimer in
155129044dSC.J. Collier *       the documentation and/or other materials provided with the
165129044dSC.J. Collier *       distribution.
175129044dSC.J. Collier *     * Neither the name of Cavium Networks nor the names of its
185129044dSC.J. Collier *       contributors may be used to endorse or promote products derived
195129044dSC.J. Collier *       from this software without specific prior written permission.
205129044dSC.J. Collier *
215129044dSC.J. Collier *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
225129044dSC.J. Collier *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
235129044dSC.J. Collier *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
245129044dSC.J. Collier *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
255129044dSC.J. Collier *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
265129044dSC.J. Collier *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
275129044dSC.J. Collier *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
285129044dSC.J. Collier *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
295129044dSC.J. Collier *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
305129044dSC.J. Collier *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
315129044dSC.J. Collier *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
325129044dSC.J. Collier */
335129044dSC.J. Collier
345129044dSC.J. Collier#ifndef _TEST_XMMT_OPS_H_
355129044dSC.J. Collier#define _TEST_XMMT_OPS_H_
365129044dSC.J. Collier
375129044dSC.J. Collier#include <rte_vect.h>
385129044dSC.J. Collier
395129044dSC.J. Collier#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
405129044dSC.J. Collier
415129044dSC.J. Collier/* vect_* abstraction implementation using NEON */
425129044dSC.J. Collier
435129044dSC.J. Collier/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
445129044dSC.J. Collier#define vect_loadu_sil128(p) vld1q_s32((const int32_t *)p)
455129044dSC.J. Collier
465129044dSC.J. Collier/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
475129044dSC.J. Collierstatic inline xmm_t  __attribute__((always_inline))
485129044dSC.J. Colliervect_set_epi32(int i3, int i2, int i1, int i0)
495129044dSC.J. Collier{
505129044dSC.J. Collier	int32_t data[4] = {i0, i1, i2, i3};
515129044dSC.J. Collier
525129044dSC.J. Collier	return vld1q_s32(data);
535129044dSC.J. Collier}
545129044dSC.J. Collier
555129044dSC.J. Collier#elif defined(RTE_ARCH_X86)
565129044dSC.J. Collier
575129044dSC.J. Collier/* vect_* abstraction implementation using SSE */
585129044dSC.J. Collier
595129044dSC.J. Collier/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
605129044dSC.J. Collier#define vect_loadu_sil128(p) _mm_loadu_si128(p)
615129044dSC.J. Collier
625129044dSC.J. Collier/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
635129044dSC.J. Collier#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
645129044dSC.J. Collier
653d9b7210SChristian Ehrhardt#elif defined(RTE_ARCH_PPC_64)
663d9b7210SChristian Ehrhardt
673d9b7210SChristian Ehrhardt/* vect_* abstraction implementation using ALTIVEC */
683d9b7210SChristian Ehrhardt
693d9b7210SChristian Ehrhardt/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
703d9b7210SChristian Ehrhardt#define vect_loadu_sil128(p) vec_ld(0, p)
713d9b7210SChristian Ehrhardt
723d9b7210SChristian Ehrhardt/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
733d9b7210SChristian Ehrhardtstatic inline xmm_t  __attribute__((always_inline))
743d9b7210SChristian Ehrhardtvect_set_epi32(int i3, int i2, int i1, int i0)
753d9b7210SChristian Ehrhardt{
763d9b7210SChristian Ehrhardt	xmm_t data = (xmm_t){i0, i1, i2, i3};
773d9b7210SChristian Ehrhardt
783d9b7210SChristian Ehrhardt	return data;
793d9b7210SChristian Ehrhardt}
803d9b7210SChristian Ehrhardt
815129044dSC.J. Collier#endif
825129044dSC.J. Collier
835129044dSC.J. Collier#endif /* _TEST_XMMT_OPS_H_ */
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