elink.h revision 3d9b7210
1/*
2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
3 *
4 * Eric Davis        <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano     <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
11 * www.qlogic.com
12 *
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
14 */
15
16#ifndef ELINK_H
17#define ELINK_H
18
19#define ELINK_DEBUG
20
21
22
23
24
25
26/***********************************************************/
27/*                  CLC Call backs functions               */
28/***********************************************************/
29/* CLC device structure */
30struct bnx2x_softc;
31
32extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
33extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
34
35/* mode - 0( LOW ) /1(HIGH)*/
36extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
37			    uint16_t gpio_num,
38			    uint8_t mode, uint8_t port);
39extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc,
40			    uint8_t pins,
41			    uint8_t mode);
42
43extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port);
44extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
45				uint16_t gpio_num,
46				uint8_t mode, uint8_t port);
47
48extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
49
50/* This function is called every 1024 bytes downloading of phy firmware.
51Driver can use it to print to screen indication for download progress */
52extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);
53
54/* Each log type has its own parameters */
55typedef enum elink_log_id {
56	ELINK_LOG_ID_UNQUAL_IO_MODULE	= 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
57	ELINK_LOG_ID_OVER_CURRENT	= 1, /* uint8_t port */
58	ELINK_LOG_ID_PHY_UNINITIALIZED	= 2, /* uint8_t port */
59	ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
60	ELINK_LOG_ID_NON_10G_MODULE	= 4, /* uint8_t port */
61}elink_log_id_t;
62
63typedef enum elink_status {
64	ELINK_STATUS_OK = 0,
65	ELINK_STATUS_ERROR,
66	ELINK_STATUS_TIMEOUT,
67	ELINK_STATUS_NO_LINK,
68	ELINK_STATUS_INVALID_IMAGE,
69	ELINK_OP_NOT_SUPPORTED = 122
70} elink_status_t;
71extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);
72extern void elink_cb_load_warpcore_microcode(void);
73
74extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);
75
76#define ELINK_EVENT_LOG_LEVEL_ERROR 	1
77#define ELINK_EVENT_LOG_LEVEL_WARNING 	2
78#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 	1
79#define ELINK_EVENT_ID_SFP_POWER_FAULT 		2
80
81#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
82/* Debug prints */
83
84/***********************************************************/
85/*                         Defines                         */
86/***********************************************************/
87#define ELINK_DEFAULT_PHY_DEV_ADDR	3
88#define ELINK_E2_DEFAULT_PHY_DEV_ADDR	5
89
90
91#define DUPLEX_FULL			1
92#define DUPLEX_HALF			2
93
94#define ELINK_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
95#define ELINK_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
96#define ELINK_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
97#define ELINK_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
98#define ELINK_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE
99
100#define ELINK_NET_SERDES_IF_XFI		1
101#define ELINK_NET_SERDES_IF_SFI		2
102#define ELINK_NET_SERDES_IF_KR		3
103#define ELINK_NET_SERDES_IF_DXGXS	4
104
105#define ELINK_SPEED_AUTO_NEG		0
106#define ELINK_SPEED_10			10
107#define ELINK_SPEED_100			100
108#define ELINK_SPEED_1000		1000
109#define ELINK_SPEED_2500		2500
110#define ELINK_SPEED_10000		10000
111#define ELINK_SPEED_20000		20000
112
113#define ELINK_I2C_DEV_ADDR_A0			0xa0
114#define ELINK_I2C_DEV_ADDR_A2			0xa2
115
116#define ELINK_SFP_EEPROM_PAGE_SIZE			16
117#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR		0x14
118#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE		16
119#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR		0x25
120#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE		3
121#define ELINK_SFP_EEPROM_PART_NO_ADDR			0x28
122#define ELINK_SFP_EEPROM_PART_NO_SIZE			16
123#define ELINK_SFP_EEPROM_REVISION_ADDR		0x38
124#define ELINK_SFP_EEPROM_REVISION_SIZE		4
125#define ELINK_SFP_EEPROM_SERIAL_ADDR			0x44
126#define ELINK_SFP_EEPROM_SERIAL_SIZE			16
127#define ELINK_SFP_EEPROM_DATE_ADDR			0x54 /* ASCII YYMMDD */
128#define ELINK_SFP_EEPROM_DATE_SIZE			6
129#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR			0x5c
130#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE			1
131#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ		(1<<2)
132#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR		0x5e
133#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE		1
134
135#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE		0x5e
136#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR			0x5f
137
138#define ELINK_PWR_FLT_ERR_MSG_LEN			250
139
140#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
141		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
142#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
143		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
144		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
145#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
146		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
147
148/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
149#define ELINK_SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
150/* Single Media board contains single external phy */
151#define ELINK_SINGLE_MEDIA(params)		(params->num_phys == 2)
152/* Dual Media board contains two external phy with different media */
153#define ELINK_DUAL_MEDIA(params)		(params->num_phys == 3)
154
155#define ELINK_FW_PARAM_PHY_ADDR_MASK		0x000000FF
156#define ELINK_FW_PARAM_PHY_TYPE_MASK		0x0000FF00
157#define ELINK_FW_PARAM_MDIO_CTRL_MASK		0xFFFF0000
158#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET		16
159#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
160					   ELINK_FW_PARAM_PHY_ADDR_MASK)
161#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
162					   ELINK_FW_PARAM_PHY_TYPE_MASK)
163#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
164					    ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
165					    ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
166#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
167	(phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
168
169
170#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
171#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD				250
172
173#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
174
175#define ELINK_BMAC_CONTROL_RX_ENABLE		2
176/***********************************************************/
177/*                         Structs                         */
178/***********************************************************/
179#define ELINK_INT_PHY		0
180#define ELINK_EXT_PHY1	1
181#define ELINK_EXT_PHY2	2
182#define ELINK_MAX_PHYS	3
183
184/* Same configuration is shared between the XGXS and the first external phy */
185#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
186#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
187					 0 : (_phy_idx - 1))
188/***********************************************************/
189/*                      elink_phy struct                   */
190/*  Defines the required arguments and function per phy    */
191/***********************************************************/
192struct elink_vars;
193struct elink_params;
194struct elink_phy;
195
196typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
197			    struct elink_vars *vars);
198typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
199			    struct elink_vars *vars);
200typedef void (*link_reset_t)(struct elink_phy *phy,
201			     struct elink_params *params);
202typedef void (*config_loopback_t)(struct elink_phy *phy,
203				  struct elink_params *params);
204typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
205typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
206typedef void (*set_link_led_t)(struct elink_phy *phy,
207			       struct elink_params *params, uint8_t mode);
208typedef void (*phy_specific_func_t)(struct elink_phy *phy,
209				    struct elink_params *params, uint32_t action);
210struct elink_reg_set {
211	uint8_t  devad;
212	uint16_t reg;
213	uint16_t val;
214};
215
216struct elink_phy {
217	uint32_t type;
218
219	/* Loaded during init */
220	uint8_t addr;
221	uint8_t def_md_devad;
222	uint16_t flags;
223	/* No Over-Current detection */
224#define ELINK_FLAGS_NOC			(1<<1)
225	/* Fan failure detection required */
226#define ELINK_FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
227	/* Initialize first the XGXS and only then the phy itself */
228#define ELINK_FLAGS_INIT_XGXS_FIRST		(1<<3)
229#define ELINK_FLAGS_WC_DUAL_MODE		(1<<4)
230#define ELINK_FLAGS_4_PORT_MODE		(1<<5)
231#define ELINK_FLAGS_REARM_LATCH_SIGNAL		(1<<6)
232#define ELINK_FLAGS_SFP_NOT_APPROVED		(1<<7)
233#define ELINK_FLAGS_MDC_MDIO_WA		(1<<8)
234#define ELINK_FLAGS_DUMMY_READ			(1<<9)
235#define ELINK_FLAGS_MDC_MDIO_WA_B0		(1<<10)
236#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC	(1<<11)
237#define ELINK_FLAGS_TX_ERROR_CHECK		(1<<12)
238#define ELINK_FLAGS_EEE			(1<<13)
239#define ELINK_FLAGS_TEMPERATURE		(1<<14)
240#define ELINK_FLAGS_MDC_MDIO_WA_G		(1<<15)
241
242	/* preemphasis values for the rx side */
243	uint16_t rx_preemphasis[4];
244
245	/* preemphasis values for the tx side */
246	uint16_t tx_preemphasis[4];
247
248	/* EMAC address for access MDIO */
249	uint32_t mdio_ctrl;
250
251	uint32_t supported;
252#define ELINK_SUPPORTED_10baseT_Half		(1<<0)
253#define ELINK_SUPPORTED_10baseT_Full		(1<<1)
254#define ELINK_SUPPORTED_100baseT_Half		(1<<2)
255#define ELINK_SUPPORTED_100baseT_Full 		(1<<3)
256#define ELINK_SUPPORTED_1000baseT_Full 	(1<<4)
257#define ELINK_SUPPORTED_2500baseX_Full 	(1<<5)
258#define ELINK_SUPPORTED_10000baseT_Full 	(1<<6)
259#define ELINK_SUPPORTED_TP 			(1<<7)
260#define ELINK_SUPPORTED_FIBRE 			(1<<8)
261#define ELINK_SUPPORTED_Autoneg 		(1<<9)
262#define ELINK_SUPPORTED_Pause 			(1<<10)
263#define ELINK_SUPPORTED_Asym_Pause		(1<<11)
264#define ELINK_SUPPORTED_20000baseMLD2_Full	(1<<21)
265#define ELINK_SUPPORTED_20000baseKR2_Full	(1<<22)
266
267	uint32_t media_type;
268#define	ELINK_ETH_PHY_UNSPECIFIED	0x0
269#define	ELINK_ETH_PHY_SFPP_10G_FIBER	0x1
270#define	ELINK_ETH_PHY_XFP_FIBER		0x2
271#define	ELINK_ETH_PHY_DA_TWINAX		0x3
272#define	ELINK_ETH_PHY_BASE_T		0x4
273#define ELINK_ETH_PHY_SFP_1G_FIBER	0x5
274#define	ELINK_ETH_PHY_KR		0xf0
275#define	ELINK_ETH_PHY_CX4		0xf1
276#define	ELINK_ETH_PHY_NOT_PRESENT	0xff
277
278	/* The address in which version is located*/
279	uint32_t ver_addr;
280
281	uint16_t req_flow_ctrl;
282
283	uint16_t req_line_speed;
284
285	uint32_t speed_cap_mask;
286
287	uint16_t req_duplex;
288	uint16_t rsrv;
289	/* Called per phy/port init, and it configures LASI, speed, autoneg,
290	 duplex, flow control negotiation, etc. */
291	config_init_t config_init;
292
293	/* Called due to interrupt. It determines the link, speed */
294	read_status_t read_status;
295
296	/* Called when driver is unloading. Should reset the phy */
297	link_reset_t link_reset;
298
299	/* Set the loopback configuration for the phy */
300	config_loopback_t config_loopback;
301
302	/* Format the given raw number into str up to len */
303	format_fw_ver_t format_fw_ver;
304
305	/* Reset the phy (both ports) */
306	hw_reset_t hw_reset;
307
308	/* Set link led mode (on/off/oper)*/
309	set_link_led_t set_link_led;
310
311	/* PHY Specific tasks */
312	phy_specific_func_t phy_specific_func;
313#define ELINK_DISABLE_TX	1
314#define ELINK_ENABLE_TX	2
315#define ELINK_PHY_INIT	3
316};
317
318/* Inputs parameters to the CLC */
319struct elink_params {
320
321	uint8_t port;
322
323	/* Default / User Configuration */
324	uint8_t loopback_mode;
325#define ELINK_LOOPBACK_NONE		0
326#define ELINK_LOOPBACK_EMAC		1
327#define ELINK_LOOPBACK_BMAC		2
328#define ELINK_LOOPBACK_XGXS		3
329#define ELINK_LOOPBACK_EXT_PHY		4
330#define ELINK_LOOPBACK_EXT		5
331#define ELINK_LOOPBACK_UMAC		6
332#define ELINK_LOOPBACK_XMAC		7
333
334	/* Device parameters */
335	uint8_t mac_addr[6];
336
337	uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
338	uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
339
340	uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
341
342	/* shmem parameters */
343	uint32_t shmem_base;
344	uint32_t shmem2_base;
345	uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
346	uint32_t switch_cfg;
347#define ELINK_SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
348#define ELINK_SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
349#define ELINK_SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT
350
351	uint32_t lane_config;
352
353	/* Phy register parameter */
354	uint32_t chip_id;
355
356	/* features */
357	uint32_t feature_config_flags;
358#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
359#define ELINK_FEATURE_CONFIG_PFC_ENABLED			(1<<1)
360#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
361#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
362#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX			(1<<8)
363#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED		(1<<9)
364#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED	(1<<10)
365#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET		(1<<11)
366#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST			(1<<12)
367#define ELINK_FEATURE_CONFIG_MT_SUPPORT			(1<<13)
368#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN			(1<<14)
369
370	/* Will be populated during common init */
371	struct elink_phy phy[ELINK_MAX_PHYS];
372
373	/* Will be populated during common init */
374	uint8_t num_phys;
375
376	uint8_t rsrv;
377
378	/* Used to configure the EEE Tx LPI timer, has several modes of
379	 * operation, according to bits 29:28 -
380	 * 2'b00: Timer will be configured by nvram, output will be the value
381	 *        from nvram.
382	 * 2'b01: Timer will be configured by nvram, output will be in
383	 *        microseconds.
384	 * 2'b10: bits 1:0 contain an nvram value which will be used instead
385	 *        of the one located in the nvram. Output will be that value.
386	 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
387	 *        will be in microseconds.
388	 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
389	 */
390	uint32_t eee_mode;
391#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME		(0xa00)
392#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME		(0x100)
393#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME		(0x6000)
394#define ELINK_EEE_MODE_NVRAM_MASK		(0x3)
395#define ELINK_EEE_MODE_TIMER_MASK		(0xfffff)
396#define ELINK_EEE_MODE_OUTPUT_TIME		(1<<28)
397#define ELINK_EEE_MODE_OVERRIDE_NVRAM		(1<<29)
398#define ELINK_EEE_MODE_ENABLE_LPI		(1<<30)
399#define ELINK_EEE_MODE_ADV_LPI			(1<<31)
400
401	uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
402	uint32_t multi_phy_config;
403
404	/* Device pointer passed to all callback functions */
405	struct bnx2x_softc *sc;
406	uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
407				req_flow_ctrl is set to AUTO */
408	uint16_t link_flags;
409#define ELINK_LINK_FLAGS_INT_DISABLED		(1<<0)
410#define ELINK_PHY_INITIALIZED		(1<<1)
411	uint32_t lfa_base;
412};
413
414/* Output parameters */
415struct elink_vars {
416	uint8_t phy_flags;
417#define PHY_XGXS_FLAG			(1<<0)
418#define PHY_SGMII_FLAG			(1<<1)
419#define PHY_PHYSICAL_LINK_FLAG		(1<<2)
420#define PHY_HALF_OPEN_CONN_FLAG		(1<<3)
421#define PHY_OVER_CURRENT_FLAG		(1<<4)
422#define PHY_SFP_TX_FAULT_FLAG		(1<<5)
423
424	uint8_t mac_type;
425#define ELINK_MAC_TYPE_NONE		0
426#define ELINK_MAC_TYPE_EMAC		1
427#define ELINK_MAC_TYPE_BMAC		2
428#define ELINK_MAC_TYPE_UMAC		3
429#define ELINK_MAC_TYPE_XMAC		4
430
431	uint8_t phy_link_up; /* internal phy link indication */
432	uint8_t link_up;
433
434	uint16_t line_speed;
435	uint16_t duplex;
436
437	uint16_t flow_ctrl;
438	uint16_t ieee_fc;
439
440	/* The same definitions as the shmem parameter */
441	uint32_t link_status;
442	uint32_t eee_status;
443	uint8_t fault_detected;
444	uint8_t check_kr2_recovery_cnt;
445#define ELINK_CHECK_KR2_RECOVERY_CNT	5
446	uint16_t periodic_flags;
447#define ELINK_PERIODIC_FLAGS_LINK_EVENT	0x0001
448
449	uint32_t aeu_int_mask;
450	uint8_t rx_tx_asic_rst;
451	uint8_t turn_to_run_wc_rt;
452	uint16_t rsrv2;
453	/* The same definitions as the shmem2 parameter */
454	uint32_t link_attr_sync;
455};
456
457/***********************************************************/
458/*                         Functions                       */
459/***********************************************************/
460elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
461
462/* Reset the link. Should be called when driver or interface goes down
463   Before calling phy firmware upgrade, the reset_ext_phy should be set
464   to 0 */
465elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
466/* elink_link_update should be called upon link interrupt */
467elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
468
469/* Reads the link_status from the shmem,
470   and update the link vars accordingly */
471void elink_link_status_update(struct elink_params *input,
472			    struct elink_vars *output);
473
474/* Set/Unset the led
475   Basically, the CLC takes care of the led for the link, but in case one needs
476   to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
477   blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
478elink_status_t elink_set_led(struct elink_params *params,
479		  struct elink_vars *vars, uint8_t mode, uint32_t speed);
480#define ELINK_LED_MODE_OFF			0
481#define ELINK_LED_MODE_ON			1
482#define ELINK_LED_MODE_OPER			2
483#define ELINK_LED_MODE_FRONT_PANEL_OFF	3
484
485/* elink_handle_module_detect_int should be called upon module detection
486   interrupt */
487void elink_handle_module_detect_int(struct elink_params *params);
488
489/* One-time initialization for external phy after power up */
490elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],
491			  uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
492
493void elink_hw_reset_phy(struct elink_params *params);
494
495/* Check swap bit and adjust PHY order */
496uint32_t elink_phy_selection(struct elink_params *params);
497
498/* Probe the phys on board, and populate them in "params" */
499elink_status_t elink_phy_probe(struct elink_params *params);
500
501/* Checks if fan failure detection is required on one of the phys on board */
502uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base,
503			     uint32_t shmem2_base, uint8_t port);
504
505/* Open / close the gate between the NIG and the BRB */
506void elink_set_rx_filter(struct elink_params *params, uint8_t en);
507
508/* DCBX structs */
509
510/* Number of maximum COS per chip */
511#define ELINK_DCBX_E2E3_MAX_NUM_COS		(2)
512#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
513#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
514#define ELINK_DCBX_E3B0_MAX_NUM_COS		( \
515			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
516			    ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
517
518#define ELINK_DCBX_MAX_NUM_COS			( \
519			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
520			    ELINK_DCBX_E2E3_MAX_NUM_COS))
521
522/* PFC port configuration params */
523struct elink_nig_brb_pfc_port_params {
524	/* NIG */
525	uint32_t pause_enable;
526	uint32_t llfc_out_en;
527	uint32_t llfc_enable;
528	uint32_t pkt_priority_to_cos;
529	uint8_t num_of_rx_cos_priority_mask;
530	uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
531	uint32_t llfc_high_priority_classes;
532	uint32_t llfc_low_priority_classes;
533};
534
535
536/* ETS port configuration params */
537struct elink_ets_bw_params {
538	uint8_t bw;
539};
540
541struct elink_ets_sp_params {
542	/**
543	 * valid values are 0 - 5. 0 is highest strict priority.
544	 * There can't be two COS's with the same pri.
545	 */
546	uint8_t pri;
547};
548
549enum elink_cos_state {
550	elink_cos_state_strict = 0,
551	elink_cos_state_bw = 1,
552};
553
554struct elink_ets_cos_params {
555	enum elink_cos_state state ;
556	union {
557		struct elink_ets_bw_params bw_params;
558		struct elink_ets_sp_params sp_params;
559	} params;
560};
561
562struct elink_ets_params {
563	uint8_t num_of_cos; /* Number of valid COS entries*/
564	struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
565};
566
567/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
568 * when link is already up
569 */
570elink_status_t elink_update_pfc(struct elink_params *params,
571		      struct elink_vars *vars,
572		      struct elink_nig_brb_pfc_port_params *pfc_params);
573
574void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
575			    uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
576			    uint8_t port);
577
578void elink_period_func(struct elink_params *params, struct elink_vars *vars);
579
580void elink_enable_pmd_tx(struct elink_params *params);
581
582
583
584#endif /* ELINK_H */
585