t4_hw.c revision ce3d555e
1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2014-2016 Chelsio Communications.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Chelsio Communications nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <netinet/in.h>
35
36#include <rte_interrupts.h>
37#include <rte_log.h>
38#include <rte_debug.h>
39#include <rte_pci.h>
40#include <rte_atomic.h>
41#include <rte_branch_prediction.h>
42#include <rte_memory.h>
43#include <rte_memzone.h>
44#include <rte_tailq.h>
45#include <rte_eal.h>
46#include <rte_alarm.h>
47#include <rte_ether.h>
48#include <rte_ethdev.h>
49#include <rte_atomic.h>
50#include <rte_malloc.h>
51#include <rte_random.h>
52#include <rte_dev.h>
53#include <rte_byteorder.h>
54
55#include "common.h"
56#include "t4_regs.h"
57#include "t4_regs_values.h"
58#include "t4fw_interface.h"
59
60static void init_link_config(struct link_config *lc, unsigned int caps);
61
62/**
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
64 * @adap: the adapter
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
67 *
68 * Reads the HW path MTU table.
69 */
70void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
71{
72	u32 v;
73	int i;
74
75	for (i = 0; i < NMTUS; ++i) {
76		t4_write_reg(adap, A_TP_MTU_TABLE,
77			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
78		v = t4_read_reg(adap, A_TP_MTU_TABLE);
79		mtus[i] = G_MTUVALUE(v);
80		if (mtu_log)
81			mtu_log[i] = G_MTUWIDTH(v);
82	}
83}
84
85/**
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
87 * @adap: the adapter
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
91 *
92 * Sets a field of an indirect TP register to the given value.
93 */
94void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95			    unsigned int mask, unsigned int val)
96{
97	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99	t4_write_reg(adap, A_TP_PIO_DATA, val);
100}
101
102/* The minimum additive increment value for the congestion control table */
103#define CC_MIN_INCR 2U
104
105/**
106 * t4_load_mtus - write the MTU and congestion control HW tables
107 * @adap: the adapter
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
111 *
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
116 */
117void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118		  const unsigned short *alpha, const unsigned short *beta)
119{
120	static const unsigned int avg_pkts[NCCTRL_WIN] = {
121		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123		28672, 40960, 57344, 81920, 114688, 163840, 229376
124	};
125
126	unsigned int i, w;
127
128	for (i = 0; i < NMTUS; ++i) {
129		unsigned int mtu = mtus[i];
130		unsigned int log2 = cxgbe_fls(mtu);
131
132		if (!(mtu & ((1 << log2) >> 2)))     /* round */
133			log2--;
134		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
136
137		for (w = 0; w < NCCTRL_WIN; ++w) {
138			unsigned int inc;
139
140			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
141				  CC_MIN_INCR);
142
143			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144				     (w << 16) | (beta[w] << 13) | inc);
145		}
146	}
147}
148
149/**
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
158 *
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times.  If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there.  Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
163 */
164int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165			int polarity, int attempts, int delay, u32 *valp)
166{
167	while (1) {
168		u32 val = t4_read_reg(adapter, reg);
169
170		if (!!(val & mask) == polarity) {
171			if (valp)
172				*valp = val;
173			return 0;
174		}
175		if (--attempts == 0)
176			return -EAGAIN;
177		if (delay)
178			udelay(delay);
179	}
180}
181
182/**
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
188 *
189 * Sets a register field specified by the supplied mask to the
190 * given value.
191 */
192void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
193		      u32 val)
194{
195	u32 v = t4_read_reg(adapter, addr) & ~mask;
196
197	t4_write_reg(adapter, addr, v | val);
198	(void)t4_read_reg(adapter, addr);      /* flush */
199}
200
201/**
202 * t4_read_indirect - read indirectly addressed registers
203 * @adap: the adapter
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
209 *
210 * Reads registers that are accessed indirectly through an address/data
211 * register pair.
212 */
213void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214		      unsigned int data_reg, u32 *vals, unsigned int nregs,
215		      unsigned int start_idx)
216{
217	while (nregs--) {
218		t4_write_reg(adap, addr_reg, start_idx);
219		*vals++ = t4_read_reg(adap, data_reg);
220		start_idx++;
221	}
222}
223
224/**
225 * t4_write_indirect - write indirectly addressed registers
226 * @adap: the adapter
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
232 *
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
235 */
236void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237		       unsigned int data_reg, const u32 *vals,
238		       unsigned int nregs, unsigned int start_idx)
239{
240	while (nregs--) {
241		t4_write_reg(adap, addr_reg, start_idx++);
242		t4_write_reg(adap, data_reg, *vals++);
243	}
244}
245
246/**
247 * t4_report_fw_error - report firmware error
248 * @adap: the adapter
249 *
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
253 */
254static void t4_report_fw_error(struct adapter *adap)
255{
256	static const char * const reason[] = {
257		"Crash",			/* PCIE_FW_EVAL_CRASH */
258		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
259		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
260		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
261		"Unexpected Event",	/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
263		"Device Shutdown",	/* PCIE_FW_EVAL_DEVICESHUTDOWN */
264		"Reserved",			/* reserved */
265	};
266	u32 pcie_fw;
267
268	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269	if (pcie_fw & F_PCIE_FW_ERR)
270		pr_err("%s: Firmware reports adapter error: %s\n",
271		       __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
272}
273
274/*
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
276 */
277static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
278			 u32 mbox_addr)
279{
280	for ( ; nflit; nflit--, mbox_addr += 8)
281		*rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
282}
283
284/*
285 * Handle a FW assertion reported in a mailbox.
286 */
287static void fw_asrt(struct adapter *adap, u32 mbox_addr)
288{
289	struct fw_debug_cmd asrt;
290
291	get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292	pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293		asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294		be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
295}
296
297#define X_CIM_PF_NOACCESS 0xeeeeeeee
298
299/*
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
302 */
303/* makes single-statement usage a bit cleaner ... */
304#ifdef T4_OS_NEEDS_MBOX_LOCKING
305#define T4_OS_MBOX_LOCKING(x) x
306#else
307#define T4_OS_MBOX_LOCKING(x) do {} while (0)
308#endif
309
310/**
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
312 * @adap: the adapter
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 *	     (negative implies @sleep_ok=false)
320 *
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command.  If @rpl is not %NULL it is used to
323 * store the FW's reply to the command.  The command and its optional
324 * reply are of the same length.  Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false.  This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
331 *
332 * Returns 0 on success or a negative errno on failure.  A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error.  In the latter case
335 * the return value is the error code indicated by FW (negated).
336 */
337int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338			    const void __attribute__((__may_alias__)) *cmd,
339			    int size, void *rpl, bool sleep_ok, int timeout)
340{
341	/*
342	 * We delay in small increments at first in an effort to maintain
343	 * responsiveness for simple, fast executing commands but then back
344	 * off to larger delays to a maximum retry delay.
345	 */
346	static const int delay[] = {
347		1, 1, 3, 5, 10, 10, 20, 50, 100
348	};
349
350	u32 v;
351	u64 res;
352	int i, ms;
353	unsigned int delay_idx;
354	__be64 *temp = (__be64 *)malloc(size * sizeof(char));
355	__be64 *p = temp;
356	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
358	u32 ctl;
359	struct mbox_entry entry;
360	u32 pcie_fw = 0;
361
362	if ((size & 15) || size > MBOX_LEN) {
363		free(temp);
364		return -EINVAL;
365	}
366
367	bzero(p, size);
368	memcpy(p, (const __be64 *)cmd, size);
369
370	/*
371	 * If we have a negative timeout, that implies that we can't sleep.
372	 */
373	if (timeout < 0) {
374		sleep_ok = false;
375		timeout = -timeout;
376	}
377
378#ifdef T4_OS_NEEDS_MBOX_LOCKING
379	/*
380	 * Queue ourselves onto the mailbox access list.  When our entry is at
381	 * the front of the list, we have rights to access the mailbox.  So we
382	 * wait [for a while] till we're at the front [or bail out with an
383	 * EBUSY] ...
384	 */
385	t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
386
387	delay_idx = 0;
388	ms = delay[0];
389
390	for (i = 0; ; i += ms) {
391		/*
392		 * If we've waited too long, return a busy indication.  This
393		 * really ought to be based on our initial position in the
394		 * mailbox access list but this is a start.  We very rarely
395		 * contend on access to the mailbox ...  Also check for a
396		 * firmware error which we'll report as a device error.
397		 */
398		pcie_fw = t4_read_reg(adap, A_PCIE_FW);
399		if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
400			t4_os_atomic_list_del(&entry, &adap->mbox_list,
401					      &adap->mbox_lock);
402			t4_report_fw_error(adap);
403			return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
404		}
405
406		/*
407		 * If we're at the head, break out and start the mailbox
408		 * protocol.
409		 */
410		if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
411			break;
412
413		/*
414		 * Delay for a bit before checking again ...
415		 */
416		if (sleep_ok) {
417			ms = delay[delay_idx];  /* last element may repeat */
418			if (delay_idx < ARRAY_SIZE(delay) - 1)
419				delay_idx++;
420			msleep(ms);
421		} else {
422			rte_delay_ms(ms);
423		}
424	}
425#endif /* T4_OS_NEEDS_MBOX_LOCKING */
426
427	/*
428	 * Attempt to gain access to the mailbox.
429	 */
430	for (i = 0; i < 4; i++) {
431		ctl = t4_read_reg(adap, ctl_reg);
432		v = G_MBOWNER(ctl);
433		if (v != X_MBOWNER_NONE)
434			break;
435	}
436
437	/*
438	 * If we were unable to gain access, dequeue ourselves from the
439	 * mailbox atomic access list and report the error to our caller.
440	 */
441	if (v != X_MBOWNER_PL) {
442		T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
443							 &adap->mbox_list,
444							 &adap->mbox_lock));
445		t4_report_fw_error(adap);
446		return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
447	}
448
449	/*
450	 * If we gain ownership of the mailbox and there's a "valid" message
451	 * in it, this is likely an asynchronous error message from the
452	 * firmware.  So we'll report that and then proceed on with attempting
453	 * to issue our own command ... which may well fail if the error
454	 * presaged the firmware crashing ...
455	 */
456	if (ctl & F_MBMSGVALID) {
457		dev_err(adap, "found VALID command in mbox %u: "
458			"%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
459			(unsigned long long)t4_read_reg64(adap, data_reg),
460			(unsigned long long)t4_read_reg64(adap, data_reg + 8),
461			(unsigned long long)t4_read_reg64(adap, data_reg + 16),
462			(unsigned long long)t4_read_reg64(adap, data_reg + 24),
463			(unsigned long long)t4_read_reg64(adap, data_reg + 32),
464			(unsigned long long)t4_read_reg64(adap, data_reg + 40),
465			(unsigned long long)t4_read_reg64(adap, data_reg + 48),
466			(unsigned long long)t4_read_reg64(adap, data_reg + 56));
467	}
468
469	/*
470	 * Copy in the new mailbox command and send it on its way ...
471	 */
472	for (i = 0; i < size; i += 8, p++)
473		t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
474
475	CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
476			"%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
477			(unsigned long long)t4_read_reg64(adap, data_reg),
478			(unsigned long long)t4_read_reg64(adap, data_reg + 8),
479			(unsigned long long)t4_read_reg64(adap, data_reg + 16),
480			(unsigned long long)t4_read_reg64(adap, data_reg + 24),
481			(unsigned long long)t4_read_reg64(adap, data_reg + 32),
482			(unsigned long long)t4_read_reg64(adap, data_reg + 40),
483			(unsigned long long)t4_read_reg64(adap, data_reg + 48),
484			(unsigned long long)t4_read_reg64(adap, data_reg + 56));
485
486	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
487	t4_read_reg(adap, ctl_reg);          /* flush write */
488
489	delay_idx = 0;
490	ms = delay[0];
491
492	/*
493	 * Loop waiting for the reply; bail out if we time out or the firmware
494	 * reports an error.
495	 */
496	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
497	for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
498		if (sleep_ok) {
499			ms = delay[delay_idx];  /* last element may repeat */
500			if (delay_idx < ARRAY_SIZE(delay) - 1)
501				delay_idx++;
502			msleep(ms);
503		} else {
504			msleep(ms);
505		}
506
507		pcie_fw = t4_read_reg(adap, A_PCIE_FW);
508		v = t4_read_reg(adap, ctl_reg);
509		if (v == X_CIM_PF_NOACCESS)
510			continue;
511		if (G_MBOWNER(v) == X_MBOWNER_PL) {
512			if (!(v & F_MBMSGVALID)) {
513				t4_write_reg(adap, ctl_reg,
514					     V_MBOWNER(X_MBOWNER_NONE));
515				continue;
516			}
517
518			CXGBE_DEBUG_MBOX(adap,
519			"%s: mbox %u: %016llx %016llx %016llx %016llx "
520			"%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
521			(unsigned long long)t4_read_reg64(adap, data_reg),
522			(unsigned long long)t4_read_reg64(adap, data_reg + 8),
523			(unsigned long long)t4_read_reg64(adap, data_reg + 16),
524			(unsigned long long)t4_read_reg64(adap, data_reg + 24),
525			(unsigned long long)t4_read_reg64(adap, data_reg + 32),
526			(unsigned long long)t4_read_reg64(adap, data_reg + 40),
527			(unsigned long long)t4_read_reg64(adap, data_reg + 48),
528			(unsigned long long)t4_read_reg64(adap, data_reg + 56));
529
530			CXGBE_DEBUG_MBOX(adap,
531				"command %#x completed in %d ms (%ssleeping)\n",
532				*(const u8 *)cmd,
533				i + ms, sleep_ok ? "" : "non-");
534
535			res = t4_read_reg64(adap, data_reg);
536			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
537				fw_asrt(adap, data_reg);
538				res = V_FW_CMD_RETVAL(EIO);
539			} else if (rpl) {
540				get_mbox_rpl(adap, rpl, size / 8, data_reg);
541			}
542			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
543			T4_OS_MBOX_LOCKING(
544				t4_os_atomic_list_del(&entry, &adap->mbox_list,
545						      &adap->mbox_lock));
546			return -G_FW_CMD_RETVAL((int)res);
547		}
548	}
549
550	/*
551	 * We timed out waiting for a reply to our mailbox command.  Report
552	 * the error and also check to see if the firmware reported any
553	 * errors ...
554	 */
555	dev_err(adap, "command %#x in mailbox %d timed out\n",
556		*(const u8 *)cmd, mbox);
557	T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
558						 &adap->mbox_list,
559						 &adap->mbox_lock));
560	t4_report_fw_error(adap);
561	free(temp);
562	return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
563}
564
565int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
566		    void *rpl, bool sleep_ok)
567{
568	return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
569				       FW_CMD_MAX_TIMEOUT);
570}
571
572/**
573 * t4_get_regs_len - return the size of the chips register set
574 * @adapter: the adapter
575 *
576 * Returns the size of the chip's BAR0 register space.
577 */
578unsigned int t4_get_regs_len(struct adapter *adapter)
579{
580	unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
581
582	switch (chip_version) {
583	case CHELSIO_T5:
584		return T5_REGMAP_SIZE;
585	}
586
587	dev_err(adapter,
588		"Unsupported chip version %d\n", chip_version);
589	return 0;
590}
591
592/**
593 * t4_get_regs - read chip registers into provided buffer
594 * @adap: the adapter
595 * @buf: register buffer
596 * @buf_size: size (in bytes) of register buffer
597 *
598 * If the provided register buffer isn't large enough for the chip's
599 * full register range, the register dump will be truncated to the
600 * register buffer's size.
601 */
602void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
603{
604	static const unsigned int t5_reg_ranges[] = {
605		0x1008, 0x10c0,
606		0x10cc, 0x10f8,
607		0x1100, 0x1100,
608		0x110c, 0x1148,
609		0x1180, 0x1184,
610		0x1190, 0x1194,
611		0x11a0, 0x11a4,
612		0x11b0, 0x11b4,
613		0x11fc, 0x123c,
614		0x1280, 0x173c,
615		0x1800, 0x18fc,
616		0x3000, 0x3028,
617		0x3060, 0x30b0,
618		0x30b8, 0x30d8,
619		0x30e0, 0x30fc,
620		0x3140, 0x357c,
621		0x35a8, 0x35cc,
622		0x35ec, 0x35ec,
623		0x3600, 0x5624,
624		0x56cc, 0x56ec,
625		0x56f4, 0x5720,
626		0x5728, 0x575c,
627		0x580c, 0x5814,
628		0x5890, 0x589c,
629		0x58a4, 0x58ac,
630		0x58b8, 0x58bc,
631		0x5940, 0x59c8,
632		0x59d0, 0x59dc,
633		0x59fc, 0x5a18,
634		0x5a60, 0x5a70,
635		0x5a80, 0x5a9c,
636		0x5b94, 0x5bfc,
637		0x6000, 0x6020,
638		0x6028, 0x6040,
639		0x6058, 0x609c,
640		0x60a8, 0x614c,
641		0x7700, 0x7798,
642		0x77c0, 0x78fc,
643		0x7b00, 0x7b58,
644		0x7b60, 0x7b84,
645		0x7b8c, 0x7c54,
646		0x7d00, 0x7d38,
647		0x7d40, 0x7d80,
648		0x7d8c, 0x7ddc,
649		0x7de4, 0x7e04,
650		0x7e10, 0x7e1c,
651		0x7e24, 0x7e38,
652		0x7e40, 0x7e44,
653		0x7e4c, 0x7e78,
654		0x7e80, 0x7edc,
655		0x7ee8, 0x7efc,
656		0x8dc0, 0x8de0,
657		0x8df8, 0x8e04,
658		0x8e10, 0x8e84,
659		0x8ea0, 0x8f84,
660		0x8fc0, 0x9058,
661		0x9060, 0x9060,
662		0x9068, 0x90f8,
663		0x9400, 0x9408,
664		0x9410, 0x9470,
665		0x9600, 0x9600,
666		0x9608, 0x9638,
667		0x9640, 0x96f4,
668		0x9800, 0x9808,
669		0x9820, 0x983c,
670		0x9850, 0x9864,
671		0x9c00, 0x9c6c,
672		0x9c80, 0x9cec,
673		0x9d00, 0x9d6c,
674		0x9d80, 0x9dec,
675		0x9e00, 0x9e6c,
676		0x9e80, 0x9eec,
677		0x9f00, 0x9f6c,
678		0x9f80, 0xa020,
679		0xd004, 0xd004,
680		0xd010, 0xd03c,
681		0xdfc0, 0xdfe0,
682		0xe000, 0x1106c,
683		0x11074, 0x11088,
684		0x1109c, 0x1117c,
685		0x11190, 0x11204,
686		0x19040, 0x1906c,
687		0x19078, 0x19080,
688		0x1908c, 0x190e8,
689		0x190f0, 0x190f8,
690		0x19100, 0x19110,
691		0x19120, 0x19124,
692		0x19150, 0x19194,
693		0x1919c, 0x191b0,
694		0x191d0, 0x191e8,
695		0x19238, 0x19290,
696		0x193f8, 0x19428,
697		0x19430, 0x19444,
698		0x1944c, 0x1946c,
699		0x19474, 0x19474,
700		0x19490, 0x194cc,
701		0x194f0, 0x194f8,
702		0x19c00, 0x19c08,
703		0x19c10, 0x19c60,
704		0x19c94, 0x19ce4,
705		0x19cf0, 0x19d40,
706		0x19d50, 0x19d94,
707		0x19da0, 0x19de8,
708		0x19df0, 0x19e10,
709		0x19e50, 0x19e90,
710		0x19ea0, 0x19f24,
711		0x19f34, 0x19f34,
712		0x19f40, 0x19f50,
713		0x19f90, 0x19fb4,
714		0x19fc4, 0x19fe4,
715		0x1a000, 0x1a004,
716		0x1a010, 0x1a06c,
717		0x1a0b0, 0x1a0e4,
718		0x1a0ec, 0x1a0f8,
719		0x1a100, 0x1a108,
720		0x1a114, 0x1a120,
721		0x1a128, 0x1a130,
722		0x1a138, 0x1a138,
723		0x1a190, 0x1a1c4,
724		0x1a1fc, 0x1a1fc,
725		0x1e008, 0x1e00c,
726		0x1e040, 0x1e044,
727		0x1e04c, 0x1e04c,
728		0x1e284, 0x1e290,
729		0x1e2c0, 0x1e2c0,
730		0x1e2e0, 0x1e2e0,
731		0x1e300, 0x1e384,
732		0x1e3c0, 0x1e3c8,
733		0x1e408, 0x1e40c,
734		0x1e440, 0x1e444,
735		0x1e44c, 0x1e44c,
736		0x1e684, 0x1e690,
737		0x1e6c0, 0x1e6c0,
738		0x1e6e0, 0x1e6e0,
739		0x1e700, 0x1e784,
740		0x1e7c0, 0x1e7c8,
741		0x1e808, 0x1e80c,
742		0x1e840, 0x1e844,
743		0x1e84c, 0x1e84c,
744		0x1ea84, 0x1ea90,
745		0x1eac0, 0x1eac0,
746		0x1eae0, 0x1eae0,
747		0x1eb00, 0x1eb84,
748		0x1ebc0, 0x1ebc8,
749		0x1ec08, 0x1ec0c,
750		0x1ec40, 0x1ec44,
751		0x1ec4c, 0x1ec4c,
752		0x1ee84, 0x1ee90,
753		0x1eec0, 0x1eec0,
754		0x1eee0, 0x1eee0,
755		0x1ef00, 0x1ef84,
756		0x1efc0, 0x1efc8,
757		0x1f008, 0x1f00c,
758		0x1f040, 0x1f044,
759		0x1f04c, 0x1f04c,
760		0x1f284, 0x1f290,
761		0x1f2c0, 0x1f2c0,
762		0x1f2e0, 0x1f2e0,
763		0x1f300, 0x1f384,
764		0x1f3c0, 0x1f3c8,
765		0x1f408, 0x1f40c,
766		0x1f440, 0x1f444,
767		0x1f44c, 0x1f44c,
768		0x1f684, 0x1f690,
769		0x1f6c0, 0x1f6c0,
770		0x1f6e0, 0x1f6e0,
771		0x1f700, 0x1f784,
772		0x1f7c0, 0x1f7c8,
773		0x1f808, 0x1f80c,
774		0x1f840, 0x1f844,
775		0x1f84c, 0x1f84c,
776		0x1fa84, 0x1fa90,
777		0x1fac0, 0x1fac0,
778		0x1fae0, 0x1fae0,
779		0x1fb00, 0x1fb84,
780		0x1fbc0, 0x1fbc8,
781		0x1fc08, 0x1fc0c,
782		0x1fc40, 0x1fc44,
783		0x1fc4c, 0x1fc4c,
784		0x1fe84, 0x1fe90,
785		0x1fec0, 0x1fec0,
786		0x1fee0, 0x1fee0,
787		0x1ff00, 0x1ff84,
788		0x1ffc0, 0x1ffc8,
789		0x30000, 0x30030,
790		0x30038, 0x30038,
791		0x30040, 0x30040,
792		0x30100, 0x30144,
793		0x30190, 0x301a0,
794		0x301a8, 0x301b8,
795		0x301c4, 0x301c8,
796		0x301d0, 0x301d0,
797		0x30200, 0x30318,
798		0x30400, 0x304b4,
799		0x304c0, 0x3052c,
800		0x30540, 0x3061c,
801		0x30800, 0x30828,
802		0x30834, 0x30834,
803		0x308c0, 0x30908,
804		0x30910, 0x309ac,
805		0x30a00, 0x30a14,
806		0x30a1c, 0x30a2c,
807		0x30a44, 0x30a50,
808		0x30a74, 0x30a74,
809		0x30a7c, 0x30afc,
810		0x30b08, 0x30c24,
811		0x30d00, 0x30d00,
812		0x30d08, 0x30d14,
813		0x30d1c, 0x30d20,
814		0x30d3c, 0x30d3c,
815		0x30d48, 0x30d50,
816		0x31200, 0x3120c,
817		0x31220, 0x31220,
818		0x31240, 0x31240,
819		0x31600, 0x3160c,
820		0x31a00, 0x31a1c,
821		0x31e00, 0x31e20,
822		0x31e38, 0x31e3c,
823		0x31e80, 0x31e80,
824		0x31e88, 0x31ea8,
825		0x31eb0, 0x31eb4,
826		0x31ec8, 0x31ed4,
827		0x31fb8, 0x32004,
828		0x32200, 0x32200,
829		0x32208, 0x32240,
830		0x32248, 0x32280,
831		0x32288, 0x322c0,
832		0x322c8, 0x322fc,
833		0x32600, 0x32630,
834		0x32a00, 0x32abc,
835		0x32b00, 0x32b10,
836		0x32b20, 0x32b30,
837		0x32b40, 0x32b50,
838		0x32b60, 0x32b70,
839		0x33000, 0x33028,
840		0x33030, 0x33048,
841		0x33060, 0x33068,
842		0x33070, 0x3309c,
843		0x330f0, 0x33128,
844		0x33130, 0x33148,
845		0x33160, 0x33168,
846		0x33170, 0x3319c,
847		0x331f0, 0x33238,
848		0x33240, 0x33240,
849		0x33248, 0x33250,
850		0x3325c, 0x33264,
851		0x33270, 0x332b8,
852		0x332c0, 0x332e4,
853		0x332f8, 0x33338,
854		0x33340, 0x33340,
855		0x33348, 0x33350,
856		0x3335c, 0x33364,
857		0x33370, 0x333b8,
858		0x333c0, 0x333e4,
859		0x333f8, 0x33428,
860		0x33430, 0x33448,
861		0x33460, 0x33468,
862		0x33470, 0x3349c,
863		0x334f0, 0x33528,
864		0x33530, 0x33548,
865		0x33560, 0x33568,
866		0x33570, 0x3359c,
867		0x335f0, 0x33638,
868		0x33640, 0x33640,
869		0x33648, 0x33650,
870		0x3365c, 0x33664,
871		0x33670, 0x336b8,
872		0x336c0, 0x336e4,
873		0x336f8, 0x33738,
874		0x33740, 0x33740,
875		0x33748, 0x33750,
876		0x3375c, 0x33764,
877		0x33770, 0x337b8,
878		0x337c0, 0x337e4,
879		0x337f8, 0x337fc,
880		0x33814, 0x33814,
881		0x3382c, 0x3382c,
882		0x33880, 0x3388c,
883		0x338e8, 0x338ec,
884		0x33900, 0x33928,
885		0x33930, 0x33948,
886		0x33960, 0x33968,
887		0x33970, 0x3399c,
888		0x339f0, 0x33a38,
889		0x33a40, 0x33a40,
890		0x33a48, 0x33a50,
891		0x33a5c, 0x33a64,
892		0x33a70, 0x33ab8,
893		0x33ac0, 0x33ae4,
894		0x33af8, 0x33b10,
895		0x33b28, 0x33b28,
896		0x33b3c, 0x33b50,
897		0x33bf0, 0x33c10,
898		0x33c28, 0x33c28,
899		0x33c3c, 0x33c50,
900		0x33cf0, 0x33cfc,
901		0x34000, 0x34030,
902		0x34038, 0x34038,
903		0x34040, 0x34040,
904		0x34100, 0x34144,
905		0x34190, 0x341a0,
906		0x341a8, 0x341b8,
907		0x341c4, 0x341c8,
908		0x341d0, 0x341d0,
909		0x34200, 0x34318,
910		0x34400, 0x344b4,
911		0x344c0, 0x3452c,
912		0x34540, 0x3461c,
913		0x34800, 0x34828,
914		0x34834, 0x34834,
915		0x348c0, 0x34908,
916		0x34910, 0x349ac,
917		0x34a00, 0x34a14,
918		0x34a1c, 0x34a2c,
919		0x34a44, 0x34a50,
920		0x34a74, 0x34a74,
921		0x34a7c, 0x34afc,
922		0x34b08, 0x34c24,
923		0x34d00, 0x34d00,
924		0x34d08, 0x34d14,
925		0x34d1c, 0x34d20,
926		0x34d3c, 0x34d3c,
927		0x34d48, 0x34d50,
928		0x35200, 0x3520c,
929		0x35220, 0x35220,
930		0x35240, 0x35240,
931		0x35600, 0x3560c,
932		0x35a00, 0x35a1c,
933		0x35e00, 0x35e20,
934		0x35e38, 0x35e3c,
935		0x35e80, 0x35e80,
936		0x35e88, 0x35ea8,
937		0x35eb0, 0x35eb4,
938		0x35ec8, 0x35ed4,
939		0x35fb8, 0x36004,
940		0x36200, 0x36200,
941		0x36208, 0x36240,
942		0x36248, 0x36280,
943		0x36288, 0x362c0,
944		0x362c8, 0x362fc,
945		0x36600, 0x36630,
946		0x36a00, 0x36abc,
947		0x36b00, 0x36b10,
948		0x36b20, 0x36b30,
949		0x36b40, 0x36b50,
950		0x36b60, 0x36b70,
951		0x37000, 0x37028,
952		0x37030, 0x37048,
953		0x37060, 0x37068,
954		0x37070, 0x3709c,
955		0x370f0, 0x37128,
956		0x37130, 0x37148,
957		0x37160, 0x37168,
958		0x37170, 0x3719c,
959		0x371f0, 0x37238,
960		0x37240, 0x37240,
961		0x37248, 0x37250,
962		0x3725c, 0x37264,
963		0x37270, 0x372b8,
964		0x372c0, 0x372e4,
965		0x372f8, 0x37338,
966		0x37340, 0x37340,
967		0x37348, 0x37350,
968		0x3735c, 0x37364,
969		0x37370, 0x373b8,
970		0x373c0, 0x373e4,
971		0x373f8, 0x37428,
972		0x37430, 0x37448,
973		0x37460, 0x37468,
974		0x37470, 0x3749c,
975		0x374f0, 0x37528,
976		0x37530, 0x37548,
977		0x37560, 0x37568,
978		0x37570, 0x3759c,
979		0x375f0, 0x37638,
980		0x37640, 0x37640,
981		0x37648, 0x37650,
982		0x3765c, 0x37664,
983		0x37670, 0x376b8,
984		0x376c0, 0x376e4,
985		0x376f8, 0x37738,
986		0x37740, 0x37740,
987		0x37748, 0x37750,
988		0x3775c, 0x37764,
989		0x37770, 0x377b8,
990		0x377c0, 0x377e4,
991		0x377f8, 0x377fc,
992		0x37814, 0x37814,
993		0x3782c, 0x3782c,
994		0x37880, 0x3788c,
995		0x378e8, 0x378ec,
996		0x37900, 0x37928,
997		0x37930, 0x37948,
998		0x37960, 0x37968,
999		0x37970, 0x3799c,
1000		0x379f0, 0x37a38,
1001		0x37a40, 0x37a40,
1002		0x37a48, 0x37a50,
1003		0x37a5c, 0x37a64,
1004		0x37a70, 0x37ab8,
1005		0x37ac0, 0x37ae4,
1006		0x37af8, 0x37b10,
1007		0x37b28, 0x37b28,
1008		0x37b3c, 0x37b50,
1009		0x37bf0, 0x37c10,
1010		0x37c28, 0x37c28,
1011		0x37c3c, 0x37c50,
1012		0x37cf0, 0x37cfc,
1013		0x38000, 0x38030,
1014		0x38038, 0x38038,
1015		0x38040, 0x38040,
1016		0x38100, 0x38144,
1017		0x38190, 0x381a0,
1018		0x381a8, 0x381b8,
1019		0x381c4, 0x381c8,
1020		0x381d0, 0x381d0,
1021		0x38200, 0x38318,
1022		0x38400, 0x384b4,
1023		0x384c0, 0x3852c,
1024		0x38540, 0x3861c,
1025		0x38800, 0x38828,
1026		0x38834, 0x38834,
1027		0x388c0, 0x38908,
1028		0x38910, 0x389ac,
1029		0x38a00, 0x38a14,
1030		0x38a1c, 0x38a2c,
1031		0x38a44, 0x38a50,
1032		0x38a74, 0x38a74,
1033		0x38a7c, 0x38afc,
1034		0x38b08, 0x38c24,
1035		0x38d00, 0x38d00,
1036		0x38d08, 0x38d14,
1037		0x38d1c, 0x38d20,
1038		0x38d3c, 0x38d3c,
1039		0x38d48, 0x38d50,
1040		0x39200, 0x3920c,
1041		0x39220, 0x39220,
1042		0x39240, 0x39240,
1043		0x39600, 0x3960c,
1044		0x39a00, 0x39a1c,
1045		0x39e00, 0x39e20,
1046		0x39e38, 0x39e3c,
1047		0x39e80, 0x39e80,
1048		0x39e88, 0x39ea8,
1049		0x39eb0, 0x39eb4,
1050		0x39ec8, 0x39ed4,
1051		0x39fb8, 0x3a004,
1052		0x3a200, 0x3a200,
1053		0x3a208, 0x3a240,
1054		0x3a248, 0x3a280,
1055		0x3a288, 0x3a2c0,
1056		0x3a2c8, 0x3a2fc,
1057		0x3a600, 0x3a630,
1058		0x3aa00, 0x3aabc,
1059		0x3ab00, 0x3ab10,
1060		0x3ab20, 0x3ab30,
1061		0x3ab40, 0x3ab50,
1062		0x3ab60, 0x3ab70,
1063		0x3b000, 0x3b028,
1064		0x3b030, 0x3b048,
1065		0x3b060, 0x3b068,
1066		0x3b070, 0x3b09c,
1067		0x3b0f0, 0x3b128,
1068		0x3b130, 0x3b148,
1069		0x3b160, 0x3b168,
1070		0x3b170, 0x3b19c,
1071		0x3b1f0, 0x3b238,
1072		0x3b240, 0x3b240,
1073		0x3b248, 0x3b250,
1074		0x3b25c, 0x3b264,
1075		0x3b270, 0x3b2b8,
1076		0x3b2c0, 0x3b2e4,
1077		0x3b2f8, 0x3b338,
1078		0x3b340, 0x3b340,
1079		0x3b348, 0x3b350,
1080		0x3b35c, 0x3b364,
1081		0x3b370, 0x3b3b8,
1082		0x3b3c0, 0x3b3e4,
1083		0x3b3f8, 0x3b428,
1084		0x3b430, 0x3b448,
1085		0x3b460, 0x3b468,
1086		0x3b470, 0x3b49c,
1087		0x3b4f0, 0x3b528,
1088		0x3b530, 0x3b548,
1089		0x3b560, 0x3b568,
1090		0x3b570, 0x3b59c,
1091		0x3b5f0, 0x3b638,
1092		0x3b640, 0x3b640,
1093		0x3b648, 0x3b650,
1094		0x3b65c, 0x3b664,
1095		0x3b670, 0x3b6b8,
1096		0x3b6c0, 0x3b6e4,
1097		0x3b6f8, 0x3b738,
1098		0x3b740, 0x3b740,
1099		0x3b748, 0x3b750,
1100		0x3b75c, 0x3b764,
1101		0x3b770, 0x3b7b8,
1102		0x3b7c0, 0x3b7e4,
1103		0x3b7f8, 0x3b7fc,
1104		0x3b814, 0x3b814,
1105		0x3b82c, 0x3b82c,
1106		0x3b880, 0x3b88c,
1107		0x3b8e8, 0x3b8ec,
1108		0x3b900, 0x3b928,
1109		0x3b930, 0x3b948,
1110		0x3b960, 0x3b968,
1111		0x3b970, 0x3b99c,
1112		0x3b9f0, 0x3ba38,
1113		0x3ba40, 0x3ba40,
1114		0x3ba48, 0x3ba50,
1115		0x3ba5c, 0x3ba64,
1116		0x3ba70, 0x3bab8,
1117		0x3bac0, 0x3bae4,
1118		0x3baf8, 0x3bb10,
1119		0x3bb28, 0x3bb28,
1120		0x3bb3c, 0x3bb50,
1121		0x3bbf0, 0x3bc10,
1122		0x3bc28, 0x3bc28,
1123		0x3bc3c, 0x3bc50,
1124		0x3bcf0, 0x3bcfc,
1125		0x3c000, 0x3c030,
1126		0x3c038, 0x3c038,
1127		0x3c040, 0x3c040,
1128		0x3c100, 0x3c144,
1129		0x3c190, 0x3c1a0,
1130		0x3c1a8, 0x3c1b8,
1131		0x3c1c4, 0x3c1c8,
1132		0x3c1d0, 0x3c1d0,
1133		0x3c200, 0x3c318,
1134		0x3c400, 0x3c4b4,
1135		0x3c4c0, 0x3c52c,
1136		0x3c540, 0x3c61c,
1137		0x3c800, 0x3c828,
1138		0x3c834, 0x3c834,
1139		0x3c8c0, 0x3c908,
1140		0x3c910, 0x3c9ac,
1141		0x3ca00, 0x3ca14,
1142		0x3ca1c, 0x3ca2c,
1143		0x3ca44, 0x3ca50,
1144		0x3ca74, 0x3ca74,
1145		0x3ca7c, 0x3cafc,
1146		0x3cb08, 0x3cc24,
1147		0x3cd00, 0x3cd00,
1148		0x3cd08, 0x3cd14,
1149		0x3cd1c, 0x3cd20,
1150		0x3cd3c, 0x3cd3c,
1151		0x3cd48, 0x3cd50,
1152		0x3d200, 0x3d20c,
1153		0x3d220, 0x3d220,
1154		0x3d240, 0x3d240,
1155		0x3d600, 0x3d60c,
1156		0x3da00, 0x3da1c,
1157		0x3de00, 0x3de20,
1158		0x3de38, 0x3de3c,
1159		0x3de80, 0x3de80,
1160		0x3de88, 0x3dea8,
1161		0x3deb0, 0x3deb4,
1162		0x3dec8, 0x3ded4,
1163		0x3dfb8, 0x3e004,
1164		0x3e200, 0x3e200,
1165		0x3e208, 0x3e240,
1166		0x3e248, 0x3e280,
1167		0x3e288, 0x3e2c0,
1168		0x3e2c8, 0x3e2fc,
1169		0x3e600, 0x3e630,
1170		0x3ea00, 0x3eabc,
1171		0x3eb00, 0x3eb10,
1172		0x3eb20, 0x3eb30,
1173		0x3eb40, 0x3eb50,
1174		0x3eb60, 0x3eb70,
1175		0x3f000, 0x3f028,
1176		0x3f030, 0x3f048,
1177		0x3f060, 0x3f068,
1178		0x3f070, 0x3f09c,
1179		0x3f0f0, 0x3f128,
1180		0x3f130, 0x3f148,
1181		0x3f160, 0x3f168,
1182		0x3f170, 0x3f19c,
1183		0x3f1f0, 0x3f238,
1184		0x3f240, 0x3f240,
1185		0x3f248, 0x3f250,
1186		0x3f25c, 0x3f264,
1187		0x3f270, 0x3f2b8,
1188		0x3f2c0, 0x3f2e4,
1189		0x3f2f8, 0x3f338,
1190		0x3f340, 0x3f340,
1191		0x3f348, 0x3f350,
1192		0x3f35c, 0x3f364,
1193		0x3f370, 0x3f3b8,
1194		0x3f3c0, 0x3f3e4,
1195		0x3f3f8, 0x3f428,
1196		0x3f430, 0x3f448,
1197		0x3f460, 0x3f468,
1198		0x3f470, 0x3f49c,
1199		0x3f4f0, 0x3f528,
1200		0x3f530, 0x3f548,
1201		0x3f560, 0x3f568,
1202		0x3f570, 0x3f59c,
1203		0x3f5f0, 0x3f638,
1204		0x3f640, 0x3f640,
1205		0x3f648, 0x3f650,
1206		0x3f65c, 0x3f664,
1207		0x3f670, 0x3f6b8,
1208		0x3f6c0, 0x3f6e4,
1209		0x3f6f8, 0x3f738,
1210		0x3f740, 0x3f740,
1211		0x3f748, 0x3f750,
1212		0x3f75c, 0x3f764,
1213		0x3f770, 0x3f7b8,
1214		0x3f7c0, 0x3f7e4,
1215		0x3f7f8, 0x3f7fc,
1216		0x3f814, 0x3f814,
1217		0x3f82c, 0x3f82c,
1218		0x3f880, 0x3f88c,
1219		0x3f8e8, 0x3f8ec,
1220		0x3f900, 0x3f928,
1221		0x3f930, 0x3f948,
1222		0x3f960, 0x3f968,
1223		0x3f970, 0x3f99c,
1224		0x3f9f0, 0x3fa38,
1225		0x3fa40, 0x3fa40,
1226		0x3fa48, 0x3fa50,
1227		0x3fa5c, 0x3fa64,
1228		0x3fa70, 0x3fab8,
1229		0x3fac0, 0x3fae4,
1230		0x3faf8, 0x3fb10,
1231		0x3fb28, 0x3fb28,
1232		0x3fb3c, 0x3fb50,
1233		0x3fbf0, 0x3fc10,
1234		0x3fc28, 0x3fc28,
1235		0x3fc3c, 0x3fc50,
1236		0x3fcf0, 0x3fcfc,
1237		0x40000, 0x4000c,
1238		0x40040, 0x40050,
1239		0x40060, 0x40068,
1240		0x4007c, 0x4008c,
1241		0x40094, 0x400b0,
1242		0x400c0, 0x40144,
1243		0x40180, 0x4018c,
1244		0x40200, 0x40254,
1245		0x40260, 0x40264,
1246		0x40270, 0x40288,
1247		0x40290, 0x40298,
1248		0x402ac, 0x402c8,
1249		0x402d0, 0x402e0,
1250		0x402f0, 0x402f0,
1251		0x40300, 0x4033c,
1252		0x403f8, 0x403fc,
1253		0x41304, 0x413c4,
1254		0x41400, 0x4140c,
1255		0x41414, 0x4141c,
1256		0x41480, 0x414d0,
1257		0x44000, 0x44054,
1258		0x4405c, 0x44078,
1259		0x440c0, 0x44174,
1260		0x44180, 0x441ac,
1261		0x441b4, 0x441b8,
1262		0x441c0, 0x44254,
1263		0x4425c, 0x44278,
1264		0x442c0, 0x44374,
1265		0x44380, 0x443ac,
1266		0x443b4, 0x443b8,
1267		0x443c0, 0x44454,
1268		0x4445c, 0x44478,
1269		0x444c0, 0x44574,
1270		0x44580, 0x445ac,
1271		0x445b4, 0x445b8,
1272		0x445c0, 0x44654,
1273		0x4465c, 0x44678,
1274		0x446c0, 0x44774,
1275		0x44780, 0x447ac,
1276		0x447b4, 0x447b8,
1277		0x447c0, 0x44854,
1278		0x4485c, 0x44878,
1279		0x448c0, 0x44974,
1280		0x44980, 0x449ac,
1281		0x449b4, 0x449b8,
1282		0x449c0, 0x449fc,
1283		0x45000, 0x45004,
1284		0x45010, 0x45030,
1285		0x45040, 0x45060,
1286		0x45068, 0x45068,
1287		0x45080, 0x45084,
1288		0x450a0, 0x450b0,
1289		0x45200, 0x45204,
1290		0x45210, 0x45230,
1291		0x45240, 0x45260,
1292		0x45268, 0x45268,
1293		0x45280, 0x45284,
1294		0x452a0, 0x452b0,
1295		0x460c0, 0x460e4,
1296		0x47000, 0x4703c,
1297		0x47044, 0x4708c,
1298		0x47200, 0x47250,
1299		0x47400, 0x47408,
1300		0x47414, 0x47420,
1301		0x47600, 0x47618,
1302		0x47800, 0x47814,
1303		0x48000, 0x4800c,
1304		0x48040, 0x48050,
1305		0x48060, 0x48068,
1306		0x4807c, 0x4808c,
1307		0x48094, 0x480b0,
1308		0x480c0, 0x48144,
1309		0x48180, 0x4818c,
1310		0x48200, 0x48254,
1311		0x48260, 0x48264,
1312		0x48270, 0x48288,
1313		0x48290, 0x48298,
1314		0x482ac, 0x482c8,
1315		0x482d0, 0x482e0,
1316		0x482f0, 0x482f0,
1317		0x48300, 0x4833c,
1318		0x483f8, 0x483fc,
1319		0x49304, 0x493c4,
1320		0x49400, 0x4940c,
1321		0x49414, 0x4941c,
1322		0x49480, 0x494d0,
1323		0x4c000, 0x4c054,
1324		0x4c05c, 0x4c078,
1325		0x4c0c0, 0x4c174,
1326		0x4c180, 0x4c1ac,
1327		0x4c1b4, 0x4c1b8,
1328		0x4c1c0, 0x4c254,
1329		0x4c25c, 0x4c278,
1330		0x4c2c0, 0x4c374,
1331		0x4c380, 0x4c3ac,
1332		0x4c3b4, 0x4c3b8,
1333		0x4c3c0, 0x4c454,
1334		0x4c45c, 0x4c478,
1335		0x4c4c0, 0x4c574,
1336		0x4c580, 0x4c5ac,
1337		0x4c5b4, 0x4c5b8,
1338		0x4c5c0, 0x4c654,
1339		0x4c65c, 0x4c678,
1340		0x4c6c0, 0x4c774,
1341		0x4c780, 0x4c7ac,
1342		0x4c7b4, 0x4c7b8,
1343		0x4c7c0, 0x4c854,
1344		0x4c85c, 0x4c878,
1345		0x4c8c0, 0x4c974,
1346		0x4c980, 0x4c9ac,
1347		0x4c9b4, 0x4c9b8,
1348		0x4c9c0, 0x4c9fc,
1349		0x4d000, 0x4d004,
1350		0x4d010, 0x4d030,
1351		0x4d040, 0x4d060,
1352		0x4d068, 0x4d068,
1353		0x4d080, 0x4d084,
1354		0x4d0a0, 0x4d0b0,
1355		0x4d200, 0x4d204,
1356		0x4d210, 0x4d230,
1357		0x4d240, 0x4d260,
1358		0x4d268, 0x4d268,
1359		0x4d280, 0x4d284,
1360		0x4d2a0, 0x4d2b0,
1361		0x4e0c0, 0x4e0e4,
1362		0x4f000, 0x4f03c,
1363		0x4f044, 0x4f08c,
1364		0x4f200, 0x4f250,
1365		0x4f400, 0x4f408,
1366		0x4f414, 0x4f420,
1367		0x4f600, 0x4f618,
1368		0x4f800, 0x4f814,
1369		0x50000, 0x50084,
1370		0x50090, 0x500cc,
1371		0x50400, 0x50400,
1372		0x50800, 0x50884,
1373		0x50890, 0x508cc,
1374		0x50c00, 0x50c00,
1375		0x51000, 0x5101c,
1376		0x51300, 0x51308,
1377	};
1378
1379	u32 *buf_end = (u32 *)((char *)buf + buf_size);
1380	const unsigned int *reg_ranges;
1381	int reg_ranges_size, range;
1382	unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1383
1384	/* Select the right set of register ranges to dump depending on the
1385	 * adapter chip type.
1386	 */
1387	switch (chip_version) {
1388	case CHELSIO_T5:
1389		reg_ranges = t5_reg_ranges;
1390		reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1391		break;
1392
1393	default:
1394		dev_err(adap,
1395			"Unsupported chip version %d\n", chip_version);
1396		return;
1397	}
1398
1399	/* Clear the register buffer and insert the appropriate register
1400	 * values selected by the above register ranges.
1401	 */
1402	memset(buf, 0, buf_size);
1403	for (range = 0; range < reg_ranges_size; range += 2) {
1404		unsigned int reg = reg_ranges[range];
1405		unsigned int last_reg = reg_ranges[range + 1];
1406		u32 *bufp = (u32 *)((char *)buf + reg);
1407
1408		/* Iterate across the register range filling in the register
1409		 * buffer but don't write past the end of the register buffer.
1410		 */
1411		while (reg <= last_reg && bufp < buf_end) {
1412			*bufp++ = t4_read_reg(adap, reg);
1413			reg += sizeof(u32);
1414		}
1415	}
1416}
1417
1418/* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1419#define EEPROM_DELAY            10              /* 10us per poll spin */
1420#define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1421
1422#define EEPROM_STAT_ADDR        0x7bfc
1423
1424/**
1425 * Small utility function to wait till any outstanding VPD Access is complete.
1426 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1427 * VPD Access in flight.  This allows us to handle the problem of having a
1428 * previous VPD Access time out and prevent an attempt to inject a new VPD
1429 * Request before any in-flight VPD request has completed.
1430 */
1431static int t4_seeprom_wait(struct adapter *adapter)
1432{
1433	unsigned int base = adapter->params.pci.vpd_cap_addr;
1434	int max_poll;
1435
1436	/* If no VPD Access is in flight, we can just return success right
1437	 * away.
1438	 */
1439	if (!adapter->vpd_busy)
1440		return 0;
1441
1442	/* Poll the VPD Capability Address/Flag register waiting for it
1443	 * to indicate that the operation is complete.
1444	 */
1445	max_poll = EEPROM_MAX_POLL;
1446	do {
1447		u16 val;
1448
1449		udelay(EEPROM_DELAY);
1450		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1451
1452		/* If the operation is complete, mark the VPD as no longer
1453		 * busy and return success.
1454		 */
1455		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1456			adapter->vpd_busy = 0;
1457			return 0;
1458		}
1459	} while (--max_poll);
1460
1461	/* Failure!  Note that we leave the VPD Busy status set in order to
1462	 * avoid pushing a new VPD Access request into the VPD Capability till
1463	 * the current operation eventually succeeds.  It's a bug to issue a
1464	 * new request when an existing request is in flight and will result
1465	 * in corrupt hardware state.
1466	 */
1467	return -ETIMEDOUT;
1468}
1469
1470/**
1471 * t4_seeprom_read - read a serial EEPROM location
1472 * @adapter: adapter to read
1473 * @addr: EEPROM virtual address
1474 * @data: where to store the read data
1475 *
1476 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
1477 * VPD capability.  Note that this function must be called with a virtual
1478 * address.
1479 */
1480int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
1481{
1482	unsigned int base = adapter->params.pci.vpd_cap_addr;
1483	int ret;
1484
1485	/* VPD Accesses must alway be 4-byte aligned!
1486	 */
1487	if (addr >= EEPROMVSIZE || (addr & 3))
1488		return -EINVAL;
1489
1490	/* Wait for any previous operation which may still be in flight to
1491	 * complete.
1492	 */
1493	ret = t4_seeprom_wait(adapter);
1494	if (ret) {
1495		dev_err(adapter, "VPD still busy from previous operation\n");
1496		return ret;
1497	}
1498
1499	/* Issue our new VPD Read request, mark the VPD as being busy and wait
1500	 * for our request to complete.  If it doesn't complete, note the
1501	 * error and return it to our caller.  Note that we do not reset the
1502	 * VPD Busy status!
1503	 */
1504	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
1505	adapter->vpd_busy = 1;
1506	adapter->vpd_flag = PCI_VPD_ADDR_F;
1507	ret = t4_seeprom_wait(adapter);
1508	if (ret) {
1509		dev_err(adapter, "VPD read of address %#x failed\n", addr);
1510		return ret;
1511	}
1512
1513	/* Grab the returned data, swizzle it into our endianness and
1514	 * return success.
1515	 */
1516	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
1517	*data = le32_to_cpu(*data);
1518	return 0;
1519}
1520
1521/**
1522 * t4_seeprom_write - write a serial EEPROM location
1523 * @adapter: adapter to write
1524 * @addr: virtual EEPROM address
1525 * @data: value to write
1526 *
1527 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
1528 * VPD capability.  Note that this function must be called with a virtual
1529 * address.
1530 */
1531int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
1532{
1533	unsigned int base = adapter->params.pci.vpd_cap_addr;
1534	int ret;
1535	u32 stats_reg = 0;
1536	int max_poll;
1537
1538	/* VPD Accesses must alway be 4-byte aligned!
1539	 */
1540	if (addr >= EEPROMVSIZE || (addr & 3))
1541		return -EINVAL;
1542
1543	/* Wait for any previous operation which may still be in flight to
1544	 * complete.
1545	 */
1546	ret = t4_seeprom_wait(adapter);
1547	if (ret) {
1548		dev_err(adapter, "VPD still busy from previous operation\n");
1549		return ret;
1550	}
1551
1552	/* Issue our new VPD Read request, mark the VPD as being busy and wait
1553	 * for our request to complete.  If it doesn't complete, note the
1554	 * error and return it to our caller.  Note that we do not reset the
1555	 * VPD Busy status!
1556	 */
1557	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
1558			     cpu_to_le32(data));
1559	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
1560			     (u16)addr | PCI_VPD_ADDR_F);
1561	adapter->vpd_busy = 1;
1562	adapter->vpd_flag = 0;
1563	ret = t4_seeprom_wait(adapter);
1564	if (ret) {
1565		dev_err(adapter, "VPD write of address %#x failed\n", addr);
1566		return ret;
1567	}
1568
1569	/* Reset PCI_VPD_DATA register after a transaction and wait for our
1570	 * request to complete. If it doesn't complete, return error.
1571	 */
1572	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
1573	max_poll = EEPROM_MAX_POLL;
1574	do {
1575		udelay(EEPROM_DELAY);
1576		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
1577	} while ((stats_reg & 0x1) && --max_poll);
1578	if (!max_poll)
1579		return -ETIMEDOUT;
1580
1581	/* Return success! */
1582	return 0;
1583}
1584
1585/**
1586 * t4_seeprom_wp - enable/disable EEPROM write protection
1587 * @adapter: the adapter
1588 * @enable: whether to enable or disable write protection
1589 *
1590 * Enables or disables write protection on the serial EEPROM.
1591 */
1592int t4_seeprom_wp(struct adapter *adapter, int enable)
1593{
1594	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
1595}
1596
1597/**
1598 * t4_config_rss_range - configure a portion of the RSS mapping table
1599 * @adapter: the adapter
1600 * @mbox: mbox to use for the FW command
1601 * @viid: virtual interface whose RSS subtable is to be written
1602 * @start: start entry in the table to write
1603 * @n: how many table entries to write
1604 * @rspq: values for the "response queue" (Ingress Queue) lookup table
1605 * @nrspq: number of values in @rspq
1606 *
1607 * Programs the selected part of the VI's RSS mapping table with the
1608 * provided values.  If @nrspq < @n the supplied values are used repeatedly
1609 * until the full table range is populated.
1610 *
1611 * The caller must ensure the values in @rspq are in the range allowed for
1612 * @viid.
1613 */
1614int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1615			int start, int n, const u16 *rspq, unsigned int nrspq)
1616{
1617	int ret;
1618	const u16 *rsp = rspq;
1619	const u16 *rsp_end = rspq + nrspq;
1620	struct fw_rss_ind_tbl_cmd cmd;
1621
1622	memset(&cmd, 0, sizeof(cmd));
1623	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1624				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1625				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
1626	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1627
1628	/*
1629	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
1630	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
1631	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
1632	 * reserved.
1633	 */
1634	while (n > 0) {
1635		int nq = min(n, 32);
1636		int nq_packed = 0;
1637		__be32 *qp = &cmd.iq0_to_iq2;
1638
1639		/*
1640		 * Set up the firmware RSS command header to send the next
1641		 * "nq" Ingress Queue IDs to the firmware.
1642		 */
1643		cmd.niqid = cpu_to_be16(nq);
1644		cmd.startidx = cpu_to_be16(start);
1645
1646		/*
1647		 * "nq" more done for the start of the next loop.
1648		 */
1649		start += nq;
1650		n -= nq;
1651
1652		/*
1653		 * While there are still Ingress Queue IDs to stuff into the
1654		 * current firmware RSS command, retrieve them from the
1655		 * Ingress Queue ID array and insert them into the command.
1656		 */
1657		while (nq > 0) {
1658			/*
1659			 * Grab up to the next 3 Ingress Queue IDs (wrapping
1660			 * around the Ingress Queue ID array if necessary) and
1661			 * insert them into the firmware RSS command at the
1662			 * current 3-tuple position within the commad.
1663			 */
1664			u16 qbuf[3];
1665			u16 *qbp = qbuf;
1666			int nqbuf = min(3, nq);
1667
1668			nq -= nqbuf;
1669			qbuf[0] = 0;
1670			qbuf[1] = 0;
1671			qbuf[2] = 0;
1672			while (nqbuf && nq_packed < 32) {
1673				nqbuf--;
1674				nq_packed++;
1675				*qbp++ = *rsp++;
1676				if (rsp >= rsp_end)
1677					rsp = rspq;
1678			}
1679			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
1680					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
1681					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
1682		}
1683
1684		/*
1685		 * Send this portion of the RRS table update to the firmware;
1686		 * bail out on any errors.
1687		 */
1688		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1689		if (ret)
1690			return ret;
1691	}
1692
1693	return 0;
1694}
1695
1696/**
1697 * t4_config_vi_rss - configure per VI RSS settings
1698 * @adapter: the adapter
1699 * @mbox: mbox to use for the FW command
1700 * @viid: the VI id
1701 * @flags: RSS flags
1702 * @defq: id of the default RSS queue for the VI.
1703 *
1704 * Configures VI-specific RSS properties.
1705 */
1706int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1707		     unsigned int flags, unsigned int defq)
1708{
1709	struct fw_rss_vi_config_cmd c;
1710
1711	memset(&c, 0, sizeof(c));
1712	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
1713				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1714				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
1715	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1716	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
1717			V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
1718	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1719}
1720
1721/**
1722 * init_cong_ctrl - initialize congestion control parameters
1723 * @a: the alpha values for congestion control
1724 * @b: the beta values for congestion control
1725 *
1726 * Initialize the congestion control parameters.
1727 */
1728static void init_cong_ctrl(unsigned short *a, unsigned short *b)
1729{
1730	int i;
1731
1732	for (i = 0; i < 9; i++) {
1733		a[i] = 1;
1734		b[i] = 0;
1735	}
1736
1737	a[9] = 2;
1738	a[10] = 3;
1739	a[11] = 4;
1740	a[12] = 5;
1741	a[13] = 6;
1742	a[14] = 7;
1743	a[15] = 8;
1744	a[16] = 9;
1745	a[17] = 10;
1746	a[18] = 14;
1747	a[19] = 17;
1748	a[20] = 21;
1749	a[21] = 25;
1750	a[22] = 30;
1751	a[23] = 35;
1752	a[24] = 45;
1753	a[25] = 60;
1754	a[26] = 80;
1755	a[27] = 100;
1756	a[28] = 200;
1757	a[29] = 300;
1758	a[30] = 400;
1759	a[31] = 500;
1760
1761	b[9] = 1;
1762	b[10] = 1;
1763	b[11] = 2;
1764	b[12] = 2;
1765	b[13] = 3;
1766	b[14] = 3;
1767	b[15] = 3;
1768	b[16] = 3;
1769	b[17] = 4;
1770	b[18] = 4;
1771	b[19] = 4;
1772	b[20] = 4;
1773	b[21] = 4;
1774	b[22] = 5;
1775	b[23] = 5;
1776	b[24] = 5;
1777	b[25] = 5;
1778	b[26] = 5;
1779	b[27] = 5;
1780	b[28] = 6;
1781	b[29] = 6;
1782	b[30] = 7;
1783	b[31] = 7;
1784}
1785
1786#define INIT_CMD(var, cmd, rd_wr) do { \
1787	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
1788			F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
1789	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
1790} while (0)
1791
1792int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
1793{
1794	u32 cclk_param, cclk_val;
1795	int ret;
1796
1797	/*
1798	 * Ask firmware for the Core Clock since it knows how to translate the
1799	 * Reference Clock ('V2') VPD field into a Core Clock value ...
1800	 */
1801	cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1802		      V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
1803	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1804			      1, &cclk_param, &cclk_val);
1805	if (ret) {
1806		dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
1807			__func__, ret);
1808		return ret;
1809	}
1810
1811	p->cclk = cclk_val;
1812	dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
1813	return 0;
1814}
1815
1816/* serial flash and firmware constants and flash config file constants */
1817enum {
1818	SF_ATTEMPTS = 10,             /* max retries for SF operations */
1819
1820	/* flash command opcodes */
1821	SF_PROG_PAGE    = 2,          /* program page */
1822	SF_WR_DISABLE   = 4,          /* disable writes */
1823	SF_RD_STATUS    = 5,          /* read status register */
1824	SF_WR_ENABLE    = 6,          /* enable writes */
1825	SF_RD_DATA_FAST = 0xb,        /* read flash */
1826	SF_RD_ID        = 0x9f,       /* read ID */
1827	SF_ERASE_SECTOR = 0xd8,       /* erase sector */
1828};
1829
1830/**
1831 * sf1_read - read data from the serial flash
1832 * @adapter: the adapter
1833 * @byte_cnt: number of bytes to read
1834 * @cont: whether another operation will be chained
1835 * @lock: whether to lock SF for PL access only
1836 * @valp: where to store the read data
1837 *
1838 * Reads up to 4 bytes of data from the serial flash.  The location of
1839 * the read needs to be specified prior to calling this by issuing the
1840 * appropriate commands to the serial flash.
1841 */
1842static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1843		    int lock, u32 *valp)
1844{
1845	int ret;
1846
1847	if (!byte_cnt || byte_cnt > 4)
1848		return -EINVAL;
1849	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1850		return -EBUSY;
1851	t4_write_reg(adapter, A_SF_OP,
1852		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
1853	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1854	if (!ret)
1855		*valp = t4_read_reg(adapter, A_SF_DATA);
1856	return ret;
1857}
1858
1859/**
1860 * sf1_write - write data to the serial flash
1861 * @adapter: the adapter
1862 * @byte_cnt: number of bytes to write
1863 * @cont: whether another operation will be chained
1864 * @lock: whether to lock SF for PL access only
1865 * @val: value to write
1866 *
1867 * Writes up to 4 bytes of data to the serial flash.  The location of
1868 * the write needs to be specified prior to calling this by issuing the
1869 * appropriate commands to the serial flash.
1870 */
1871static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1872		     int lock, u32 val)
1873{
1874	if (!byte_cnt || byte_cnt > 4)
1875		return -EINVAL;
1876	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1877		return -EBUSY;
1878	t4_write_reg(adapter, A_SF_DATA, val);
1879	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
1880		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
1881	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1882}
1883
1884/**
1885 * t4_read_flash - read words from serial flash
1886 * @adapter: the adapter
1887 * @addr: the start address for the read
1888 * @nwords: how many 32-bit words to read
1889 * @data: where to store the read data
1890 * @byte_oriented: whether to store data as bytes or as words
1891 *
1892 * Read the specified number of 32-bit words from the serial flash.
1893 * If @byte_oriented is set the read data is stored as a byte array
1894 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1895 * natural endianness.
1896 */
1897int t4_read_flash(struct adapter *adapter, unsigned int addr,
1898		  unsigned int nwords, u32 *data, int byte_oriented)
1899{
1900	int ret;
1901
1902	if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
1903	    (addr & 3))
1904		return -EINVAL;
1905
1906	addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
1907
1908	ret = sf1_write(adapter, 4, 1, 0, addr);
1909	if (ret != 0)
1910		return ret;
1911
1912	ret = sf1_read(adapter, 1, 1, 0, data);
1913	if (ret != 0)
1914		return ret;
1915
1916	for ( ; nwords; nwords--, data++) {
1917		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
1918		if (nwords == 1)
1919			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
1920		if (ret)
1921			return ret;
1922		if (byte_oriented)
1923			*data = cpu_to_be32(*data);
1924	}
1925	return 0;
1926}
1927
1928/**
1929 * t4_get_fw_version - read the firmware version
1930 * @adapter: the adapter
1931 * @vers: where to place the version
1932 *
1933 * Reads the FW version from flash.
1934 */
1935int t4_get_fw_version(struct adapter *adapter, u32 *vers)
1936{
1937	return t4_read_flash(adapter, FLASH_FW_START +
1938			     offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
1939}
1940
1941/**
1942 * t4_get_tp_version - read the TP microcode version
1943 * @adapter: the adapter
1944 * @vers: where to place the version
1945 *
1946 * Reads the TP microcode version from flash.
1947 */
1948int t4_get_tp_version(struct adapter *adapter, u32 *vers)
1949{
1950	return t4_read_flash(adapter, FLASH_FW_START +
1951			     offsetof(struct fw_hdr, tp_microcode_ver),
1952			     1, vers, 0);
1953}
1954
1955#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1956		FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1957		FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
1958
1959/**
1960 * t4_link_l1cfg - apply link configuration to MAC/PHY
1961 * @phy: the PHY to setup
1962 * @mac: the MAC to setup
1963 * @lc: the requested link configuration
1964 *
1965 * Set up a port's MAC and PHY according to a desired link configuration.
1966 * - If the PHY can auto-negotiate first decide what to advertise, then
1967 *   enable/disable auto-negotiation as desired, and reset.
1968 * - If the PHY does not auto-negotiate just reset it.
1969 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1970 *   otherwise do it later based on the outcome of auto-negotiation.
1971 */
1972int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1973		  struct link_config *lc)
1974{
1975	struct fw_port_cmd c;
1976	unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
1977
1978	lc->link_ok = 0;
1979	if (lc->requested_fc & PAUSE_RX)
1980		fc |= FW_PORT_CAP_FC_RX;
1981	if (lc->requested_fc & PAUSE_TX)
1982		fc |= FW_PORT_CAP_FC_TX;
1983
1984	memset(&c, 0, sizeof(c));
1985	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
1986				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
1987				     V_FW_PORT_CMD_PORTID(port));
1988	c.action_to_len16 =
1989		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1990			    FW_LEN16(c));
1991
1992	if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1993		c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
1994					     fc);
1995		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1996	} else if (lc->autoneg == AUTONEG_DISABLE) {
1997		c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
1998		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1999	} else {
2000		c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2001	}
2002
2003	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2004}
2005
2006/**
2007 * t4_flash_cfg_addr - return the address of the flash configuration file
2008 * @adapter: the adapter
2009 *
2010 * Return the address within the flash where the Firmware Configuration
2011 * File is stored, or an error if the device FLASH is too small to contain
2012 * a Firmware Configuration File.
2013 */
2014int t4_flash_cfg_addr(struct adapter *adapter)
2015{
2016	/*
2017	 * If the device FLASH isn't large enough to hold a Firmware
2018	 * Configuration File, return an error.
2019	 */
2020	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2021		return -ENOSPC;
2022
2023	return FLASH_CFG_START;
2024}
2025
2026#define PF_INTR_MASK (F_PFSW | F_PFCIM)
2027
2028/**
2029 * t4_intr_enable - enable interrupts
2030 * @adapter: the adapter whose interrupts should be enabled
2031 *
2032 * Enable PF-specific interrupts for the calling function and the top-level
2033 * interrupt concentrator for global interrupts.  Interrupts are already
2034 * enabled at each module, here we just enable the roots of the interrupt
2035 * hierarchies.
2036 *
2037 * Note: this function should be called only when the driver manages
2038 * non PF-specific interrupts from the various HW modules.  Only one PCI
2039 * function at a time should be doing this.
2040 */
2041void t4_intr_enable(struct adapter *adapter)
2042{
2043	u32 val = 0;
2044	u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2045
2046	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2047		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2048	t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2049		     F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2050		     F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2051		     F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2052		     F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2053		     F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2054		     F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2055	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2056	t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2057}
2058
2059/**
2060 * t4_intr_disable - disable interrupts
2061 * @adapter: the adapter whose interrupts should be disabled
2062 *
2063 * Disable interrupts.  We only disable the top-level interrupt
2064 * concentrators.  The caller must be a PCI function managing global
2065 * interrupts.
2066 */
2067void t4_intr_disable(struct adapter *adapter)
2068{
2069	u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2070
2071	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2072	t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2073}
2074
2075/**
2076 * t4_get_port_type_description - return Port Type string description
2077 * @port_type: firmware Port Type enumeration
2078 */
2079const char *t4_get_port_type_description(enum fw_port_type port_type)
2080{
2081	static const char * const port_type_description[] = {
2082		"Fiber_XFI",
2083		"Fiber_XAUI",
2084		"BT_SGMII",
2085		"BT_XFI",
2086		"BT_XAUI",
2087		"KX4",
2088		"CX4",
2089		"KX",
2090		"KR",
2091		"SFP",
2092		"BP_AP",
2093		"BP4_AP",
2094		"QSFP_10G",
2095		"QSA",
2096		"QSFP",
2097		"BP40_BA",
2098	};
2099
2100	if (port_type < ARRAY_SIZE(port_type_description))
2101		return port_type_description[port_type];
2102	return "UNKNOWN";
2103}
2104
2105/**
2106 * t4_get_mps_bg_map - return the buffer groups associated with a port
2107 * @adap: the adapter
2108 * @idx: the port index
2109 *
2110 * Returns a bitmap indicating which MPS buffer groups are associated
2111 * with the given port.  Bit i is set if buffer group i is used by the
2112 * port.
2113 */
2114unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2115{
2116	u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2117
2118	if (n == 0)
2119		return idx == 0 ? 0xf : 0;
2120	if (n == 1)
2121		return idx < 2 ? (3 << (2 * idx)) : 0;
2122	return 1 << idx;
2123}
2124
2125/**
2126 * t4_get_port_stats - collect port statistics
2127 * @adap: the adapter
2128 * @idx: the port index
2129 * @p: the stats structure to fill
2130 *
2131 * Collect statistics related to the given port from HW.
2132 */
2133void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2134{
2135	u32 bgmap = t4_get_mps_bg_map(adap, idx);
2136
2137#define GET_STAT(name) \
2138	t4_read_reg64(adap, \
2139		      (is_t4(adap->params.chip) ? \
2140		       PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2141		       T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2142#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2143
2144	p->tx_octets           = GET_STAT(TX_PORT_BYTES);
2145	p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
2146	p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
2147	p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
2148	p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
2149	p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
2150	p->tx_frames_64        = GET_STAT(TX_PORT_64B);
2151	p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
2152	p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
2153	p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
2154	p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
2155	p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2156	p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
2157	p->tx_drop             = GET_STAT(TX_PORT_DROP);
2158	p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
2159	p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
2160	p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
2161	p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
2162	p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
2163	p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
2164	p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
2165	p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
2166	p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
2167
2168	p->rx_octets           = GET_STAT(RX_PORT_BYTES);
2169	p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
2170	p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
2171	p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
2172	p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
2173	p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
2174	p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2175	p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
2176	p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
2177	p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
2178	p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
2179	p->rx_frames_64        = GET_STAT(RX_PORT_64B);
2180	p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
2181	p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
2182	p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
2183	p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
2184	p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2185	p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
2186	p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
2187	p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
2188	p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
2189	p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
2190	p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
2191	p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
2192	p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
2193	p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
2194	p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
2195	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2196	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2197	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2198	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2199	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2200	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2201	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2202	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2203
2204#undef GET_STAT
2205#undef GET_STAT_COM
2206}
2207
2208/**
2209 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2210 * @adap: The adapter
2211 * @idx: The port
2212 * @stats: Current stats to fill
2213 * @offset: Previous stats snapshot
2214 */
2215void t4_get_port_stats_offset(struct adapter *adap, int idx,
2216			      struct port_stats *stats,
2217			      struct port_stats *offset)
2218{
2219	u64 *s, *o;
2220	unsigned int i;
2221
2222	t4_get_port_stats(adap, idx, stats);
2223	for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2224	     i < (sizeof(struct port_stats) / sizeof(u64));
2225	     i++, s++, o++)
2226		*s -= *o;
2227}
2228
2229/**
2230 * t4_clr_port_stats - clear port statistics
2231 * @adap: the adapter
2232 * @idx: the port index
2233 *
2234 * Clear HW statistics for the given port.
2235 */
2236void t4_clr_port_stats(struct adapter *adap, int idx)
2237{
2238	unsigned int i;
2239	u32 bgmap = t4_get_mps_bg_map(adap, idx);
2240	u32 port_base_addr;
2241
2242	if (is_t4(adap->params.chip))
2243		port_base_addr = PORT_BASE(idx);
2244	else
2245		port_base_addr = T5_PORT_BASE(idx);
2246
2247	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2248	     i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2249		t4_write_reg(adap, port_base_addr + i, 0);
2250	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2251	     i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2252		t4_write_reg(adap, port_base_addr + i, 0);
2253	for (i = 0; i < 4; i++)
2254		if (bgmap & (1 << i)) {
2255			t4_write_reg(adap,
2256				     A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2257				     i * 8, 0);
2258			t4_write_reg(adap,
2259				     A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2260				     i * 8, 0);
2261		}
2262}
2263
2264/**
2265 * t4_fw_hello - establish communication with FW
2266 * @adap: the adapter
2267 * @mbox: mailbox to use for the FW command
2268 * @evt_mbox: mailbox to receive async FW events
2269 * @master: specifies the caller's willingness to be the device master
2270 * @state: returns the current device state (if non-NULL)
2271 *
2272 * Issues a command to establish communication with FW.  Returns either
2273 * an error (negative integer) or the mailbox of the Master PF.
2274 */
2275int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2276		enum dev_master master, enum dev_state *state)
2277{
2278	int ret;
2279	struct fw_hello_cmd c;
2280	u32 v;
2281	unsigned int master_mbox;
2282	int retries = FW_CMD_HELLO_RETRIES;
2283
2284retry:
2285	memset(&c, 0, sizeof(c));
2286	INIT_CMD(c, HELLO, WRITE);
2287	c.err_to_clearinit = cpu_to_be32(
2288			V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2289			V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2290			V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2291						M_FW_HELLO_CMD_MBMASTER) |
2292			V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2293			V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2294			F_FW_HELLO_CMD_CLEARINIT);
2295
2296	/*
2297	 * Issue the HELLO command to the firmware.  If it's not successful
2298	 * but indicates that we got a "busy" or "timeout" condition, retry
2299	 * the HELLO until we exhaust our retry limit.  If we do exceed our
2300	 * retry limit, check to see if the firmware left us any error
2301	 * information and report that if so ...
2302	 */
2303	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2304	if (ret != FW_SUCCESS) {
2305		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2306			goto retry;
2307		if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2308			t4_report_fw_error(adap);
2309		return ret;
2310	}
2311
2312	v = be32_to_cpu(c.err_to_clearinit);
2313	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2314	if (state) {
2315		if (v & F_FW_HELLO_CMD_ERR)
2316			*state = DEV_STATE_ERR;
2317		else if (v & F_FW_HELLO_CMD_INIT)
2318			*state = DEV_STATE_INIT;
2319		else
2320			*state = DEV_STATE_UNINIT;
2321	}
2322
2323	/*
2324	 * If we're not the Master PF then we need to wait around for the
2325	 * Master PF Driver to finish setting up the adapter.
2326	 *
2327	 * Note that we also do this wait if we're a non-Master-capable PF and
2328	 * there is no current Master PF; a Master PF may show up momentarily
2329	 * and we wouldn't want to fail pointlessly.  (This can happen when an
2330	 * OS loads lots of different drivers rapidly at the same time).  In
2331	 * this case, the Master PF returned by the firmware will be
2332	 * M_PCIE_FW_MASTER so the test below will work ...
2333	 */
2334	if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2335	    master_mbox != mbox) {
2336		int waiting = FW_CMD_HELLO_TIMEOUT;
2337
2338		/*
2339		 * Wait for the firmware to either indicate an error or
2340		 * initialized state.  If we see either of these we bail out
2341		 * and report the issue to the caller.  If we exhaust the
2342		 * "hello timeout" and we haven't exhausted our retries, try
2343		 * again.  Otherwise bail with a timeout error.
2344		 */
2345		for (;;) {
2346			u32 pcie_fw;
2347
2348			msleep(50);
2349			waiting -= 50;
2350
2351			/*
2352			 * If neither Error nor Initialialized are indicated
2353			 * by the firmware keep waiting till we exaust our
2354			 * timeout ... and then retry if we haven't exhausted
2355			 * our retries ...
2356			 */
2357			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2358			if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2359				if (waiting <= 0) {
2360					if (retries-- > 0)
2361						goto retry;
2362
2363					return -ETIMEDOUT;
2364				}
2365				continue;
2366			}
2367
2368			/*
2369			 * We either have an Error or Initialized condition
2370			 * report errors preferentially.
2371			 */
2372			if (state) {
2373				if (pcie_fw & F_PCIE_FW_ERR)
2374					*state = DEV_STATE_ERR;
2375				else if (pcie_fw & F_PCIE_FW_INIT)
2376					*state = DEV_STATE_INIT;
2377			}
2378
2379			/*
2380			 * If we arrived before a Master PF was selected and
2381			 * there's not a valid Master PF, grab its identity
2382			 * for our caller.
2383			 */
2384			if (master_mbox == M_PCIE_FW_MASTER &&
2385			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
2386				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2387			break;
2388		}
2389	}
2390
2391	return master_mbox;
2392}
2393
2394/**
2395 * t4_fw_bye - end communication with FW
2396 * @adap: the adapter
2397 * @mbox: mailbox to use for the FW command
2398 *
2399 * Issues a command to terminate communication with FW.
2400 */
2401int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2402{
2403	struct fw_bye_cmd c;
2404
2405	memset(&c, 0, sizeof(c));
2406	INIT_CMD(c, BYE, WRITE);
2407	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2408}
2409
2410/**
2411 * t4_fw_reset - issue a reset to FW
2412 * @adap: the adapter
2413 * @mbox: mailbox to use for the FW command
2414 * @reset: specifies the type of reset to perform
2415 *
2416 * Issues a reset command of the specified type to FW.
2417 */
2418int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2419{
2420	struct fw_reset_cmd c;
2421
2422	memset(&c, 0, sizeof(c));
2423	INIT_CMD(c, RESET, WRITE);
2424	c.val = cpu_to_be32(reset);
2425	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2426}
2427
2428/**
2429 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2430 * @adap: the adapter
2431 * @mbox: mailbox to use for the FW RESET command (if desired)
2432 * @force: force uP into RESET even if FW RESET command fails
2433 *
2434 * Issues a RESET command to firmware (if desired) with a HALT indication
2435 * and then puts the microprocessor into RESET state.  The RESET command
2436 * will only be issued if a legitimate mailbox is provided (mbox <=
2437 * M_PCIE_FW_MASTER).
2438 *
2439 * This is generally used in order for the host to safely manipulate the
2440 * adapter without fear of conflicting with whatever the firmware might
2441 * be doing.  The only way out of this state is to RESTART the firmware
2442 * ...
2443 */
2444int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2445{
2446	int ret = 0;
2447
2448	/*
2449	 * If a legitimate mailbox is provided, issue a RESET command
2450	 * with a HALT indication.
2451	 */
2452	if (mbox <= M_PCIE_FW_MASTER) {
2453		struct fw_reset_cmd c;
2454
2455		memset(&c, 0, sizeof(c));
2456		INIT_CMD(c, RESET, WRITE);
2457		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
2458		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
2459		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2460	}
2461
2462	/*
2463	 * Normally we won't complete the operation if the firmware RESET
2464	 * command fails but if our caller insists we'll go ahead and put the
2465	 * uP into RESET.  This can be useful if the firmware is hung or even
2466	 * missing ...  We'll have to take the risk of putting the uP into
2467	 * RESET without the cooperation of firmware in that case.
2468	 *
2469	 * We also force the firmware's HALT flag to be on in case we bypassed
2470	 * the firmware RESET command above or we're dealing with old firmware
2471	 * which doesn't have the HALT capability.  This will serve as a flag
2472	 * for the incoming firmware to know that it's coming out of a HALT
2473	 * rather than a RESET ... if it's new enough to understand that ...
2474	 */
2475	if (ret == 0 || force) {
2476		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
2477		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
2478				 F_PCIE_FW_HALT);
2479	}
2480
2481	/*
2482	 * And we always return the result of the firmware RESET command
2483	 * even when we force the uP into RESET ...
2484	 */
2485	return ret;
2486}
2487
2488/**
2489 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2490 * @adap: the adapter
2491 * @mbox: mailbox to use for the FW RESET command (if desired)
2492 * @reset: if we want to do a RESET to restart things
2493 *
2494 * Restart firmware previously halted by t4_fw_halt().  On successful
2495 * return the previous PF Master remains as the new PF Master and there
2496 * is no need to issue a new HELLO command, etc.
2497 *
2498 * We do this in two ways:
2499 *
2500 * 1. If we're dealing with newer firmware we'll simply want to take
2501 *    the chip's microprocessor out of RESET.  This will cause the
2502 *    firmware to start up from its start vector.  And then we'll loop
2503 *    until the firmware indicates it's started again (PCIE_FW.HALT
2504 *    reset to 0) or we timeout.
2505 *
2506 * 2. If we're dealing with older firmware then we'll need to RESET
2507 *    the chip since older firmware won't recognize the PCIE_FW.HALT
2508 *    flag and automatically RESET itself on startup.
2509 */
2510int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2511{
2512	if (reset) {
2513		/*
2514		 * Since we're directing the RESET instead of the firmware
2515		 * doing it automatically, we need to clear the PCIE_FW.HALT
2516		 * bit.
2517		 */
2518		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
2519
2520		/*
2521		 * If we've been given a valid mailbox, first try to get the
2522		 * firmware to do the RESET.  If that works, great and we can
2523		 * return success.  Otherwise, if we haven't been given a
2524		 * valid mailbox or the RESET command failed, fall back to
2525		 * hitting the chip with a hammer.
2526		 */
2527		if (mbox <= M_PCIE_FW_MASTER) {
2528			t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2529			msleep(100);
2530			if (t4_fw_reset(adap, mbox,
2531					F_PIORST | F_PIORSTMODE) == 0)
2532				return 0;
2533		}
2534
2535		t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
2536		msleep(2000);
2537	} else {
2538		int ms;
2539
2540		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2541		for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2542			if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
2543				return FW_SUCCESS;
2544			msleep(100);
2545			ms += 100;
2546		}
2547		return -ETIMEDOUT;
2548	}
2549	return 0;
2550}
2551
2552/**
2553 * t4_fixup_host_params_compat - fix up host-dependent parameters
2554 * @adap: the adapter
2555 * @page_size: the host's Base Page Size
2556 * @cache_line_size: the host's Cache Line Size
2557 * @chip_compat: maintain compatibility with designated chip
2558 *
2559 * Various registers in the chip contain values which are dependent on the
2560 * host's Base Page and Cache Line Sizes.  This function will fix all of
2561 * those registers with the appropriate values as passed in ...
2562 *
2563 * @chip_compat is used to limit the set of changes that are made
2564 * to be compatible with the indicated chip release.  This is used by
2565 * drivers to maintain compatibility with chip register settings when
2566 * the drivers haven't [yet] been updated with new chip support.
2567 */
2568int t4_fixup_host_params_compat(struct adapter *adap,
2569				unsigned int page_size,
2570				unsigned int cache_line_size,
2571				enum chip_type chip_compat)
2572{
2573	unsigned int page_shift = cxgbe_fls(page_size) - 1;
2574	unsigned int sge_hps = page_shift - 10;
2575	unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2576	unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2577	unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
2578
2579	t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
2580		     V_HOSTPAGESIZEPF0(sge_hps) |
2581		     V_HOSTPAGESIZEPF1(sge_hps) |
2582		     V_HOSTPAGESIZEPF2(sge_hps) |
2583		     V_HOSTPAGESIZEPF3(sge_hps) |
2584		     V_HOSTPAGESIZEPF4(sge_hps) |
2585		     V_HOSTPAGESIZEPF5(sge_hps) |
2586		     V_HOSTPAGESIZEPF6(sge_hps) |
2587		     V_HOSTPAGESIZEPF7(sge_hps));
2588
2589	if (is_t4(adap->params.chip) || is_t4(chip_compat))
2590		t4_set_reg_field(adap, A_SGE_CONTROL,
2591				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2592				 F_EGRSTATUSPAGESIZE,
2593				 V_INGPADBOUNDARY(fl_align_log -
2594						  X_INGPADBOUNDARY_SHIFT) |
2595				V_EGRSTATUSPAGESIZE(stat_len != 64));
2596	else {
2597		/*
2598		 * T5 introduced the separation of the Free List Padding and
2599		 * Packing Boundaries.  Thus, we can select a smaller Padding
2600		 * Boundary to avoid uselessly chewing up PCIe Link and Memory
2601		 * Bandwidth, and use a Packing Boundary which is large enough
2602		 * to avoid false sharing between CPUs, etc.
2603		 *
2604		 * For the PCI Link, the smaller the Padding Boundary the
2605		 * better.  For the Memory Controller, a smaller Padding
2606		 * Boundary is better until we cross under the Memory Line
2607		 * Size (the minimum unit of transfer to/from Memory).  If we
2608		 * have a Padding Boundary which is smaller than the Memory
2609		 * Line Size, that'll involve a Read-Modify-Write cycle on the
2610		 * Memory Controller which is never good.  For T5 the smallest
2611		 * Padding Boundary which we can select is 32 bytes which is
2612		 * larger than any known Memory Controller Line Size so we'll
2613		 * use that.
2614		 */
2615
2616		/*
2617		 * N.B. T5 has a different interpretation of the "0" value for
2618		 * the Packing Boundary.  This corresponds to 16 bytes instead
2619		 * of the expected 32 bytes.  We never have a Packing Boundary
2620		 * less than 32 bytes so we can't use that special value but
2621		 * on the other hand, if we wanted 32 bytes, the best we can
2622		 * really do is 64 bytes ...
2623		 */
2624		if (fl_align <= 32) {
2625			fl_align = 64;
2626			fl_align_log = 6;
2627		}
2628		t4_set_reg_field(adap, A_SGE_CONTROL,
2629				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2630				 F_EGRSTATUSPAGESIZE,
2631				 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
2632				 V_EGRSTATUSPAGESIZE(stat_len != 64));
2633		t4_set_reg_field(adap, A_SGE_CONTROL2,
2634				 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
2635				 V_INGPACKBOUNDARY(fl_align_log -
2636						   X_INGPACKBOUNDARY_SHIFT));
2637	}
2638
2639	/*
2640	 * Adjust various SGE Free List Host Buffer Sizes.
2641	 *
2642	 * The first four entries are:
2643	 *
2644	 *   0: Host Page Size
2645	 *   1: 64KB
2646	 *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2647	 *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2648	 *
2649	 * For the single-MTU buffers in unpacked mode we need to include
2650	 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2651	 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2652	 * Padding boundary.  All of these are accommodated in the Factory
2653	 * Default Firmware Configuration File but we need to adjust it for
2654	 * this host's cache line size.
2655	 */
2656	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
2657	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
2658		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
2659		     & ~(fl_align - 1));
2660	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
2661		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
2662		     & ~(fl_align - 1));
2663
2664	t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
2665
2666	return 0;
2667}
2668
2669/**
2670 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
2671 * @adap: the adapter
2672 * @page_size: the host's Base Page Size
2673 * @cache_line_size: the host's Cache Line Size
2674 *
2675 * Various registers in T4 contain values which are dependent on the
2676 * host's Base Page and Cache Line Sizes.  This function will fix all of
2677 * those registers with the appropriate values as passed in ...
2678 *
2679 * This routine makes changes which are compatible with T4 chips.
2680 */
2681int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2682			 unsigned int cache_line_size)
2683{
2684	return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
2685					   T4_LAST_REV);
2686}
2687
2688/**
2689 * t4_fw_initialize - ask FW to initialize the device
2690 * @adap: the adapter
2691 * @mbox: mailbox to use for the FW command
2692 *
2693 * Issues a command to FW to partially initialize the device.  This
2694 * performs initialization that generally doesn't depend on user input.
2695 */
2696int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2697{
2698	struct fw_initialize_cmd c;
2699
2700	memset(&c, 0, sizeof(c));
2701	INIT_CMD(c, INITIALIZE, WRITE);
2702	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2703}
2704
2705/**
2706 * t4_query_params_rw - query FW or device parameters
2707 * @adap: the adapter
2708 * @mbox: mailbox to use for the FW command
2709 * @pf: the PF
2710 * @vf: the VF
2711 * @nparams: the number of parameters
2712 * @params: the parameter names
2713 * @val: the parameter values
2714 * @rw: Write and read flag
2715 *
2716 * Reads the value of FW or device parameters.  Up to 7 parameters can be
2717 * queried at once.
2718 */
2719static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
2720			      unsigned int pf, unsigned int vf,
2721			      unsigned int nparams, const u32 *params,
2722			      u32 *val, int rw)
2723{
2724	unsigned int i;
2725	int ret;
2726	struct fw_params_cmd c;
2727	__be32 *p = &c.param[0].mnem;
2728
2729	if (nparams > 7)
2730		return -EINVAL;
2731
2732	memset(&c, 0, sizeof(c));
2733	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2734				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
2735				  V_FW_PARAMS_CMD_PFN(pf) |
2736				  V_FW_PARAMS_CMD_VFN(vf));
2737	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2738
2739	for (i = 0; i < nparams; i++) {
2740		*p++ = cpu_to_be32(*params++);
2741		if (rw)
2742			*p = cpu_to_be32(*(val + i));
2743		p++;
2744	}
2745
2746	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2747	if (ret == 0)
2748		for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2749			*val++ = be32_to_cpu(*p);
2750	return ret;
2751}
2752
2753int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2754		    unsigned int vf, unsigned int nparams, const u32 *params,
2755		    u32 *val)
2756{
2757	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
2758}
2759
2760/**
2761 * t4_set_params_timeout - sets FW or device parameters
2762 * @adap: the adapter
2763 * @mbox: mailbox to use for the FW command
2764 * @pf: the PF
2765 * @vf: the VF
2766 * @nparams: the number of parameters
2767 * @params: the parameter names
2768 * @val: the parameter values
2769 * @timeout: the timeout time
2770 *
2771 * Sets the value of FW or device parameters.  Up to 7 parameters can be
2772 * specified at once.
2773 */
2774int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
2775			  unsigned int pf, unsigned int vf,
2776			  unsigned int nparams, const u32 *params,
2777			  const u32 *val, int timeout)
2778{
2779	struct fw_params_cmd c;
2780	__be32 *p = &c.param[0].mnem;
2781
2782	if (nparams > 7)
2783		return -EINVAL;
2784
2785	memset(&c, 0, sizeof(c));
2786	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2787				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2788				  V_FW_PARAMS_CMD_PFN(pf) |
2789				  V_FW_PARAMS_CMD_VFN(vf));
2790	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2791
2792	while (nparams--) {
2793		*p++ = cpu_to_be32(*params++);
2794		*p++ = cpu_to_be32(*val++);
2795	}
2796
2797	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
2798}
2799
2800int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2801		  unsigned int vf, unsigned int nparams, const u32 *params,
2802		  const u32 *val)
2803{
2804	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
2805				     FW_CMD_MAX_TIMEOUT);
2806}
2807
2808/**
2809 * t4_alloc_vi_func - allocate a virtual interface
2810 * @adap: the adapter
2811 * @mbox: mailbox to use for the FW command
2812 * @port: physical port associated with the VI
2813 * @pf: the PF owning the VI
2814 * @vf: the VF owning the VI
2815 * @nmac: number of MAC addresses needed (1 to 5)
2816 * @mac: the MAC addresses of the VI
2817 * @rss_size: size of RSS table slice associated with this VI
2818 * @portfunc: which Port Application Function MAC Address is desired
2819 * @idstype: Intrusion Detection Type
2820 *
2821 * Allocates a virtual interface for the given physical port.  If @mac is
2822 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2823 * @mac should be large enough to hold @nmac Ethernet addresses, they are
2824 * stored consecutively so the space needed is @nmac * 6 bytes.
2825 * Returns a negative error number or the non-negative VI id.
2826 */
2827int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
2828		     unsigned int port, unsigned int pf, unsigned int vf,
2829		     unsigned int nmac, u8 *mac, unsigned int *rss_size,
2830		     unsigned int portfunc, unsigned int idstype)
2831{
2832	int ret;
2833	struct fw_vi_cmd c;
2834
2835	memset(&c, 0, sizeof(c));
2836	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2837				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2838				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
2839	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
2840	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
2841				     V_FW_VI_CMD_FUNC(portfunc));
2842	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
2843	c.nmac = nmac - 1;
2844
2845	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2846	if (ret)
2847		return ret;
2848
2849	if (mac) {
2850		memcpy(mac, c.mac, sizeof(c.mac));
2851		switch (nmac) {
2852		case 5:
2853			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2854			/* FALLTHROUGH */
2855		case 4:
2856			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2857			/* FALLTHROUGH */
2858		case 3:
2859			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2860			/* FALLTHROUGH */
2861		case 2:
2862			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
2863			/* FALLTHROUGH */
2864		}
2865	}
2866	if (rss_size)
2867		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
2868	return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
2869}
2870
2871/**
2872 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
2873 * @adap: the adapter
2874 * @mbox: mailbox to use for the FW command
2875 * @port: physical port associated with the VI
2876 * @pf: the PF owning the VI
2877 * @vf: the VF owning the VI
2878 * @nmac: number of MAC addresses needed (1 to 5)
2879 * @mac: the MAC addresses of the VI
2880 * @rss_size: size of RSS table slice associated with this VI
2881 *
2882 * Backwards compatible and convieniance routine to allocate a Virtual
2883 * Interface with a Ethernet Port Application Function and Intrustion
2884 * Detection System disabled.
2885 */
2886int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2887		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2888		unsigned int *rss_size)
2889{
2890	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
2891				FW_VI_FUNC_ETH, 0);
2892}
2893
2894/**
2895 * t4_free_vi - free a virtual interface
2896 * @adap: the adapter
2897 * @mbox: mailbox to use for the FW command
2898 * @pf: the PF owning the VI
2899 * @vf: the VF owning the VI
2900 * @viid: virtual interface identifiler
2901 *
2902 * Free a previously allocated virtual interface.
2903 */
2904int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2905	       unsigned int vf, unsigned int viid)
2906{
2907	struct fw_vi_cmd c;
2908
2909	memset(&c, 0, sizeof(c));
2910	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2911				  F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
2912				  V_FW_VI_CMD_VFN(vf));
2913	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
2914	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
2915
2916	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2917}
2918
2919/**
2920 * t4_set_rxmode - set Rx properties of a virtual interface
2921 * @adap: the adapter
2922 * @mbox: mailbox to use for the FW command
2923 * @viid: the VI id
2924 * @mtu: the new MTU or -1
2925 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2926 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2927 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2928 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
2929 *          -1 no change
2930 * @sleep_ok: if true we may sleep while awaiting command completion
2931 *
2932 * Sets Rx properties of a virtual interface.
2933 */
2934int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2935		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
2936		  bool sleep_ok)
2937{
2938	struct fw_vi_rxmode_cmd c;
2939
2940	/* convert to FW values */
2941	if (mtu < 0)
2942		mtu = M_FW_VI_RXMODE_CMD_MTU;
2943	if (promisc < 0)
2944		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
2945	if (all_multi < 0)
2946		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
2947	if (bcast < 0)
2948		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
2949	if (vlanex < 0)
2950		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
2951
2952	memset(&c, 0, sizeof(c));
2953	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
2954				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2955				   V_FW_VI_RXMODE_CMD_VIID(viid));
2956	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2957	c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
2958			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2959			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2960			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
2961			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
2962	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2963}
2964
2965/**
2966 * t4_change_mac - modifies the exact-match filter for a MAC address
2967 * @adap: the adapter
2968 * @mbox: mailbox to use for the FW command
2969 * @viid: the VI id
2970 * @idx: index of existing filter for old value of MAC address, or -1
2971 * @addr: the new MAC address value
2972 * @persist: whether a new MAC allocation should be persistent
2973 * @add_smt: if true also add the address to the HW SMT
2974 *
2975 * Modifies an exact-match filter and sets it to the new MAC address if
2976 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
2977 * latter case the address is added persistently if @persist is %true.
2978 *
2979 * Note that in general it is not possible to modify the value of a given
2980 * filter so the generic way to modify an address filter is to free the one
2981 * being used by the old address value and allocate a new filter for the
2982 * new address value.
2983 *
2984 * Returns a negative error number or the index of the filter with the new
2985 * MAC value.  Note that this index may differ from @idx.
2986 */
2987int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2988		  int idx, const u8 *addr, bool persist, bool add_smt)
2989{
2990	int ret, mode;
2991	struct fw_vi_mac_cmd c;
2992	struct fw_vi_mac_exact *p = c.u.exact;
2993	int max_mac_addr = adap->params.arch.mps_tcam_size;
2994
2995	if (idx < 0)                             /* new allocation */
2996		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
2997	mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
2998
2999	memset(&c, 0, sizeof(c));
3000	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3001				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3002				   V_FW_VI_MAC_CMD_VIID(viid));
3003	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3004	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3005				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3006				      V_FW_VI_MAC_CMD_IDX(idx));
3007	memcpy(p->macaddr, addr, sizeof(p->macaddr));
3008
3009	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3010	if (ret == 0) {
3011		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3012		if (ret >= max_mac_addr)
3013			ret = -ENOMEM;
3014	}
3015	return ret;
3016}
3017
3018/**
3019 * t4_enable_vi_params - enable/disable a virtual interface
3020 * @adap: the adapter
3021 * @mbox: mailbox to use for the FW command
3022 * @viid: the VI id
3023 * @rx_en: 1=enable Rx, 0=disable Rx
3024 * @tx_en: 1=enable Tx, 0=disable Tx
3025 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3026 *
3027 * Enables/disables a virtual interface.  Note that setting DCB Enable
3028 * only makes sense when enabling a Virtual Interface ...
3029 */
3030int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3031			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3032{
3033	struct fw_vi_enable_cmd c;
3034
3035	memset(&c, 0, sizeof(c));
3036	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3037				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3038				   V_FW_VI_ENABLE_CMD_VIID(viid));
3039	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3040				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3041				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3042				     FW_LEN16(c));
3043	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3044}
3045
3046/**
3047 * t4_enable_vi - enable/disable a virtual interface
3048 * @adap: the adapter
3049 * @mbox: mailbox to use for the FW command
3050 * @viid: the VI id
3051 * @rx_en: 1=enable Rx, 0=disable Rx
3052 * @tx_en: 1=enable Tx, 0=disable Tx
3053 *
3054 * Enables/disables a virtual interface.  Note that setting DCB Enable
3055 * only makes sense when enabling a Virtual Interface ...
3056 */
3057int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3058		 bool rx_en, bool tx_en)
3059{
3060	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3061}
3062
3063/**
3064 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3065 * @adap: the adapter
3066 * @mbox: mailbox to use for the FW command
3067 * @start: %true to enable the queues, %false to disable them
3068 * @pf: the PF owning the queues
3069 * @vf: the VF owning the queues
3070 * @iqid: ingress queue id
3071 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3072 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3073 *
3074 * Starts or stops an ingress queue and its associated FLs, if any.
3075 */
3076int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3077		     unsigned int pf, unsigned int vf, unsigned int iqid,
3078		     unsigned int fl0id, unsigned int fl1id)
3079{
3080	struct fw_iq_cmd c;
3081
3082	memset(&c, 0, sizeof(c));
3083	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3084				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3085				  V_FW_IQ_CMD_VFN(vf));
3086	c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3087				       V_FW_IQ_CMD_IQSTOP(!start) |
3088				       FW_LEN16(c));
3089	c.iqid = cpu_to_be16(iqid);
3090	c.fl0id = cpu_to_be16(fl0id);
3091	c.fl1id = cpu_to_be16(fl1id);
3092	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3093}
3094
3095/**
3096 * t4_iq_free - free an ingress queue and its FLs
3097 * @adap: the adapter
3098 * @mbox: mailbox to use for the FW command
3099 * @pf: the PF owning the queues
3100 * @vf: the VF owning the queues
3101 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3102 * @iqid: ingress queue id
3103 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3104 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3105 *
3106 * Frees an ingress queue and its associated FLs, if any.
3107 */
3108int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3109	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
3110	       unsigned int fl0id, unsigned int fl1id)
3111{
3112	struct fw_iq_cmd c;
3113
3114	memset(&c, 0, sizeof(c));
3115	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3116				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3117				  V_FW_IQ_CMD_VFN(vf));
3118	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3119	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3120	c.iqid = cpu_to_be16(iqid);
3121	c.fl0id = cpu_to_be16(fl0id);
3122	c.fl1id = cpu_to_be16(fl1id);
3123	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3124}
3125
3126/**
3127 * t4_eth_eq_free - free an Ethernet egress queue
3128 * @adap: the adapter
3129 * @mbox: mailbox to use for the FW command
3130 * @pf: the PF owning the queue
3131 * @vf: the VF owning the queue
3132 * @eqid: egress queue id
3133 *
3134 * Frees an Ethernet egress queue.
3135 */
3136int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3137		   unsigned int vf, unsigned int eqid)
3138{
3139	struct fw_eq_eth_cmd c;
3140
3141	memset(&c, 0, sizeof(c));
3142	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3143				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3144				  V_FW_EQ_ETH_CMD_PFN(pf) |
3145				  V_FW_EQ_ETH_CMD_VFN(vf));
3146	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3147	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3148	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3149}
3150
3151/**
3152 * t4_handle_fw_rpl - process a FW reply message
3153 * @adap: the adapter
3154 * @rpl: start of the FW message
3155 *
3156 * Processes a FW message, such as link state change messages.
3157 */
3158int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3159{
3160	u8 opcode = *(const u8 *)rpl;
3161
3162	/*
3163	 * This might be a port command ... this simplifies the following
3164	 * conditionals ...  We can get away with pre-dereferencing
3165	 * action_to_len16 because it's in the first 16 bytes and all messages
3166	 * will be at least that long.
3167	 */
3168	const struct fw_port_cmd *p = (const void *)rpl;
3169	unsigned int action =
3170		G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3171
3172	if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3173		/* link/module state change message */
3174		int speed = 0, fc = 0, i;
3175		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3176		struct port_info *pi = NULL;
3177		struct link_config *lc;
3178		u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3179		int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3180		u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3181
3182		if (stat & F_FW_PORT_CMD_RXPAUSE)
3183			fc |= PAUSE_RX;
3184		if (stat & F_FW_PORT_CMD_TXPAUSE)
3185			fc |= PAUSE_TX;
3186		if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3187			speed = ETH_SPEED_NUM_100M;
3188		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3189			speed = ETH_SPEED_NUM_1G;
3190		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3191			speed = ETH_SPEED_NUM_10G;
3192		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3193			speed = ETH_SPEED_NUM_40G;
3194
3195		for_each_port(adap, i) {
3196			pi = adap2pinfo(adap, i);
3197			if (pi->tx_chan == chan)
3198				break;
3199		}
3200		lc = &pi->link_cfg;
3201
3202		if (mod != pi->mod_type) {
3203			pi->mod_type = mod;
3204			t4_os_portmod_changed(adap, i);
3205		}
3206		if (link_ok != lc->link_ok || speed != lc->speed ||
3207		    fc != lc->fc) {                    /* something changed */
3208			if (!link_ok && lc->link_ok) {
3209				static const char * const reason[] = {
3210					"Link Down",
3211					"Remote Fault",
3212					"Auto-negotiation Failure",
3213					"Reserved",
3214					"Insufficient Airflow",
3215					"Unable To Determine Reason",
3216					"No RX Signal Detected",
3217					"Reserved",
3218				};
3219				unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3220
3221				dev_warn(adap, "Port %d link down, reason: %s\n",
3222					 chan, reason[rc]);
3223			}
3224			lc->link_ok = link_ok;
3225			lc->speed = speed;
3226			lc->fc = fc;
3227			lc->supported = be16_to_cpu(p->u.info.pcap);
3228		}
3229	} else {
3230		dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3231		return -EINVAL;
3232	}
3233	return 0;
3234}
3235
3236void t4_reset_link_config(struct adapter *adap, int idx)
3237{
3238	struct port_info *pi = adap2pinfo(adap, idx);
3239	struct link_config *lc = &pi->link_cfg;
3240
3241	lc->link_ok = 0;
3242	lc->requested_speed = 0;
3243	lc->requested_fc = 0;
3244	lc->speed = 0;
3245	lc->fc = 0;
3246}
3247
3248/**
3249 * init_link_config - initialize a link's SW state
3250 * @lc: structure holding the link state
3251 * @caps: link capabilities
3252 *
3253 * Initializes the SW state maintained for each link, including the link's
3254 * capabilities and default speed/flow-control/autonegotiation settings.
3255 */
3256static void init_link_config(struct link_config *lc,
3257			     unsigned int caps)
3258{
3259	lc->supported = caps;
3260	lc->requested_speed = 0;
3261	lc->speed = 0;
3262	lc->requested_fc = 0;
3263	lc->fc = 0;
3264	if (lc->supported & FW_PORT_CAP_ANEG) {
3265		lc->advertising = lc->supported & ADVERT_MASK;
3266		lc->autoneg = AUTONEG_ENABLE;
3267	} else {
3268		lc->advertising = 0;
3269		lc->autoneg = AUTONEG_DISABLE;
3270	}
3271}
3272
3273/**
3274 * t4_wait_dev_ready - wait till to reads of registers work
3275 *
3276 * Right after the device is RESET is can take a small amount of time
3277 * for it to respond to register reads.  Until then, all reads will
3278 * return either 0xff...ff or 0xee...ee.  Return an error if reads
3279 * don't work within a reasonable time frame.
3280 */
3281static int t4_wait_dev_ready(struct adapter *adapter)
3282{
3283	u32 whoami;
3284
3285	whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3286
3287	if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3288		return 0;
3289
3290	msleep(500);
3291	whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3292	return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
3293			? 0 : -EIO);
3294}
3295
3296struct flash_desc {
3297	u32 vendor_and_model_id;
3298	u32 size_mb;
3299};
3300
3301int t4_get_flash_params(struct adapter *adapter)
3302{
3303	/*
3304	 * Table for non-Numonix supported flash parts.  Numonix parts are left
3305	 * to the preexisting well-tested code.  All flash parts have 64KB
3306	 * sectors.
3307	 */
3308	static struct flash_desc supported_flash[] = {
3309		{ 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
3310	};
3311
3312	int ret;
3313	unsigned int i;
3314	u32 info = 0;
3315
3316	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3317	if (!ret)
3318		ret = sf1_read(adapter, 3, 0, 1, &info);
3319	t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
3320	if (ret < 0)
3321		return ret;
3322
3323	for (i = 0; i < ARRAY_SIZE(supported_flash); ++i)
3324		if (supported_flash[i].vendor_and_model_id == info) {
3325			adapter->params.sf_size = supported_flash[i].size_mb;
3326			adapter->params.sf_nsec =
3327				adapter->params.sf_size / SF_SEC_SIZE;
3328			return 0;
3329		}
3330
3331	if ((info & 0xff) != 0x20)             /* not a Numonix flash */
3332		return -EINVAL;
3333	info >>= 16;                           /* log2 of size */
3334	if (info >= 0x14 && info < 0x18)
3335		adapter->params.sf_nsec = 1 << (info - 16);
3336	else if (info == 0x18)
3337		adapter->params.sf_nsec = 64;
3338	else
3339		return -EINVAL;
3340	adapter->params.sf_size = 1 << info;
3341
3342	/*
3343	 * We should reject adapters with FLASHes which are too small. So, emit
3344	 * a warning.
3345	 */
3346	if (adapter->params.sf_size < FLASH_MIN_SIZE) {
3347		dev_warn(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
3348			 adapter->params.sf_size, FLASH_MIN_SIZE);
3349	}
3350
3351	return 0;
3352}
3353
3354static void set_pcie_completion_timeout(struct adapter *adapter,
3355					u8 range)
3356{
3357	u32 pcie_cap;
3358	u16 val;
3359
3360	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3361	if (pcie_cap) {
3362		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
3363		val &= 0xfff0;
3364		val |= range;
3365		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
3366	}
3367}
3368
3369/**
3370 * t4_prep_adapter - prepare SW and HW for operation
3371 * @adapter: the adapter
3372 *
3373 * Initialize adapter SW state for the various HW modules, set initial
3374 * values for some adapter tunables, take PHYs out of reset, and
3375 * initialize the MDIO interface.
3376 */
3377int t4_prep_adapter(struct adapter *adapter)
3378{
3379	int ret, ver;
3380	u32 pl_rev;
3381
3382	ret = t4_wait_dev_ready(adapter);
3383	if (ret < 0)
3384		return ret;
3385
3386	pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
3387	adapter->params.pci.device_id = adapter->pdev->id.device_id;
3388	adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
3389
3390	/*
3391	 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
3392	 * ADAPTER (VERSION << 4 | REVISION)
3393	 */
3394	ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
3395	adapter->params.chip = 0;
3396	switch (ver) {
3397	case CHELSIO_T5:
3398		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3399		adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
3400		adapter->params.arch.mps_tcam_size =
3401						NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3402		adapter->params.arch.mps_rplc_size = 128;
3403		adapter->params.arch.nchan = NCHAN;
3404		adapter->params.arch.vfcount = 128;
3405		break;
3406	default:
3407		dev_err(adapter, "%s: Device %d is not supported\n",
3408			__func__, adapter->params.pci.device_id);
3409		return -EINVAL;
3410	}
3411
3412	adapter->params.pci.vpd_cap_addr =
3413		t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3414
3415	ret = t4_get_flash_params(adapter);
3416	if (ret < 0)
3417		return ret;
3418
3419	adapter->params.cim_la_size = CIMLA_SIZE;
3420
3421	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3422
3423	/*
3424	 * Default port and clock for debugging in case we can't reach FW.
3425	 */
3426	adapter->params.nports = 1;
3427	adapter->params.portvec = 1;
3428	adapter->params.vpd.cclk = 50000;
3429
3430	/* Set pci completion timeout value to 4 seconds. */
3431	set_pcie_completion_timeout(adapter, 0xd);
3432	return 0;
3433}
3434
3435/**
3436 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
3437 * @adapter: the adapter
3438 * @qid: the Queue ID
3439 * @qtype: the Ingress or Egress type for @qid
3440 * @pbar2_qoffset: BAR2 Queue Offset
3441 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
3442 *
3443 * Returns the BAR2 SGE Queue Registers information associated with the
3444 * indicated Absolute Queue ID.  These are passed back in return value
3445 * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
3446 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
3447 *
3448 * This may return an error which indicates that BAR2 SGE Queue
3449 * registers aren't available.  If an error is not returned, then the
3450 * following values are returned:
3451 *
3452 *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
3453 *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
3454 *
3455 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
3456 * require the "Inferred Queue ID" ability may be used.  E.g. the
3457 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
3458 * then these "Inferred Queue ID" register may not be used.
3459 */
3460int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
3461		      enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
3462		      unsigned int *pbar2_qid)
3463{
3464	unsigned int page_shift, page_size, qpp_shift, qpp_mask;
3465	u64 bar2_page_offset, bar2_qoffset;
3466	unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
3467
3468	/*
3469	 * T4 doesn't support BAR2 SGE Queue registers.
3470	 */
3471	if (is_t4(adapter->params.chip))
3472		return -EINVAL;
3473
3474	/*
3475	 * Get our SGE Page Size parameters.
3476	 */
3477	page_shift = adapter->params.sge.hps + 10;
3478	page_size = 1 << page_shift;
3479
3480	/*
3481	 * Get the right Queues per Page parameters for our Queue.
3482	 */
3483	qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
3484			      adapter->params.sge.eq_qpp :
3485			      adapter->params.sge.iq_qpp);
3486	qpp_mask = (1 << qpp_shift) - 1;
3487
3488	/*
3489	 * Calculate the basics of the BAR2 SGE Queue register area:
3490	 *  o The BAR2 page the Queue registers will be in.
3491	 *  o The BAR2 Queue ID.
3492	 *  o The BAR2 Queue ID Offset into the BAR2 page.
3493	 */
3494	bar2_page_offset = ((qid >> qpp_shift) << page_shift);
3495	bar2_qid = qid & qpp_mask;
3496	bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
3497
3498	/*
3499	 * If the BAR2 Queue ID Offset is less than the Page Size, then the
3500	 * hardware will infer the Absolute Queue ID simply from the writes to
3501	 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
3502	 * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
3503	 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
3504	 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
3505	 * from the BAR2 Page and BAR2 Queue ID.
3506	 *
3507	 * One important censequence of this is that some BAR2 SGE registers
3508	 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
3509	 * there.  But other registers synthesize the SGE Queue ID purely
3510	 * from the writes to the registers -- the Write Combined Doorbell
3511	 * Buffer is a good example.  These BAR2 SGE Registers are only
3512	 * available for those BAR2 SGE Register areas where the SGE Absolute
3513	 * Queue ID can be inferred from simple writes.
3514	 */
3515	bar2_qoffset = bar2_page_offset;
3516	bar2_qinferred = (bar2_qid_offset < page_size);
3517	if (bar2_qinferred) {
3518		bar2_qoffset += bar2_qid_offset;
3519		bar2_qid = 0;
3520	}
3521
3522	*pbar2_qoffset = bar2_qoffset;
3523	*pbar2_qid = bar2_qid;
3524	return 0;
3525}
3526
3527/**
3528 * t4_init_sge_params - initialize adap->params.sge
3529 * @adapter: the adapter
3530 *
3531 * Initialize various fields of the adapter's SGE Parameters structure.
3532 */
3533int t4_init_sge_params(struct adapter *adapter)
3534{
3535	struct sge_params *sge_params = &adapter->params.sge;
3536	u32 hps, qpp;
3537	unsigned int s_hps, s_qpp;
3538
3539	/*
3540	 * Extract the SGE Page Size for our PF.
3541	 */
3542	hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
3543	s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
3544		 adapter->pf);
3545	sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
3546
3547	/*
3548	 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
3549	 */
3550	s_qpp = (S_QUEUESPERPAGEPF0 +
3551		 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
3552	qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
3553	sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3554	qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
3555	sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3556
3557	return 0;
3558}
3559
3560/**
3561 * t4_init_tp_params - initialize adap->params.tp
3562 * @adap: the adapter
3563 *
3564 * Initialize various fields of the adapter's TP Parameters structure.
3565 */
3566int t4_init_tp_params(struct adapter *adap)
3567{
3568	int chan;
3569	u32 v;
3570
3571	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
3572	adap->params.tp.tre = G_TIMERRESOLUTION(v);
3573	adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
3574
3575	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3576	for (chan = 0; chan < NCHAN; chan++)
3577		adap->params.tp.tx_modq[chan] = chan;
3578
3579	/*
3580	 * Cache the adapter's Compressed Filter Mode and global Incress
3581	 * Configuration.
3582	 */
3583	t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3584			 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
3585	t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3586			 &adap->params.tp.ingress_config, 1,
3587			 A_TP_INGRESS_CONFIG);
3588
3589	/*
3590	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3591	 * shift positions of several elements of the Compressed Filter Tuple
3592	 * for this adapter which we need frequently ...
3593	 */
3594	adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
3595	adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
3596	adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
3597	adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
3598							       F_PROTOCOL);
3599
3600	/*
3601	 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
3602	 * represents the presense of an Outer VLAN instead of a VNIC ID.
3603	 */
3604	if ((adap->params.tp.ingress_config & F_VNIC) == 0)
3605		adap->params.tp.vnic_shift = -1;
3606
3607	return 0;
3608}
3609
3610/**
3611 * t4_filter_field_shift - calculate filter field shift
3612 * @adap: the adapter
3613 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
3614 *
3615 * Return the shift position of a filter field within the Compressed
3616 * Filter Tuple.  The filter field is specified via its selection bit
3617 * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
3618 */
3619int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
3620{
3621	unsigned int filter_mode = adap->params.tp.vlan_pri_map;
3622	unsigned int sel;
3623	int field_shift;
3624
3625	if ((filter_mode & filter_sel) == 0)
3626		return -1;
3627
3628	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
3629		switch (filter_mode & sel) {
3630		case F_FCOE:
3631			field_shift += W_FT_FCOE;
3632			break;
3633		case F_PORT:
3634			field_shift += W_FT_PORT;
3635			break;
3636		case F_VNIC_ID:
3637			field_shift += W_FT_VNIC_ID;
3638			break;
3639		case F_VLAN:
3640			field_shift += W_FT_VLAN;
3641			break;
3642		case F_TOS:
3643			field_shift += W_FT_TOS;
3644			break;
3645		case F_PROTOCOL:
3646			field_shift += W_FT_PROTOCOL;
3647			break;
3648		case F_ETHERTYPE:
3649			field_shift += W_FT_ETHERTYPE;
3650			break;
3651		case F_MACMATCH:
3652			field_shift += W_FT_MACMATCH;
3653			break;
3654		case F_MPSHITTYPE:
3655			field_shift += W_FT_MPSHITTYPE;
3656			break;
3657		case F_FRAGMENTATION:
3658			field_shift += W_FT_FRAGMENTATION;
3659			break;
3660		}
3661	}
3662	return field_shift;
3663}
3664
3665int t4_init_rss_mode(struct adapter *adap, int mbox)
3666{
3667	int i, ret;
3668	struct fw_rss_vi_config_cmd rvc;
3669
3670	memset(&rvc, 0, sizeof(rvc));
3671
3672	for_each_port(adap, i) {
3673		struct port_info *p = adap2pinfo(adap, i);
3674
3675		rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3676				       F_FW_CMD_REQUEST | F_FW_CMD_READ |
3677				       V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3678		rvc.retval_len16 = htonl(FW_LEN16(rvc));
3679		ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3680		if (ret)
3681			return ret;
3682		p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3683	}
3684	return 0;
3685}
3686
3687int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3688{
3689	u8 addr[6];
3690	int ret, i, j = 0;
3691	struct fw_port_cmd c;
3692
3693	memset(&c, 0, sizeof(c));
3694
3695	for_each_port(adap, i) {
3696		unsigned int rss_size = 0;
3697		struct port_info *p = adap2pinfo(adap, i);
3698
3699		while ((adap->params.portvec & (1 << j)) == 0)
3700			j++;
3701
3702		c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3703					     F_FW_CMD_REQUEST | F_FW_CMD_READ |
3704					     V_FW_PORT_CMD_PORTID(j));
3705		c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
3706						FW_PORT_ACTION_GET_PORT_INFO) |
3707						FW_LEN16(c));
3708		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3709		if (ret)
3710			return ret;
3711
3712		ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3713		if (ret < 0)
3714			return ret;
3715
3716		p->viid = ret;
3717		p->tx_chan = j;
3718		p->rss_size = rss_size;
3719		t4_os_set_hw_addr(adap, i, addr);
3720
3721		ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
3722		p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
3723				G_FW_PORT_CMD_MDIOADDR(ret) : -1;
3724		p->port_type = G_FW_PORT_CMD_PTYPE(ret);
3725		p->mod_type = FW_PORT_MOD_TYPE_NA;
3726
3727		init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
3728		j++;
3729	}
3730	return 0;
3731}
3732