ena_plat_dpdk.h revision 8b25d1ad
1/*-
2* BSD LICENSE
3*
4* Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
5* All rights reserved.
6*
7* Redistribution and use in source and binary forms, with or without
8* modification, are permitted provided that the following conditions
9* are met:
10*
11* * Redistributions of source code must retain the above copyright
12* notice, this list of conditions and the following disclaimer.
13* * Redistributions in binary form must reproduce the above copyright
14* notice, this list of conditions and the following disclaimer in
15* the documentation and/or other materials provided with the
16* distribution.
17* * Neither the name of copyright holder nor the names of its
18* contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*/
33
34#ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_
35#define DPDK_ENA_COM_ENA_PLAT_DPDK_H_
36
37#include <stdbool.h>
38#include <stdlib.h>
39#include <pthread.h>
40#include <stdint.h>
41#include <string.h>
42#include <errno.h>
43
44#include <rte_atomic.h>
45#include <rte_branch_prediction.h>
46#include <rte_cycles.h>
47#include <rte_log.h>
48#include <rte_malloc.h>
49#include <rte_memzone.h>
50#include <rte_spinlock.h>
51
52#include <sys/time.h>
53
54typedef uint64_t u64;
55typedef uint32_t u32;
56typedef uint16_t u16;
57typedef uint8_t u8;
58
59typedef uint64_t dma_addr_t;
60#ifndef ETIME
61#define ETIME ETIMEDOUT
62#endif
63
64#define ena_atomic32_t rte_atomic32_t
65#define ena_mem_handle_t void *
66
67#define SZ_256 (256)
68#define SZ_4K (4096)
69
70#define ENA_COM_OK	0
71#define ENA_COM_NO_MEM	-ENOMEM
72#define ENA_COM_INVAL	-EINVAL
73#define ENA_COM_NO_SPACE	-ENOSPC
74#define ENA_COM_NO_DEVICE	-ENODEV
75#define ENA_COM_PERMISSION	-EPERM
76#define ENA_COM_TIMER_EXPIRED	-ETIME
77#define ENA_COM_FAULT	-EFAULT
78
79#define ____cacheline_aligned __rte_cache_aligned
80
81#define ENA_ABORT() abort()
82
83#define ENA_MSLEEP(x) rte_delay_ms(x)
84#define ENA_UDELAY(x) rte_delay_us(x)
85
86#define memcpy_toio memcpy
87#define wmb rte_wmb
88#define rmb rte_wmb
89#define mb rte_mb
90#define __iomem
91
92#define US_PER_S 1000000
93#define ENA_GET_SYSTEM_USECS()						\
94	(rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())
95
96#if RTE_LOG_LEVEL >= RTE_LOG_DEBUG
97#define ENA_ASSERT(cond, format, arg...)				\
98	do {								\
99		if (unlikely(!(cond))) {				\
100			RTE_LOG(ERR, PMD, format, ##arg);		\
101			rte_panic("line %d\tassert \"" #cond "\""	\
102					"failed\n", __LINE__);		\
103		}							\
104	} while (0)
105#else
106#define ENA_ASSERT(cond, format, arg...) do {} while (0)
107#endif
108
109#define ENA_MAX32(x, y) RTE_MAX((x), (y))
110#define ENA_MAX16(x, y) RTE_MAX((x), (y))
111#define ENA_MAX8(x, y) RTE_MAX((x), (y))
112#define ENA_MIN32(x, y) RTE_MIN((x), (y))
113#define ENA_MIN16(x, y) RTE_MIN((x), (y))
114#define ENA_MIN8(x, y) RTE_MIN((x), (y))
115
116#define U64_C(x) x ## ULL
117#define BIT(nr)         (1UL << (nr))
118#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
119#define GENMASK(h, l)	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
120#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l))
121
122#ifdef RTE_LIBRTE_ENA_COM_DEBUG
123#define ena_trc_dbg(format, arg...)					\
124	RTE_LOG(DEBUG, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
125#define ena_trc_info(format, arg...)					\
126	RTE_LOG(INFO, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
127#define ena_trc_warn(format, arg...)					\
128	RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
129#define ena_trc_err(format, arg...)					\
130	RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
131#else
132#define ena_trc_dbg(format, arg...) do { } while (0)
133#define ena_trc_info(format, arg...) do { } while (0)
134#define ena_trc_warn(format, arg...) do { } while (0)
135#define ena_trc_err(format, arg...) do { } while (0)
136#endif /* RTE_LIBRTE_ENA_COM_DEBUG */
137
138/* Spinlock related methods */
139#define ena_spinlock_t rte_spinlock_t
140#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)
141#define ENA_SPINLOCK_LOCK(spinlock, flags)				\
142	({(void)flags; rte_spinlock_lock(&spinlock); })
143#define ENA_SPINLOCK_UNLOCK(spinlock, flags)				\
144	({(void)flags; rte_spinlock_unlock(&(spinlock)); })
145
146#define q_waitqueue_t			\
147	struct {			\
148		pthread_cond_t cond;	\
149		pthread_mutex_t mutex;	\
150	}
151
152#define ena_wait_queue_t q_waitqueue_t
153
154#define ENA_WAIT_EVENT_INIT(waitqueue)					\
155	do {								\
156		pthread_mutex_init(&(waitqueue).mutex, NULL);		\
157		pthread_cond_init(&(waitqueue).cond, NULL);		\
158	} while (0)
159
160#define ENA_WAIT_EVENT_WAIT(waitevent, timeout)				\
161	do {								\
162		struct timespec wait;					\
163		struct timeval now;					\
164		unsigned long timeout_us;				\
165		gettimeofday(&now, NULL);				\
166		wait.tv_sec = now.tv_sec + timeout / 1000000UL;		\
167		timeout_us = timeout % 1000000UL;			\
168		wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;	\
169		pthread_mutex_lock(&waitevent.mutex);			\
170		pthread_cond_timedwait(&waitevent.cond,			\
171				&waitevent.mutex, &wait);		\
172		pthread_mutex_unlock(&waitevent.mutex);			\
173	} while (0)
174#define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
175/* pthread condition doesn't need to be rearmed after usage */
176#define ENA_WAIT_EVENT_CLEAR(...)
177
178#define ena_wait_event_t ena_wait_queue_t
179#define ENA_MIGHT_SLEEP()
180
181#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)	\
182	do {								\
183		const struct rte_memzone *mz;				\
184		char z_name[RTE_MEMZONE_NAMESIZE];			\
185		(void)dmadev; (void)handle;				\
186		snprintf(z_name, sizeof(z_name),			\
187				"ena_alloc_%d", ena_alloc_cnt++);	\
188		mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, 0); \
189		virt = mz->addr;					\
190		phys = mz->phys_addr;					\
191	} while (0)
192#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) 	\
193	({(void)size; rte_free(virt); })
194#define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
195#define ENA_MEM_FREE(dmadev, ptr) ({(void)dmadev; rte_free(ptr); })
196
197static inline void writel(u32 value, volatile void  *addr)
198{
199	*(volatile u32 *)addr = value;
200}
201
202static inline u32 readl(const volatile void *addr)
203{
204	return *(const volatile u32 *)addr;
205}
206
207#define ENA_REG_WRITE32(value, reg) writel((value), (reg))
208#define ENA_REG_READ32(reg) readl((reg))
209
210#define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
211#define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
212#define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val)
213#define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr)
214
215#define msleep(x) rte_delay_us(x * 1000)
216#define udelay(x) rte_delay_us(x)
217
218#define MAX_ERRNO       4095
219#define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO)
220#define ERR_PTR(error) ((void *)(long)error)
221#define PTR_ERR(error) ((long)(void *)error)
222#define might_sleep()
223
224#endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */
225