enic_rxtx.c revision 5d4e5dcd
1/* Copyright 2008-2016 Cisco Systems, Inc.  All rights reserved.
2 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
3 *
4 * Copyright (c) 2014, Cisco Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
27 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <rte_mbuf.h>
34#include <rte_ethdev.h>
35#include <rte_prefetch.h>
36
37#include "enic_compat.h"
38#include "rq_enet_desc.h"
39#include "enic.h"
40
41#define RTE_PMD_USE_PREFETCH
42
43#ifdef RTE_PMD_USE_PREFETCH
44/*Prefetch a cache line into all cache levels. */
45#define rte_enic_prefetch(p) rte_prefetch0(p)
46#else
47#define rte_enic_prefetch(p) do {} while (0)
48#endif
49
50#ifdef RTE_PMD_PACKET_PREFETCH
51#define rte_packet_prefetch(p) rte_prefetch1(p)
52#else
53#define rte_packet_prefetch(p) do {} while (0)
54#endif
55
56static inline uint16_t
57enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
58{
59	return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
60}
61
62static inline uint16_t
63enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
64{
65	return le16_to_cpu(crd->bytes_written_flags) &
66			   ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
67}
68
69static inline uint8_t
70enic_cq_rx_desc_packet_error(uint16_t bwflags)
71{
72	return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
73		CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
74}
75
76static inline uint8_t
77enic_cq_rx_desc_eop(uint16_t ciflags)
78{
79	return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
80		== CQ_ENET_RQ_DESC_FLAGS_EOP;
81}
82
83static inline uint8_t
84enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
85{
86	return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
87		CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
88		CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
89}
90
91static inline uint8_t
92enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
93{
94	return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
95		CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
96}
97
98static inline uint8_t
99enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
100{
101	return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
102		CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
103}
104
105static inline uint8_t
106enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
107{
108	return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
109		CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
110}
111
112static inline uint32_t
113enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
114{
115	return le32_to_cpu(cqrd->rss_hash);
116}
117
118static inline uint16_t
119enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
120{
121	return le16_to_cpu(cqrd->vlan);
122}
123
124static inline uint16_t
125enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
126{
127	struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
128	return le16_to_cpu(cqrd->bytes_written_flags) &
129		CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
130}
131
132static inline uint8_t
133enic_cq_rx_check_err(struct cq_desc *cqd)
134{
135	struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
136	uint16_t bwflags;
137
138	bwflags = enic_cq_rx_desc_bwflags(cqrd);
139	if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
140		return 1;
141	return 0;
142}
143
144/* Lookup table to translate RX CQ flags to mbuf flags. */
145static inline uint32_t
146enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
147{
148	struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
149	uint8_t cqrd_flags = cqrd->flags;
150	static const uint32_t cq_type_table[128] __rte_cache_aligned = {
151		[0x00] = RTE_PTYPE_UNKNOWN,
152		[0x20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
153			  | RTE_PTYPE_L4_NONFRAG,
154		[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
155			  | RTE_PTYPE_L4_UDP,
156		[0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
157			  | RTE_PTYPE_L4_TCP,
158		[0x60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
159			  | RTE_PTYPE_L4_FRAG,
160		[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
161			  | RTE_PTYPE_L4_UDP,
162		[0x64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN
163			  | RTE_PTYPE_L4_TCP,
164		[0x10] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
165			  | RTE_PTYPE_L4_NONFRAG,
166		[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
167			  | RTE_PTYPE_L4_UDP,
168		[0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
169			  | RTE_PTYPE_L4_TCP,
170		[0x50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
171			  | RTE_PTYPE_L4_FRAG,
172		[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
173			  | RTE_PTYPE_L4_UDP,
174		[0x54] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN
175			  | RTE_PTYPE_L4_TCP,
176		/* All others reserved */
177	};
178	cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
179		| CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
180		| CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
181	return cq_type_table[cqrd_flags];
182}
183
184static inline void
185enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
186{
187	struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
188	uint16_t ciflags, bwflags, pkt_flags = 0;
189	ciflags = enic_cq_rx_desc_ciflags(cqrd);
190	bwflags = enic_cq_rx_desc_bwflags(cqrd);
191
192	mbuf->ol_flags = 0;
193
194	/* flags are meaningless if !EOP */
195	if (unlikely(!enic_cq_rx_desc_eop(ciflags)))
196		goto mbuf_flags_done;
197
198	/* VLAN stripping */
199	if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
200		pkt_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
201		mbuf->vlan_tci = enic_cq_rx_desc_vlan(cqrd);
202	} else {
203		mbuf->vlan_tci = 0;
204	}
205
206	/* RSS flag */
207	if (enic_cq_rx_desc_rss_type(cqrd)) {
208		pkt_flags |= PKT_RX_RSS_HASH;
209		mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
210	}
211
212	/* checksum flags */
213	if (!enic_cq_rx_desc_csum_not_calc(cqrd) &&
214		(mbuf->packet_type & RTE_PTYPE_L3_IPV4)) {
215		if (unlikely(!enic_cq_rx_desc_ipv4_csum_ok(cqrd)))
216			pkt_flags |= PKT_RX_IP_CKSUM_BAD;
217		if (mbuf->packet_type & (RTE_PTYPE_L4_UDP | RTE_PTYPE_L4_TCP)) {
218			if (unlikely(!enic_cq_rx_desc_tcp_udp_csum_ok(cqrd)))
219				pkt_flags |= PKT_RX_L4_CKSUM_BAD;
220		}
221	}
222
223 mbuf_flags_done:
224	mbuf->ol_flags = pkt_flags;
225}
226
227uint16_t
228enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
229	       uint16_t nb_pkts)
230{
231	struct vnic_rq *sop_rq = rx_queue;
232	struct vnic_rq *data_rq;
233	struct vnic_rq *rq;
234	struct enic *enic = vnic_dev_priv(sop_rq->vdev);
235	uint16_t cq_idx;
236	uint16_t rq_idx;
237	uint16_t rq_num;
238	struct rte_mbuf *nmb, *rxmb;
239	uint16_t nb_rx = 0;
240	struct vnic_cq *cq;
241	volatile struct cq_desc *cqd_ptr;
242	uint8_t color;
243	uint16_t seg_length;
244	struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
245	struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
246
247	cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
248	cq_idx = cq->to_clean;		/* index of cqd, rqd, mbuf_table */
249	cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
250
251	data_rq = &enic->rq[sop_rq->data_queue_idx];
252
253	while (nb_rx < nb_pkts) {
254		volatile struct rq_enet_desc *rqd_ptr;
255		dma_addr_t dma_addr;
256		struct cq_desc cqd;
257		uint8_t packet_error;
258		uint16_t ciflags;
259
260		/* Check for pkts available */
261		color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
262			& CQ_DESC_COLOR_MASK;
263		if (color == cq->last_color)
264			break;
265
266		/* Get the cq descriptor and extract rq info from it */
267		cqd = *cqd_ptr;
268		rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
269		rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
270
271		rq = &enic->rq[rq_num];
272		rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
273
274		/* allocate a new mbuf */
275		nmb = rte_mbuf_raw_alloc(rq->mp);
276		if (nmb == NULL) {
277			rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
278			break;
279		}
280
281		/* A packet error means descriptor and data are untrusted */
282		packet_error = enic_cq_rx_check_err(&cqd);
283
284		/* Get the mbuf to return and replace with one just allocated */
285		rxmb = rq->mbuf_ring[rq_idx];
286		rq->mbuf_ring[rq_idx] = nmb;
287
288		/* Increment cqd, rqd, mbuf_table index */
289		cq_idx++;
290		if (unlikely(cq_idx == cq->ring.desc_count)) {
291			cq_idx = 0;
292			cq->last_color = cq->last_color ? 0 : 1;
293		}
294
295		/* Prefetch next mbuf & desc while processing current one */
296		cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
297		rte_enic_prefetch(cqd_ptr);
298
299		ciflags = enic_cq_rx_desc_ciflags(
300			(struct cq_enet_rq_desc *)&cqd);
301
302		/* Push descriptor for newly allocated mbuf */
303		dma_addr = (dma_addr_t)(nmb->buf_physaddr +
304					RTE_PKTMBUF_HEADROOM);
305		rq_enet_desc_enc(rqd_ptr, dma_addr,
306				(rq->is_sop ? RQ_ENET_TYPE_ONLY_SOP
307				: RQ_ENET_TYPE_NOT_SOP),
308				nmb->buf_len - RTE_PKTMBUF_HEADROOM);
309
310		/* Fill in the rest of the mbuf */
311		seg_length = enic_cq_rx_desc_n_bytes(&cqd);
312
313		if (rq->is_sop) {
314			first_seg = rxmb;
315			first_seg->nb_segs = 1;
316			first_seg->pkt_len = seg_length;
317		} else {
318			first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
319							+ seg_length);
320			first_seg->nb_segs++;
321			last_seg->next = rxmb;
322		}
323
324		rxmb->next = NULL;
325		rxmb->port = enic->port_id;
326		rxmb->data_len = seg_length;
327
328		rq->rx_nb_hold++;
329
330		if (!(enic_cq_rx_desc_eop(ciflags))) {
331			last_seg = rxmb;
332			continue;
333		}
334
335		/* cq rx flags are only valid if eop bit is set */
336		first_seg->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
337		enic_cq_rx_to_pkt_flags(&cqd, first_seg);
338
339		if (unlikely(packet_error)) {
340			rte_pktmbuf_free(first_seg);
341			rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
342			continue;
343		}
344
345
346		/* prefetch mbuf data for caller */
347		rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
348				    RTE_PKTMBUF_HEADROOM));
349
350		/* store the mbuf address into the next entry of the array */
351		rx_pkts[nb_rx++] = first_seg;
352	}
353
354	sop_rq->pkt_first_seg = first_seg;
355	sop_rq->pkt_last_seg = last_seg;
356
357	cq->to_clean = cq_idx;
358
359	if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
360	    sop_rq->rx_free_thresh) {
361		if (data_rq->in_use) {
362			data_rq->posted_index =
363				enic_ring_add(data_rq->ring.desc_count,
364					      data_rq->posted_index,
365					      data_rq->rx_nb_hold);
366			data_rq->rx_nb_hold = 0;
367		}
368		sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
369						     sop_rq->posted_index,
370						     sop_rq->rx_nb_hold);
371		sop_rq->rx_nb_hold = 0;
372
373		rte_mb();
374		if (data_rq->in_use)
375			iowrite32(data_rq->posted_index,
376				  &data_rq->ctrl->posted_index);
377		rte_compiler_barrier();
378		iowrite32(sop_rq->posted_index, &sop_rq->ctrl->posted_index);
379	}
380
381
382	return nb_rx;
383}
384
385static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
386{
387	struct vnic_wq_buf *buf;
388	struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
389	unsigned int nb_to_free, nb_free = 0, i;
390	struct rte_mempool *pool;
391	unsigned int tail_idx;
392	unsigned int desc_count = wq->ring.desc_count;
393
394	nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
395				   + 1;
396	tail_idx = wq->tail_idx;
397	buf = &wq->bufs[tail_idx];
398	pool = ((struct rte_mbuf *)buf->mb)->pool;
399	for (i = 0; i < nb_to_free; i++) {
400		buf = &wq->bufs[tail_idx];
401		m = __rte_pktmbuf_prefree_seg((struct rte_mbuf *)(buf->mb));
402		buf->mb = NULL;
403
404		if (unlikely(m == NULL)) {
405			tail_idx = enic_ring_incr(desc_count, tail_idx);
406			continue;
407		}
408
409		if (likely(m->pool == pool)) {
410			RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
411			free[nb_free++] = m;
412		} else {
413			rte_mempool_put_bulk(pool, (void *)free, nb_free);
414			free[0] = m;
415			nb_free = 1;
416			pool = m->pool;
417		}
418		tail_idx = enic_ring_incr(desc_count, tail_idx);
419	}
420
421	rte_mempool_put_bulk(pool, (void **)free, nb_free);
422
423	wq->tail_idx = tail_idx;
424	wq->ring.desc_avail += nb_to_free;
425}
426
427unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
428{
429	u16 completed_index;
430
431	completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
432
433	if (wq->last_completed_index != completed_index) {
434		enic_free_wq_bufs(wq, completed_index);
435		wq->last_completed_index = completed_index;
436	}
437	return 0;
438}
439
440uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
441	uint16_t nb_pkts)
442{
443	uint16_t index;
444	unsigned int pkt_len, data_len;
445	unsigned int nb_segs;
446	struct rte_mbuf *tx_pkt;
447	struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
448	struct enic *enic = vnic_dev_priv(wq->vdev);
449	unsigned short vlan_id;
450	uint64_t ol_flags;
451	uint64_t ol_flags_mask;
452	unsigned int wq_desc_avail;
453	int head_idx;
454	struct vnic_wq_buf *buf;
455	unsigned int desc_count;
456	struct wq_enet_desc *descs, *desc_p, desc_tmp;
457	uint16_t mss;
458	uint8_t vlan_tag_insert;
459	uint8_t eop;
460	uint64_t bus_addr;
461
462	enic_cleanup_wq(enic, wq);
463	wq_desc_avail = vnic_wq_desc_avail(wq);
464	head_idx = wq->head_idx;
465	desc_count = wq->ring.desc_count;
466	ol_flags_mask = PKT_TX_VLAN_PKT | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
467
468	nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
469
470	for (index = 0; index < nb_pkts; index++) {
471		tx_pkt = *tx_pkts++;
472		nb_segs = tx_pkt->nb_segs;
473		if (nb_segs > wq_desc_avail) {
474			if (index > 0)
475				goto post;
476			goto done;
477		}
478
479		pkt_len = tx_pkt->pkt_len;
480		data_len = tx_pkt->data_len;
481		ol_flags = tx_pkt->ol_flags;
482		mss = 0;
483		vlan_id = 0;
484		vlan_tag_insert = 0;
485		bus_addr = (dma_addr_t)
486			   (tx_pkt->buf_physaddr + tx_pkt->data_off);
487
488		descs = (struct wq_enet_desc *)wq->ring.descs;
489		desc_p = descs + head_idx;
490
491		eop = (data_len == pkt_len);
492
493		if (ol_flags & ol_flags_mask) {
494			if (ol_flags & PKT_TX_VLAN_PKT) {
495				vlan_tag_insert = 1;
496				vlan_id = tx_pkt->vlan_tci;
497			}
498
499			if (ol_flags & PKT_TX_IP_CKSUM)
500				mss |= ENIC_CALC_IP_CKSUM;
501
502			/* Nic uses just 1 bit for UDP and TCP */
503			switch (ol_flags & PKT_TX_L4_MASK) {
504			case PKT_TX_TCP_CKSUM:
505			case PKT_TX_UDP_CKSUM:
506				mss |= ENIC_CALC_TCP_UDP_CKSUM;
507				break;
508			}
509		}
510
511		wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, 0, 0, eop,
512				 eop, 0, vlan_tag_insert, vlan_id, 0);
513
514		*desc_p = desc_tmp;
515		buf = &wq->bufs[head_idx];
516		buf->mb = (void *)tx_pkt;
517		head_idx = enic_ring_incr(desc_count, head_idx);
518		wq_desc_avail--;
519
520		if (!eop) {
521			for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
522			    tx_pkt->next) {
523				data_len = tx_pkt->data_len;
524
525				if (tx_pkt->next == NULL)
526					eop = 1;
527				desc_p = descs + head_idx;
528				bus_addr = (dma_addr_t)(tx_pkt->buf_physaddr
529					   + tx_pkt->data_off);
530				wq_enet_desc_enc((struct wq_enet_desc *)
531						 &desc_tmp, bus_addr, data_len,
532						 mss, 0, 0, eop, eop, 0,
533						 vlan_tag_insert, vlan_id, 0);
534
535				*desc_p = desc_tmp;
536				buf = &wq->bufs[head_idx];
537				buf->mb = (void *)tx_pkt;
538				head_idx = enic_ring_incr(desc_count, head_idx);
539				wq_desc_avail--;
540			}
541		}
542	}
543 post:
544	rte_wmb();
545	iowrite32(head_idx, &wq->ctrl->posted_index);
546 done:
547	wq->ring.desc_avail = wq_desc_avail;
548	wq->head_idx = head_idx;
549
550	return index;
551}
552
553
554