1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef _I40E_RXTX_VEC_COMMON_H_
35#define _I40E_RXTX_VEC_COMMON_H_
36#include <stdint.h>
37#include <rte_ethdev.h>
38#include <rte_malloc.h>
39
40#include "i40e_ethdev.h"
41#include "i40e_rxtx.h"
42
43static inline uint16_t
44reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,
45		   uint16_t nb_bufs, uint8_t *split_flags)
46{
47	struct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/
48	struct rte_mbuf *start = rxq->pkt_first_seg;
49	struct rte_mbuf *end =  rxq->pkt_last_seg;
50	unsigned pkt_idx, buf_idx;
51
52	for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
53		if (end != NULL) {
54			/* processing a split packet */
55			end->next = rx_bufs[buf_idx];
56			rx_bufs[buf_idx]->data_len += rxq->crc_len;
57
58			start->nb_segs++;
59			start->pkt_len += rx_bufs[buf_idx]->data_len;
60			end = end->next;
61
62			if (!split_flags[buf_idx]) {
63				/* it's the last packet of the set */
64				start->hash = end->hash;
65				start->ol_flags = end->ol_flags;
66				/* we need to strip crc for the whole packet */
67				start->pkt_len -= rxq->crc_len;
68				if (end->data_len > rxq->crc_len) {
69					end->data_len -= rxq->crc_len;
70				} else {
71					/* free up last mbuf */
72					struct rte_mbuf *secondlast = start;
73
74					start->nb_segs--;
75					while (secondlast->next != end)
76						secondlast = secondlast->next;
77					secondlast->data_len -= (rxq->crc_len -
78							end->data_len);
79					secondlast->next = NULL;
80					rte_pktmbuf_free_seg(end);
81					end = secondlast;
82				}
83				pkts[pkt_idx++] = start;
84				start = end = NULL;
85			}
86		} else {
87			/* not processing a split packet */
88			if (!split_flags[buf_idx]) {
89				/* not a split packet, save and skip */
90				pkts[pkt_idx++] = rx_bufs[buf_idx];
91				continue;
92			}
93			end = start = rx_bufs[buf_idx];
94			rx_bufs[buf_idx]->data_len += rxq->crc_len;
95			rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
96		}
97	}
98
99	/* save the partial packet for next time */
100	rxq->pkt_first_seg = start;
101	rxq->pkt_last_seg = end;
102	memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
103	return pkt_idx;
104}
105
106static inline int __attribute__((always_inline))
107i40e_tx_free_bufs(struct i40e_tx_queue *txq)
108{
109	struct i40e_tx_entry *txep;
110	uint32_t n;
111	uint32_t i;
112	int nb_free = 0;
113	struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
114
115	/* check DD bits on threshold descriptor */
116	if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
117			rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
118			rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
119		return 0;
120
121	n = txq->tx_rs_thresh;
122
123	 /* first buffer to free from S/W ring is at index
124	  * tx_next_dd - (tx_rs_thresh-1)
125	  */
126	txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
127	m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
128	if (likely(m != NULL)) {
129		free[0] = m;
130		nb_free = 1;
131		for (i = 1; i < n; i++) {
132			m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
133			if (likely(m != NULL)) {
134				if (likely(m->pool == free[0]->pool)) {
135					free[nb_free++] = m;
136				} else {
137					rte_mempool_put_bulk(free[0]->pool,
138							     (void *)free,
139							     nb_free);
140					free[0] = m;
141					nb_free = 1;
142				}
143			}
144		}
145		rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
146	} else {
147		for (i = 1; i < n; i++) {
148			m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
149			if (m != NULL)
150				rte_mempool_put(m->pool, m);
151		}
152	}
153
154	/* buffers were freed, update counters */
155	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
156	txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
157	if (txq->tx_next_dd >= txq->nb_tx_desc)
158		txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
159
160	return txq->tx_rs_thresh;
161}
162
163static inline void __attribute__((always_inline))
164tx_backlog_entry(struct i40e_tx_entry *txep,
165		 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
166{
167	int i;
168
169	for (i = 0; i < (int)nb_pkts; ++i)
170		txep[i].mbuf = tx_pkts[i];
171}
172
173static inline void
174_i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
175{
176	const unsigned mask = rxq->nb_rx_desc - 1;
177	unsigned i;
178
179	if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
180		return;
181
182	/* free all mbufs that are valid in the ring */
183	if (rxq->rxrearm_nb == 0) {
184		for (i = 0; i < rxq->nb_rx_desc; i++) {
185			if (rxq->sw_ring[i].mbuf != NULL)
186				rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
187		}
188	} else {
189		for (i = rxq->rx_tail;
190		     i != rxq->rxrearm_start;
191		     i = (i + 1) & mask) {
192			if (rxq->sw_ring[i].mbuf != NULL)
193				rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
194		}
195	}
196
197	rxq->rxrearm_nb = rxq->nb_rx_desc;
198
199	/* set all entries to NULL */
200	memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
201}
202
203static inline int
204i40e_rxq_vec_setup_default(struct i40e_rx_queue *rxq)
205{
206	uintptr_t p;
207	struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
208
209	mb_def.nb_segs = 1;
210	mb_def.data_off = RTE_PKTMBUF_HEADROOM;
211	mb_def.port = rxq->port_id;
212	rte_mbuf_refcnt_set(&mb_def, 1);
213
214	/* prevent compiler reordering: rearm_data covers previous fields */
215	rte_compiler_barrier();
216	p = (uintptr_t)&mb_def.rearm_data;
217	rxq->mbuf_initializer = *(uint64_t *)p;
218	return 0;
219}
220
221static inline int
222i40e_rx_vec_dev_conf_condition_check_default(struct rte_eth_dev *dev)
223{
224#ifndef RTE_LIBRTE_IEEE1588
225	struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
226	struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
227
228#ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
229	/* whithout rx ol_flags, no VP flag report */
230	if (rxmode->hw_vlan_strip != 0 ||
231	    rxmode->hw_vlan_extend != 0 ||
232	    rxmode->hw_ip_checksum != 0)
233		return -1;
234#endif
235
236	/* no fdir support */
237	if (fconf->mode != RTE_FDIR_MODE_NONE)
238		return -1;
239
240	 /* - no csum error report support
241	 * - no header split support
242	 */
243	if (rxmode->header_split == 1)
244		return -1;
245
246	/* no QinQ support */
247	if (rxmode->hw_vlan_extend == 1)
248		return -1;
249
250	return 0;
251#else
252	RTE_SET_USED(dev);
253	return -1;
254#endif
255}
256#endif
257