1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   Copyright(c) 2016, Linaro Limited
6 *   All rights reserved.
7 *
8 *   Redistribution and use in source and binary forms, with or without
9 *   modification, are permitted provided that the following conditions
10 *   are met:
11 *
12 *     * Redistributions of source code must retain the above copyright
13 *       notice, this list of conditions and the following disclaimer.
14 *     * Redistributions in binary form must reproduce the above copyright
15 *       notice, this list of conditions and the following disclaimer in
16 *       the documentation and/or other materials provided with the
17 *       distribution.
18 *     * Neither the name of Intel Corporation nor the names of its
19 *       contributors may be used to endorse or promote products derived
20 *       from this software without specific prior written permission.
21 *
22 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <stdint.h>
36#include <rte_ethdev.h>
37#include <rte_malloc.h>
38
39#include "base/i40e_prototype.h"
40#include "base/i40e_type.h"
41#include "i40e_ethdev.h"
42#include "i40e_rxtx.h"
43#include "i40e_rxtx_vec_common.h"
44
45#include <arm_neon.h>
46
47#pragma GCC diagnostic ignored "-Wcast-qual"
48
49static inline void
50i40e_rxq_rearm(struct i40e_rx_queue *rxq)
51{
52	int i;
53	uint16_t rx_id;
54	volatile union i40e_rx_desc *rxdp;
55	struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
56	struct rte_mbuf *mb0, *mb1;
57	uint64x2_t dma_addr0, dma_addr1;
58	uint64x2_t zero = vdupq_n_u64(0);
59	uint64_t paddr;
60	uint8x8_t p;
61
62	rxdp = rxq->rx_ring + rxq->rxrearm_start;
63
64	/* Pull 'n' more MBUFs into the software ring */
65	if (unlikely(rte_mempool_get_bulk(rxq->mp,
66					  (void *)rxep,
67					  RTE_I40E_RXQ_REARM_THRESH) < 0)) {
68		if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
69		    rxq->nb_rx_desc) {
70			for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
71				rxep[i].mbuf = &rxq->fake_mbuf;
72				vst1q_u64((uint64_t *)&rxdp[i].read, zero);
73			}
74		}
75		rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
76			RTE_I40E_RXQ_REARM_THRESH;
77		return;
78	}
79
80	p = vld1_u8((uint8_t *)&rxq->mbuf_initializer);
81
82	/* Initialize the mbufs in vector, process 2 mbufs in one loop */
83	for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84		mb0 = rxep[0].mbuf;
85		mb1 = rxep[1].mbuf;
86
87		 /* Flush mbuf with pkt template.
88		 * Data to be rearmed is 6 bytes long.
89		 * Though, RX will overwrite ol_flags that are coming next
90		 * anyway. So overwrite whole 8 bytes with one load:
91		 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
92		 */
93		vst1_u8((uint8_t *)&mb0->rearm_data, p);
94		paddr = mb0->buf_physaddr + RTE_PKTMBUF_HEADROOM;
95		dma_addr0 = vdupq_n_u64(paddr);
96
97		/* flush desc with pa dma_addr */
98		vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
99
100		vst1_u8((uint8_t *)&mb1->rearm_data, p);
101		paddr = mb1->buf_physaddr + RTE_PKTMBUF_HEADROOM;
102		dma_addr1 = vdupq_n_u64(paddr);
103		vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
104	}
105
106	rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
107	if (rxq->rxrearm_start >= rxq->nb_rx_desc)
108		rxq->rxrearm_start = 0;
109
110	rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
111
112	rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
113			     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
114
115	/* Update the tail pointer on the NIC */
116	I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
117}
118
119/* Handling the offload flags (olflags) field takes computation
120 * time when receiving packets. Therefore we provide a flag to disable
121 * the processing of the olflags field when they are not needed. This
122 * gives improved performance, at the cost of losing the offload info
123 * in the received packet
124 */
125#ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
126
127static inline void
128desc_to_olflags_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
129{
130	uint32x4_t vlan0, vlan1, rss, l3_l4e;
131
132	/* mask everything except RSS, flow director and VLAN flags
133	 * bit2 is for VLAN tag, bit11 for flow director indication
134	 * bit13:12 for RSS indication.
135	 */
136	const uint32x4_t rss_vlan_msk = {
137			0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
138
139	/* map rss and vlan type to rss hash and vlan flag */
140	const uint8x16_t vlan_flags = {
141			0, 0, 0, 0,
142			PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
143			0, 0, 0, 0,
144			0, 0, 0, 0};
145
146	const uint8x16_t rss_flags = {
147			0, PKT_RX_FDIR, 0, 0,
148			0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR,
149			0, 0, 0, 0,
150			0, 0, 0, 0};
151
152	const uint8x16_t l3_l4e_flags = {
153			0,
154			PKT_RX_IP_CKSUM_BAD,
155			PKT_RX_L4_CKSUM_BAD,
156			PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
157			PKT_RX_EIP_CKSUM_BAD,
158			PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
159			PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
160			PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
161			0, 0, 0, 0, 0, 0, 0, 0};
162
163	vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
164			  vreinterpretq_u32_u64(descs[2])).val[1];
165	vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
166			  vreinterpretq_u32_u64(descs[3])).val[1];
167	vlan0 = vzipq_u32(vlan0, vlan1).val[0];
168
169	vlan1 = vandq_u32(vlan0, rss_vlan_msk);
170	vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
171						vreinterpretq_u8_u32(vlan1)));
172
173	rss = vshrq_n_u32(vlan1, 11);
174	rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
175					      vreinterpretq_u8_u32(rss)));
176
177	l3_l4e = vshrq_n_u32(vlan1, 22);
178	l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
179					      vreinterpretq_u8_u32(l3_l4e)));
180
181
182	vlan0 = vorrq_u32(vlan0, rss);
183	vlan0 = vorrq_u32(vlan0, l3_l4e);
184
185	rx_pkts[0]->ol_flags = vgetq_lane_u32(vlan0, 0);
186	rx_pkts[1]->ol_flags = vgetq_lane_u32(vlan0, 1);
187	rx_pkts[2]->ol_flags = vgetq_lane_u32(vlan0, 2);
188	rx_pkts[3]->ol_flags = vgetq_lane_u32(vlan0, 3);
189}
190#else
191#define desc_to_olflags_v(descs, rx_pkts) do {} while (0)
192#endif
193
194#define PKTLEN_SHIFT     10
195#define I40E_UINT16_BIT (CHAR_BIT * sizeof(uint16_t))
196
197static inline void
198desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
199{
200	int i;
201	uint8_t ptype;
202	uint8x16_t tmp;
203
204	for (i = 0; i < 4; i++) {
205		tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
206		ptype = vgetq_lane_u8(tmp, 8);
207		rx_pkts[i]->packet_type = i40e_rxd_pkt_type_mapping(ptype);
208	}
209
210}
211
212 /*
213 * Notice:
214 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
215 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
216 *   numbers of DD bits
217 */
218static inline uint16_t
219_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
220		   uint16_t nb_pkts, uint8_t *split_packet)
221{
222	volatile union i40e_rx_desc *rxdp;
223	struct i40e_rx_entry *sw_ring;
224	uint16_t nb_pkts_recd;
225	int pos;
226
227	/* mask to shuffle from desc. to mbuf */
228	uint8x16_t shuf_msk = {
229		0xFF, 0xFF,   /* pkt_type set as unknown */
230		0xFF, 0xFF,   /* pkt_type set as unknown */
231		14, 15,       /* octet 15~14, low 16 bits pkt_len */
232		0xFF, 0xFF,   /* skip high 16 bits pkt_len, zero out */
233		14, 15,       /* octet 15~14, 16 bits data_len */
234		2, 3,         /* octet 2~3, low 16 bits vlan_macip */
235		4, 5, 6, 7    /* octet 4~7, 32bits rss */
236		};
237
238	uint8x16_t eop_check = {
239		0x02, 0x00, 0x02, 0x00,
240		0x02, 0x00, 0x02, 0x00,
241		0x00, 0x00, 0x00, 0x00,
242		0x00, 0x00, 0x00, 0x00
243		};
244
245	uint16x8_t crc_adjust = {
246		0, 0,         /* ignore pkt_type field */
247		rxq->crc_len, /* sub crc on pkt_len */
248		0,            /* ignore high-16bits of pkt_len */
249		rxq->crc_len, /* sub crc on data_len */
250		0, 0, 0       /* ignore non-length fields */
251		};
252
253	/* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
254	nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
255
256	/* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
257	nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
258
259	/* Just the act of getting into the function from the application is
260	 * going to cost about 7 cycles
261	 */
262	rxdp = rxq->rx_ring + rxq->rx_tail;
263
264	rte_prefetch_non_temporal(rxdp);
265
266	/* See if we need to rearm the RX queue - gives the prefetch a bit
267	 * of time to act
268	 */
269	if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
270		i40e_rxq_rearm(rxq);
271
272	/* Before we start moving massive data around, check to see if
273	 * there is actually a packet available
274	 */
275	if (!(rxdp->wb.qword1.status_error_len &
276			rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
277		return 0;
278
279	/* Cache is empty -> need to scan the buffer rings, but first move
280	 * the next 'n' mbufs into the cache
281	 */
282	sw_ring = &rxq->sw_ring[rxq->rx_tail];
283
284	/* A. load 4 packet in one loop
285	 * [A*. mask out 4 unused dirty field in desc]
286	 * B. copy 4 mbuf point from swring to rx_pkts
287	 * C. calc the number of DD bits among the 4 packets
288	 * [C*. extract the end-of-packet bit, if requested]
289	 * D. fill info. from desc to mbuf
290	 */
291
292	for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
293			pos += RTE_I40E_DESCS_PER_LOOP,
294			rxdp += RTE_I40E_DESCS_PER_LOOP) {
295		uint64x2_t descs[RTE_I40E_DESCS_PER_LOOP];
296		uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
297		uint16x8x2_t sterr_tmp1, sterr_tmp2;
298		uint64x2_t mbp1, mbp2;
299		uint16x8_t staterr;
300		uint16x8_t tmp;
301		uint64_t stat;
302
303		int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
304
305		/* B.1 load 1 mbuf point */
306		mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
307		/* Read desc statuses backwards to avoid race condition */
308		/* A.1 load 4 pkts desc */
309		descs[3] =  vld1q_u64((uint64_t *)(rxdp + 3));
310		rte_rmb();
311
312		/* B.2 copy 2 mbuf point into rx_pkts  */
313		vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
314
315		/* B.1 load 1 mbuf point */
316		mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
317
318		descs[2] =  vld1q_u64((uint64_t *)(rxdp + 2));
319		/* B.1 load 2 mbuf point */
320		descs[1] =  vld1q_u64((uint64_t *)(rxdp + 1));
321		descs[0] =  vld1q_u64((uint64_t *)(rxdp));
322
323		/* B.2 copy 2 mbuf point into rx_pkts  */
324		vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
325
326		if (split_packet) {
327			rte_mbuf_prefetch_part2(rx_pkts[pos]);
328			rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
329			rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
330			rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
331		}
332
333		/* avoid compiler reorder optimization */
334		rte_compiler_barrier();
335
336		/* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
337		uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
338					    len_shl);
339		descs[3] = vreinterpretq_u64_u32(len3);
340		uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
341					    len_shl);
342		descs[2] = vreinterpretq_u64_u32(len2);
343
344		/* D.1 pkt 3,4 convert format from desc to pktmbuf */
345		pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
346		pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
347
348		/* C.1 4=>2 filter staterr info only */
349		sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
350				       vreinterpretq_u16_u64(descs[3]));
351		/* C.1 4=>2 filter staterr info only */
352		sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
353				       vreinterpretq_u16_u64(descs[2]));
354
355		/* C.2 get 4 pkts staterr value  */
356		staterr = vzipq_u16(sterr_tmp1.val[1],
357				    sterr_tmp2.val[1]).val[0];
358
359		desc_to_olflags_v(descs, &rx_pkts[pos]);
360
361		/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
362		tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
363		pkt_mb4 = vreinterpretq_u8_u16(tmp);
364		tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
365		pkt_mb3 = vreinterpretq_u8_u16(tmp);
366
367		/* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
368		uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
369					    len_shl);
370		descs[1] = vreinterpretq_u64_u32(len1);
371		uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
372					    len_shl);
373		descs[0] = vreinterpretq_u64_u32(len0);
374
375		/* D.1 pkt 1,2 convert format from desc to pktmbuf */
376		pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
377		pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
378
379		/* D.3 copy final 3,4 data to rx_pkts */
380		vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
381				 pkt_mb4);
382		vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
383				 pkt_mb3);
384
385		/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
386		tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
387		pkt_mb2 = vreinterpretq_u8_u16(tmp);
388		tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
389		pkt_mb1 = vreinterpretq_u8_u16(tmp);
390
391		/* C* extract and record EOP bit */
392		if (split_packet) {
393			uint8x16_t eop_shuf_mask = {
394					0x00, 0x02, 0x04, 0x06,
395					0xFF, 0xFF, 0xFF, 0xFF,
396					0xFF, 0xFF, 0xFF, 0xFF,
397					0xFF, 0xFF, 0xFF, 0xFF};
398			uint8x16_t eop_bits;
399
400			/* and with mask to extract bits, flipping 1-0 */
401			eop_bits = vmvnq_u8(vreinterpretq_u8_u16(staterr));
402			eop_bits = vandq_u8(eop_bits, eop_check);
403			/* the staterr values are not in order, as the count
404			 * count of dd bits doesn't care. However, for end of
405			 * packet tracking, we do care, so shuffle. This also
406			 * compresses the 32-bit values to 8-bit
407			 */
408			eop_bits = vqtbl1q_u8(eop_bits, eop_shuf_mask);
409
410			/* store the resulting 32-bit value */
411			vst1q_lane_u32((uint32_t *)split_packet,
412				       vreinterpretq_u32_u8(eop_bits), 0);
413			split_packet += RTE_I40E_DESCS_PER_LOOP;
414
415			/* zero-out next pointers */
416			rx_pkts[pos]->next = NULL;
417			rx_pkts[pos + 1]->next = NULL;
418			rx_pkts[pos + 2]->next = NULL;
419			rx_pkts[pos + 3]->next = NULL;
420		}
421
422		staterr = vshlq_n_u16(staterr, I40E_UINT16_BIT - 1);
423		staterr = vreinterpretq_u16_s16(
424				vshrq_n_s16(vreinterpretq_s16_u16(staterr),
425					    I40E_UINT16_BIT - 1));
426		stat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
427
428		rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
429
430		/* D.3 copy final 1,2 data to rx_pkts */
431		vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
432			 pkt_mb2);
433		vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
434			 pkt_mb1);
435		desc_to_ptype_v(descs, &rx_pkts[pos]);
436		/* C.4 calc avaialbe number of desc */
437		if (unlikely(stat == 0)) {
438			nb_pkts_recd += RTE_I40E_DESCS_PER_LOOP;
439		} else {
440			nb_pkts_recd += __builtin_ctzl(stat) / I40E_UINT16_BIT;
441			break;
442		}
443	}
444
445	/* Update our internal tail pointer */
446	rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
447	rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
448	rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
449
450	return nb_pkts_recd;
451}
452
453 /*
454 * Notice:
455 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
456 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
457 *   numbers of DD bits
458 */
459uint16_t
460i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
461		   uint16_t nb_pkts)
462{
463	return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
464}
465
466 /* vPMD receive routine that reassembles scattered packets
467 * Notice:
468 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
469 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
470 *   numbers of DD bits
471 */
472uint16_t
473i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
474			     uint16_t nb_pkts)
475{
476
477	struct i40e_rx_queue *rxq = rx_queue;
478	uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
479
480	/* get some new buffers */
481	uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
482			split_flags);
483	if (nb_bufs == 0)
484		return 0;
485
486	/* happy day case, full burst + no packets to be joined */
487	const uint64_t *split_fl64 = (uint64_t *)split_flags;
488
489	if (rxq->pkt_first_seg == NULL &&
490			split_fl64[0] == 0 && split_fl64[1] == 0 &&
491			split_fl64[2] == 0 && split_fl64[3] == 0)
492		return nb_bufs;
493
494	/* reassemble any packets that need reassembly*/
495	unsigned i = 0;
496
497	if (rxq->pkt_first_seg == NULL) {
498		/* find the first split flag, and only reassemble then*/
499		while (i < nb_bufs && !split_flags[i])
500			i++;
501		if (i == nb_bufs)
502			return nb_bufs;
503	}
504	return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
505		&split_flags[i]);
506}
507
508static inline void
509vtx1(volatile struct i40e_tx_desc *txdp,
510		struct rte_mbuf *pkt, uint64_t flags)
511{
512	uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
513			((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
514			((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
515
516	uint64x2_t descriptor = {pkt->buf_physaddr + pkt->data_off, high_qw};
517	vst1q_u64((uint64_t *)txdp, descriptor);
518}
519
520static inline void
521vtx(volatile struct i40e_tx_desc *txdp,
522		struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
523{
524	int i;
525
526	for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
527		vtx1(txdp, *pkt, flags);
528}
529
530uint16_t
531i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
532		   uint16_t nb_pkts)
533{
534	struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
535	volatile struct i40e_tx_desc *txdp;
536	struct i40e_tx_entry *txep;
537	uint16_t n, nb_commit, tx_id;
538	uint64_t flags = I40E_TD_CMD;
539	uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
540	int i;
541
542	/* cross rx_thresh boundary is not allowed */
543	nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
544
545	if (txq->nb_tx_free < txq->tx_free_thresh)
546		i40e_tx_free_bufs(txq);
547
548	nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
549	if (unlikely(nb_pkts == 0))
550		return 0;
551
552	tx_id = txq->tx_tail;
553	txdp = &txq->tx_ring[tx_id];
554	txep = &txq->sw_ring[tx_id];
555
556	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
557
558	n = (uint16_t)(txq->nb_tx_desc - tx_id);
559	if (nb_commit >= n) {
560		tx_backlog_entry(txep, tx_pkts, n);
561
562		for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
563			vtx1(txdp, *tx_pkts, flags);
564
565		vtx1(txdp, *tx_pkts++, rs);
566
567		nb_commit = (uint16_t)(nb_commit - n);
568
569		tx_id = 0;
570		txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
571
572		/* avoid reach the end of ring */
573		txdp = &txq->tx_ring[tx_id];
574		txep = &txq->sw_ring[tx_id];
575	}
576
577	tx_backlog_entry(txep, tx_pkts, nb_commit);
578
579	vtx(txdp, tx_pkts, nb_commit, flags);
580
581	tx_id = (uint16_t)(tx_id + nb_commit);
582	if (tx_id > txq->tx_next_rs) {
583		txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
584			rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
585						I40E_TXD_QW1_CMD_SHIFT);
586		txq->tx_next_rs =
587			(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
588	}
589
590	txq->tx_tail = tx_id;
591
592	I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
593
594	return nb_pkts;
595}
596
597void __attribute__((cold))
598i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
599{
600	_i40e_rx_queue_release_mbufs_vec(rxq);
601}
602
603int __attribute__((cold))
604i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
605{
606	return i40e_rxq_vec_setup_default(rxq);
607}
608
609int __attribute__((cold))
610i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
611{
612	return 0;
613}
614
615int __attribute__((cold))
616i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
617{
618	return i40e_rx_vec_dev_conf_condition_check_default(dev);
619}
620