1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <stdint.h>
35#include <rte_ethdev.h>
36#include <rte_malloc.h>
37
38#include "ixgbe_ethdev.h"
39#include "ixgbe_rxtx.h"
40#include "ixgbe_rxtx_vec_common.h"
41
42#include <tmmintrin.h>
43
44#ifndef __INTEL_COMPILER
45#pragma GCC diagnostic ignored "-Wcast-qual"
46#endif
47
48static inline void
49ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
50{
51	int i;
52	uint16_t rx_id;
53	volatile union ixgbe_adv_rx_desc *rxdp;
54	struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55	struct rte_mbuf *mb0, *mb1;
56	__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57			RTE_PKTMBUF_HEADROOM);
58	__m128i dma_addr0, dma_addr1;
59
60	const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
61
62	rxdp = rxq->rx_ring + rxq->rxrearm_start;
63
64	/* Pull 'n' more MBUFs into the software ring */
65	if (rte_mempool_get_bulk(rxq->mb_pool,
66				 (void *)rxep,
67				 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68		if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
69		    rxq->nb_rx_desc) {
70			dma_addr0 = _mm_setzero_si128();
71			for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72				rxep[i].mbuf = &rxq->fake_mbuf;
73				_mm_store_si128((__m128i *)&rxdp[i].read,
74						dma_addr0);
75			}
76		}
77		rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78			RTE_IXGBE_RXQ_REARM_THRESH;
79		return;
80	}
81
82	/* Initialize the mbufs in vector, process 2 mbufs in one loop */
83	for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84		__m128i vaddr0, vaddr1;
85		uintptr_t p0, p1;
86
87		mb0 = rxep[0].mbuf;
88		mb1 = rxep[1].mbuf;
89
90		/*
91		 * Flush mbuf with pkt template.
92		 * Data to be rearmed is 6 bytes long.
93		 * Though, RX will overwrite ol_flags that are coming next
94		 * anyway. So overwrite whole 8 bytes with one load:
95		 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
96		 */
97		p0 = (uintptr_t)&mb0->rearm_data;
98		*(uint64_t *)p0 = rxq->mbuf_initializer;
99		p1 = (uintptr_t)&mb1->rearm_data;
100		*(uint64_t *)p1 = rxq->mbuf_initializer;
101
102		/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
103		vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
104		vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
105
106		/* convert pa to dma_addr hdr/data */
107		dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
108		dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
109
110		/* add headroom to pa values */
111		dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
112		dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
113
114		/* set Header Buffer Address to zero */
115		dma_addr0 =  _mm_and_si128(dma_addr0, hba_msk);
116		dma_addr1 =  _mm_and_si128(dma_addr1, hba_msk);
117
118		/* flush desc with pa dma_addr */
119		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
120		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
121	}
122
123	rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
124	if (rxq->rxrearm_start >= rxq->nb_rx_desc)
125		rxq->rxrearm_start = 0;
126
127	rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
128
129	rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
130			     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131
132	/* Update the tail pointer on the NIC */
133	IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
134}
135
136/* Handling the offload flags (olflags) field takes computation
137 * time when receiving packets. Therefore we provide a flag to disable
138 * the processing of the olflags field when they are not needed. This
139 * gives improved performance, at the cost of losing the offload info
140 * in the received packet
141 */
142#ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
143
144static inline void
145desc_to_olflags_v(__m128i descs[4], uint8_t vlan_flags,
146	struct rte_mbuf **rx_pkts)
147{
148	__m128i ptype0, ptype1, vtag0, vtag1, csum;
149	union {
150		uint16_t e[4];
151		uint64_t dword;
152	} vol;
153
154	/* mask everything except rss type */
155	const __m128i rsstype_msk = _mm_set_epi16(
156			0x0000, 0x0000, 0x0000, 0x0000,
157			0x000F, 0x000F, 0x000F, 0x000F);
158
159	/* mask the lower byte of ol_flags */
160	const __m128i ol_flags_msk = _mm_set_epi16(
161			0x0000, 0x0000, 0x0000, 0x0000,
162			0x00FF, 0x00FF, 0x00FF, 0x00FF);
163
164	/* map rss type to rss hash flag */
165	const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
166			0, 0, 0, PKT_RX_RSS_HASH,
167			PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
168			PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
169
170	/* mask everything except vlan present and l4/ip csum error */
171	const __m128i vlan_csum_msk = _mm_set_epi16(
172		(IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
173		(IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
174		(IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
175		(IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
176		IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
177		IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
178	/* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
179	const __m128i vlan_csum_map_lo = _mm_set_epi8(
180		0, 0, 0, 0,
181		vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
182		vlan_flags | PKT_RX_IP_CKSUM_BAD,
183		vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
184		vlan_flags | PKT_RX_IP_CKSUM_GOOD,
185		0, 0, 0, 0,
186		PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
187		PKT_RX_IP_CKSUM_BAD,
188		PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
189		PKT_RX_IP_CKSUM_GOOD);
190
191	const __m128i vlan_csum_map_hi = _mm_set_epi8(
192		0, 0, 0, 0,
193		0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
194		PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t),
195		0, 0, 0, 0,
196		0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
197		PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t));
198
199	ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
200	ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
201	vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
202	vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
203
204	ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
205	ptype0 = _mm_and_si128(ptype0, rsstype_msk);
206	ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
207
208	vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
209	vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
210
211	/* csum bits are in the most significant, to use shuffle we need to
212	 * shift them. Change mask to 0xc000 to 0x0003.
213	 */
214	csum = _mm_srli_epi16(vtag1, 14);
215
216	/* now or the most significant 64 bits containing the checksum
217	 * flags with the vlan present flags.
218	 */
219	csum = _mm_srli_si128(csum, 8);
220	vtag1 = _mm_or_si128(csum, vtag1);
221
222	/* convert VP, IPE, L4E to ol_flags */
223	vtag0 = _mm_shuffle_epi8(vlan_csum_map_hi, vtag1);
224	vtag0 = _mm_slli_epi16(vtag0, sizeof(uint8_t));
225
226	vtag1 = _mm_shuffle_epi8(vlan_csum_map_lo, vtag1);
227	vtag1 = _mm_and_si128(vtag1, ol_flags_msk);
228	vtag1 = _mm_or_si128(vtag0, vtag1);
229
230	vtag1 = _mm_or_si128(ptype0, vtag1);
231	vol.dword = _mm_cvtsi128_si64(vtag1);
232
233	rx_pkts[0]->ol_flags = vol.e[0];
234	rx_pkts[1]->ol_flags = vol.e[1];
235	rx_pkts[2]->ol_flags = vol.e[2];
236	rx_pkts[3]->ol_flags = vol.e[3];
237}
238#else
239#define desc_to_olflags_v(desc, vlan_flags, rx_pkts) do { \
240		RTE_SET_USED(vlan_flags); \
241	} while (0)
242#endif
243
244/*
245 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
246 *
247 * Notice:
248 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
249 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
250 *   numbers of DD bit
251 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
252 */
253static inline uint16_t
254_recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
255		uint16_t nb_pkts, uint8_t *split_packet)
256{
257	volatile union ixgbe_adv_rx_desc *rxdp;
258	struct ixgbe_rx_entry *sw_ring;
259	uint16_t nb_pkts_recd;
260	int pos;
261	uint64_t var;
262	__m128i shuf_msk;
263	__m128i crc_adjust = _mm_set_epi16(
264				0, 0, 0,    /* ignore non-length fields */
265				-rxq->crc_len, /* sub crc on data_len */
266				0,          /* ignore high-16bits of pkt_len */
267				-rxq->crc_len, /* sub crc on pkt_len */
268				0, 0            /* ignore pkt_type field */
269			);
270	__m128i dd_check, eop_check;
271	uint8_t vlan_flags;
272
273	/* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
274	nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
275
276	/* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
277	nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
278
279	/* Just the act of getting into the function from the application is
280	 * going to cost about 7 cycles
281	 */
282	rxdp = rxq->rx_ring + rxq->rx_tail;
283
284	rte_prefetch0(rxdp);
285
286	/* See if we need to rearm the RX queue - gives the prefetch a bit
287	 * of time to act
288	 */
289	if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
290		ixgbe_rxq_rearm(rxq);
291
292	/* Before we start moving massive data around, check to see if
293	 * there is actually a packet available
294	 */
295	if (!(rxdp->wb.upper.status_error &
296				rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
297		return 0;
298
299	/* 4 packets DD mask */
300	dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
301
302	/* 4 packets EOP mask */
303	eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
304
305	/* mask to shuffle from desc. to mbuf */
306	shuf_msk = _mm_set_epi8(
307		7, 6, 5, 4,  /* octet 4~7, 32bits rss */
308		15, 14,      /* octet 14~15, low 16 bits vlan_macip */
309		13, 12,      /* octet 12~13, 16 bits data_len */
310		0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
311		13, 12,      /* octet 12~13, low 16 bits pkt_len */
312		0xFF, 0xFF,  /* skip 32 bit pkt_type */
313		0xFF, 0xFF
314		);
315
316	/* Cache is empty -> need to scan the buffer rings, but first move
317	 * the next 'n' mbufs into the cache
318	 */
319	sw_ring = &rxq->sw_ring[rxq->rx_tail];
320
321	/* ensure these 2 flags are in the lower 8 bits */
322	RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
323	vlan_flags = rxq->vlan_flags & UINT8_MAX;
324
325	/* A. load 4 packet in one loop
326	 * [A*. mask out 4 unused dirty field in desc]
327	 * B. copy 4 mbuf point from swring to rx_pkts
328	 * C. calc the number of DD bits among the 4 packets
329	 * [C*. extract the end-of-packet bit, if requested]
330	 * D. fill info. from desc to mbuf
331	 */
332	for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
333			pos += RTE_IXGBE_DESCS_PER_LOOP,
334			rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
335		__m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
336		__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
337		__m128i zero, staterr, sterr_tmp1, sterr_tmp2;
338		/* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
339		__m128i mbp1;
340#if defined(RTE_ARCH_X86_64)
341		__m128i mbp2;
342#endif
343
344		/* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
345		mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
346
347		/* Read desc statuses backwards to avoid race condition */
348		/* A.1 load 4 pkts desc */
349		descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
350		rte_compiler_barrier();
351
352		/* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
353		_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
354
355#if defined(RTE_ARCH_X86_64)
356		/* B.1 load 2 64 bit mbuf points */
357		mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
358#endif
359
360		descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
361		rte_compiler_barrier();
362		/* B.1 load 2 mbuf point */
363		descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
364		rte_compiler_barrier();
365		descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
366
367#if defined(RTE_ARCH_X86_64)
368		/* B.2 copy 2 mbuf point into rx_pkts  */
369		_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
370#endif
371
372		if (split_packet) {
373			rte_mbuf_prefetch_part2(rx_pkts[pos]);
374			rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
375			rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
376			rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
377		}
378
379		/* avoid compiler reorder optimization */
380		rte_compiler_barrier();
381
382		/* D.1 pkt 3,4 convert format from desc to pktmbuf */
383		pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
384		pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
385
386		/* D.1 pkt 1,2 convert format from desc to pktmbuf */
387		pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
388		pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
389
390		/* C.1 4=>2 filter staterr info only */
391		sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
392		/* C.1 4=>2 filter staterr info only */
393		sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
394
395		/* set ol_flags with vlan packet type */
396		desc_to_olflags_v(descs, vlan_flags, &rx_pkts[pos]);
397
398		/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
399		pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
400		pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
401
402		/* C.2 get 4 pkts staterr value  */
403		zero = _mm_xor_si128(dd_check, dd_check);
404		staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
405
406		/* D.3 copy final 3,4 data to rx_pkts */
407		_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
408				pkt_mb4);
409		_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
410				pkt_mb3);
411
412		/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
413		pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
414		pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
415
416		/* C* extract and record EOP bit */
417		if (split_packet) {
418			__m128i eop_shuf_mask = _mm_set_epi8(
419					0xFF, 0xFF, 0xFF, 0xFF,
420					0xFF, 0xFF, 0xFF, 0xFF,
421					0xFF, 0xFF, 0xFF, 0xFF,
422					0x04, 0x0C, 0x00, 0x08
423					);
424
425			/* and with mask to extract bits, flipping 1-0 */
426			__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
427			/* the staterr values are not in order, as the count
428			 * count of dd bits doesn't care. However, for end of
429			 * packet tracking, we do care, so shuffle. This also
430			 * compresses the 32-bit values to 8-bit
431			 */
432			eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
433			/* store the resulting 32-bit value */
434			*(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
435			split_packet += RTE_IXGBE_DESCS_PER_LOOP;
436
437			/* zero-out next pointers */
438			rx_pkts[pos]->next = NULL;
439			rx_pkts[pos + 1]->next = NULL;
440			rx_pkts[pos + 2]->next = NULL;
441			rx_pkts[pos + 3]->next = NULL;
442		}
443
444		/* C.3 calc available number of desc */
445		staterr = _mm_and_si128(staterr, dd_check);
446		staterr = _mm_packs_epi32(staterr, zero);
447
448		/* D.3 copy final 1,2 data to rx_pkts */
449		_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
450				pkt_mb2);
451		_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
452				pkt_mb1);
453
454		/* C.4 calc avaialbe number of desc */
455		var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
456		nb_pkts_recd += var;
457		if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
458			break;
459	}
460
461	/* Update our internal tail pointer */
462	rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
463	rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
464	rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
465
466	return nb_pkts_recd;
467}
468
469/*
470 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
471 *
472 * Notice:
473 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
474 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
475 *   numbers of DD bit
476 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
477 */
478uint16_t
479ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
480		uint16_t nb_pkts)
481{
482	return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
483}
484
485/*
486 * vPMD receive routine that reassembles scattered packets
487 *
488 * Notice:
489 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
490 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
491 *   numbers of DD bit
492 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
493 */
494uint16_t
495ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
496		uint16_t nb_pkts)
497{
498	struct ixgbe_rx_queue *rxq = rx_queue;
499	uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
500
501	/* get some new buffers */
502	uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
503			split_flags);
504	if (nb_bufs == 0)
505		return 0;
506
507	/* happy day case, full burst + no packets to be joined */
508	const uint64_t *split_fl64 = (uint64_t *)split_flags;
509	if (rxq->pkt_first_seg == NULL &&
510			split_fl64[0] == 0 && split_fl64[1] == 0 &&
511			split_fl64[2] == 0 && split_fl64[3] == 0)
512		return nb_bufs;
513
514	/* reassemble any packets that need reassembly*/
515	unsigned i = 0;
516	if (rxq->pkt_first_seg == NULL) {
517		/* find the first split flag, and only reassemble then*/
518		while (i < nb_bufs && !split_flags[i])
519			i++;
520		if (i == nb_bufs)
521			return nb_bufs;
522	}
523	return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
524		&split_flags[i]);
525}
526
527static inline void
528vtx1(volatile union ixgbe_adv_tx_desc *txdp,
529		struct rte_mbuf *pkt, uint64_t flags)
530{
531	__m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
532			flags | pkt->data_len,
533			pkt->buf_physaddr + pkt->data_off);
534	_mm_store_si128((__m128i *)&txdp->read, descriptor);
535}
536
537static inline void
538vtx(volatile union ixgbe_adv_tx_desc *txdp,
539		struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
540{
541	int i;
542
543	for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
544		vtx1(txdp, *pkt, flags);
545}
546
547uint16_t
548ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
549		       uint16_t nb_pkts)
550{
551	struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
552	volatile union ixgbe_adv_tx_desc *txdp;
553	struct ixgbe_tx_entry_v *txep;
554	uint16_t n, nb_commit, tx_id;
555	uint64_t flags = DCMD_DTYP_FLAGS;
556	uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
557	int i;
558
559	/* cross rx_thresh boundary is not allowed */
560	nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
561
562	if (txq->nb_tx_free < txq->tx_free_thresh)
563		ixgbe_tx_free_bufs(txq);
564
565	nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
566	if (unlikely(nb_pkts == 0))
567		return 0;
568
569	tx_id = txq->tx_tail;
570	txdp = &txq->tx_ring[tx_id];
571	txep = &txq->sw_ring_v[tx_id];
572
573	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
574
575	n = (uint16_t)(txq->nb_tx_desc - tx_id);
576	if (nb_commit >= n) {
577
578		tx_backlog_entry(txep, tx_pkts, n);
579
580		for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
581			vtx1(txdp, *tx_pkts, flags);
582
583		vtx1(txdp, *tx_pkts++, rs);
584
585		nb_commit = (uint16_t)(nb_commit - n);
586
587		tx_id = 0;
588		txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
589
590		/* avoid reach the end of ring */
591		txdp = &(txq->tx_ring[tx_id]);
592		txep = &txq->sw_ring_v[tx_id];
593	}
594
595	tx_backlog_entry(txep, tx_pkts, nb_commit);
596
597	vtx(txdp, tx_pkts, nb_commit, flags);
598
599	tx_id = (uint16_t)(tx_id + nb_commit);
600	if (tx_id > txq->tx_next_rs) {
601		txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
602			rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
603		txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
604			txq->tx_rs_thresh);
605	}
606
607	txq->tx_tail = tx_id;
608
609	IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
610
611	return nb_pkts;
612}
613
614static void __attribute__((cold))
615ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
616{
617	_ixgbe_tx_queue_release_mbufs_vec(txq);
618}
619
620void __attribute__((cold))
621ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
622{
623	_ixgbe_rx_queue_release_mbufs_vec(rxq);
624}
625
626static void __attribute__((cold))
627ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
628{
629	_ixgbe_tx_free_swring_vec(txq);
630}
631
632static void __attribute__((cold))
633ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
634{
635	_ixgbe_reset_tx_queue_vec(txq);
636}
637
638static const struct ixgbe_txq_ops vec_txq_ops = {
639	.release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
640	.free_swring = ixgbe_tx_free_swring,
641	.reset = ixgbe_reset_tx_queue,
642};
643
644int __attribute__((cold))
645ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
646{
647	return ixgbe_rxq_vec_setup_default(rxq);
648}
649
650int __attribute__((cold))
651ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
652{
653	return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
654}
655
656int __attribute__((cold))
657ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
658{
659	return ixgbe_rx_vec_dev_conf_condition_check_default(dev);
660}
661