ixgbe_rxtx_vec_sse.c revision c300e355
1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <stdint.h>
35#include <rte_ethdev.h>
36#include <rte_malloc.h>
37
38#include "ixgbe_ethdev.h"
39#include "ixgbe_rxtx.h"
40#include "ixgbe_rxtx_vec_common.h"
41
42#include <tmmintrin.h>
43
44#ifndef __INTEL_COMPILER
45#pragma GCC diagnostic ignored "-Wcast-qual"
46#endif
47
48static inline void
49ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
50{
51	int i;
52	uint16_t rx_id;
53	volatile union ixgbe_adv_rx_desc *rxdp;
54	struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55	struct rte_mbuf *mb0, *mb1;
56	__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57			RTE_PKTMBUF_HEADROOM);
58	__m128i dma_addr0, dma_addr1;
59
60	const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
61
62	rxdp = rxq->rx_ring + rxq->rxrearm_start;
63
64	/* Pull 'n' more MBUFs into the software ring */
65	if (rte_mempool_get_bulk(rxq->mb_pool,
66				 (void *)rxep,
67				 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68		if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
69		    rxq->nb_rx_desc) {
70			dma_addr0 = _mm_setzero_si128();
71			for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72				rxep[i].mbuf = &rxq->fake_mbuf;
73				_mm_store_si128((__m128i *)&rxdp[i].read,
74						dma_addr0);
75			}
76		}
77		rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78			RTE_IXGBE_RXQ_REARM_THRESH;
79		return;
80	}
81
82	/* Initialize the mbufs in vector, process 2 mbufs in one loop */
83	for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84		__m128i vaddr0, vaddr1;
85		uintptr_t p0, p1;
86
87		mb0 = rxep[0].mbuf;
88		mb1 = rxep[1].mbuf;
89
90		/*
91		 * Flush mbuf with pkt template.
92		 * Data to be rearmed is 6 bytes long.
93		 * Though, RX will overwrite ol_flags that are coming next
94		 * anyway. So overwrite whole 8 bytes with one load:
95		 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
96		 */
97		p0 = (uintptr_t)&mb0->rearm_data;
98		*(uint64_t *)p0 = rxq->mbuf_initializer;
99		p1 = (uintptr_t)&mb1->rearm_data;
100		*(uint64_t *)p1 = rxq->mbuf_initializer;
101
102		/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
103		vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
104		vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
105
106		/* convert pa to dma_addr hdr/data */
107		dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
108		dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
109
110		/* add headroom to pa values */
111		dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
112		dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
113
114		/* set Header Buffer Address to zero */
115		dma_addr0 =  _mm_and_si128(dma_addr0, hba_msk);
116		dma_addr1 =  _mm_and_si128(dma_addr1, hba_msk);
117
118		/* flush desc with pa dma_addr */
119		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
120		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
121	}
122
123	rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
124	if (rxq->rxrearm_start >= rxq->nb_rx_desc)
125		rxq->rxrearm_start = 0;
126
127	rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
128
129	rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
130			     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131
132	/* Update the tail pointer on the NIC */
133	IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
134}
135
136/* Handling the offload flags (olflags) field takes computation
137 * time when receiving packets. Therefore we provide a flag to disable
138 * the processing of the olflags field when they are not needed. This
139 * gives improved performance, at the cost of losing the offload info
140 * in the received packet
141 */
142#ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
143
144static inline void
145desc_to_olflags_v(__m128i descs[4], uint8_t vlan_flags,
146	struct rte_mbuf **rx_pkts)
147{
148	__m128i ptype0, ptype1, vtag0, vtag1;
149	union {
150		uint16_t e[4];
151		uint64_t dword;
152	} vol;
153
154	/* mask everything except rss type */
155	const __m128i rsstype_msk = _mm_set_epi16(
156			0x0000, 0x0000, 0x0000, 0x0000,
157			0x000F, 0x000F, 0x000F, 0x000F);
158
159	/* map rss type to rss hash flag */
160	const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
161			0, 0, 0, PKT_RX_RSS_HASH,
162			PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
163			PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
164
165	/* mask everything except vlan present bit */
166	const __m128i vlan_msk = _mm_set_epi16(
167			0x0000, 0x0000,
168			0x0000, 0x0000,
169			IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
170			IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
171	/* map vlan present (0x8) to ol_flags */
172	const __m128i vlan_map = _mm_set_epi8(
173		0, 0, 0, 0,
174		0, 0, 0, vlan_flags,
175		0, 0, 0, 0,
176		0, 0, 0, 0);
177
178	ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
179	ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
180	vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
181	vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
182
183	ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
184	ptype0 = _mm_and_si128(ptype0, rsstype_msk);
185	ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
186
187	vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
188	vtag1 = _mm_and_si128(vtag1, vlan_msk);
189	vtag1 = _mm_shuffle_epi8(vlan_map, vtag1);
190
191	vtag1 = _mm_or_si128(ptype0, vtag1);
192	vol.dword = _mm_cvtsi128_si64(vtag1);
193
194	rx_pkts[0]->ol_flags = vol.e[0];
195	rx_pkts[1]->ol_flags = vol.e[1];
196	rx_pkts[2]->ol_flags = vol.e[2];
197	rx_pkts[3]->ol_flags = vol.e[3];
198}
199#else
200#define desc_to_olflags_v(desc, vlan_flags, rx_pkts) do { \
201		RTE_SET_USED(vlan_flags); \
202	} while (0)
203#endif
204
205/*
206 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
207 *
208 * Notice:
209 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
210 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
211 *   numbers of DD bit
212 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
213 * - don't support ol_flags for rss and csum err
214 */
215static inline uint16_t
216_recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
217		uint16_t nb_pkts, uint8_t *split_packet)
218{
219	volatile union ixgbe_adv_rx_desc *rxdp;
220	struct ixgbe_rx_entry *sw_ring;
221	uint16_t nb_pkts_recd;
222	int pos;
223	uint64_t var;
224	__m128i shuf_msk;
225	__m128i crc_adjust = _mm_set_epi16(
226				0, 0, 0,    /* ignore non-length fields */
227				-rxq->crc_len, /* sub crc on data_len */
228				0,          /* ignore high-16bits of pkt_len */
229				-rxq->crc_len, /* sub crc on pkt_len */
230				0, 0            /* ignore pkt_type field */
231			);
232	__m128i dd_check, eop_check;
233	uint8_t vlan_flags;
234
235	/* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
236	nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
237
238	/* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
239	nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
240
241	/* Just the act of getting into the function from the application is
242	 * going to cost about 7 cycles
243	 */
244	rxdp = rxq->rx_ring + rxq->rx_tail;
245
246	_mm_prefetch((const void *)rxdp, _MM_HINT_T0);
247
248	/* See if we need to rearm the RX queue - gives the prefetch a bit
249	 * of time to act
250	 */
251	if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
252		ixgbe_rxq_rearm(rxq);
253
254	/* Before we start moving massive data around, check to see if
255	 * there is actually a packet available
256	 */
257	if (!(rxdp->wb.upper.status_error &
258				rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
259		return 0;
260
261	/* 4 packets DD mask */
262	dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
263
264	/* 4 packets EOP mask */
265	eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
266
267	/* mask to shuffle from desc. to mbuf */
268	shuf_msk = _mm_set_epi8(
269		7, 6, 5, 4,  /* octet 4~7, 32bits rss */
270		15, 14,      /* octet 14~15, low 16 bits vlan_macip */
271		13, 12,      /* octet 12~13, 16 bits data_len */
272		0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
273		13, 12,      /* octet 12~13, low 16 bits pkt_len */
274		0xFF, 0xFF,  /* skip 32 bit pkt_type */
275		0xFF, 0xFF
276		);
277
278	/* Cache is empty -> need to scan the buffer rings, but first move
279	 * the next 'n' mbufs into the cache
280	 */
281	sw_ring = &rxq->sw_ring[rxq->rx_tail];
282
283	/* ensure these 2 flags are in the lower 8 bits */
284	RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
285	vlan_flags = rxq->vlan_flags & UINT8_MAX;
286
287	/* A. load 4 packet in one loop
288	 * [A*. mask out 4 unused dirty field in desc]
289	 * B. copy 4 mbuf point from swring to rx_pkts
290	 * C. calc the number of DD bits among the 4 packets
291	 * [C*. extract the end-of-packet bit, if requested]
292	 * D. fill info. from desc to mbuf
293	 */
294	for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
295			pos += RTE_IXGBE_DESCS_PER_LOOP,
296			rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
297		__m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
298		__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
299		__m128i zero, staterr, sterr_tmp1, sterr_tmp2;
300		__m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
301
302		/* B.1 load 1 mbuf point */
303		mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
304
305		/* Read desc statuses backwards to avoid race condition */
306		/* A.1 load 4 pkts desc */
307		descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
308		rte_compiler_barrier();
309
310		/* B.2 copy 2 mbuf point into rx_pkts  */
311		_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
312
313		/* B.1 load 1 mbuf point */
314		mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
315
316		descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
317		rte_compiler_barrier();
318		/* B.1 load 2 mbuf point */
319		descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
320		rte_compiler_barrier();
321		descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
322
323		/* B.2 copy 2 mbuf point into rx_pkts  */
324		_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
325
326		if (split_packet) {
327			rte_mbuf_prefetch_part2(rx_pkts[pos]);
328			rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
329			rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
330			rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
331		}
332
333		/* avoid compiler reorder optimization */
334		rte_compiler_barrier();
335
336		/* D.1 pkt 3,4 convert format from desc to pktmbuf */
337		pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
338		pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
339
340		/* D.1 pkt 1,2 convert format from desc to pktmbuf */
341		pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
342		pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
343
344		/* C.1 4=>2 filter staterr info only */
345		sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
346		/* C.1 4=>2 filter staterr info only */
347		sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
348
349		/* set ol_flags with vlan packet type */
350		desc_to_olflags_v(descs, vlan_flags, &rx_pkts[pos]);
351
352		/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
353		pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
354		pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
355
356		/* C.2 get 4 pkts staterr value  */
357		zero = _mm_xor_si128(dd_check, dd_check);
358		staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
359
360		/* D.3 copy final 3,4 data to rx_pkts */
361		_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
362				pkt_mb4);
363		_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
364				pkt_mb3);
365
366		/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
367		pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
368		pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
369
370		/* C* extract and record EOP bit */
371		if (split_packet) {
372			__m128i eop_shuf_mask = _mm_set_epi8(
373					0xFF, 0xFF, 0xFF, 0xFF,
374					0xFF, 0xFF, 0xFF, 0xFF,
375					0xFF, 0xFF, 0xFF, 0xFF,
376					0x04, 0x0C, 0x00, 0x08
377					);
378
379			/* and with mask to extract bits, flipping 1-0 */
380			__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
381			/* the staterr values are not in order, as the count
382			 * count of dd bits doesn't care. However, for end of
383			 * packet tracking, we do care, so shuffle. This also
384			 * compresses the 32-bit values to 8-bit
385			 */
386			eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
387			/* store the resulting 32-bit value */
388			*(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
389			split_packet += RTE_IXGBE_DESCS_PER_LOOP;
390
391			/* zero-out next pointers */
392			rx_pkts[pos]->next = NULL;
393			rx_pkts[pos + 1]->next = NULL;
394			rx_pkts[pos + 2]->next = NULL;
395			rx_pkts[pos + 3]->next = NULL;
396		}
397
398		/* C.3 calc available number of desc */
399		staterr = _mm_and_si128(staterr, dd_check);
400		staterr = _mm_packs_epi32(staterr, zero);
401
402		/* D.3 copy final 1,2 data to rx_pkts */
403		_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
404				pkt_mb2);
405		_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
406				pkt_mb1);
407
408		/* C.4 calc avaialbe number of desc */
409		var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
410		nb_pkts_recd += var;
411		if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
412			break;
413	}
414
415	/* Update our internal tail pointer */
416	rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
417	rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
418	rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
419
420	return nb_pkts_recd;
421}
422
423/*
424 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
425 *
426 * Notice:
427 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
428 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
429 *   numbers of DD bit
430 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
431 * - don't support ol_flags for rss and csum err
432 */
433uint16_t
434ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
435		uint16_t nb_pkts)
436{
437	return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
438}
439
440/*
441 * vPMD receive routine that reassembles scattered packets
442 *
443 * Notice:
444 * - don't support ol_flags for rss and csum err
445 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
446 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
447 *   numbers of DD bit
448 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
449 */
450uint16_t
451ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
452		uint16_t nb_pkts)
453{
454	struct ixgbe_rx_queue *rxq = rx_queue;
455	uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
456
457	/* get some new buffers */
458	uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
459			split_flags);
460	if (nb_bufs == 0)
461		return 0;
462
463	/* happy day case, full burst + no packets to be joined */
464	const uint64_t *split_fl64 = (uint64_t *)split_flags;
465	if (rxq->pkt_first_seg == NULL &&
466			split_fl64[0] == 0 && split_fl64[1] == 0 &&
467			split_fl64[2] == 0 && split_fl64[3] == 0)
468		return nb_bufs;
469
470	/* reassemble any packets that need reassembly*/
471	unsigned i = 0;
472	if (rxq->pkt_first_seg == NULL) {
473		/* find the first split flag, and only reassemble then*/
474		while (i < nb_bufs && !split_flags[i])
475			i++;
476		if (i == nb_bufs)
477			return nb_bufs;
478	}
479	return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
480		&split_flags[i]);
481}
482
483static inline void
484vtx1(volatile union ixgbe_adv_tx_desc *txdp,
485		struct rte_mbuf *pkt, uint64_t flags)
486{
487	__m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
488			flags | pkt->data_len,
489			pkt->buf_physaddr + pkt->data_off);
490	_mm_store_si128((__m128i *)&txdp->read, descriptor);
491}
492
493static inline void
494vtx(volatile union ixgbe_adv_tx_desc *txdp,
495		struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
496{
497	int i;
498
499	for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
500		vtx1(txdp, *pkt, flags);
501}
502
503uint16_t
504ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
505		       uint16_t nb_pkts)
506{
507	struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
508	volatile union ixgbe_adv_tx_desc *txdp;
509	struct ixgbe_tx_entry_v *txep;
510	uint16_t n, nb_commit, tx_id;
511	uint64_t flags = DCMD_DTYP_FLAGS;
512	uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
513	int i;
514
515	/* cross rx_thresh boundary is not allowed */
516	nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
517
518	if (txq->nb_tx_free < txq->tx_free_thresh)
519		ixgbe_tx_free_bufs(txq);
520
521	nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
522	if (unlikely(nb_pkts == 0))
523		return 0;
524
525	tx_id = txq->tx_tail;
526	txdp = &txq->tx_ring[tx_id];
527	txep = &txq->sw_ring_v[tx_id];
528
529	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
530
531	n = (uint16_t)(txq->nb_tx_desc - tx_id);
532	if (nb_commit >= n) {
533
534		tx_backlog_entry(txep, tx_pkts, n);
535
536		for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
537			vtx1(txdp, *tx_pkts, flags);
538
539		vtx1(txdp, *tx_pkts++, rs);
540
541		nb_commit = (uint16_t)(nb_commit - n);
542
543		tx_id = 0;
544		txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
545
546		/* avoid reach the end of ring */
547		txdp = &(txq->tx_ring[tx_id]);
548		txep = &txq->sw_ring_v[tx_id];
549	}
550
551	tx_backlog_entry(txep, tx_pkts, nb_commit);
552
553	vtx(txdp, tx_pkts, nb_commit, flags);
554
555	tx_id = (uint16_t)(tx_id + nb_commit);
556	if (tx_id > txq->tx_next_rs) {
557		txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
558			rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
559		txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
560			txq->tx_rs_thresh);
561	}
562
563	txq->tx_tail = tx_id;
564
565	IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
566
567	return nb_pkts;
568}
569
570static void __attribute__((cold))
571ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
572{
573	_ixgbe_tx_queue_release_mbufs_vec(txq);
574}
575
576void __attribute__((cold))
577ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
578{
579	_ixgbe_rx_queue_release_mbufs_vec(rxq);
580}
581
582static void __attribute__((cold))
583ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
584{
585	_ixgbe_tx_free_swring_vec(txq);
586}
587
588static void __attribute__((cold))
589ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
590{
591	_ixgbe_reset_tx_queue_vec(txq);
592}
593
594static const struct ixgbe_txq_ops vec_txq_ops = {
595	.release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
596	.free_swring = ixgbe_tx_free_swring,
597	.reset = ixgbe_reset_tx_queue,
598};
599
600int __attribute__((cold))
601ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
602{
603	return ixgbe_rxq_vec_setup_default(rxq);
604}
605
606int __attribute__((cold))
607ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
608{
609	return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
610}
611
612int __attribute__((cold))
613ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
614{
615	return ixgbe_rx_vec_dev_conf_condition_check_default(dev);
616}
617