1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright 2016 6WIND S.A.
5 *   Copyright 2016 Mellanox.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of 6WIND S.A. nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef RTE_PMD_MLX5_PRM_H_
35#define RTE_PMD_MLX5_PRM_H_
36
37/* Verbs header. */
38/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
39#ifdef PEDANTIC
40#pragma GCC diagnostic ignored "-Wpedantic"
41#endif
42#include <infiniband/mlx5_hw.h>
43#ifdef PEDANTIC
44#pragma GCC diagnostic error "-Wpedantic"
45#endif
46
47#include "mlx5_autoconf.h"
48
49/* Get CQE owner bit. */
50#define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
51
52/* Get CQE format. */
53#define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
54
55/* Get CQE opcode. */
56#define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
57
58/* Get CQE solicited event. */
59#define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
60
61/* Invalidate a CQE. */
62#define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
63
64/* Maximum number of packets a multi-packet WQE can handle. */
65#define MLX5_MPW_DSEG_MAX 5
66
67/* WQE DWORD size */
68#define MLX5_WQE_DWORD_SIZE 16
69
70/* WQE size */
71#define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
72
73/* Compute the number of DS. */
74#define MLX5_WQE_DS(n) \
75	(((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
76
77/* Room for inline data in multi-packet WQE. */
78#define MLX5_MWQE64_INL_DATA 28
79
80#ifndef HAVE_VERBS_MLX5_OPCODE_TSO
81#define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
82#endif
83
84/* CQE value to inform that VLAN is stripped. */
85#define MLX5_CQE_VLAN_STRIPPED (1u << 0)
86
87/* IPv4 options. */
88#define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
89
90/* IPv6 packet. */
91#define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
92
93/* IPv4 packet. */
94#define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
95
96/* TCP packet. */
97#define MLX5_CQE_RX_TCP_PACKET (1u << 4)
98
99/* UDP packet. */
100#define MLX5_CQE_RX_UDP_PACKET (1u << 5)
101
102/* IP is fragmented. */
103#define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
104
105/* L2 header is valid. */
106#define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
107
108/* L3 header is valid. */
109#define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
110
111/* L4 header is valid. */
112#define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
113
114/* Outer packet, 0 IPv4, 1 IPv6. */
115#define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
116
117/* Tunnel packet bit in the CQE. */
118#define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
119
120/* Subset of struct mlx5_wqe_eth_seg. */
121struct mlx5_wqe_eth_seg_small {
122	uint32_t rsvd0;
123	uint8_t	cs_flags;
124	uint8_t	rsvd1;
125	uint16_t mss;
126	uint32_t rsvd2;
127	uint16_t inline_hdr_sz;
128	uint8_t inline_hdr[2];
129};
130
131struct mlx5_wqe_inl_small {
132	uint32_t byte_cnt;
133	uint8_t raw;
134};
135
136/* Small common part of the WQE. */
137struct mlx5_wqe {
138	uint32_t ctrl[4];
139	struct mlx5_wqe_eth_seg_small eseg;
140};
141
142/* WQE. */
143struct mlx5_wqe64 {
144	struct mlx5_wqe hdr;
145	uint8_t raw[32];
146} __rte_aligned(64);
147
148/* MPW session status. */
149enum mlx5_mpw_state {
150	MLX5_MPW_STATE_OPENED,
151	MLX5_MPW_INL_STATE_OPENED,
152	MLX5_MPW_STATE_CLOSED,
153};
154
155/* MPW session descriptor. */
156struct mlx5_mpw {
157	enum mlx5_mpw_state state;
158	unsigned int pkts_n;
159	unsigned int len;
160	unsigned int total_len;
161	volatile struct mlx5_wqe *wqe;
162	union {
163		volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
164		volatile uint8_t *raw;
165	} data;
166};
167
168/* CQ element structure - should be equal to the cache line size */
169struct mlx5_cqe {
170#if (RTE_CACHE_LINE_SIZE == 128)
171	uint8_t padding[64];
172#endif
173	uint8_t pkt_info;
174	uint8_t rsvd0[11];
175	uint32_t rx_hash_res;
176	uint8_t rx_hash_type;
177	uint8_t rsvd1[11];
178	uint16_t hdr_type_etc;
179	uint16_t vlan_info;
180	uint8_t rsvd2[12];
181	uint32_t byte_cnt;
182	uint64_t timestamp;
183	uint8_t rsvd3[4];
184	uint16_t wqe_counter;
185	uint8_t rsvd4;
186	uint8_t op_own;
187};
188
189#endif /* RTE_PMD_MLX5_PRM_H_ */
190