1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright 2015 6WIND S.A.
5 *   Copyright 2015 Mellanox.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of 6WIND S.A. nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef RTE_PMD_MLX5_RXTX_H_
35#define RTE_PMD_MLX5_RXTX_H_
36
37#include <stddef.h>
38#include <stdint.h>
39
40/* Verbs header. */
41/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42#ifdef PEDANTIC
43#pragma GCC diagnostic ignored "-Wpedantic"
44#endif
45#include <infiniband/verbs.h>
46#include <infiniband/mlx5_hw.h>
47#ifdef PEDANTIC
48#pragma GCC diagnostic error "-Wpedantic"
49#endif
50
51/* DPDK headers don't like -pedantic. */
52#ifdef PEDANTIC
53#pragma GCC diagnostic ignored "-Wpedantic"
54#endif
55#include <rte_mbuf.h>
56#include <rte_mempool.h>
57#include <rte_common.h>
58#ifdef PEDANTIC
59#pragma GCC diagnostic error "-Wpedantic"
60#endif
61
62#include "mlx5_utils.h"
63#include "mlx5.h"
64#include "mlx5_autoconf.h"
65#include "mlx5_defs.h"
66#include "mlx5_prm.h"
67
68struct mlx5_rxq_stats {
69	unsigned int idx; /**< Mapping index. */
70#ifdef MLX5_PMD_SOFT_COUNTERS
71	uint64_t ipackets; /**< Total of successfully received packets. */
72	uint64_t ibytes; /**< Total of successfully received bytes. */
73#endif
74	uint64_t idropped; /**< Total of packets dropped when RX ring full. */
75	uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
76};
77
78struct mlx5_txq_stats {
79	unsigned int idx; /**< Mapping index. */
80#ifdef MLX5_PMD_SOFT_COUNTERS
81	uint64_t opackets; /**< Total of successfully sent packets. */
82	uint64_t obytes; /**< Total of successfully sent bytes. */
83#endif
84	uint64_t oerrors; /**< Total number of failed transmitted packets. */
85};
86
87/* Flow director queue structure. */
88struct fdir_queue {
89	struct ibv_qp *qp; /* Associated RX QP. */
90	struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
91	struct ibv_exp_wq *wq; /* Work queue. */
92	struct ibv_cq *cq; /* Completion queue. */
93};
94
95struct priv;
96
97/* Compressed CQE context. */
98struct rxq_zip {
99	uint16_t ai; /* Array index. */
100	uint16_t ca; /* Current array index. */
101	uint16_t na; /* Next array index. */
102	uint16_t cq_ci; /* The next CQE. */
103	uint32_t cqe_cnt; /* Number of CQEs. */
104};
105
106/* RX queue descriptor. */
107struct rxq {
108	unsigned int csum:1; /* Enable checksum offloading. */
109	unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
110	unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111	unsigned int crc_present:1; /* CRC must be subtracted. */
112	unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113	unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114	unsigned int elts_n:4; /* Log 2 of Mbufs. */
115	unsigned int port_id:8;
116	unsigned int rss_hash:1; /* RSS hash result is enabled. */
117	unsigned int :9; /* Remaining bits. */
118	volatile uint32_t *rq_db;
119	volatile uint32_t *cq_db;
120	uint16_t rq_ci;
121	uint16_t cq_ci;
122	volatile struct mlx5_wqe_data_seg(*wqes)[];
123	volatile struct mlx5_cqe(*cqes)[];
124	struct rxq_zip zip; /* Compressed context. */
125	struct rte_mbuf *(*elts)[];
126	struct rte_mempool *mp;
127	struct mlx5_rxq_stats stats;
128} __rte_cache_aligned;
129
130/* RX queue control descriptor. */
131struct rxq_ctrl {
132	struct priv *priv; /* Back pointer to private data. */
133	struct ibv_cq *cq; /* Completion Queue. */
134	struct ibv_exp_wq *wq; /* Work Queue. */
135	struct ibv_exp_res_domain *rd; /* Resource Domain. */
136	struct fdir_queue *fdir_queue; /* Flow director queue. */
137	struct ibv_mr *mr; /* Memory Region (for mp). */
138	struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
139	struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
140	unsigned int socket; /* CPU socket ID for allocations. */
141	struct rxq rxq; /* Data path structure. */
142};
143
144/* Hash RX queue types. */
145enum hash_rxq_type {
146	HASH_RXQ_TCPV4,
147	HASH_RXQ_UDPV4,
148	HASH_RXQ_IPV4,
149	HASH_RXQ_TCPV6,
150	HASH_RXQ_UDPV6,
151	HASH_RXQ_IPV6,
152	HASH_RXQ_ETH,
153};
154
155/* Flow structure with Ethernet specification. It is packed to prevent padding
156 * between attr and spec as this layout is expected by libibverbs. */
157struct flow_attr_spec_eth {
158	struct ibv_exp_flow_attr attr;
159	struct ibv_exp_flow_spec_eth spec;
160} __attribute__((packed));
161
162/* Define a struct flow_attr_spec_eth object as an array of at least
163 * "size" bytes. Room after the first index is normally used to store
164 * extra flow specifications. */
165#define FLOW_ATTR_SPEC_ETH(name, size) \
166	struct flow_attr_spec_eth name \
167		[((size) / sizeof(struct flow_attr_spec_eth)) + \
168		 !!((size) % sizeof(struct flow_attr_spec_eth))]
169
170/* Initialization data for hash RX queue. */
171struct hash_rxq_init {
172	uint64_t hash_fields; /* Fields that participate in the hash. */
173	uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
174	unsigned int flow_priority; /* Flow priority to use. */
175	union {
176		struct {
177			enum ibv_exp_flow_spec_type type;
178			uint16_t size;
179		} hdr;
180		struct ibv_exp_flow_spec_tcp_udp tcp_udp;
181		struct ibv_exp_flow_spec_ipv4 ipv4;
182		struct ibv_exp_flow_spec_ipv6 ipv6;
183		struct ibv_exp_flow_spec_eth eth;
184	} flow_spec; /* Flow specification template. */
185	const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
186};
187
188/* Initialization data for indirection table. */
189struct ind_table_init {
190	unsigned int max_size; /* Maximum number of WQs. */
191	/* Hash RX queues using this table. */
192	unsigned int hash_types;
193	unsigned int hash_types_n;
194};
195
196/* Initialization data for special flows. */
197struct special_flow_init {
198	uint8_t dst_mac_val[6];
199	uint8_t dst_mac_mask[6];
200	unsigned int hash_types;
201	unsigned int per_vlan:1;
202};
203
204enum hash_rxq_flow_type {
205	HASH_RXQ_FLOW_TYPE_PROMISC,
206	HASH_RXQ_FLOW_TYPE_ALLMULTI,
207	HASH_RXQ_FLOW_TYPE_BROADCAST,
208	HASH_RXQ_FLOW_TYPE_IPV6MULTI,
209	HASH_RXQ_FLOW_TYPE_MAC,
210};
211
212#ifndef NDEBUG
213static inline const char *
214hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
215{
216	switch (flow_type) {
217	case HASH_RXQ_FLOW_TYPE_PROMISC:
218		return "promiscuous";
219	case HASH_RXQ_FLOW_TYPE_ALLMULTI:
220		return "allmulticast";
221	case HASH_RXQ_FLOW_TYPE_BROADCAST:
222		return "broadcast";
223	case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
224		return "IPv6 multicast";
225	case HASH_RXQ_FLOW_TYPE_MAC:
226		return "MAC";
227	}
228	return NULL;
229}
230#endif /* NDEBUG */
231
232struct hash_rxq {
233	struct priv *priv; /* Back pointer to private data. */
234	struct ibv_qp *qp; /* Hash RX QP. */
235	enum hash_rxq_type type; /* Hash RX queue type. */
236	/* MAC flow steering rules, one per VLAN ID. */
237	struct ibv_exp_flow *mac_flow
238		[MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
239	struct ibv_exp_flow *special_flow
240		[MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
241};
242
243/* TX queue descriptor. */
244RTE_STD_C11
245struct txq {
246	uint16_t elts_head; /* Current index in (*elts)[]. */
247	uint16_t elts_tail; /* First element awaiting completion. */
248	uint16_t elts_comp; /* Counter since last completion request. */
249	uint16_t cq_ci; /* Consumer index for completion queue. */
250	uint16_t wqe_ci; /* Consumer index for work queue. */
251	uint16_t elts_n:4; /* (*elts)[] length (in log2). */
252	uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
253	uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
254	uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
255	uint32_t qp_num_8s; /* QP number shifted by 8. */
256	volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
257	volatile struct mlx5_wqe64 (*wqes)[]; /* Work queue. */
258	volatile uint32_t *qp_db; /* Work queue doorbell. */
259	volatile uint32_t *cq_db; /* Completion queue doorbell. */
260	volatile void *bf_reg; /* Blueflame register. */
261	struct {
262		const struct rte_mempool *mp; /* Cached Memory Pool. */
263		struct ibv_mr *mr; /* Memory Region (for mp). */
264		uint32_t lkey; /* htonl(mr->lkey) */
265	} mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
266	struct rte_mbuf *(*elts)[]; /* TX elements. */
267	struct mlx5_txq_stats stats; /* TX queue counters. */
268} __rte_cache_aligned;
269
270/* TX queue control descriptor. */
271struct txq_ctrl {
272	struct priv *priv; /* Back pointer to private data. */
273	struct ibv_cq *cq; /* Completion Queue. */
274	struct ibv_qp *qp; /* Queue Pair. */
275	struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
276	struct ibv_exp_cq_family *if_cq; /* CQ interface. */
277	struct ibv_exp_res_domain *rd; /* Resource Domain. */
278	unsigned int socket; /* CPU socket ID for allocations. */
279	struct txq txq; /* Data path structure. */
280};
281
282/* mlx5_rxq.c */
283
284extern const struct hash_rxq_init hash_rxq_init[];
285extern const unsigned int hash_rxq_init_n;
286
287extern uint8_t rss_hash_default_key[];
288extern const size_t rss_hash_default_key_len;
289
290size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
291		      size_t, enum hash_rxq_type);
292int priv_create_hash_rxqs(struct priv *);
293void priv_destroy_hash_rxqs(struct priv *);
294int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
295int priv_rehash_flows(struct priv *);
296void rxq_cleanup(struct rxq_ctrl *);
297int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
298int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
299		   unsigned int, const struct rte_eth_rxconf *,
300		   struct rte_mempool *);
301int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
302			const struct rte_eth_rxconf *, struct rte_mempool *);
303void mlx5_rx_queue_release(void *);
304uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
305
306/* mlx5_txq.c */
307
308void txq_cleanup(struct txq_ctrl *);
309int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
310		   unsigned int, const struct rte_eth_txconf *);
311int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
312			const struct rte_eth_txconf *);
313void mlx5_tx_queue_release(void *);
314uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
315
316/* mlx5_rxtx.c */
317
318uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
319uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
320uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
321uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
322uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
323uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
324
325/* mlx5_mr.c */
326
327struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
328void txq_mp2mr_iter(struct rte_mempool *, void *);
329uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
330
331#endif /* RTE_PMD_MLX5_RXTX_H_ */
332