nfp_net.c revision 8be94df6
1/*
2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
3 * All rights reserved.
4 *
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 *  this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *  notice, this list of conditions and the following disclaimer in the
15 *  documentation and/or other materials provided with the distribution
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 *  contributors may be used to endorse or promote products derived from this
19 *  software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * vim:shiftwidth=8:noexpandtab
36 *
37 * @file dpdk/pmd/nfp_net.c
38 *
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
40 */
41
42#include <math.h>
43
44#include <rte_byteorder.h>
45#include <rte_common.h>
46#include <rte_log.h>
47#include <rte_debug.h>
48#include <rte_ethdev.h>
49#include <rte_dev.h>
50#include <rte_ether.h>
51#include <rte_malloc.h>
52#include <rte_memzone.h>
53#include <rte_mempool.h>
54#include <rte_version.h>
55#include <rte_string_fns.h>
56#include <rte_alarm.h>
57#include <rte_spinlock.h>
58
59#include "nfp_net_pmd.h"
60#include "nfp_net_logs.h"
61#include "nfp_net_ctrl.h"
62
63/* Prototypes */
64static void nfp_net_close(struct rte_eth_dev *dev);
65static int nfp_net_configure(struct rte_eth_dev *dev);
66static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
67					  void *param);
68static void nfp_net_dev_interrupt_delayed_handler(void *param);
69static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70static void nfp_net_infos_get(struct rte_eth_dev *dev,
71			      struct rte_eth_dev_info *dev_info);
72static int nfp_net_init(struct rte_eth_dev *eth_dev);
73static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78				       uint16_t queue_idx);
79static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80				  uint16_t nb_pkts);
81static void nfp_net_rx_queue_release(void *rxq);
82static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83				  uint16_t nb_desc, unsigned int socket_id,
84				  const struct rte_eth_rxconf *rx_conf,
85				  struct rte_mempool *mp);
86static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87static void nfp_net_tx_queue_release(void *txq);
88static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89				  uint16_t nb_desc, unsigned int socket_id,
90				  const struct rte_eth_txconf *tx_conf);
91static int nfp_net_start(struct rte_eth_dev *dev);
92static void nfp_net_stats_get(struct rte_eth_dev *dev,
93			      struct rte_eth_stats *stats);
94static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95static void nfp_net_stop(struct rte_eth_dev *dev);
96static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
97				  uint16_t nb_pkts);
98
99/*
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
103 */
104#define NFP_PCIE_QUEUE(_q)	(0x80000 + (0x800 * ((_q) & 0xff)))
105
106/* Maximum value which can be added to a queue with one transaction */
107#define NFP_QCP_MAX_ADD	0x7f
108
109#define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110	(uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111
112/* nfp_qcp_ptr - Read or Write Pointer of a queue */
113enum nfp_qcp_ptr {
114	NFP_QCP_READ_PTR = 0,
115	NFP_QCP_WRITE_PTR
116};
117
118/*
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
123 *
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
125 */
126static inline void
127nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
128{
129	uint32_t off;
130
131	if (ptr == NFP_QCP_READ_PTR)
132		off = NFP_QCP_QUEUE_ADD_RPTR;
133	else
134		off = NFP_QCP_QUEUE_ADD_WPTR;
135
136	while (val > NFP_QCP_MAX_ADD) {
137		nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138		val -= NFP_QCP_MAX_ADD;
139	}
140
141	nn_writel(rte_cpu_to_le_32(val), q + off);
142}
143
144/*
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q:  Base address for queue structure
147 * @ptr: Read or Write pointer
148 */
149static inline uint32_t
150nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
151{
152	uint32_t off;
153	uint32_t val;
154
155	if (ptr == NFP_QCP_READ_PTR)
156		off = NFP_QCP_QUEUE_STS_LO;
157	else
158		off = NFP_QCP_QUEUE_STS_HI;
159
160	val = rte_cpu_to_le_32(nn_readl(q + off));
161
162	if (ptr == NFP_QCP_READ_PTR)
163		return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164	else
165		return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
166}
167
168/*
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
171 */
172static inline uint8_t
173nn_cfg_readb(struct nfp_net_hw *hw, int off)
174{
175	return nn_readb(hw->ctrl_bar + off);
176}
177
178static inline void
179nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180{
181	nn_writeb(val, hw->ctrl_bar + off);
182}
183
184static inline uint32_t
185nn_cfg_readl(struct nfp_net_hw *hw, int off)
186{
187	return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
188}
189
190static inline void
191nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192{
193	nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
194}
195
196static inline uint64_t
197nn_cfg_readq(struct nfp_net_hw *hw, int off)
198{
199	return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
200}
201
202static inline void
203nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204{
205	nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
206}
207
208/* Creating memzone for hardware rings. */
209static const struct rte_memzone *
210ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211		      uint16_t queue_id, uint32_t ring_size, int socket_id)
212{
213	char z_name[RTE_MEMZONE_NAMESIZE];
214	const struct rte_memzone *mz;
215
216	snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217		 dev->driver->pci_drv.name,
218		 ring_name, dev->data->port_id, queue_id);
219
220	mz = rte_memzone_lookup(z_name);
221	if (mz)
222		return mz;
223
224	return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
225					   NFP_MEMZONE_ALIGN);
226}
227
228/*
229 * Atomically reads link status information from global structure rte_eth_dev.
230 *
231 * @param dev
232 *   - Pointer to the structure rte_eth_dev to read from.
233 *   - Pointer to the buffer to be saved with the link status.
234 *
235 * @return
236 *   - On success, zero.
237 *   - On failure, negative value.
238 */
239static inline int
240nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241				    struct rte_eth_link *link)
242{
243	struct rte_eth_link *dst = link;
244	struct rte_eth_link *src = &dev->data->dev_link;
245
246	if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247				*(uint64_t *)src) == 0)
248		return -1;
249
250	return 0;
251}
252
253/*
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
256 *
257 * @param dev
258 *   - Pointer to the structure rte_eth_dev to read from.
259 *   - Pointer to the buffer to be saved with the link status.
260 *
261 * @return
262 *   - On success, zero.
263 *   - On failure, negative value.
264 */
265static inline int
266nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267				     struct rte_eth_link *link)
268{
269	struct rte_eth_link *dst = &dev->data->dev_link;
270	struct rte_eth_link *src = link;
271
272	if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273				*(uint64_t *)src) == 0)
274		return -1;
275
276	return 0;
277}
278
279static void
280nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
281{
282	unsigned i;
283
284	if (rxq->rxbufs == NULL)
285		return;
286
287	for (i = 0; i < rxq->rx_count; i++) {
288		if (rxq->rxbufs[i].mbuf) {
289			rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290			rxq->rxbufs[i].mbuf = NULL;
291		}
292	}
293}
294
295static void
296nfp_net_rx_queue_release(void *rx_queue)
297{
298	struct nfp_net_rxq *rxq = rx_queue;
299
300	if (rxq) {
301		nfp_net_rx_queue_release_mbufs(rxq);
302		rte_free(rxq->rxbufs);
303		rte_free(rxq);
304	}
305}
306
307static void
308nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
309{
310	nfp_net_rx_queue_release_mbufs(rxq);
311	rxq->wr_p = 0;
312	rxq->rd_p = 0;
313	rxq->nb_rx_hold = 0;
314}
315
316static void
317nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
318{
319	unsigned i;
320
321	if (txq->txbufs == NULL)
322		return;
323
324	for (i = 0; i < txq->tx_count; i++) {
325		if (txq->txbufs[i].mbuf) {
326			rte_pktmbuf_free(txq->txbufs[i].mbuf);
327			txq->txbufs[i].mbuf = NULL;
328		}
329	}
330}
331
332static void
333nfp_net_tx_queue_release(void *tx_queue)
334{
335	struct nfp_net_txq *txq = tx_queue;
336
337	if (txq) {
338		nfp_net_tx_queue_release_mbufs(txq);
339		rte_free(txq->txbufs);
340		rte_free(txq);
341	}
342}
343
344static void
345nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
346{
347	nfp_net_tx_queue_release_mbufs(txq);
348	txq->wr_p = 0;
349	txq->rd_p = 0;
350	txq->tail = 0;
351	txq->qcp_rd_p = 0;
352}
353
354static int
355__nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
356{
357	int cnt;
358	uint32_t new;
359	struct timespec wait;
360
361	PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
362		    hw->qcp_cfg);
363
364	if (hw->qcp_cfg == NULL)
365		rte_panic("Bad configuration queue pointer\n");
366
367	nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
368
369	wait.tv_sec = 0;
370	wait.tv_nsec = 1000000;
371
372	PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
373
374	/* Poll update field, waiting for NFP to ack the config */
375	for (cnt = 0; ; cnt++) {
376		new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
377		if (new == 0)
378			break;
379		if (new & NFP_NET_CFG_UPDATE_ERR) {
380			PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
381			return -1;
382		}
383		if (cnt >= NFP_NET_POLL_TIMEOUT) {
384			PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
385					  " %dms\n", update, cnt);
386			rte_panic("Exiting\n");
387		}
388		nanosleep(&wait, 0); /* waiting for a 1ms */
389	}
390	PMD_DRV_LOG(DEBUG, "Ack DONE\n");
391	return 0;
392}
393
394/*
395 * Reconfigure the NIC
396 * @nn:    device to reconfigure
397 * @ctrl:    The value for the ctrl field in the BAR config
398 * @update:  The value for the update field in the BAR config
399 *
400 * Write the update word to the BAR and ping the reconfig queue. Then poll
401 * until the firmware has acknowledged the update by zeroing the update word.
402 */
403static int
404nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
405{
406	uint32_t err;
407
408	PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
409		    ctrl, update);
410
411	rte_spinlock_lock(&hw->reconfig_lock);
412
413	nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
414	nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
415
416	rte_wmb();
417
418	err = __nfp_net_reconfig(hw, update);
419
420	rte_spinlock_unlock(&hw->reconfig_lock);
421
422	if (!err)
423		return 0;
424
425	/*
426	 * Reconfig errors imply situations where they can be handled.
427	 * Otherwise, rte_panic is called inside __nfp_net_reconfig
428	 */
429	PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
430		     ctrl, update);
431	return -EIO;
432}
433
434/*
435 * Configure an Ethernet device. This function must be invoked first
436 * before any other function in the Ethernet API. This function can
437 * also be re-invoked when a device is in the stopped state.
438 */
439static int
440nfp_net_configure(struct rte_eth_dev *dev)
441{
442	struct rte_eth_conf *dev_conf;
443	struct rte_eth_rxmode *rxmode;
444	struct rte_eth_txmode *txmode;
445	uint32_t new_ctrl = 0;
446	uint32_t update = 0;
447	struct nfp_net_hw *hw;
448
449	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
450
451	/*
452	 * A DPDK app sends info about how many queues to use and how
453	 * those queues need to be configured. This is used by the
454	 * DPDK core and it makes sure no more queues than those
455	 * advertised by the driver are requested. This function is
456	 * called after that internal process
457	 */
458
459	PMD_INIT_LOG(DEBUG, "Configure\n");
460
461	dev_conf = &dev->data->dev_conf;
462	rxmode = &dev_conf->rxmode;
463	txmode = &dev_conf->txmode;
464
465	/* Checking TX mode */
466	if (txmode->mq_mode) {
467		PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
468		return -EINVAL;
469	}
470
471	/* Checking RX mode */
472	if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
473		if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
474			update = NFP_NET_CFG_UPDATE_RSS;
475			new_ctrl = NFP_NET_CFG_CTRL_RSS;
476		} else {
477			PMD_INIT_LOG(INFO, "RSS not supported\n");
478			return -EINVAL;
479		}
480	}
481
482	if (rxmode->split_hdr_size) {
483		PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
484		return -EINVAL;
485	}
486
487	if (rxmode->hw_ip_checksum) {
488		if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
489			new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
490		} else {
491			PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
492			return -EINVAL;
493		}
494	}
495
496	if (rxmode->hw_vlan_filter) {
497		PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
498		return -EINVAL;
499	}
500
501	if (rxmode->hw_vlan_strip) {
502		if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
503			new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
504		} else {
505			PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
506			return -EINVAL;
507		}
508	}
509
510	if (rxmode->hw_vlan_extend) {
511		PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
512		return -EINVAL;
513	}
514
515	/* Supporting VLAN insertion by default */
516	if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
517		new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
518
519	if (rxmode->jumbo_frame)
520		/* this is handled in rte_eth_dev_configure */
521
522	if (rxmode->hw_strip_crc) {
523		PMD_INIT_LOG(INFO, "strip CRC not supported\n");
524		return -EINVAL;
525	}
526
527	if (rxmode->enable_scatter) {
528		PMD_INIT_LOG(INFO, "Scatter not supported\n");
529		return -EINVAL;
530	}
531
532	if (!new_ctrl)
533		return 0;
534
535	update |= NFP_NET_CFG_UPDATE_GEN;
536
537	nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
538	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
539		return -EIO;
540
541	hw->ctrl = new_ctrl;
542
543	return 0;
544}
545
546static void
547nfp_net_enable_queues(struct rte_eth_dev *dev)
548{
549	struct nfp_net_hw *hw;
550	uint64_t enabled_queues = 0;
551	int i;
552
553	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
554
555	/* Enabling the required TX queues in the device */
556	for (i = 0; i < dev->data->nb_tx_queues; i++)
557		enabled_queues |= (1 << i);
558
559	nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
560
561	enabled_queues = 0;
562
563	/* Enabling the required RX queues in the device */
564	for (i = 0; i < dev->data->nb_rx_queues; i++)
565		enabled_queues |= (1 << i);
566
567	nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
568}
569
570static void
571nfp_net_disable_queues(struct rte_eth_dev *dev)
572{
573	struct nfp_net_hw *hw;
574	uint32_t new_ctrl, update = 0;
575
576	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577
578	nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
579	nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
580
581	new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
582	update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
583		 NFP_NET_CFG_UPDATE_MSIX;
584
585	if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
586		new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
587
588	/* If an error when reconfig we avoid to change hw state */
589	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
590		return;
591
592	hw->ctrl = new_ctrl;
593}
594
595static int
596nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
597{
598	int i;
599
600	for (i = 0; i < dev->data->nb_rx_queues; i++) {
601		if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
602			return -1;
603	}
604	return 0;
605}
606
607static void
608nfp_net_params_setup(struct nfp_net_hw *hw)
609{
610	uint32_t *mac_address;
611
612	nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
613	nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
614
615	/* A MAC address is 8 bytes long */
616	mac_address = (uint32_t *)(hw->mac_addr);
617
618	nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
619		      rte_cpu_to_be_32(*mac_address));
620	nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
621		      rte_cpu_to_be_32(*(mac_address + 4)));
622}
623
624static void
625nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
626{
627	hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
628}
629
630static int
631nfp_net_start(struct rte_eth_dev *dev)
632{
633	uint32_t new_ctrl, update = 0;
634	struct nfp_net_hw *hw;
635	int ret;
636
637	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
638
639	PMD_INIT_LOG(DEBUG, "Start\n");
640
641	/* Disabling queues just in case... */
642	nfp_net_disable_queues(dev);
643
644	/* Writing configuration parameters in the device */
645	nfp_net_params_setup(hw);
646
647	/* Enabling the required queues in the device */
648	nfp_net_enable_queues(dev);
649
650	/* Enable device */
651	new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
652	update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
653
654	if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
655		new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
656
657	nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
658	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
659		return -EIO;
660
661	/*
662	 * Allocating rte mbuffs for configured rx queues.
663	 * This requires queues being enabled before
664	 */
665	if (nfp_net_rx_freelist_setup(dev) < 0) {
666		ret = -ENOMEM;
667		goto error;
668	}
669
670	hw->ctrl = new_ctrl;
671
672	return 0;
673
674error:
675	/*
676	 * An error returned by this function should mean the app
677	 * exiting and then the system releasing all the memory
678	 * allocated even memory coming from hugepages.
679	 *
680	 * The device could be enabled at this point with some queues
681	 * ready for getting packets. This is true if the call to
682	 * nfp_net_rx_freelist_setup() succeeds for some queues but
683	 * fails for subsequent queues.
684	 *
685	 * This should make the app exiting but better if we tell the
686	 * device first.
687	 */
688	nfp_net_disable_queues(dev);
689
690	return ret;
691}
692
693/* Stop device: disable rx and tx functions to allow for reconfiguring. */
694static void
695nfp_net_stop(struct rte_eth_dev *dev)
696{
697	int i;
698
699	PMD_INIT_LOG(DEBUG, "Stop\n");
700
701	nfp_net_disable_queues(dev);
702
703	/* Clear queues */
704	for (i = 0; i < dev->data->nb_tx_queues; i++) {
705		nfp_net_reset_tx_queue(
706			(struct nfp_net_txq *)dev->data->tx_queues[i]);
707	}
708
709	for (i = 0; i < dev->data->nb_rx_queues; i++) {
710		nfp_net_reset_rx_queue(
711			(struct nfp_net_rxq *)dev->data->rx_queues[i]);
712	}
713}
714
715/* Reset and stop device. The device can not be restarted. */
716static void
717nfp_net_close(struct rte_eth_dev *dev)
718{
719	struct nfp_net_hw *hw;
720
721	PMD_INIT_LOG(DEBUG, "Close\n");
722
723	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
724
725	/*
726	 * We assume that the DPDK application is stopping all the
727	 * threads/queues before calling the device close function.
728	 */
729
730	nfp_net_stop(dev);
731
732	rte_intr_disable(&dev->pci_dev->intr_handle);
733	nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
734
735	/*
736	 * The ixgbe PMD driver disables the pcie master on the
737	 * device. The i40e does not...
738	 */
739}
740
741static void
742nfp_net_promisc_enable(struct rte_eth_dev *dev)
743{
744	uint32_t new_ctrl, update = 0;
745	struct nfp_net_hw *hw;
746
747	PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
748
749	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
750
751	if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
752		PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
753		return;
754	}
755
756	if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
757		PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
758		return;
759	}
760
761	new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
762	update = NFP_NET_CFG_UPDATE_GEN;
763
764	/*
765	 * DPDK sets promiscuous mode on just after this call assuming
766	 * it can not fail ...
767	 */
768	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
769		return;
770
771	hw->ctrl = new_ctrl;
772}
773
774static void
775nfp_net_promisc_disable(struct rte_eth_dev *dev)
776{
777	uint32_t new_ctrl, update = 0;
778	struct nfp_net_hw *hw;
779
780	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
781
782	if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
783		PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
784		return;
785	}
786
787	new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
788	update = NFP_NET_CFG_UPDATE_GEN;
789
790	/*
791	 * DPDK sets promiscuous mode off just before this call
792	 * assuming it can not fail ...
793	 */
794	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
795		return;
796
797	hw->ctrl = new_ctrl;
798}
799
800/*
801 * return 0 means link status changed, -1 means not changed
802 *
803 * Wait to complete is needed as it can take up to 9 seconds to get the Link
804 * status.
805 */
806static int
807nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
808{
809	struct nfp_net_hw *hw;
810	struct rte_eth_link link, old;
811	uint32_t nn_link_status;
812
813	PMD_DRV_LOG(DEBUG, "Link update\n");
814
815	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
816
817	memset(&old, 0, sizeof(old));
818	nfp_net_dev_atomic_read_link_status(dev, &old);
819
820	nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
821
822	memset(&link, 0, sizeof(struct rte_eth_link));
823
824	if (nn_link_status & NFP_NET_CFG_STS_LINK)
825		link.link_status = ETH_LINK_UP;
826
827	link.link_duplex = ETH_LINK_FULL_DUPLEX;
828	/* Other cards can limit the tx and rx rate per VF */
829	link.link_speed = ETH_SPEED_NUM_40G;
830
831	if (old.link_status != link.link_status) {
832		nfp_net_dev_atomic_write_link_status(dev, &link);
833		if (link.link_status)
834			PMD_DRV_LOG(INFO, "NIC Link is Up\n");
835		else
836			PMD_DRV_LOG(INFO, "NIC Link is Down\n");
837		return 0;
838	}
839
840	return -1;
841}
842
843static void
844nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
845{
846	int i;
847	struct nfp_net_hw *hw;
848	struct rte_eth_stats nfp_dev_stats;
849
850	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
851
852	/* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
853
854	/* reading per RX ring stats */
855	for (i = 0; i < dev->data->nb_rx_queues; i++) {
856		if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
857			break;
858
859		nfp_dev_stats.q_ipackets[i] =
860			nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
861
862		nfp_dev_stats.q_ipackets[i] -=
863			hw->eth_stats_base.q_ipackets[i];
864
865		nfp_dev_stats.q_ibytes[i] =
866			nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
867
868		nfp_dev_stats.q_ibytes[i] -=
869			hw->eth_stats_base.q_ibytes[i];
870	}
871
872	/* reading per TX ring stats */
873	for (i = 0; i < dev->data->nb_tx_queues; i++) {
874		if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
875			break;
876
877		nfp_dev_stats.q_opackets[i] =
878			nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
879
880		nfp_dev_stats.q_opackets[i] -=
881			hw->eth_stats_base.q_opackets[i];
882
883		nfp_dev_stats.q_obytes[i] =
884			nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
885
886		nfp_dev_stats.q_obytes[i] -=
887			hw->eth_stats_base.q_obytes[i];
888	}
889
890	nfp_dev_stats.ipackets =
891		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
892
893	nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
894
895	nfp_dev_stats.ibytes =
896		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
897
898	nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
899
900	nfp_dev_stats.opackets =
901		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
902
903	nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
904
905	nfp_dev_stats.obytes =
906		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
907
908	nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
909
910	/* reading general device stats */
911	nfp_dev_stats.ierrors =
912		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
913
914	nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
915
916	nfp_dev_stats.oerrors =
917		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
918
919	nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
920
921	/* RX ring mbuf allocation failures */
922	nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
923
924	nfp_dev_stats.imissed =
925		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
926
927	nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
928
929	if (stats)
930		memcpy(stats, &nfp_dev_stats, sizeof(*stats));
931}
932
933static void
934nfp_net_stats_reset(struct rte_eth_dev *dev)
935{
936	int i;
937	struct nfp_net_hw *hw;
938
939	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
940
941	/*
942	 * hw->eth_stats_base records the per counter starting point.
943	 * Lets update it now
944	 */
945
946	/* reading per RX ring stats */
947	for (i = 0; i < dev->data->nb_rx_queues; i++) {
948		if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
949			break;
950
951		hw->eth_stats_base.q_ipackets[i] =
952			nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
953
954		hw->eth_stats_base.q_ibytes[i] =
955			nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
956	}
957
958	/* reading per TX ring stats */
959	for (i = 0; i < dev->data->nb_tx_queues; i++) {
960		if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
961			break;
962
963		hw->eth_stats_base.q_opackets[i] =
964			nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
965
966		hw->eth_stats_base.q_obytes[i] =
967			nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
968	}
969
970	hw->eth_stats_base.ipackets =
971		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
972
973	hw->eth_stats_base.ibytes =
974		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
975
976	hw->eth_stats_base.opackets =
977		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
978
979	hw->eth_stats_base.obytes =
980		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
981
982	/* reading general device stats */
983	hw->eth_stats_base.ierrors =
984		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
985
986	hw->eth_stats_base.oerrors =
987		nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
988
989	/* RX ring mbuf allocation failures */
990	dev->data->rx_mbuf_alloc_failed = 0;
991
992	hw->eth_stats_base.imissed =
993		nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
994}
995
996static void
997nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
998{
999	struct nfp_net_hw *hw;
1000
1001	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002
1003	dev_info->driver_name = dev->driver->pci_drv.name;
1004	dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1005	dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1006	dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1007	dev_info->max_rx_pktlen = hw->mtu;
1008	/* Next should change when PF support is implemented */
1009	dev_info->max_mac_addrs = 1;
1010
1011	if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1012		dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1013
1014	if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1015		dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1016					     DEV_RX_OFFLOAD_UDP_CKSUM |
1017					     DEV_RX_OFFLOAD_TCP_CKSUM;
1018
1019	if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1020		dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1021
1022	if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1023		dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1024					     DEV_RX_OFFLOAD_UDP_CKSUM |
1025					     DEV_RX_OFFLOAD_TCP_CKSUM;
1026
1027	dev_info->default_rxconf = (struct rte_eth_rxconf) {
1028		.rx_thresh = {
1029			.pthresh = DEFAULT_RX_PTHRESH,
1030			.hthresh = DEFAULT_RX_HTHRESH,
1031			.wthresh = DEFAULT_RX_WTHRESH,
1032		},
1033		.rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1034		.rx_drop_en = 0,
1035	};
1036
1037	dev_info->default_txconf = (struct rte_eth_txconf) {
1038		.tx_thresh = {
1039			.pthresh = DEFAULT_TX_PTHRESH,
1040			.hthresh = DEFAULT_TX_HTHRESH,
1041			.wthresh = DEFAULT_TX_WTHRESH,
1042		},
1043		.tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1044		.tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1045		.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1046			     ETH_TXQ_FLAGS_NOOFFLOADS,
1047	};
1048
1049	dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1050	dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1051
1052	dev_info->speed_capa = ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1053}
1054
1055static const uint32_t *
1056nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1057{
1058	static const uint32_t ptypes[] = {
1059		/* refers to nfp_net_set_hash() */
1060		RTE_PTYPE_INNER_L3_IPV4,
1061		RTE_PTYPE_INNER_L3_IPV6,
1062		RTE_PTYPE_INNER_L3_IPV6_EXT,
1063		RTE_PTYPE_INNER_L4_MASK,
1064		RTE_PTYPE_UNKNOWN
1065	};
1066
1067	if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1068		return ptypes;
1069	return NULL;
1070}
1071
1072static uint32_t
1073nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1074{
1075	struct nfp_net_rxq *rxq;
1076	struct nfp_net_rx_desc *rxds;
1077	uint32_t idx;
1078	uint32_t count;
1079
1080	rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1081
1082	if (rxq == NULL) {
1083		PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1084		return 0;
1085	}
1086
1087	idx = rxq->rd_p % rxq->rx_count;
1088	rxds = &rxq->rxds[idx];
1089
1090	count = 0;
1091
1092	/*
1093	 * Other PMDs are just checking the DD bit in intervals of 4
1094	 * descriptors and counting all four if the first has the DD
1095	 * bit on. Of course, this is not accurate but can be good for
1096	 * perfomance. But ideally that should be done in descriptors
1097	 * chunks belonging to the same cache line
1098	 */
1099
1100	while (count < rxq->rx_count) {
1101		rxds = &rxq->rxds[idx];
1102		if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1103			break;
1104
1105		count++;
1106		idx++;
1107
1108		/* Wrapping? */
1109		if ((idx) == rxq->rx_count)
1110			idx = 0;
1111	}
1112
1113	return count;
1114}
1115
1116static void
1117nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1118{
1119	struct rte_eth_link link;
1120
1121	memset(&link, 0, sizeof(link));
1122	nfp_net_dev_atomic_read_link_status(dev, &link);
1123	if (link.link_status)
1124		RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1125			(int)(dev->data->port_id), (unsigned)link.link_speed,
1126			link.link_duplex == ETH_LINK_FULL_DUPLEX
1127			? "full-duplex" : "half-duplex");
1128	else
1129		RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1130			(int)(dev->data->port_id));
1131
1132	RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1133		dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1134		dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1135}
1136
1137/* Interrupt configuration and handling */
1138
1139/*
1140 * nfp_net_irq_unmask - Unmask an interrupt
1141 *
1142 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1143 * clear the ICR for the entry.
1144 */
1145static void
1146nfp_net_irq_unmask(struct rte_eth_dev *dev)
1147{
1148	struct nfp_net_hw *hw;
1149
1150	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151
1152	if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1153		/* If MSI-X auto-masking is used, clear the entry */
1154		rte_wmb();
1155		rte_intr_enable(&dev->pci_dev->intr_handle);
1156	} else {
1157		/* Make sure all updates are written before un-masking */
1158		rte_wmb();
1159		nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1160			      NFP_NET_CFG_ICR_UNMASKED);
1161	}
1162}
1163
1164static void
1165nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1166			      void *param)
1167{
1168	int64_t timeout;
1169	struct rte_eth_link link;
1170	struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1171
1172	PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1173
1174	/* get the link status */
1175	memset(&link, 0, sizeof(link));
1176	nfp_net_dev_atomic_read_link_status(dev, &link);
1177
1178	nfp_net_link_update(dev, 0);
1179
1180	/* likely to up */
1181	if (!link.link_status) {
1182		/* handle it 1 sec later, wait it being stable */
1183		timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1184		/* likely to down */
1185	} else {
1186		/* handle it 4 sec later, wait it being stable */
1187		timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1188	}
1189
1190	if (rte_eal_alarm_set(timeout * 1000,
1191			      nfp_net_dev_interrupt_delayed_handler,
1192			      (void *)dev) < 0) {
1193		RTE_LOG(ERR, PMD, "Error setting alarm");
1194		/* Unmasking */
1195		nfp_net_irq_unmask(dev);
1196	}
1197}
1198
1199/*
1200 * Interrupt handler which shall be registered for alarm callback for delayed
1201 * handling specific interrupt to wait for the stable nic state. As the NIC
1202 * interrupt state is not stable for nfp after link is just down, it needs
1203 * to wait 4 seconds to get the stable status.
1204 *
1205 * @param handle   Pointer to interrupt handle.
1206 * @param param    The address of parameter (struct rte_eth_dev *)
1207 *
1208 * @return  void
1209 */
1210static void
1211nfp_net_dev_interrupt_delayed_handler(void *param)
1212{
1213	struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1214
1215	nfp_net_link_update(dev, 0);
1216	_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1217
1218	nfp_net_dev_link_status_print(dev);
1219
1220	/* Unmasking */
1221	nfp_net_irq_unmask(dev);
1222}
1223
1224static int
1225nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1226{
1227	struct nfp_net_hw *hw;
1228
1229	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230
1231	/* check that mtu is within the allowed range */
1232	if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1233		return -EINVAL;
1234
1235	/* switch to jumbo mode if needed */
1236	if ((uint32_t)mtu > ETHER_MAX_LEN)
1237		dev->data->dev_conf.rxmode.jumbo_frame = 1;
1238	else
1239		dev->data->dev_conf.rxmode.jumbo_frame = 0;
1240
1241	/* update max frame size */
1242	dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1243
1244	/* writing to configuration space */
1245	nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1246
1247	hw->mtu = mtu;
1248
1249	return 0;
1250}
1251
1252static int
1253nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1254		       uint16_t queue_idx, uint16_t nb_desc,
1255		       unsigned int socket_id,
1256		       const struct rte_eth_rxconf *rx_conf,
1257		       struct rte_mempool *mp)
1258{
1259	const struct rte_memzone *tz;
1260	struct nfp_net_rxq *rxq;
1261	struct nfp_net_hw *hw;
1262
1263	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264
1265	PMD_INIT_FUNC_TRACE();
1266
1267	/* Validating number of descriptors */
1268	if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1269	    (nb_desc > NFP_NET_MAX_RX_DESC) ||
1270	    (nb_desc < NFP_NET_MIN_RX_DESC)) {
1271		RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1272		return -EINVAL;
1273	}
1274
1275	/*
1276	 * Free memory prior to re-allocation if needed. This is the case after
1277	 * calling nfp_net_stop
1278	 */
1279	if (dev->data->rx_queues[queue_idx]) {
1280		nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1281		dev->data->rx_queues[queue_idx] = NULL;
1282	}
1283
1284	/* Allocating rx queue data structure */
1285	rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1286				 RTE_CACHE_LINE_SIZE, socket_id);
1287	if (rxq == NULL)
1288		return -ENOMEM;
1289
1290	/* Hw queues mapping based on firmware confifguration */
1291	rxq->qidx = queue_idx;
1292	rxq->fl_qcidx = queue_idx * hw->stride_rx;
1293	rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1294	rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1295	rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1296
1297	/*
1298	 * Tracking mbuf size for detecting a potential mbuf overflow due to
1299	 * RX offset
1300	 */
1301	rxq->mem_pool = mp;
1302	rxq->mbuf_size = rxq->mem_pool->elt_size;
1303	rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1304	hw->flbufsz = rxq->mbuf_size;
1305
1306	rxq->rx_count = nb_desc;
1307	rxq->port_id = dev->data->port_id;
1308	rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1309	rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1310				  : ETHER_CRC_LEN);
1311	rxq->drop_en = rx_conf->rx_drop_en;
1312
1313	/*
1314	 * Allocate RX ring hardware descriptors. A memzone large enough to
1315	 * handle the maximum ring size is allocated in order to allow for
1316	 * resizing in later calls to the queue setup function.
1317	 */
1318	tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1319				   sizeof(struct nfp_net_rx_desc) *
1320				   NFP_NET_MAX_RX_DESC, socket_id);
1321
1322	if (tz == NULL) {
1323		RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1324		nfp_net_rx_queue_release(rxq);
1325		return -ENOMEM;
1326	}
1327
1328	/* Saving physical and virtual addresses for the RX ring */
1329	rxq->dma = (uint64_t)tz->phys_addr;
1330	rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1331
1332	/* mbuf pointers array for referencing mbufs linked to RX descriptors */
1333	rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1334					 sizeof(*rxq->rxbufs) * nb_desc,
1335					 RTE_CACHE_LINE_SIZE, socket_id);
1336	if (rxq->rxbufs == NULL) {
1337		nfp_net_rx_queue_release(rxq);
1338		return -ENOMEM;
1339	}
1340
1341	PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1342		   rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1343
1344	nfp_net_reset_rx_queue(rxq);
1345
1346	dev->data->rx_queues[queue_idx] = rxq;
1347	rxq->hw = hw;
1348
1349	/*
1350	 * Telling the HW about the physical address of the RX ring and number
1351	 * of descriptors in log2 format
1352	 */
1353	nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1354	nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1355
1356	return 0;
1357}
1358
1359static int
1360nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1361{
1362	struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1363	uint64_t dma_addr;
1364	unsigned i;
1365
1366	PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1367		   rxq->rx_count);
1368
1369	for (i = 0; i < rxq->rx_count; i++) {
1370		struct nfp_net_rx_desc *rxd;
1371		struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1372
1373		if (mbuf == NULL) {
1374			RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1375				(unsigned)rxq->qidx);
1376			return -ENOMEM;
1377		}
1378
1379		dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1380
1381		rxd = &rxq->rxds[i];
1382		rxd->fld.dd = 0;
1383		rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1384		rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1385		rxe[i].mbuf = mbuf;
1386		PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1387
1388		rxq->wr_p++;
1389	}
1390
1391	/* Make sure all writes are flushed before telling the hardware */
1392	rte_wmb();
1393
1394	/* Not advertising the whole ring as the firmware gets confused if so */
1395	PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1396		   rxq->rx_count - 1);
1397
1398	nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1399
1400	return 0;
1401}
1402
1403static int
1404nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1405		       uint16_t nb_desc, unsigned int socket_id,
1406		       const struct rte_eth_txconf *tx_conf)
1407{
1408	const struct rte_memzone *tz;
1409	struct nfp_net_txq *txq;
1410	uint16_t tx_free_thresh;
1411	struct nfp_net_hw *hw;
1412
1413	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414
1415	PMD_INIT_FUNC_TRACE();
1416
1417	/* Validating number of descriptors */
1418	if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1419	    (nb_desc > NFP_NET_MAX_TX_DESC) ||
1420	    (nb_desc < NFP_NET_MIN_TX_DESC)) {
1421		RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1422		return -EINVAL;
1423	}
1424
1425	tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1426				    tx_conf->tx_free_thresh :
1427				    DEFAULT_TX_FREE_THRESH);
1428
1429	if (tx_free_thresh > (nb_desc)) {
1430		RTE_LOG(ERR, PMD,
1431			"tx_free_thresh must be less than the number of TX "
1432			"descriptors. (tx_free_thresh=%u port=%d "
1433			"queue=%d)\n", (unsigned int)tx_free_thresh,
1434			(int)dev->data->port_id, (int)queue_idx);
1435		return -(EINVAL);
1436	}
1437
1438	/*
1439	 * Free memory prior to re-allocation if needed. This is the case after
1440	 * calling nfp_net_stop
1441	 */
1442	if (dev->data->tx_queues[queue_idx]) {
1443		PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1444			   queue_idx);
1445		nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1446		dev->data->tx_queues[queue_idx] = NULL;
1447	}
1448
1449	/* Allocating tx queue data structure */
1450	txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1451				 RTE_CACHE_LINE_SIZE, socket_id);
1452	if (txq == NULL) {
1453		RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1454		return -ENOMEM;
1455	}
1456
1457	/*
1458	 * Allocate TX ring hardware descriptors. A memzone large enough to
1459	 * handle the maximum ring size is allocated in order to allow for
1460	 * resizing in later calls to the queue setup function.
1461	 */
1462	tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1463				   sizeof(struct nfp_net_tx_desc) *
1464				   NFP_NET_MAX_TX_DESC, socket_id);
1465	if (tz == NULL) {
1466		RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1467		nfp_net_tx_queue_release(txq);
1468		return -ENOMEM;
1469	}
1470
1471	txq->tx_count = nb_desc;
1472	txq->tail = 0;
1473	txq->tx_free_thresh = tx_free_thresh;
1474	txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1475	txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1476	txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1477
1478	/* queue mapping based on firmware configuration */
1479	txq->qidx = queue_idx;
1480	txq->tx_qcidx = queue_idx * hw->stride_tx;
1481	txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1482
1483	txq->port_id = dev->data->port_id;
1484	txq->txq_flags = tx_conf->txq_flags;
1485
1486	/* Saving physical and virtual addresses for the TX ring */
1487	txq->dma = (uint64_t)tz->phys_addr;
1488	txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1489
1490	/* mbuf pointers array for referencing mbufs linked to TX descriptors */
1491	txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1492					 sizeof(*txq->txbufs) * nb_desc,
1493					 RTE_CACHE_LINE_SIZE, socket_id);
1494	if (txq->txbufs == NULL) {
1495		nfp_net_tx_queue_release(txq);
1496		return -ENOMEM;
1497	}
1498	PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1499		   txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1500
1501	nfp_net_reset_tx_queue(txq);
1502
1503	dev->data->tx_queues[queue_idx] = txq;
1504	txq->hw = hw;
1505
1506	/*
1507	 * Telling the HW about the physical address of the TX ring and number
1508	 * of descriptors in log2 format
1509	 */
1510	nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1511	nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1512
1513	return 0;
1514}
1515
1516/* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1517static inline void
1518nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1519		 struct rte_mbuf *mb)
1520{
1521	uint64_t ol_flags;
1522	struct nfp_net_hw *hw = txq->hw;
1523
1524	if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1525		return;
1526
1527	ol_flags = mb->ol_flags;
1528
1529	/* IPv6 does not need checksum */
1530	if (ol_flags & PKT_TX_IP_CKSUM)
1531		txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1532
1533	switch (ol_flags & PKT_TX_L4_MASK) {
1534	case PKT_TX_UDP_CKSUM:
1535		txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1536		break;
1537	case PKT_TX_TCP_CKSUM:
1538		txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1539		break;
1540	}
1541
1542	if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1543		txd->flags |= PCIE_DESC_TX_CSUM;
1544}
1545
1546/* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1547static inline void
1548nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1549		 struct rte_mbuf *mb)
1550{
1551	struct nfp_net_hw *hw = rxq->hw;
1552
1553	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1554		return;
1555
1556	/* If IPv4 and IP checksum error, fail */
1557	if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1558	    !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1559		mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1560
1561	/* If neither UDP nor TCP return */
1562	if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1563	    !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1564		return;
1565
1566	if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1567	    !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1568		mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1569
1570	if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1571	    !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1572		mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1573}
1574
1575#define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1576#define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1577
1578/*
1579 * nfp_net_set_hash - Set mbuf hash data
1580 *
1581 * The RSS hash and hash-type are pre-pended to the packet data.
1582 * Extract and decode it and set the mbuf fields.
1583 */
1584static inline void
1585nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1586		 struct rte_mbuf *mbuf)
1587{
1588	uint32_t hash;
1589	uint32_t hash_type;
1590	struct nfp_net_hw *hw = rxq->hw;
1591
1592	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1593		return;
1594
1595	if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1596		return;
1597
1598	hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1599	hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1600
1601	/*
1602	 * hash type is sharing the same word with input port info
1603	 * 31-8: input port
1604	 * 7:0: hash type
1605	 */
1606	hash_type &= 0xff;
1607	mbuf->hash.rss = hash;
1608	mbuf->ol_flags |= PKT_RX_RSS_HASH;
1609
1610	switch (hash_type) {
1611	case NFP_NET_RSS_IPV4:
1612		mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1613		break;
1614	case NFP_NET_RSS_IPV6:
1615		mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1616		break;
1617	case NFP_NET_RSS_IPV6_EX:
1618		mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1619		break;
1620	default:
1621		mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1622	}
1623}
1624
1625/* nfp_net_check_port - Set mbuf in_port field */
1626static void
1627nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1628{
1629	uint32_t port;
1630
1631	if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1632		mbuf->port = 0;
1633		return;
1634	}
1635
1636	port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1637					      mbuf->data_off - 8));
1638
1639	/*
1640	 * hash type is sharing the same word with input port info
1641	 * 31-8: input port
1642	 * 7:0: hash type
1643	 */
1644	port = (uint8_t)(port >> 8);
1645	mbuf->port = port;
1646}
1647
1648static inline void
1649nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1650{
1651	rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1652}
1653
1654#define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1655
1656/*
1657 * RX path design:
1658 *
1659 * There are some decissions to take:
1660 * 1) How to check DD RX descriptors bit
1661 * 2) How and when to allocate new mbufs
1662 *
1663 * Current implementation checks just one single DD bit each loop. As each
1664 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1665 * a single cache line instead. Tests with this change have not shown any
1666 * performance improvement but it requires further investigation. For example,
1667 * depending on which descriptor is next, the number of descriptors could be
1668 * less than 8 for just checking those in the same cache line. This implies
1669 * extra work which could be counterproductive by itself. Indeed, last firmware
1670 * changes are just doing this: writing several descriptors with the DD bit
1671 * for saving PCIe bandwidth and DMA operations from the NFP.
1672 *
1673 * Mbuf allocation is done when a new packet is received. Then the descriptor
1674 * is automatically linked with the new mbuf and the old one is given to the
1675 * user. The main drawback with this design is mbuf allocation is heavier than
1676 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1677 * cache point of view it does not seem allocating the mbuf early on as we are
1678 * doing now have any benefit at all. Again, tests with this change have not
1679 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1680 * so looking at the implications of this type of allocation should be studied
1681 * deeply
1682 */
1683
1684static uint16_t
1685nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1686{
1687	struct nfp_net_rxq *rxq;
1688	struct nfp_net_rx_desc *rxds;
1689	struct nfp_net_rx_buff *rxb;
1690	struct nfp_net_hw *hw;
1691	struct rte_mbuf *mb;
1692	struct rte_mbuf *new_mb;
1693	int idx;
1694	uint16_t nb_hold;
1695	uint64_t dma_addr;
1696	int avail;
1697
1698	rxq = rx_queue;
1699	if (unlikely(rxq == NULL)) {
1700		/*
1701		 * DPDK just checks the queue is lower than max queues
1702		 * enabled. But the queue needs to be configured
1703		 */
1704		RTE_LOG(ERR, PMD, "RX Bad queue\n");
1705		return -EINVAL;
1706	}
1707
1708	hw = rxq->hw;
1709	avail = 0;
1710	nb_hold = 0;
1711
1712	while (avail < nb_pkts) {
1713		idx = rxq->rd_p % rxq->rx_count;
1714
1715		rxb = &rxq->rxbufs[idx];
1716		if (unlikely(rxb == NULL)) {
1717			RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1718			break;
1719		}
1720
1721		/*
1722		 * Memory barrier to ensure that we won't do other
1723		 * reads before the DD bit.
1724		 */
1725		rte_rmb();
1726
1727		rxds = &rxq->rxds[idx];
1728		if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1729			break;
1730
1731		/*
1732		 * We got a packet. Let's alloc a new mbuff for refilling the
1733		 * free descriptor ring as soon as possible
1734		 */
1735		new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1736		if (unlikely(new_mb == NULL)) {
1737			RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1738				"queue_id=%u\n", (unsigned)rxq->port_id,
1739				(unsigned)rxq->qidx);
1740			nfp_net_mbuf_alloc_failed(rxq);
1741			break;
1742		}
1743
1744		nb_hold++;
1745
1746		/*
1747		 * Grab the mbuff and refill the descriptor with the
1748		 * previously allocated mbuff
1749		 */
1750		mb = rxb->mbuf;
1751		rxb->mbuf = new_mb;
1752
1753		PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1754			   rxds->rxd.data_len, rxq->mbuf_size);
1755
1756		/* Size of this segment */
1757		mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1758		/* Size of the whole packet. We just support 1 segment */
1759		mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1760
1761		if (unlikely((mb->data_len + hw->rx_offset) >
1762			     rxq->mbuf_size)) {
1763			/*
1764			 * This should not happen and the user has the
1765			 * responsibility of avoiding it. But we have
1766			 * to give some info about the error
1767			 */
1768			RTE_LOG(ERR, PMD,
1769				"mbuf overflow likely due to the RX offset.\n"
1770				"\t\tYour mbuf size should have extra space for"
1771				" RX offset=%u bytes.\n"
1772				"\t\tCurrently you just have %u bytes available"
1773				" but the received packet is %u bytes long",
1774				hw->rx_offset,
1775				rxq->mbuf_size - hw->rx_offset,
1776				mb->data_len);
1777			return -EINVAL;
1778		}
1779
1780		/* Filling the received mbuff with packet info */
1781		if (hw->rx_offset)
1782			mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1783		else
1784			mb->data_off = RTE_PKTMBUF_HEADROOM +
1785				       NFP_DESC_META_LEN(rxds);
1786
1787		/* No scatter mode supported */
1788		mb->nb_segs = 1;
1789		mb->next = NULL;
1790
1791		/* Checking the RSS flag */
1792		nfp_net_set_hash(rxq, rxds, mb);
1793
1794		/* Checking the checksum flag */
1795		nfp_net_rx_cksum(rxq, rxds, mb);
1796
1797		/* Checking the port flag */
1798		nfp_net_check_port(rxds, mb);
1799
1800		if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1801		    (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1802			mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1803			mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1804		}
1805
1806		/* Adding the mbuff to the mbuff array passed by the app */
1807		rx_pkts[avail++] = mb;
1808
1809		/* Now resetting and updating the descriptor */
1810		rxds->vals[0] = 0;
1811		rxds->vals[1] = 0;
1812		dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1813		rxds->fld.dd = 0;
1814		rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1815		rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1816
1817		rxq->rd_p++;
1818	}
1819
1820	if (nb_hold == 0)
1821		return nb_hold;
1822
1823	PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
1824		   (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1825
1826	nb_hold += rxq->nb_rx_hold;
1827
1828	/*
1829	 * FL descriptors needs to be written before incrementing the
1830	 * FL queue WR pointer
1831	 */
1832	rte_wmb();
1833	if (nb_hold > rxq->rx_free_thresh) {
1834		PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1835			   (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1836			   (unsigned)nb_hold, (unsigned)avail);
1837		nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1838		nb_hold = 0;
1839	}
1840	rxq->nb_rx_hold = nb_hold;
1841
1842	return avail;
1843}
1844
1845/*
1846 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1847 * status
1848 * @txq: TX queue to work with
1849 * Returns number of descriptors freed
1850 */
1851int
1852nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1853{
1854	uint32_t qcp_rd_p;
1855	int todo;
1856
1857	PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1858		   " status\n", txq->qidx);
1859
1860	/* Work out how many packets have been sent */
1861	qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1862
1863	if (qcp_rd_p == txq->qcp_rd_p) {
1864		PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1865			   "packets (%u, %u)\n", txq->qidx,
1866			   qcp_rd_p, txq->qcp_rd_p);
1867		return 0;
1868	}
1869
1870	if (qcp_rd_p > txq->qcp_rd_p)
1871		todo = qcp_rd_p - txq->qcp_rd_p;
1872	else
1873		todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1874
1875	PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1876		   qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1877
1878	if (todo == 0)
1879		return todo;
1880
1881	txq->qcp_rd_p += todo;
1882	txq->qcp_rd_p %= txq->tx_count;
1883	txq->rd_p += todo;
1884
1885	return todo;
1886}
1887
1888/* Leaving always free descriptors for avoiding wrapping confusion */
1889#define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1890
1891/*
1892 * nfp_net_txq_full - Check if the TX queue free descriptors
1893 * is below tx_free_threshold
1894 *
1895 * @txq: TX queue to check
1896 *
1897 * This function uses the host copy* of read/write pointers
1898 */
1899static inline
1900int nfp_net_txq_full(struct nfp_net_txq *txq)
1901{
1902	return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1903}
1904
1905static uint16_t
1906nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1907{
1908	struct nfp_net_txq *txq;
1909	struct nfp_net_hw *hw;
1910	struct nfp_net_tx_desc *txds;
1911	struct rte_mbuf *pkt;
1912	uint64_t dma_addr;
1913	int pkt_size, dma_size;
1914	uint16_t free_descs, issued_descs;
1915	struct rte_mbuf **lmbuf;
1916	int i;
1917
1918	txq = tx_queue;
1919	hw = txq->hw;
1920	txds = &txq->txds[txq->tail];
1921
1922	PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1923		   txq->qidx, txq->tail, nb_pkts);
1924
1925	if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1926		nfp_net_tx_free_bufs(txq);
1927
1928	free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1929	if (unlikely(free_descs == 0))
1930		return 0;
1931
1932	pkt = *tx_pkts;
1933
1934	i = 0;
1935	issued_descs = 0;
1936	PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1937		   txq->qidx, nb_pkts);
1938	/* Sending packets */
1939	while ((i < nb_pkts) && free_descs) {
1940		/* Grabbing the mbuf linked to the current descriptor */
1941		lmbuf = &txq->txbufs[txq->tail].mbuf;
1942		/* Warming the cache for releasing the mbuf later on */
1943		RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1944
1945		pkt = *(tx_pkts + i);
1946
1947		if (unlikely((pkt->nb_segs > 1) &&
1948			     !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1949			PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1950			rte_panic("Multisegment packet unsupported\n");
1951		}
1952
1953		/* Checking if we have enough descriptors */
1954		if (unlikely(pkt->nb_segs > free_descs))
1955			goto xmit_end;
1956
1957		/*
1958		 * Checksum and VLAN flags just in the first descriptor for a
1959		 * multisegment packet
1960		 */
1961		nfp_net_tx_cksum(txq, txds, pkt);
1962
1963		if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1964		    (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1965			txds->flags |= PCIE_DESC_TX_VLAN;
1966			txds->vlan = pkt->vlan_tci;
1967		}
1968
1969		if (pkt->ol_flags & PKT_TX_TCP_SEG)
1970			rte_panic("TSO is not supported\n");
1971
1972		/*
1973		 * mbuf data_len is the data in one segment and pkt_len data
1974		 * in the whole packet. When the packet is just one segment,
1975		 * then data_len = pkt_len
1976		 */
1977		pkt_size = pkt->pkt_len;
1978
1979		/* Releasing mbuf which was prefetched above */
1980		if (*lmbuf)
1981			rte_pktmbuf_free(*lmbuf);
1982		/*
1983		 * Linking mbuf with descriptor for being released
1984		 * next time descriptor is used
1985		 */
1986		*lmbuf = pkt;
1987
1988		while (pkt_size) {
1989			dma_size = pkt->data_len;
1990			dma_addr = rte_mbuf_data_dma_addr(pkt);
1991			PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1992				   "%" PRIx64 "\n", dma_addr);
1993
1994			/* Filling descriptors fields */
1995			txds->dma_len = dma_size;
1996			txds->data_len = pkt->pkt_len;
1997			txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1998			txds->dma_addr_lo = (dma_addr & 0xffffffff);
1999			ASSERT(free_descs > 0);
2000			free_descs--;
2001
2002			txq->wr_p++;
2003			txq->tail++;
2004			if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2005				txq->tail = 0;
2006
2007			pkt_size -= dma_size;
2008			if (!pkt_size) {
2009				/* End of packet */
2010				txds->offset_eop |= PCIE_DESC_TX_EOP;
2011			} else {
2012				txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2013				pkt = pkt->next;
2014			}
2015			/* Referencing next free TX descriptor */
2016			txds = &txq->txds[txq->tail];
2017			issued_descs++;
2018		}
2019		i++;
2020	}
2021
2022xmit_end:
2023	/* Increment write pointers. Force memory write before we let HW know */
2024	rte_wmb();
2025	nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2026
2027	return i;
2028}
2029
2030static void
2031nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2032{
2033	uint32_t new_ctrl, update;
2034	struct nfp_net_hw *hw;
2035
2036	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2037	new_ctrl = 0;
2038
2039	if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2040	    (mask & ETH_VLAN_FILTER_OFFLOAD))
2041		RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2042			" ETH_VLAN_FILTER_EXTEND");
2043
2044	/* Enable vlan strip if it is not configured yet */
2045	if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2046	    !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2047		new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2048
2049	/* Disable vlan strip just if it is configured */
2050	if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2051	    (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2052		new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2053
2054	if (new_ctrl == 0)
2055		return;
2056
2057	update = NFP_NET_CFG_UPDATE_GEN;
2058
2059	if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2060		return;
2061
2062	hw->ctrl = new_ctrl;
2063}
2064
2065/* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2066static int
2067nfp_net_reta_update(struct rte_eth_dev *dev,
2068		    struct rte_eth_rss_reta_entry64 *reta_conf,
2069		    uint16_t reta_size)
2070{
2071	uint32_t reta, mask;
2072	int i, j;
2073	int idx, shift;
2074	uint32_t update;
2075	struct nfp_net_hw *hw =
2076		NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077
2078	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2079		return -EINVAL;
2080
2081	if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2082		RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2083			"(%d) doesn't match the number hardware can supported "
2084			"(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2085		return -EINVAL;
2086	}
2087
2088	/*
2089	 * Update Redirection Table. There are 128 8bit-entries which can be
2090	 * manage as 32 32bit-entries
2091	 */
2092	for (i = 0; i < reta_size; i += 4) {
2093		/* Handling 4 RSS entries per loop */
2094		idx = i / RTE_RETA_GROUP_SIZE;
2095		shift = i % RTE_RETA_GROUP_SIZE;
2096		mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2097
2098		if (!mask)
2099			continue;
2100
2101		reta = 0;
2102		/* If all 4 entries were set, don't need read RETA register */
2103		if (mask != 0xF)
2104			reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2105
2106		for (j = 0; j < 4; j++) {
2107			if (!(mask & (0x1 << j)))
2108				continue;
2109			if (mask != 0xF)
2110				/* Clearing the entry bits */
2111				reta &= ~(0xFF << (8 * j));
2112			reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2113		}
2114		nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2115	}
2116
2117	update = NFP_NET_CFG_UPDATE_RSS;
2118
2119	if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2120		return -EIO;
2121
2122	return 0;
2123}
2124
2125 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2126static int
2127nfp_net_reta_query(struct rte_eth_dev *dev,
2128		   struct rte_eth_rss_reta_entry64 *reta_conf,
2129		   uint16_t reta_size)
2130{
2131	uint8_t i, j, mask;
2132	int idx, shift;
2133	uint32_t reta;
2134	struct nfp_net_hw *hw;
2135
2136	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137
2138	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2139		return -EINVAL;
2140
2141	if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2142		RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2143			"(%d) doesn't match the number hardware can supported "
2144			"(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2145		return -EINVAL;
2146	}
2147
2148	/*
2149	 * Reading Redirection Table. There are 128 8bit-entries which can be
2150	 * manage as 32 32bit-entries
2151	 */
2152	for (i = 0; i < reta_size; i += 4) {
2153		/* Handling 4 RSS entries per loop */
2154		idx = i / RTE_RETA_GROUP_SIZE;
2155		shift = i % RTE_RETA_GROUP_SIZE;
2156		mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2157
2158		if (!mask)
2159			continue;
2160
2161		reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2162		for (j = 0; j < 4; j++) {
2163			if (!(mask & (0x1 << j)))
2164				continue;
2165			reta_conf->reta[shift + j] =
2166				(uint8_t)((reta >> (8 * j)) & 0xF);
2167		}
2168	}
2169	return 0;
2170}
2171
2172static int
2173nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2174			struct rte_eth_rss_conf *rss_conf)
2175{
2176	uint32_t update;
2177	uint32_t cfg_rss_ctrl = 0;
2178	uint8_t key;
2179	uint64_t rss_hf;
2180	int i;
2181	struct nfp_net_hw *hw;
2182
2183	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184
2185	rss_hf = rss_conf->rss_hf;
2186
2187	/* Checking if RSS is enabled */
2188	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2189		if (rss_hf != 0) { /* Enable RSS? */
2190			RTE_LOG(ERR, PMD, "RSS unsupported\n");
2191			return -EINVAL;
2192		}
2193		return 0; /* Nothing to do */
2194	}
2195
2196	if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2197		RTE_LOG(ERR, PMD, "hash key too long\n");
2198		return -EINVAL;
2199	}
2200
2201	if (rss_hf & ETH_RSS_IPV4)
2202		cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2203				NFP_NET_CFG_RSS_IPV4_TCP |
2204				NFP_NET_CFG_RSS_IPV4_UDP;
2205
2206	if (rss_hf & ETH_RSS_IPV6)
2207		cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2208				NFP_NET_CFG_RSS_IPV6_TCP |
2209				NFP_NET_CFG_RSS_IPV6_UDP;
2210
2211	/* configuring where to apply the RSS hash */
2212	nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2213
2214	/* Writing the key byte a byte */
2215	for (i = 0; i < rss_conf->rss_key_len; i++) {
2216		memcpy(&key, &rss_conf->rss_key[i], 1);
2217		nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2218	}
2219
2220	/* Writing the key size */
2221	nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2222
2223	update = NFP_NET_CFG_UPDATE_RSS;
2224
2225	if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2226		return -EIO;
2227
2228	return 0;
2229}
2230
2231static int
2232nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2233			  struct rte_eth_rss_conf *rss_conf)
2234{
2235	uint64_t rss_hf;
2236	uint32_t cfg_rss_ctrl;
2237	uint8_t key;
2238	int i;
2239	struct nfp_net_hw *hw;
2240
2241	hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242
2243	if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2244		return -EINVAL;
2245
2246	rss_hf = rss_conf->rss_hf;
2247	cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2248
2249	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2250		rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2251
2252	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2253		rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2254
2255	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2256		rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2257
2258	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2259		rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2260
2261	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2262		rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2263
2264	if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2265		rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2266
2267	/* Reading the key size */
2268	rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2269
2270	/* Reading the key byte a byte */
2271	for (i = 0; i < rss_conf->rss_key_len; i++) {
2272		key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2273		memcpy(&rss_conf->rss_key[i], &key, 1);
2274	}
2275
2276	return 0;
2277}
2278
2279/* Initialise and register driver with DPDK Application */
2280static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2281	.dev_configure		= nfp_net_configure,
2282	.dev_start		= nfp_net_start,
2283	.dev_stop		= nfp_net_stop,
2284	.dev_close		= nfp_net_close,
2285	.promiscuous_enable	= nfp_net_promisc_enable,
2286	.promiscuous_disable	= nfp_net_promisc_disable,
2287	.link_update		= nfp_net_link_update,
2288	.stats_get		= nfp_net_stats_get,
2289	.stats_reset		= nfp_net_stats_reset,
2290	.dev_infos_get		= nfp_net_infos_get,
2291	.dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2292	.mtu_set		= nfp_net_dev_mtu_set,
2293	.vlan_offload_set	= nfp_net_vlan_offload_set,
2294	.reta_update		= nfp_net_reta_update,
2295	.reta_query		= nfp_net_reta_query,
2296	.rss_hash_update	= nfp_net_rss_hash_update,
2297	.rss_hash_conf_get	= nfp_net_rss_hash_conf_get,
2298	.rx_queue_setup		= nfp_net_rx_queue_setup,
2299	.rx_queue_release	= nfp_net_rx_queue_release,
2300	.rx_queue_count		= nfp_net_rx_queue_count,
2301	.tx_queue_setup		= nfp_net_tx_queue_setup,
2302	.tx_queue_release	= nfp_net_tx_queue_release,
2303};
2304
2305static int
2306nfp_net_init(struct rte_eth_dev *eth_dev)
2307{
2308	struct rte_pci_device *pci_dev;
2309	struct nfp_net_hw *hw;
2310
2311	uint32_t tx_bar_off, rx_bar_off;
2312	uint32_t start_q;
2313	int stride = 4;
2314
2315	PMD_INIT_FUNC_TRACE();
2316
2317	hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2318
2319	eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2320	eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2321	eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2322
2323	/* For secondary processes, the primary has done all the work */
2324	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2325		return 0;
2326
2327	pci_dev = eth_dev->pci_dev;
2328	rte_eth_copy_pci_info(eth_dev, pci_dev);
2329
2330	hw->device_id = pci_dev->id.device_id;
2331	hw->vendor_id = pci_dev->id.vendor_id;
2332	hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2333	hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2334
2335	PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2336		     pci_dev->id.vendor_id, pci_dev->id.device_id,
2337		     pci_dev->addr.domain, pci_dev->addr.bus,
2338		     pci_dev->addr.devid, pci_dev->addr.function);
2339
2340	hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2341	if (hw->ctrl_bar == NULL) {
2342		RTE_LOG(ERR, PMD,
2343			"hw->ctrl_bar is NULL. BAR0 not configured\n");
2344		return -ENODEV;
2345	}
2346	hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2347	hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2348
2349	/* Work out where in the BAR the queues start. */
2350	switch (pci_dev->id.device_id) {
2351	case PCI_DEVICE_ID_NFP6000_VF_NIC:
2352		start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2353		tx_bar_off = NFP_PCIE_QUEUE(start_q);
2354		start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2355		rx_bar_off = NFP_PCIE_QUEUE(start_q);
2356		break;
2357	default:
2358		RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2359		return -ENODEV;
2360	}
2361
2362	PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2363	PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2364
2365	hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2366	hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2367
2368	PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2369		     hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2370
2371	nfp_net_cfg_queue_setup(hw);
2372
2373	/* Get some of the read-only fields from the config BAR */
2374	hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2375	hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2376	hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2377	hw->mtu = hw->max_mtu;
2378
2379	if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2380		hw->rx_offset = NFP_NET_RX_OFFSET;
2381	else
2382		hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2383
2384	PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2385		     hw->ver, hw->max_mtu);
2386	PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2387		     hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2388		     hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2389		     hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2390		     hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2391		     hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2392		     hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2393		     hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2394		     hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2395		     hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2396
2397	pci_dev = eth_dev->pci_dev;
2398	hw->ctrl = 0;
2399
2400	hw->stride_rx = stride;
2401	hw->stride_tx = stride;
2402
2403	PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2404		     hw->max_rx_queues, hw->max_tx_queues);
2405
2406	/* Initializing spinlock for reconfigs */
2407	rte_spinlock_init(&hw->reconfig_lock);
2408
2409	/* Allocating memory for mac addr */
2410	eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2411	if (eth_dev->data->mac_addrs == NULL) {
2412		PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2413		return -ENOMEM;
2414	}
2415
2416	/* Using random mac addresses for VFs */
2417	eth_random_addr(&hw->mac_addr[0]);
2418
2419	/* Copying mac address to DPDK eth_dev struct */
2420	ether_addr_copy(&eth_dev->data->mac_addrs[0],
2421			(struct ether_addr *)hw->mac_addr);
2422
2423	PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2424		     "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2425		     eth_dev->data->port_id, pci_dev->id.vendor_id,
2426		     pci_dev->id.device_id,
2427		     hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2428		     hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2429
2430	/* Registering LSC interrupt handler */
2431	rte_intr_callback_register(&pci_dev->intr_handle,
2432				   nfp_net_dev_interrupt_handler,
2433				   (void *)eth_dev);
2434
2435	/* enable uio intr after callback register */
2436	rte_intr_enable(&pci_dev->intr_handle);
2437
2438	/* Telling the firmware about the LSC interrupt entry */
2439	nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2440
2441	/* Recording current stats counters values */
2442	nfp_net_stats_reset(eth_dev);
2443
2444	return 0;
2445}
2446
2447static struct rte_pci_id pci_id_nfp_net_map[] = {
2448	{
2449		RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2450			       PCI_DEVICE_ID_NFP6000_PF_NIC)
2451	},
2452	{
2453		RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2454			       PCI_DEVICE_ID_NFP6000_VF_NIC)
2455	},
2456	{
2457		.vendor_id = 0,
2458	},
2459};
2460
2461static struct eth_driver rte_nfp_net_pmd = {
2462	{
2463		.name = "rte_nfp_net_pmd",
2464		.id_table = pci_id_nfp_net_map,
2465		.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2466			     RTE_PCI_DRV_DETACHABLE,
2467	},
2468	.eth_dev_init = nfp_net_init,
2469	.dev_private_size = sizeof(struct nfp_net_adapter),
2470};
2471
2472static int
2473nfp_net_pmd_init(const char *name __rte_unused,
2474		 const char *params __rte_unused)
2475{
2476	PMD_INIT_FUNC_TRACE();
2477	PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2478		     NFP_NET_PMD_VERSION);
2479
2480	rte_eth_driver_register(&rte_nfp_net_pmd);
2481	return 0;
2482}
2483
2484static struct rte_driver rte_nfp_net_driver = {
2485	.type = PMD_PDEV,
2486	.init = nfp_net_pmd_init,
2487};
2488
2489PMD_REGISTER_DRIVER(rte_nfp_net_driver, nfp);
2490DRIVER_REGISTER_PCI_TABLE(nfp, pci_id_nfp_net_map);
2491
2492/*
2493 * Local variables:
2494 * c-file-style: "Linux"
2495 * indent-tabs-mode: t
2496 * End:
2497 */
2498