reg_addr.h revision 6b3e017e
1/*
2 * Copyright (c) 2016 QLogic Corporation.
3 * All rights reserved.
4 * www.qlogic.com
5 *
6 * See LICENSE.qede_pmd for copyright and licensing details.
7 */
8
9/*
10 * Copyright (c) 2016 QLogic Corporation.
11 * All rights reserved.
12 * www.qlogic.com
13 *
14 * See LICENSE.qede_pmd for copyright and licensing details.
15 */
16
17#define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
18	0
19
20#define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE		( \
21		0xfff << 0)
22
23#define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
24	12
25
26#define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE		( \
27		0xfff << 12)
28
29#define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
30	24
31
32#define  CDU_REG_CID_ADDR_PARAMS_NCIB			( \
33		0xff << 24)
34
35#define  XSDM_REG_OPERATION_GEN \
36	0xf80408UL
37#define  NIG_REG_RX_BRB_OUT_EN \
38	0x500e18UL
39#define  NIG_REG_STORM_OUT_EN \
40	0x500e08UL
41#define  PSWRQ2_REG_L2P_VALIDATE_VFID \
42	0x240c50UL
43#define  PGLUE_B_REG_USE_CLIENTID_IN_TAG	\
44	0x2aae04UL
45#define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER	\
46	0x2aa16cUL
47#define  BAR0_MAP_REG_MSDM_RAM \
48	0x1d00000UL
49#define  BAR0_MAP_REG_USDM_RAM \
50	0x1d80000UL
51#define  BAR0_MAP_REG_PSDM_RAM \
52	0x1f00000UL
53#define  BAR0_MAP_REG_TSDM_RAM \
54	0x1c80000UL
55#define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
56	0x5011f4UL
57#define  PRS_REG_SEARCH_TCP \
58	0x1f0400UL
59#define  PRS_REG_SEARCH_UDP \
60	0x1f0404UL
61#define  PRS_REG_SEARCH_OPENFLOW	\
62	0x1f0434UL
63#define  TM_REG_PF_ENABLE_CONN \
64	0x2c043cUL
65#define  TM_REG_PF_ENABLE_TASK \
66	0x2c0444UL
67#define  TM_REG_PF_SCAN_ACTIVE_CONN \
68	0x2c04fcUL
69#define  TM_REG_PF_SCAN_ACTIVE_TASK \
70	0x2c0500UL
71#define  IGU_REG_LEADING_EDGE_LATCH \
72	0x18082cUL
73#define  IGU_REG_TRAILING_EDGE_LATCH \
74	0x180830UL
75#define  QM_REG_USG_CNT_PF_TX \
76	0x2f2eacUL
77#define  QM_REG_USG_CNT_PF_OTHER	\
78	0x2f2eb0UL
79#define  DORQ_REG_PF_DB_ENABLE \
80	0x100508UL
81#define  QM_REG_PF_EN \
82	0x2f2ea4UL
83#define  TCFC_REG_STRONG_ENABLE_PF \
84	0x2d0708UL
85#define  CCFC_REG_STRONG_ENABLE_PF \
86	0x2e0708UL
87#define  PGLUE_B_REG_PGL_ADDR_88_F0 \
88	0x2aa404UL
89#define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
90	0x2aa408UL
91#define  PGLUE_B_REG_PGL_ADDR_90_F0 \
92	0x2aa40cUL
93#define  PGLUE_B_REG_PGL_ADDR_94_F0 \
94	0x2aa410UL
95#define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
96	0x2aa138UL
97#define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
98	0x2aa174UL
99#define  MISC_REG_GEN_PURP_CR0 \
100	0x008c80UL
101#define  MCP_REG_SCRATCH	\
102	0xe20000UL
103#define  CNIG_REG_NW_PORT_MODE_BB_B0 \
104	0x218200UL
105#define  MISCS_REG_CHIP_NUM \
106	0x00976cUL
107#define  MISCS_REG_CHIP_REV \
108	0x009770UL
109#define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
110	0x00971cUL
111#define  MISCS_REG_CHIP_TEST_REG	\
112	0x009778UL
113#define  MISCS_REG_CHIP_METAL \
114	0x009774UL
115#define  BRB_REG_HEADER_SIZE \
116	0x340804UL
117#define  BTB_REG_HEADER_SIZE \
118	0xdb0804UL
119#define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
120	0x1c0708UL
121#define  CCFC_REG_ACTIVITY_COUNTER \
122	0x2e8800UL
123#define  CDU_REG_CID_ADDR_PARAMS	\
124	0x580900UL
125#define  DBG_REG_CLIENT_ENABLE \
126	0x010004UL
127#define  DMAE_REG_INIT \
128	0x00c000UL
129#define  DORQ_REG_IFEN \
130	0x100040UL
131#define  GRC_REG_TIMEOUT_EN \
132	0x050404UL
133#define  IGU_REG_BLOCK_CONFIGURATION \
134	0x180040UL
135#define  MCM_REG_INIT \
136	0x1200000UL
137#define  MCP2_REG_DBG_DWORD_ENABLE \
138	0x052404UL
139#define  MISC_REG_PORT_MODE \
140	0x008c00UL
141#define MISC_REG_BLOCK_256B_EN \
142	0x008c14UL
143#define MISCS_REG_RESET_PL_HV \
144	0x009060UL
145#define  MISCS_REG_CLK_100G_MODE	\
146	0x009070UL
147#define MISCS_REG_RESET_PL_HV_2 \
148	0x009150UL
149#define  MSDM_REG_ENABLE_IN1 \
150	0xfc0004UL
151#define  MSEM_REG_ENABLE_IN \
152	0x1800004UL
153#define  NIG_REG_CM_HDR \
154	0x500840UL
155#define  NCSI_REG_CONFIG	\
156	0x040200UL
157#define PSWRQ2_REG_RBC_DONE \
158	0x240000UL
159#define PSWRQ2_REG_CFG_DONE \
160	0x240004UL
161#define  PBF_REG_INIT \
162	0xd80000UL
163#define  PTU_REG_ATC_INIT_ARRAY \
164	0x560000UL
165#define  PCM_REG_INIT \
166	0x1100000UL
167#define  PGLUE_B_REG_ADMIN_PER_PF_REGION	\
168	0x2a9000UL
169#define  PRM_REG_DISABLE_PRM \
170	0x230000UL
171#define  PRS_REG_SOFT_RST \
172	0x1f0000UL
173#define  PSDM_REG_ENABLE_IN1 \
174	0xfa0004UL
175#define  PSEM_REG_ENABLE_IN \
176	0x1600004UL
177#define  PSWRQ_REG_DBG_SELECT \
178	0x280020UL
179#define  PSWRQ2_REG_CDUT_P_SIZE \
180	0x24000cUL
181#define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
182	0x2a0040UL
183#define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
184	0x29e050UL
185#define  PSWRD_REG_DBG_SELECT \
186	0x29c040UL
187#define  PSWRD2_REG_CONF11 \
188	0x29d064UL
189#define  PSWWR_REG_USDM_FULL_TH \
190	0x29a040UL
191#define  PSWWR2_REG_CDU_FULL_TH2	\
192	0x29b040UL
193#define  QM_REG_MAXPQSIZE_0 \
194	0x2f0434UL
195#define  RSS_REG_RSS_INIT_EN \
196	0x238804UL
197#define  RDIF_REG_STOP_ON_ERROR \
198	0x300040UL
199#define  SRC_REG_SOFT_RST \
200	0x23874cUL
201#define  TCFC_REG_ACTIVITY_COUNTER \
202	0x2d8800UL
203#define  TCM_REG_INIT \
204	0x1180000UL
205#define  TM_REG_PXP_READ_DATA_FIFO_INIT \
206	0x2c0014UL
207#define  TSDM_REG_ENABLE_IN1 \
208	0xfb0004UL
209#define  TSEM_REG_ENABLE_IN \
210	0x1700004UL
211#define  TDIF_REG_STOP_ON_ERROR \
212	0x310040UL
213#define  UCM_REG_INIT \
214	0x1280000UL
215#define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
216	0x051004UL
217#define  USDM_REG_ENABLE_IN1 \
218	0xfd0004UL
219#define  USEM_REG_ENABLE_IN \
220	0x1900004UL
221#define  XCM_REG_INIT \
222	0x1000000UL
223#define  XSDM_REG_ENABLE_IN1 \
224	0xf80004UL
225#define  XSEM_REG_ENABLE_IN \
226	0x1400004UL
227#define  YCM_REG_INIT \
228	0x1080000UL
229#define  YSDM_REG_ENABLE_IN1 \
230	0xf90004UL
231#define  YSEM_REG_ENABLE_IN \
232	0x1500004UL
233#define  XYLD_REG_SCBD_STRICT_PRIO \
234	0x4c0000UL
235#define  TMLD_REG_SCBD_STRICT_PRIO \
236	0x4d0000UL
237#define  MULD_REG_SCBD_STRICT_PRIO \
238	0x4e0000UL
239#define  YULD_REG_SCBD_STRICT_PRIO \
240	0x4c8000UL
241#define  MISC_REG_SHARED_MEM_ADDR \
242	0x008c20UL
243#define  DMAE_REG_GO_C0 \
244	0x00c048UL
245#define  DMAE_REG_GO_C1 \
246	0x00c04cUL
247#define  DMAE_REG_GO_C2 \
248	0x00c050UL
249#define  DMAE_REG_GO_C3 \
250	0x00c054UL
251#define  DMAE_REG_GO_C4 \
252	0x00c058UL
253#define  DMAE_REG_GO_C5 \
254	0x00c05cUL
255#define  DMAE_REG_GO_C6 \
256	0x00c060UL
257#define  DMAE_REG_GO_C7 \
258	0x00c064UL
259#define  DMAE_REG_GO_C8 \
260	0x00c068UL
261#define  DMAE_REG_GO_C9 \
262	0x00c06cUL
263#define  DMAE_REG_GO_C10	\
264	0x00c070UL
265#define  DMAE_REG_GO_C11	\
266	0x00c074UL
267#define  DMAE_REG_GO_C12	\
268	0x00c078UL
269#define  DMAE_REG_GO_C13	\
270	0x00c07cUL
271#define  DMAE_REG_GO_C14	\
272	0x00c080UL
273#define  DMAE_REG_GO_C15	\
274	0x00c084UL
275#define  DMAE_REG_GO_C16	\
276	0x00c088UL
277#define  DMAE_REG_GO_C17	\
278	0x00c08cUL
279#define  DMAE_REG_GO_C18	\
280	0x00c090UL
281#define  DMAE_REG_GO_C19	\
282	0x00c094UL
283#define  DMAE_REG_GO_C20	\
284	0x00c098UL
285#define  DMAE_REG_GO_C21	\
286	0x00c09cUL
287#define  DMAE_REG_GO_C22	\
288	0x00c0a0UL
289#define  DMAE_REG_GO_C23	\
290	0x00c0a4UL
291#define  DMAE_REG_GO_C24	\
292	0x00c0a8UL
293#define  DMAE_REG_GO_C25	\
294	0x00c0acUL
295#define  DMAE_REG_GO_C26	\
296	0x00c0b0UL
297#define  DMAE_REG_GO_C27	\
298	0x00c0b4UL
299#define  DMAE_REG_GO_C28	\
300	0x00c0b8UL
301#define  DMAE_REG_GO_C29	\
302	0x00c0bcUL
303#define  DMAE_REG_GO_C30	\
304	0x00c0c0UL
305#define  DMAE_REG_GO_C31	\
306	0x00c0c4UL
307#define  DMAE_REG_CMD_MEM \
308	0x00c800UL
309#define  QM_REG_MAXPQSIZETXSEL_0	\
310	0x2f0440UL
311#define  QM_REG_SDMCMDREADY \
312	0x2f1e10UL
313#define  QM_REG_SDMCMDADDR \
314	0x2f1e04UL
315#define  QM_REG_SDMCMDDATALSB \
316	0x2f1e08UL
317#define  QM_REG_SDMCMDDATAMSB \
318	0x2f1e0cUL
319#define  QM_REG_SDMCMDGO	\
320	0x2f1e14UL
321#define  QM_REG_RLPFCRD \
322	0x2f4d80UL
323#define  QM_REG_RLPFINCVAL \
324	0x2f4c80UL
325#define  QM_REG_RLGLBLCRD \
326	0x2f4400UL
327#define  QM_REG_RLGLBLINCVAL \
328	0x2f3400UL
329#define  IGU_REG_ATTENTION_ENABLE \
330	0x18083cUL
331#define  IGU_REG_ATTN_MSG_ADDR_L	\
332	0x180820UL
333#define  IGU_REG_ATTN_MSG_ADDR_H	\
334	0x180824UL
335#define  MISC_REG_AEU_GENERAL_ATTN_0 \
336	0x008400UL
337#define  CAU_REG_SB_ADDR_MEMORY \
338	0x1c8000UL
339#define  CAU_REG_SB_VAR_MEMORY \
340	0x1c6000UL
341#define  CAU_REG_PI_MEMORY \
342	0x1d0000UL
343#define  IGU_REG_PF_CONFIGURATION \
344	0x180800UL
345#define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
346	0x00849cUL
347#define  MISC_REG_AEU_MASK_ATTN_IGU \
348	0x008494UL
349#define  IGU_REG_CLEANUP_STATUS_0 \
350	0x180980UL
351#define  IGU_REG_CLEANUP_STATUS_1 \
352	0x180a00UL
353#define  IGU_REG_CLEANUP_STATUS_2 \
354	0x180a80UL
355#define  IGU_REG_CLEANUP_STATUS_3 \
356	0x180b00UL
357#define  IGU_REG_CLEANUP_STATUS_4 \
358	0x180b80UL
359#define  IGU_REG_COMMAND_REG_32LSB_DATA \
360	0x180840UL
361#define  IGU_REG_COMMAND_REG_CTRL \
362	0x180848UL
363#define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN	( \
364		0x1 << 1)
365#define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN	( \
366		0x1 << 0)
367#define  IGU_REG_MAPPING_MEMORY \
368	0x184000UL
369#define  MISCS_REG_GENERIC_POR_0	\
370	0x0096d4UL
371#define  MCP_REG_NVM_CFG4 \
372	0xe0642cUL
373#define  MCP_REG_NVM_CFG4_FLASH_SIZE	( \
374		0x7 << 0)
375#define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
376	0
377#define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL
378#define CNIG_REG_PMEG_IF_CMD_BB_B0 0x21821cUL
379#define CNIG_REG_PMEG_IF_ADDR_BB_B0 0x218224UL
380#define CNIG_REG_PMEG_IF_WRDATA_BB_B0 0x218228UL
381#define NWM_REG_MAC0 0x800400UL
382#define NWM_REG_MAC0_SIZE 256
383#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
384#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT 0
385#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT 1
386#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT 3
387#define ETH_MAC_REG_XIF_MODE 0x000080UL
388#define ETH_MAC_REG_XIF_MODE_XGMII_SHIFT 0
389#define ETH_MAC_REG_FRM_LENGTH 0x000014UL
390#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT 0
391#define ETH_MAC_REG_TX_IPG_LENGTH 0x000044UL
392#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT 0
393#define ETH_MAC_REG_RX_FIFO_SECTIONS 0x00001cUL
394#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT 0
395#define ETH_MAC_REG_TX_FIFO_SECTIONS 0x000020UL
396#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT 16
397#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT 0
398#define ETH_MAC_REG_COMMAND_CONFIG 0x000008UL
399#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL
400#define MISC_REG_XMAC_CORE_PORT_MODE 0x008c08UL
401#define MISC_REG_XMAC_PHY_PORT_MODE 0x008c04UL
402#define XMAC_REG_MODE 0x210008UL
403#define XMAC_REG_RX_MAX_SIZE 0x210040UL
404#define XMAC_REG_TX_CTRL_LO 0x210020UL
405#define XMAC_REG_CTRL 0x210000UL
406#define XMAC_REG_RX_CTRL 0x210030UL
407#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12)
408#define MISC_REG_CLK_100G_MODE 0x008c10UL
409#define MISC_REG_OPTE_MODE 0x008c0cUL
410#define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL
411#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
412#define PRS_REG_SEARCH_TAG1 0x1f0444UL
413#define PRS_REG_SEARCH_TCP_FIRST_FRAG 0x1f0410UL
414#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL
415#define MISCS_REG_ECO_RESERVED 0x0097b4UL
416#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL
417#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL
418#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
419#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
420#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
421#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
422#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
423#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
424#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
425#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
426#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
427#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
428#define NIG_REG_LLH_FUNC_FILTER_MODE 0x501ac0UL
429#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
430#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
431#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
432#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
433#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
434#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
435#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
436#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
437#define XMAC_REG_CTRL_TX_EN (0x1 << 0)
438#define XMAC_REG_CTRL_RX_EN (0x1 << 1)
439#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xff << 24)
440#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16)
441#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16
442#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16)
443#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xff << 24)
444#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0)
445#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0
446#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0)
447#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0
448#define PSWRQ2_REG_ILT_MEMORY 0x260000UL
449#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
450#define QM_REG_WFQVPWEIGHT 0x2fa000UL
451#define NIG_REG_LB_ARB_CREDIT_WEIGHT_0 0x50160cUL
452#define NIG_REG_TX_ARB_CREDIT_WEIGHT_0 0x501f88UL
453#define NIG_REG_LB_ARB_CREDIT_WEIGHT_1 0x501610UL
454#define NIG_REG_TX_ARB_CREDIT_WEIGHT_1 0x501f8cUL
455#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 0x5015e4UL
456#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL
457#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 0x5015e8UL
458#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 0x501f5cUL
459#define NIG_REG_LB_ARB_CLIENT_IS_STRICT 0x5015c0UL
460#define NIG_REG_TX_ARB_CLIENT_IS_STRICT 0x501f34UL
461#define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ 0x5015c4UL
462#define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x501f38UL
463#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT 1
464#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL
465#define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD 0x501f20UL
466#define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE 0x501f24UL
467#define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE 0x501f28UL
468#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT 0
469#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT 1
470#define NIG_REG_LB_BRBRATELIMIT_CTRL 0x50150cUL
471#define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD 0x501510UL
472#define NIG_REG_LB_BRBRATELIMIT_INC_VALUE 0x501514UL
473#define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE 0x501518UL
474#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT 0
475#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT 1
476#define NIG_REG_LB_TCRATELIMIT_CTRL_0 0x501520UL
477#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL
478#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 0x501560UL
479#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 0x501580UL
480#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT 0
481#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL
482#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL
483#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 0x1f0540UL
484#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 0x1f0534UL
485#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 0x1f053cUL
486#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 0x1f0530UL
487#define PRS_REG_ETS_ARB_CLIENT_IS_STRICT 0x1f0514UL
488#define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ 0x1f0518UL
489#define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL
490#define BRB_REG_SHARED_HR_AREA 0x340880UL
491#define BRB_REG_TC_GUARANTIED_0 0x340900UL
492#define BRB_REG_MAIN_TC_GUARANTIED_HYST_0 0x340978UL
493#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 0x340c60UL
494#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL
495#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 0x340ab0UL
496#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 0x340b88UL
497#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 0x340c00UL
498#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 0x340cd8UL
499#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 0x340a50UL
500#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 0x340b28UL
501#define PRS_REG_VXLAN_PORT 0x1f0738UL
502#define NIG_REG_VXLAN_PORT 0x50105cUL
503#define PBF_REG_VXLAN_PORT 0xd80518UL
504#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
505#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
506#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
507#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
508#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
509#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
510#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
511#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
512#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
513#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
514#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
515#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
516#define PRS_REG_NGE_PORT 0x1f086cUL
517#define NIG_REG_NGE_PORT 0x508b38UL
518#define PBF_REG_NGE_PORT 0xd8051cUL
519#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
520#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
521#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
522#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
523#define NIG_REG_NGE_COMP_VER 0x508b30UL
524#define PBF_REG_NGE_COMP_VER 0xd80524UL
525#define PRS_REG_NGE_COMP_VER 0x1f0878UL
526#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
527#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
528#define NIG_REG_PKT_PRIORITY_TO_TC 0x501ba4UL
529#define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL
530#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL
531#define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL
532#define MCP_REG_CPU_STATE 0xe05004UL
533#define MCP_REG_CPU_MODE 0xe05000UL
534#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10)
535#define MCP_REG_CPU_EVENT_MASK 0xe05008UL
536#define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL
537#define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL
538#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL
539#define PSWHST_REG_INCORRECT_ACCESS_VALID 0x2a0070UL
540#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS 0x2a0074UL
541#define PSWHST_REG_INCORRECT_ACCESS_DATA 0x2a0068UL
542#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL
543#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL
544#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL
545#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 0x050050UL
546#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x2aa150UL
547#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x2aa144UL
548#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x2aa148UL
549#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x2aa14cUL
550#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x2aa160UL
551#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x2aa154UL
552#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x2aa158UL
553#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x2aa15cUL
554#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL 0x2aa164UL
555#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL
556#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 0x2aa544UL
557#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 0x2aa548UL
558#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 0x2aae80UL
559#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 0x2aae74UL
560#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL
561#define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL
562#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL
563#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10)
564#define DORQ_REG_DB_DROP_REASON 0x100a2cUL
565#define DORQ_REG_DB_DROP_DETAILS 0x100a24UL
566#define TM_REG_INT_STS_1 0x2c0190UL
567#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6)
568#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5)
569#define TM_REG_INT_MASK_1 0x2c0194UL
570#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5)
571#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6)
572#define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL
573#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL
574#define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL
575#define YSEM_REG_FAST_MEMORY 0x1540000UL
576#define NIG_REG_FLOWCTRL_MODE 0x501ba0UL
577#define TSEM_REG_FAST_MEMORY 0x1740000UL
578#define TSEM_REG_DBG_FRAME_MODE 0x1701408UL
579#define TSEM_REG_SLOW_DBG_ACTIVE 0x1701400UL
580#define TSEM_REG_SLOW_DBG_MODE 0x1701404UL
581#define TSEM_REG_DBG_MODE1_CFG 0x1701420UL
582#define TSEM_REG_SYNC_DBG_EMPTY 0x1701160UL
583#define TSEM_REG_SLOW_DBG_EMPTY 0x1701140UL
584#define TCM_REG_CTX_RBC_ACCS 0x11814c0UL
585#define TCM_REG_AGG_CON_CTX 0x11814c4UL
586#define TCM_REG_SM_CON_CTX 0x11814ccUL
587#define TCM_REG_AGG_TASK_CTX 0x11814c8UL
588#define TCM_REG_SM_TASK_CTX 0x11814d0UL
589#define MSEM_REG_FAST_MEMORY 0x1840000UL
590#define MSEM_REG_DBG_FRAME_MODE 0x1801408UL
591#define MSEM_REG_SLOW_DBG_ACTIVE 0x1801400UL
592#define MSEM_REG_SLOW_DBG_MODE 0x1801404UL
593#define MSEM_REG_DBG_MODE1_CFG 0x1801420UL
594#define MSEM_REG_SYNC_DBG_EMPTY 0x1801160UL
595#define MSEM_REG_SLOW_DBG_EMPTY 0x1801140UL
596#define MCM_REG_CTX_RBC_ACCS 0x1201800UL
597#define MCM_REG_AGG_CON_CTX 0x1201804UL
598#define MCM_REG_SM_CON_CTX 0x120180cUL
599#define MCM_REG_AGG_TASK_CTX 0x1201808UL
600#define MCM_REG_SM_TASK_CTX 0x1201810UL
601#define USEM_REG_FAST_MEMORY 0x1940000UL
602#define USEM_REG_DBG_FRAME_MODE 0x1901408UL
603#define USEM_REG_SLOW_DBG_ACTIVE 0x1901400UL
604#define USEM_REG_SLOW_DBG_MODE 0x1901404UL
605#define USEM_REG_DBG_MODE1_CFG 0x1901420UL
606#define USEM_REG_SYNC_DBG_EMPTY 0x1901160UL
607#define USEM_REG_SLOW_DBG_EMPTY 0x1901140UL
608#define UCM_REG_CTX_RBC_ACCS 0x1281700UL
609#define UCM_REG_AGG_CON_CTX 0x1281704UL
610#define UCM_REG_SM_CON_CTX 0x128170cUL
611#define UCM_REG_AGG_TASK_CTX 0x1281708UL
612#define UCM_REG_SM_TASK_CTX 0x1281710UL
613#define XSEM_REG_FAST_MEMORY 0x1440000UL
614#define XSEM_REG_DBG_FRAME_MODE 0x1401408UL
615#define XSEM_REG_SLOW_DBG_ACTIVE 0x1401400UL
616#define XSEM_REG_SLOW_DBG_MODE 0x1401404UL
617#define XSEM_REG_DBG_MODE1_CFG 0x1401420UL
618#define XSEM_REG_SYNC_DBG_EMPTY 0x1401160UL
619#define XSEM_REG_SLOW_DBG_EMPTY 0x1401140UL
620#define XCM_REG_CTX_RBC_ACCS 0x1001800UL
621#define XCM_REG_AGG_CON_CTX 0x1001804UL
622#define XCM_REG_SM_CON_CTX 0x1001808UL
623#define YSEM_REG_DBG_FRAME_MODE 0x1501408UL
624#define YSEM_REG_SLOW_DBG_ACTIVE 0x1501400UL
625#define YSEM_REG_SLOW_DBG_MODE 0x1501404UL
626#define YSEM_REG_DBG_MODE1_CFG 0x1501420UL
627#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL
628#define YCM_REG_CTX_RBC_ACCS 0x1081800UL
629#define YCM_REG_AGG_CON_CTX 0x1081804UL
630#define YCM_REG_SM_CON_CTX 0x108180cUL
631#define YCM_REG_AGG_TASK_CTX 0x1081808UL
632#define YCM_REG_SM_TASK_CTX 0x1081810UL
633#define PSEM_REG_FAST_MEMORY 0x1640000UL
634#define PSEM_REG_DBG_FRAME_MODE 0x1601408UL
635#define PSEM_REG_SLOW_DBG_ACTIVE 0x1601400UL
636#define PSEM_REG_SLOW_DBG_MODE 0x1601404UL
637#define PSEM_REG_DBG_MODE1_CFG 0x1601420UL
638#define PSEM_REG_SYNC_DBG_EMPTY 0x1601160UL
639#define PSEM_REG_SLOW_DBG_EMPTY 0x1601140UL
640#define PCM_REG_CTX_RBC_ACCS 0x1101440UL
641#define PCM_REG_SM_CON_CTX 0x1101444UL
642#define GRC_REG_DBG_SELECT 0x0500a4UL
643#define GRC_REG_DBG_DWORD_ENABLE 0x0500a8UL
644#define GRC_REG_DBG_SHIFT 0x0500acUL
645#define GRC_REG_DBG_FORCE_VALID 0x0500b0UL
646#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL
647#define PGLUE_B_REG_DBG_SELECT 0x2a8400UL
648#define PGLUE_B_REG_DBG_DWORD_ENABLE 0x2a8404UL
649#define PGLUE_B_REG_DBG_SHIFT 0x2a8408UL
650#define PGLUE_B_REG_DBG_FORCE_VALID 0x2a840cUL
651#define PGLUE_B_REG_DBG_FORCE_FRAME 0x2a8410UL
652#define CNIG_REG_DBG_SELECT_K2 0x218254UL
653#define CNIG_REG_DBG_DWORD_ENABLE_K2 0x218258UL
654#define CNIG_REG_DBG_SHIFT_K2 0x21825cUL
655#define CNIG_REG_DBG_FORCE_VALID_K2 0x218260UL
656#define CNIG_REG_DBG_FORCE_FRAME_K2 0x218264UL
657#define NCSI_REG_DBG_SELECT 0x040474UL
658#define NCSI_REG_DBG_DWORD_ENABLE 0x040478UL
659#define NCSI_REG_DBG_SHIFT 0x04047cUL
660#define NCSI_REG_DBG_FORCE_VALID 0x040480UL
661#define NCSI_REG_DBG_FORCE_FRAME 0x040484UL
662#define BMB_REG_DBG_SELECT 0x540a7cUL
663#define BMB_REG_DBG_DWORD_ENABLE 0x540a80UL
664#define BMB_REG_DBG_SHIFT 0x540a84UL
665#define BMB_REG_DBG_FORCE_VALID 0x540a88UL
666#define BMB_REG_DBG_FORCE_FRAME 0x540a8cUL
667#define PCIE_REG_DBG_SELECT 0x0547e8UL
668#define PHY_PCIE_REG_DBG_SELECT 0x629fe8UL
669#define PCIE_REG_DBG_DWORD_ENABLE 0x0547ecUL
670#define PHY_PCIE_REG_DBG_DWORD_ENABLE 0x629fecUL
671#define PCIE_REG_DBG_SHIFT 0x0547f0UL
672#define PHY_PCIE_REG_DBG_SHIFT 0x629ff0UL
673#define PCIE_REG_DBG_FORCE_VALID 0x0547f4UL
674#define PHY_PCIE_REG_DBG_FORCE_VALID 0x629ff4UL
675#define PCIE_REG_DBG_FORCE_FRAME 0x0547f8UL
676#define PHY_PCIE_REG_DBG_FORCE_FRAME 0x629ff8UL
677#define MCP2_REG_DBG_SELECT 0x052400UL
678#define MCP2_REG_DBG_SHIFT 0x052408UL
679#define MCP2_REG_DBG_FORCE_VALID 0x052440UL
680#define MCP2_REG_DBG_FORCE_FRAME 0x052444UL
681#define PSWHST_REG_DBG_SELECT 0x2a0100UL
682#define PSWHST_REG_DBG_DWORD_ENABLE 0x2a0104UL
683#define PSWHST_REG_DBG_SHIFT 0x2a0108UL
684#define PSWHST_REG_DBG_FORCE_VALID 0x2a010cUL
685#define PSWHST_REG_DBG_FORCE_FRAME 0x2a0110UL
686#define PSWHST2_REG_DBG_SELECT 0x29e058UL
687#define PSWHST2_REG_DBG_DWORD_ENABLE 0x29e05cUL
688#define PSWHST2_REG_DBG_SHIFT 0x29e060UL
689#define PSWHST2_REG_DBG_FORCE_VALID 0x29e064UL
690#define PSWHST2_REG_DBG_FORCE_FRAME 0x29e068UL
691#define PSWRD_REG_DBG_DWORD_ENABLE 0x29c044UL
692#define PSWRD_REG_DBG_SHIFT 0x29c048UL
693#define PSWRD_REG_DBG_FORCE_VALID 0x29c04cUL
694#define PSWRD_REG_DBG_FORCE_FRAME 0x29c050UL
695#define PSWRD2_REG_DBG_SELECT 0x29d400UL
696#define PSWRD2_REG_DBG_DWORD_ENABLE 0x29d404UL
697#define PSWRD2_REG_DBG_SHIFT 0x29d408UL
698#define PSWRD2_REG_DBG_FORCE_VALID 0x29d40cUL
699#define PSWRD2_REG_DBG_FORCE_FRAME 0x29d410UL
700#define PSWWR_REG_DBG_SELECT 0x29a084UL
701#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL
702#define PSWWR_REG_DBG_SHIFT 0x29a08cUL
703#define PSWWR_REG_DBG_FORCE_VALID 0x29a090UL
704#define PSWWR_REG_DBG_FORCE_FRAME 0x29a094UL
705#define PSWRQ_REG_DBG_DWORD_ENABLE 0x280024UL
706#define PSWRQ_REG_DBG_SHIFT 0x280028UL
707#define PSWRQ_REG_DBG_FORCE_VALID 0x28002cUL
708#define PSWRQ_REG_DBG_FORCE_FRAME 0x280030UL
709#define PSWRQ2_REG_DBG_SELECT 0x240100UL
710#define PSWRQ2_REG_DBG_DWORD_ENABLE 0x240104UL
711#define PSWRQ2_REG_DBG_SHIFT 0x240108UL
712#define PSWRQ2_REG_DBG_FORCE_VALID 0x24010cUL
713#define PSWRQ2_REG_DBG_FORCE_FRAME 0x240110UL
714#define PGLCS_REG_DBG_SELECT 0x001d14UL
715#define PGLCS_REG_DBG_DWORD_ENABLE 0x001d18UL
716#define PGLCS_REG_DBG_SHIFT 0x001d1cUL
717#define PGLCS_REG_DBG_FORCE_VALID 0x001d20UL
718#define PGLCS_REG_DBG_FORCE_FRAME 0x001d24UL
719#define PTU_REG_DBG_SELECT 0x560100UL
720#define PTU_REG_DBG_DWORD_ENABLE 0x560104UL
721#define PTU_REG_DBG_SHIFT 0x560108UL
722#define PTU_REG_DBG_FORCE_VALID 0x56010cUL
723#define PTU_REG_DBG_FORCE_FRAME 0x560110UL
724#define DMAE_REG_DBG_SELECT 0x00c510UL
725#define DMAE_REG_DBG_DWORD_ENABLE 0x00c514UL
726#define DMAE_REG_DBG_SHIFT 0x00c518UL
727#define DMAE_REG_DBG_FORCE_VALID 0x00c51cUL
728#define DMAE_REG_DBG_FORCE_FRAME 0x00c520UL
729#define TCM_REG_DBG_SELECT 0x1180040UL
730#define TCM_REG_DBG_DWORD_ENABLE 0x1180044UL
731#define TCM_REG_DBG_SHIFT 0x1180048UL
732#define TCM_REG_DBG_FORCE_VALID 0x118004cUL
733#define TCM_REG_DBG_FORCE_FRAME 0x1180050UL
734#define MCM_REG_DBG_SELECT 0x1200040UL
735#define MCM_REG_DBG_DWORD_ENABLE 0x1200044UL
736#define MCM_REG_DBG_SHIFT 0x1200048UL
737#define MCM_REG_DBG_FORCE_VALID 0x120004cUL
738#define MCM_REG_DBG_FORCE_FRAME 0x1200050UL
739#define UCM_REG_DBG_SELECT 0x1280050UL
740#define UCM_REG_DBG_DWORD_ENABLE 0x1280054UL
741#define UCM_REG_DBG_SHIFT 0x1280058UL
742#define UCM_REG_DBG_FORCE_VALID 0x128005cUL
743#define UCM_REG_DBG_FORCE_FRAME 0x1280060UL
744#define XCM_REG_DBG_SELECT 0x1000040UL
745#define XCM_REG_DBG_DWORD_ENABLE 0x1000044UL
746#define XCM_REG_DBG_SHIFT 0x1000048UL
747#define XCM_REG_DBG_FORCE_VALID 0x100004cUL
748#define XCM_REG_DBG_FORCE_FRAME 0x1000050UL
749#define YCM_REG_DBG_SELECT 0x1080040UL
750#define YCM_REG_DBG_DWORD_ENABLE 0x1080044UL
751#define YCM_REG_DBG_SHIFT 0x1080048UL
752#define YCM_REG_DBG_FORCE_VALID 0x108004cUL
753#define YCM_REG_DBG_FORCE_FRAME 0x1080050UL
754#define PCM_REG_DBG_SELECT 0x1100040UL
755#define PCM_REG_DBG_DWORD_ENABLE 0x1100044UL
756#define PCM_REG_DBG_SHIFT 0x1100048UL
757#define PCM_REG_DBG_FORCE_VALID 0x110004cUL
758#define PCM_REG_DBG_FORCE_FRAME 0x1100050UL
759#define QM_REG_DBG_SELECT 0x2f2e74UL
760#define QM_REG_DBG_DWORD_ENABLE 0x2f2e78UL
761#define QM_REG_DBG_SHIFT 0x2f2e7cUL
762#define QM_REG_DBG_FORCE_VALID 0x2f2e80UL
763#define QM_REG_DBG_FORCE_FRAME 0x2f2e84UL
764#define TM_REG_DBG_SELECT 0x2c07a8UL
765#define TM_REG_DBG_DWORD_ENABLE 0x2c07acUL
766#define TM_REG_DBG_SHIFT 0x2c07b0UL
767#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL
768#define TM_REG_DBG_FORCE_FRAME 0x2c07b8UL
769#define DORQ_REG_DBG_SELECT 0x100ad0UL
770#define DORQ_REG_DBG_DWORD_ENABLE 0x100ad4UL
771#define DORQ_REG_DBG_SHIFT 0x100ad8UL
772#define DORQ_REG_DBG_FORCE_VALID 0x100adcUL
773#define DORQ_REG_DBG_FORCE_FRAME 0x100ae0UL
774#define BRB_REG_DBG_SELECT 0x340ed0UL
775#define BRB_REG_DBG_DWORD_ENABLE 0x340ed4UL
776#define BRB_REG_DBG_SHIFT 0x340ed8UL
777#define BRB_REG_DBG_FORCE_VALID 0x340edcUL
778#define BRB_REG_DBG_FORCE_FRAME 0x340ee0UL
779#define SRC_REG_DBG_SELECT 0x238700UL
780#define SRC_REG_DBG_DWORD_ENABLE 0x238704UL
781#define SRC_REG_DBG_SHIFT 0x238708UL
782#define SRC_REG_DBG_FORCE_VALID 0x23870cUL
783#define SRC_REG_DBG_FORCE_FRAME 0x238710UL
784#define PRS_REG_DBG_SELECT 0x1f0b6cUL
785#define PRS_REG_DBG_DWORD_ENABLE 0x1f0b70UL
786#define PRS_REG_DBG_SHIFT 0x1f0b74UL
787#define PRS_REG_DBG_FORCE_VALID 0x1f0ba0UL
788#define PRS_REG_DBG_FORCE_FRAME 0x1f0ba4UL
789#define TSDM_REG_DBG_SELECT 0xfb0e28UL
790#define TSDM_REG_DBG_DWORD_ENABLE 0xfb0e2cUL
791#define TSDM_REG_DBG_SHIFT 0xfb0e30UL
792#define TSDM_REG_DBG_FORCE_VALID 0xfb0e34UL
793#define TSDM_REG_DBG_FORCE_FRAME 0xfb0e38UL
794#define MSDM_REG_DBG_SELECT 0xfc0e28UL
795#define MSDM_REG_DBG_DWORD_ENABLE 0xfc0e2cUL
796#define MSDM_REG_DBG_SHIFT 0xfc0e30UL
797#define MSDM_REG_DBG_FORCE_VALID 0xfc0e34UL
798#define MSDM_REG_DBG_FORCE_FRAME 0xfc0e38UL
799#define USDM_REG_DBG_SELECT 0xfd0e28UL
800#define USDM_REG_DBG_DWORD_ENABLE 0xfd0e2cUL
801#define USDM_REG_DBG_SHIFT 0xfd0e30UL
802#define USDM_REG_DBG_FORCE_VALID 0xfd0e34UL
803#define USDM_REG_DBG_FORCE_FRAME 0xfd0e38UL
804#define XSDM_REG_DBG_SELECT 0xf80e28UL
805#define XSDM_REG_DBG_DWORD_ENABLE 0xf80e2cUL
806#define XSDM_REG_DBG_SHIFT 0xf80e30UL
807#define XSDM_REG_DBG_FORCE_VALID 0xf80e34UL
808#define XSDM_REG_DBG_FORCE_FRAME 0xf80e38UL
809#define YSDM_REG_DBG_SELECT 0xf90e28UL
810#define YSDM_REG_DBG_DWORD_ENABLE 0xf90e2cUL
811#define YSDM_REG_DBG_SHIFT 0xf90e30UL
812#define YSDM_REG_DBG_FORCE_VALID 0xf90e34UL
813#define YSDM_REG_DBG_FORCE_FRAME 0xf90e38UL
814#define PSDM_REG_DBG_SELECT 0xfa0e28UL
815#define PSDM_REG_DBG_DWORD_ENABLE 0xfa0e2cUL
816#define PSDM_REG_DBG_SHIFT 0xfa0e30UL
817#define PSDM_REG_DBG_FORCE_VALID 0xfa0e34UL
818#define PSDM_REG_DBG_FORCE_FRAME 0xfa0e38UL
819#define TSEM_REG_DBG_SELECT 0x1701528UL
820#define TSEM_REG_DBG_DWORD_ENABLE 0x170152cUL
821#define TSEM_REG_DBG_SHIFT 0x1701530UL
822#define TSEM_REG_DBG_FORCE_VALID 0x1701534UL
823#define TSEM_REG_DBG_FORCE_FRAME 0x1701538UL
824#define MSEM_REG_DBG_SELECT 0x1801528UL
825#define MSEM_REG_DBG_DWORD_ENABLE 0x180152cUL
826#define MSEM_REG_DBG_SHIFT 0x1801530UL
827#define MSEM_REG_DBG_FORCE_VALID 0x1801534UL
828#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL
829#define USEM_REG_DBG_SELECT 0x1901528UL
830#define USEM_REG_DBG_DWORD_ENABLE 0x190152cUL
831#define USEM_REG_DBG_SHIFT 0x1901530UL
832#define USEM_REG_DBG_FORCE_VALID 0x1901534UL
833#define USEM_REG_DBG_FORCE_FRAME 0x1901538UL
834#define XSEM_REG_DBG_SELECT 0x1401528UL
835#define XSEM_REG_DBG_DWORD_ENABLE 0x140152cUL
836#define XSEM_REG_DBG_SHIFT 0x1401530UL
837#define XSEM_REG_DBG_FORCE_VALID 0x1401534UL
838#define XSEM_REG_DBG_FORCE_FRAME 0x1401538UL
839#define YSEM_REG_DBG_SELECT 0x1501528UL
840#define YSEM_REG_DBG_DWORD_ENABLE 0x150152cUL
841#define YSEM_REG_DBG_SHIFT 0x1501530UL
842#define YSEM_REG_DBG_FORCE_VALID 0x1501534UL
843#define YSEM_REG_DBG_FORCE_FRAME 0x1501538UL
844#define PSEM_REG_DBG_SELECT 0x1601528UL
845#define PSEM_REG_DBG_DWORD_ENABLE 0x160152cUL
846#define PSEM_REG_DBG_SHIFT 0x1601530UL
847#define PSEM_REG_DBG_FORCE_VALID 0x1601534UL
848#define PSEM_REG_DBG_FORCE_FRAME 0x1601538UL
849#define RSS_REG_DBG_SELECT 0x238c4cUL
850#define RSS_REG_DBG_DWORD_ENABLE 0x238c50UL
851#define RSS_REG_DBG_SHIFT 0x238c54UL
852#define RSS_REG_DBG_FORCE_VALID 0x238c58UL
853#define RSS_REG_DBG_FORCE_FRAME 0x238c5cUL
854#define TMLD_REG_DBG_SELECT 0x4d1600UL
855#define TMLD_REG_DBG_DWORD_ENABLE 0x4d1604UL
856#define TMLD_REG_DBG_SHIFT 0x4d1608UL
857#define TMLD_REG_DBG_FORCE_VALID 0x4d160cUL
858#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL
859#define MULD_REG_DBG_SELECT 0x4e1600UL
860#define MULD_REG_DBG_DWORD_ENABLE 0x4e1604UL
861#define MULD_REG_DBG_SHIFT 0x4e1608UL
862#define MULD_REG_DBG_FORCE_VALID 0x4e160cUL
863#define MULD_REG_DBG_FORCE_FRAME 0x4e1610UL
864#define YULD_REG_DBG_SELECT 0x4c9600UL
865#define YULD_REG_DBG_DWORD_ENABLE 0x4c9604UL
866#define YULD_REG_DBG_SHIFT 0x4c9608UL
867#define YULD_REG_DBG_FORCE_VALID 0x4c960cUL
868#define YULD_REG_DBG_FORCE_FRAME 0x4c9610UL
869#define XYLD_REG_DBG_SELECT 0x4c1600UL
870#define XYLD_REG_DBG_DWORD_ENABLE 0x4c1604UL
871#define XYLD_REG_DBG_SHIFT 0x4c1608UL
872#define XYLD_REG_DBG_FORCE_VALID 0x4c160cUL
873#define XYLD_REG_DBG_FORCE_FRAME 0x4c1610UL
874#define PRM_REG_DBG_SELECT 0x2306a8UL
875#define PRM_REG_DBG_DWORD_ENABLE 0x2306acUL
876#define PRM_REG_DBG_SHIFT 0x2306b0UL
877#define PRM_REG_DBG_FORCE_VALID 0x2306b4UL
878#define PRM_REG_DBG_FORCE_FRAME 0x2306b8UL
879#define PBF_PB1_REG_DBG_SELECT 0xda0728UL
880#define PBF_PB1_REG_DBG_DWORD_ENABLE 0xda072cUL
881#define PBF_PB1_REG_DBG_SHIFT 0xda0730UL
882#define PBF_PB1_REG_DBG_FORCE_VALID 0xda0734UL
883#define PBF_PB1_REG_DBG_FORCE_FRAME 0xda0738UL
884#define PBF_PB2_REG_DBG_SELECT 0xda4728UL
885#define PBF_PB2_REG_DBG_DWORD_ENABLE 0xda472cUL
886#define PBF_PB2_REG_DBG_SHIFT 0xda4730UL
887#define PBF_PB2_REG_DBG_FORCE_VALID 0xda4734UL
888#define PBF_PB2_REG_DBG_FORCE_FRAME 0xda4738UL
889#define RPB_REG_DBG_SELECT 0x23c728UL
890#define RPB_REG_DBG_DWORD_ENABLE 0x23c72cUL
891#define RPB_REG_DBG_SHIFT 0x23c730UL
892#define RPB_REG_DBG_FORCE_VALID 0x23c734UL
893#define RPB_REG_DBG_FORCE_FRAME 0x23c738UL
894#define BTB_REG_DBG_SELECT 0xdb08c8UL
895#define BTB_REG_DBG_DWORD_ENABLE 0xdb08ccUL
896#define BTB_REG_DBG_SHIFT 0xdb08d0UL
897#define BTB_REG_DBG_FORCE_VALID 0xdb08d4UL
898#define BTB_REG_DBG_FORCE_FRAME 0xdb08d8UL
899#define PBF_REG_DBG_SELECT 0xd80060UL
900#define PBF_REG_DBG_DWORD_ENABLE 0xd80064UL
901#define PBF_REG_DBG_SHIFT 0xd80068UL
902#define PBF_REG_DBG_FORCE_VALID 0xd8006cUL
903#define PBF_REG_DBG_FORCE_FRAME 0xd80070UL
904#define RDIF_REG_DBG_SELECT 0x300500UL
905#define RDIF_REG_DBG_DWORD_ENABLE 0x300504UL
906#define RDIF_REG_DBG_SHIFT 0x300508UL
907#define RDIF_REG_DBG_FORCE_VALID 0x30050cUL
908#define RDIF_REG_DBG_FORCE_FRAME 0x300510UL
909#define TDIF_REG_DBG_SELECT 0x310500UL
910#define TDIF_REG_DBG_DWORD_ENABLE 0x310504UL
911#define TDIF_REG_DBG_SHIFT 0x310508UL
912#define TDIF_REG_DBG_FORCE_VALID 0x31050cUL
913#define TDIF_REG_DBG_FORCE_FRAME 0x310510UL
914#define CDU_REG_DBG_SELECT 0x580704UL
915#define CDU_REG_DBG_DWORD_ENABLE 0x580708UL
916#define CDU_REG_DBG_SHIFT 0x58070cUL
917#define CDU_REG_DBG_FORCE_VALID 0x580710UL
918#define CDU_REG_DBG_FORCE_FRAME 0x580714UL
919#define CCFC_REG_DBG_SELECT 0x2e0500UL
920#define CCFC_REG_DBG_DWORD_ENABLE 0x2e0504UL
921#define CCFC_REG_DBG_SHIFT 0x2e0508UL
922#define CCFC_REG_DBG_FORCE_VALID 0x2e050cUL
923#define CCFC_REG_DBG_FORCE_FRAME 0x2e0510UL
924#define TCFC_REG_DBG_SELECT 0x2d0500UL
925#define TCFC_REG_DBG_DWORD_ENABLE 0x2d0504UL
926#define TCFC_REG_DBG_SHIFT 0x2d0508UL
927#define TCFC_REG_DBG_FORCE_VALID 0x2d050cUL
928#define TCFC_REG_DBG_FORCE_FRAME 0x2d0510UL
929#define IGU_REG_DBG_SELECT 0x181578UL
930#define IGU_REG_DBG_DWORD_ENABLE 0x18157cUL
931#define IGU_REG_DBG_SHIFT 0x181580UL
932#define IGU_REG_DBG_FORCE_VALID 0x181584UL
933#define IGU_REG_DBG_FORCE_FRAME 0x181588UL
934#define CAU_REG_DBG_SELECT 0x1c0ea8UL
935#define CAU_REG_DBG_DWORD_ENABLE 0x1c0eacUL
936#define CAU_REG_DBG_SHIFT 0x1c0eb0UL
937#define CAU_REG_DBG_FORCE_VALID 0x1c0eb4UL
938#define CAU_REG_DBG_FORCE_FRAME 0x1c0eb8UL
939#define UMAC_REG_DBG_SELECT 0x051094UL
940#define UMAC_REG_DBG_DWORD_ENABLE 0x051098UL
941#define UMAC_REG_DBG_SHIFT 0x05109cUL
942#define UMAC_REG_DBG_FORCE_VALID 0x0510a0UL
943#define UMAC_REG_DBG_FORCE_FRAME 0x0510a4UL
944#define NIG_REG_DBG_SELECT 0x502140UL
945#define NIG_REG_DBG_DWORD_ENABLE 0x502144UL
946#define NIG_REG_DBG_SHIFT 0x502148UL
947#define NIG_REG_DBG_FORCE_VALID 0x50214cUL
948#define NIG_REG_DBG_FORCE_FRAME 0x502150UL
949#define WOL_REG_DBG_SELECT 0x600140UL
950#define WOL_REG_DBG_DWORD_ENABLE 0x600144UL
951#define WOL_REG_DBG_SHIFT 0x600148UL
952#define WOL_REG_DBG_FORCE_VALID 0x60014cUL
953#define WOL_REG_DBG_FORCE_FRAME 0x600150UL
954#define BMBN_REG_DBG_SELECT 0x610140UL
955#define BMBN_REG_DBG_DWORD_ENABLE 0x610144UL
956#define BMBN_REG_DBG_SHIFT 0x610148UL
957#define BMBN_REG_DBG_FORCE_VALID 0x61014cUL
958#define BMBN_REG_DBG_FORCE_FRAME 0x610150UL
959#define NWM_REG_DBG_SELECT 0x8000ecUL
960#define NWM_REG_DBG_DWORD_ENABLE 0x8000f0UL
961#define NWM_REG_DBG_SHIFT 0x8000f4UL
962#define NWM_REG_DBG_FORCE_VALID 0x8000f8UL
963#define NWM_REG_DBG_FORCE_FRAME 0x8000fcUL
964#define BRB_REG_BIG_RAM_ADDRESS 0x340800UL
965#define BRB_REG_BIG_RAM_DATA 0x341500UL
966#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL
967#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL
968#define BMB_REG_BIG_RAM_ADDRESS 0x540800UL
969#define BMB_REG_BIG_RAM_DATA 0x540f00UL
970#define MISCS_REG_RESET_PL_UA 0x009050UL
971#define MISC_REG_RESET_PL_UA 0x008050UL
972#define MISC_REG_RESET_PL_HV 0x008060UL
973#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL
974#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL
975#define SEM_FAST_REG_INT_RAM 0x020000UL
976#define DBG_REG_DBG_BLOCK_ON 0x010454UL
977#define DBG_REG_FRAMING_MODE 0x010058UL
978#define SEM_FAST_REG_DEBUG_MODE 0x000744UL
979#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
980#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
981#define SEM_FAST_REG_FILTER_CID 0x000754UL
982#define SEM_FAST_REG_EVENT_ID_RANGE_STRT 0x000760UL
983#define SEM_FAST_REG_EVENT_ID_RANGE_END 0x000764UL
984#define SEM_FAST_REG_FILTER_EVENT_ID 0x000758UL
985#define SEM_FAST_REG_EVENT_ID_MASK 0x00075cUL
986#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
987#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
988#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
989#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
990#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
991#define DBG_REG_FILTER_ENABLE 0x0109d0UL
992#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
993#define DBG_REG_FILTER_CNSTR_OPRTN_0 0x010a28UL
994#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0 0x01071cUL
995#define DBG_REG_FILTER_CNSTR_DATA_0 0x0109d8UL
996#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0 0x01059cUL
997#define DBG_REG_FILTER_CNSTR_DATA_MASK_0 0x0109f8UL
998#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0 0x01065cUL
999#define DBG_REG_FILTER_CNSTR_FRAME_0 0x0109e8UL
1000#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0x0105fcUL
1001#define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0x010a08UL
1002#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL
1003#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL
1004#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL
1005#define DBG_REG_FILTER_CNSTR_RANGE_0 0x010a38UL
1006#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL
1007#define DBG_REG_FILTER_CNSTR_CYCLIC_0 0x010a68UL
1008#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0x0108fcUL
1009#define DBG_REG_FILTER_CNSTR_MUST_0 0x010a48UL
1010#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0x01083cUL
1011#define DBG_REG_INTR_BUFFER 0x014000UL
1012#define DBG_REG_INTR_BUFFER_WR_PTR 0x010404UL
1013#define DBG_REG_WRAP_ON_INT_BUFFER 0x010418UL
1014#define DBG_REG_INTR_BUFFER_RD_PTR 0x010400UL
1015#define DBG_REG_EXT_BUFFER_WR_PTR 0x010410UL
1016#define DBG_REG_WRAP_ON_EXT_BUFFER 0x01041cUL
1017#define SEM_FAST_REG_STALL_0 0x000488UL
1018#define SEM_FAST_REG_STALLED 0x000494UL
1019#define SEM_FAST_REG_STORM_REG_FILE 0x008000UL
1020#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
1021#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
1022#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
1023#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
1024#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
1025#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
1026#define RSS_REG_RSS_RAM_ADDR 0x238c30UL
1027#define RSS_REG_RSS_RAM_DATA 0x238c20UL
1028#define MISCS_REG_BLOCK_256B_EN 0x009074UL
1029#define MCP_REG_CPU_REG_FILE 0xe05200UL
1030#define MCP_REG_CPU_REG_FILE_SIZE 32
1031#define DBG_REG_CALENDAR_OUT_DATA 0x010480UL
1032#define DBG_REG_FULL_MODE 0x010060UL
1033#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB 0x010430UL
1034#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB 0x010434UL
1035#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
1036#define DBG_REG_PCI_EXT_BUFFER_SIZE 0x010438UL
1037#define DBG_REG_PCI_FUNC_NUM 0x010a98UL
1038#define DBG_REG_PCI_LOGIC_ADDR 0x010460UL
1039#define DBG_REG_PCI_REQ_CREDIT 0x010440UL
1040#define DBG_REG_DEBUG_TARGET 0x01005cUL
1041#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
1042#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
1043#define DBG_REG_DEBUG_TARGET 0x01005cUL
1044#define DBG_REG_OTHER_ENGINE_MODE 0x010010UL
1045#define NIG_REG_DEBUG_PORT 0x5020d0UL
1046#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL
1047#define DBG_REG_ETHERNET_HDR_7 0x010b34UL
1048#define DBG_REG_ETHERNET_HDR_6 0x010b30UL
1049#define DBG_REG_ETHERNET_HDR_5 0x010b2cUL
1050#define DBG_REG_ETHERNET_HDR_4 0x010b28UL
1051#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
1052#define DBG_REG_NIG_DATA_LIMIT_SIZE 0x01043cUL
1053#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
1054#define DBG_REG_TIMESTAMP_FRAME_EN 0x010b54UL
1055#define DBG_REG_TIMESTAMP_TICK 0x010b50UL
1056#define DBG_REG_FILTER_ID_NUM 0x0109d4UL
1057#define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0x010a78UL
1058#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL
1059#define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS 0x010a90UL
1060#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL
1061#define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE 0x010a88UL
1062#define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0x010a8cUL
1063#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
1064#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL
1065#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0x01095cUL
1066#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL
1067#define DBG_REG_TRIGGER_STATE_SET_COUNT_0 0x010584UL
1068#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 0x01056cUL
1069#define DBG_REG_NO_GRANT_ON_FULL 0x010458UL
1070#define DBG_REG_STORM_ID_NUM 0x010b14UL
1071#define DBG_REG_CALENDAR_SLOT0 0x010014UL
1072#define DBG_REG_HW_ID_NUM 0x010b10UL
1073#define DBG_REG_FILTER_ENABLE 0x0109d0UL
1074#define DBG_REG_TIMESTAMP 0x010b4cUL
1075#define DBG_REG_CPU_TIMEOUT 0x010450UL
1076#define DBG_REG_TRIGGER_STATUS_CUR_STATE 0x010b60UL
1077#define GRC_REG_TRACE_FIFO_VALID_DATA 0x050064UL
1078#define GRC_REG_TRACE_FIFO 0x050068UL
1079#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x181530UL
1080#define IGU_REG_ERROR_HANDLING_MEMORY 0x181520UL
1081#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
1082#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
1083#define GRC_REG_PROTECTION_OVERRIDE_WINDOW 0x050500UL
1084#define TSEM_REG_VF_ERROR 0x1700408UL
1085#define USEM_REG_VF_ERROR 0x1900408UL
1086#define MSEM_REG_VF_ERROR 0x1800408UL
1087#define XSEM_REG_VF_ERROR 0x1400408UL
1088#define YSEM_REG_VF_ERROR 0x1500408UL
1089#define PSEM_REG_VF_ERROR 0x1600408UL
1090#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL
1091#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT 0x180408UL
1092#define IGU_REG_VF_CONFIGURATION 0x180804UL
1093#define PSWHST_REG_ZONE_PERMISSION_TABLE 0x2a0800UL
1094#define DORQ_REG_VF_USAGE_CNT 0x1009c4UL
1095#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 0xd806ccUL
1096#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 0xd806c8UL
1097#define PRS_REG_MSG_CT_MAIN_0 0x1f0a24UL
1098#define PRS_REG_MSG_CT_LB_0 0x1f0a28UL
1099#define BRB_REG_PER_TC_COUNTERS 0x341a00UL
1100
1101/* added */
1102#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1103#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1104#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1105#define MISCS_REG_FUNCTION_HIDE 0x0096f0UL
1106#define PCIE_REG_PRTY_MASK 0x0547b4UL
1107#define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL
1108#define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL
1109#define SEM_FAST_REG_INT_RAM_SIZE 20480
1110#define MCP_REG_SCRATCH_SIZE 57344
1111
1112#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 24
1113#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 24
1114#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 16
1115#define DORQ_REG_DB_DROP_DETAILS_ADDRESS 0x100a1cUL
1116
1117/* 8.10.9.0 FW */
1118#define NIG_REG_VXLAN_CTRL 0x50105cUL
1119#define PRS_REG_SEARCH_ROCE 0x1f040cUL
1120#define PRS_REG_CM_HDR_GFT 0x1f11c8UL
1121#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
1122#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
1123#define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL
1124#define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL
1125#define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL
1126#define PRS_REG_SEARCH_GFT 0x1f11bcUL
1127#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
1128#define PRS_REG_GFT_CAM 0x1f1100UL
1129#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
1130#define PGLUE_B_REG_MSDM_VF_SHIFT_B 0x2aa1c4UL
1131#define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL
1132#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL
1133#define PRS_REG_SEARCH_FCOE 0x1f0408UL
1134#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL
1135#define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL
1136#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL
1137#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL
1138#define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL
1139#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL
1140#define IGU_REG_WRITE_DONE_PENDING 0x180900UL
1141#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL
1142#define PRS_REG_MSG_INFO 0x1f0a1cUL
1143#define BAR0_MAP_REG_XSDM_RAM 0x1e00000UL
1144