1/*
2 *   BSD LICENSE
3 *
4 *   Copyright (C) Cavium networks Ltd. 2016.
5 *
6 *   Redistribution and use in source and binary forms, with or without
7 *   modification, are permitted provided that the following conditions
8 *   are met:
9 *
10 *     * Redistributions of source code must retain the above copyright
11 *       notice, this list of conditions and the following disclaimer.
12 *     * Redistributions in binary form must reproduce the above copyright
13 *       notice, this list of conditions and the following disclaimer in
14 *       the documentation and/or other materials provided with the
15 *       distribution.
16 *     * Neither the name of Cavium networks nor the names of its
17 *       contributors may be used to endorse or promote products derived
18 *       from this software without specific prior written permission.
19 *
20 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <unistd.h>
34#include <stdint.h>
35#include <stdio.h>
36#include <stdlib.h>
37
38#include <rte_atomic.h>
39#include <rte_branch_prediction.h>
40#include <rte_byteorder.h>
41#include <rte_common.h>
42#include <rte_cycles.h>
43#include <rte_errno.h>
44#include <rte_ethdev.h>
45#include <rte_ether.h>
46#include <rte_log.h>
47#include <rte_mbuf.h>
48#include <rte_prefetch.h>
49
50#include "base/nicvf_plat.h"
51
52#include "nicvf_ethdev.h"
53#include "nicvf_rxtx.h"
54#include "nicvf_logs.h"
55
56static inline void __hot
57fill_sq_desc_header(union sq_entry_t *entry, struct rte_mbuf *pkt)
58{
59	/* Local variable sqe to avoid read from sq desc memory*/
60	union sq_entry_t sqe;
61	uint64_t ol_flags;
62
63	/* Fill SQ header descriptor */
64	sqe.buff[0] = 0;
65	sqe.hdr.subdesc_type = SQ_DESC_TYPE_HEADER;
66	/* Number of sub-descriptors following this one */
67	sqe.hdr.subdesc_cnt = pkt->nb_segs;
68	sqe.hdr.tot_len = pkt->pkt_len;
69
70	ol_flags = pkt->ol_flags & NICVF_TX_OFFLOAD_MASK;
71	if (unlikely(ol_flags)) {
72		/* L4 cksum */
73		uint64_t l4_flags = ol_flags & PKT_TX_L4_MASK;
74		if (l4_flags == PKT_TX_TCP_CKSUM)
75			sqe.hdr.csum_l4 = SEND_L4_CSUM_TCP;
76		else if (l4_flags == PKT_TX_UDP_CKSUM)
77			sqe.hdr.csum_l4 = SEND_L4_CSUM_UDP;
78		else
79			sqe.hdr.csum_l4 = SEND_L4_CSUM_DISABLE;
80
81		sqe.hdr.l3_offset = pkt->l2_len;
82		sqe.hdr.l4_offset = pkt->l3_len + pkt->l2_len;
83
84		/* L3 cksum */
85		if (ol_flags & PKT_TX_IP_CKSUM)
86			sqe.hdr.csum_l3 = 1;
87	}
88
89	entry->buff[0] = sqe.buff[0];
90}
91
92static inline void __hot
93fill_sq_desc_header_zero_w1(union sq_entry_t *entry,
94				struct rte_mbuf *pkt)
95{
96	fill_sq_desc_header(entry, pkt);
97	entry->buff[1] = 0ULL;
98}
99
100void __hot
101nicvf_single_pool_free_xmited_buffers(struct nicvf_txq *sq)
102{
103	int j = 0;
104	uint32_t curr_head;
105	uint32_t head = sq->head;
106	struct rte_mbuf **txbuffs = sq->txbuffs;
107	void *obj_p[NICVF_MAX_TX_FREE_THRESH] __rte_cache_aligned;
108
109	curr_head = nicvf_addr_read(sq->sq_head) >> 4;
110	while (head != curr_head) {
111		if (txbuffs[head])
112			obj_p[j++] = txbuffs[head];
113
114		head = (head + 1) & sq->qlen_mask;
115	}
116
117	rte_mempool_put_bulk(sq->pool, obj_p, j);
118	sq->head = curr_head;
119	sq->xmit_bufs -= j;
120	NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
121}
122
123void __hot
124nicvf_multi_pool_free_xmited_buffers(struct nicvf_txq *sq)
125{
126	uint32_t n = 0;
127	uint32_t curr_head;
128	uint32_t head = sq->head;
129	struct rte_mbuf **txbuffs = sq->txbuffs;
130
131	curr_head = nicvf_addr_read(sq->sq_head) >> 4;
132	while (head != curr_head) {
133		if (txbuffs[head]) {
134			rte_pktmbuf_free_seg(txbuffs[head]);
135			n++;
136		}
137
138		head = (head + 1) & sq->qlen_mask;
139	}
140
141	sq->head = curr_head;
142	sq->xmit_bufs -= n;
143	NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
144}
145
146static inline uint32_t __hot
147nicvf_free_tx_desc(struct nicvf_txq *sq)
148{
149	return ((sq->head - sq->tail - 1) & sq->qlen_mask);
150}
151
152/* Send Header + Packet */
153#define TX_DESC_PER_PKT 2
154
155static inline uint32_t __hot
156nicvf_free_xmitted_buffers(struct nicvf_txq *sq, struct rte_mbuf **tx_pkts,
157			    uint16_t nb_pkts)
158{
159	uint32_t free_desc = nicvf_free_tx_desc(sq);
160
161	if (free_desc < nb_pkts * TX_DESC_PER_PKT ||
162			sq->xmit_bufs > sq->tx_free_thresh) {
163		if (unlikely(sq->pool == NULL))
164			sq->pool = tx_pkts[0]->pool;
165
166		sq->pool_free(sq);
167		/* Freed now, let see the number of free descs again */
168		free_desc = nicvf_free_tx_desc(sq);
169	}
170	return free_desc;
171}
172
173uint16_t __hot
174nicvf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
175{
176	int i;
177	uint32_t free_desc;
178	uint32_t tail;
179	struct nicvf_txq *sq = tx_queue;
180	union sq_entry_t *desc_ptr = sq->desc;
181	struct rte_mbuf **txbuffs = sq->txbuffs;
182	struct rte_mbuf *pkt;
183	uint32_t qlen_mask = sq->qlen_mask;
184
185	tail = sq->tail;
186	free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
187
188	for (i = 0; i < nb_pkts && (int)free_desc >= TX_DESC_PER_PKT; i++) {
189		pkt = tx_pkts[i];
190
191		txbuffs[tail] = NULL;
192		fill_sq_desc_header(desc_ptr + tail, pkt);
193		tail = (tail + 1) & qlen_mask;
194
195		txbuffs[tail] = pkt;
196		fill_sq_desc_gather(desc_ptr + tail, pkt);
197		tail = (tail + 1) & qlen_mask;
198		free_desc -= TX_DESC_PER_PKT;
199	}
200
201	if (likely(i)) {
202		sq->tail = tail;
203		sq->xmit_bufs += i;
204		rte_wmb();
205
206		/* Inform HW to xmit the packets */
207		nicvf_addr_write(sq->sq_door, i * TX_DESC_PER_PKT);
208	}
209	return i;
210}
211
212uint16_t __hot
213nicvf_xmit_pkts_multiseg(void *tx_queue, struct rte_mbuf **tx_pkts,
214			 uint16_t nb_pkts)
215{
216	int i, k;
217	uint32_t used_desc, next_used_desc, used_bufs, free_desc, tail;
218	struct nicvf_txq *sq = tx_queue;
219	union sq_entry_t *desc_ptr = sq->desc;
220	struct rte_mbuf **txbuffs = sq->txbuffs;
221	struct rte_mbuf *pkt, *seg;
222	uint32_t qlen_mask = sq->qlen_mask;
223	uint16_t nb_segs;
224
225	tail = sq->tail;
226	used_desc = 0;
227	used_bufs = 0;
228
229	free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
230
231	for (i = 0; i < nb_pkts; i++) {
232		pkt = tx_pkts[i];
233
234		nb_segs = pkt->nb_segs;
235
236		next_used_desc = used_desc + nb_segs + 1;
237		if (next_used_desc > free_desc)
238			break;
239		used_desc = next_used_desc;
240		used_bufs += nb_segs;
241
242		txbuffs[tail] = NULL;
243		fill_sq_desc_header_zero_w1(desc_ptr + tail, pkt);
244		tail = (tail + 1) & qlen_mask;
245
246		txbuffs[tail] = pkt;
247		fill_sq_desc_gather(desc_ptr + tail, pkt);
248		tail = (tail + 1) & qlen_mask;
249
250		seg = pkt->next;
251		for (k = 1; k < nb_segs; k++) {
252			txbuffs[tail] = seg;
253			fill_sq_desc_gather(desc_ptr + tail, seg);
254			tail = (tail + 1) & qlen_mask;
255			seg = seg->next;
256		}
257	}
258
259	if (likely(used_desc)) {
260		sq->tail = tail;
261		sq->xmit_bufs += used_bufs;
262		rte_wmb();
263
264		/* Inform HW to xmit the packets */
265		nicvf_addr_write(sq->sq_door, used_desc);
266	}
267	return i;
268}
269
270static const uint32_t ptype_table[16][16] __rte_cache_aligned = {
271	[L3_NONE][L4_NONE] = RTE_PTYPE_UNKNOWN,
272	[L3_NONE][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
273	[L3_NONE][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
274	[L3_NONE][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
275	[L3_NONE][L4_TCP] = RTE_PTYPE_L4_TCP,
276	[L3_NONE][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
277	[L3_NONE][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
278	[L3_NONE][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
279	[L3_NONE][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
280	[L3_NONE][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
281	[L3_NONE][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
282
283	[L3_IPV4][L4_NONE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
284	[L3_IPV4][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV4,
285	[L3_IPV4][L4_IPFRAG] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_FRAG,
286	[L3_IPV4][L4_IPCOMP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
287	[L3_IPV4][L4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
288	[L3_IPV4][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
289	[L3_IPV4][L4_GRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GRE,
290	[L3_IPV4][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
291	[L3_IPV4][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GENEVE,
292	[L3_IPV4][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_VXLAN,
293	[L3_IPV4][L4_NVGRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_NVGRE,
294
295	[L3_IPV4_OPT][L4_NONE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
296	[L3_IPV4_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV4_EXT |
297				RTE_PTYPE_L3_IPV4,
298	[L3_IPV4_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_FRAG,
299	[L3_IPV4_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
300	[L3_IPV4_OPT][L4_TCP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
301	[L3_IPV4_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
302	[L3_IPV4_OPT][L4_GRE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_GRE,
303	[L3_IPV4_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
304	[L3_IPV4_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4_EXT |
305				RTE_PTYPE_TUNNEL_GENEVE,
306	[L3_IPV4_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4_EXT |
307				RTE_PTYPE_TUNNEL_VXLAN,
308	[L3_IPV4_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV4_EXT |
309				RTE_PTYPE_TUNNEL_NVGRE,
310
311	[L3_IPV6][L4_NONE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
312	[L3_IPV6][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L3_IPV4,
313	[L3_IPV6][L4_IPFRAG] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_FRAG,
314	[L3_IPV6][L4_IPCOMP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
315	[L3_IPV6][L4_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
316	[L3_IPV6][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
317	[L3_IPV6][L4_GRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GRE,
318	[L3_IPV6][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
319	[L3_IPV6][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GENEVE,
320	[L3_IPV6][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_VXLAN,
321	[L3_IPV6][L4_NVGRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_NVGRE,
322
323	[L3_IPV6_OPT][L4_NONE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
324	[L3_IPV6_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV6_EXT |
325					RTE_PTYPE_L3_IPV4,
326	[L3_IPV6_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_FRAG,
327	[L3_IPV6_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
328	[L3_IPV6_OPT][L4_TCP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
329	[L3_IPV6_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
330	[L3_IPV6_OPT][L4_GRE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_TUNNEL_GRE,
331	[L3_IPV6_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
332	[L3_IPV6_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6_EXT |
333					RTE_PTYPE_TUNNEL_GENEVE,
334	[L3_IPV6_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6_EXT |
335					RTE_PTYPE_TUNNEL_VXLAN,
336	[L3_IPV6_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV6_EXT |
337					RTE_PTYPE_TUNNEL_NVGRE,
338
339	[L3_ET_STOP][L4_NONE] = RTE_PTYPE_UNKNOWN,
340	[L3_ET_STOP][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
341	[L3_ET_STOP][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
342	[L3_ET_STOP][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
343	[L3_ET_STOP][L4_TCP] = RTE_PTYPE_L4_TCP,
344	[L3_ET_STOP][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
345	[L3_ET_STOP][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
346	[L3_ET_STOP][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
347	[L3_ET_STOP][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
348	[L3_ET_STOP][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
349	[L3_ET_STOP][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
350
351	[L3_OTHER][L4_NONE] = RTE_PTYPE_UNKNOWN,
352	[L3_OTHER][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
353	[L3_OTHER][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
354	[L3_OTHER][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
355	[L3_OTHER][L4_TCP] = RTE_PTYPE_L4_TCP,
356	[L3_OTHER][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
357	[L3_OTHER][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
358	[L3_OTHER][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
359	[L3_OTHER][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
360	[L3_OTHER][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
361	[L3_OTHER][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
362};
363
364static inline uint32_t __hot
365nicvf_rx_classify_pkt(cqe_rx_word0_t cqe_rx_w0)
366{
367	return ptype_table[cqe_rx_w0.l3_type][cqe_rx_w0.l4_type];
368}
369
370static inline int __hot
371nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill)
372{
373	int i;
374	uint32_t ltail, next_tail;
375	struct nicvf_rbdr *rbdr = rxq->shared_rbdr;
376	uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
377	struct rbdr_entry_t *desc = rbdr->desc;
378	uint32_t qlen_mask = rbdr->qlen_mask;
379	uintptr_t door = rbdr->rbdr_door;
380	void *obj_p[NICVF_MAX_RX_FREE_THRESH] __rte_cache_aligned;
381
382	if (unlikely(rte_mempool_get_bulk(rxq->pool, obj_p, to_fill) < 0)) {
383		rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
384			to_fill;
385		return 0;
386	}
387
388	NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
389		(nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
390
391	next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
392					__ATOMIC_ACQUIRE);
393	ltail = next_tail;
394	for (i = 0; i < to_fill; i++) {
395		struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);
396
397		entry->full_addr = nicvf_mbuff_virt2phy((uintptr_t)obj_p[i],
398							mbuf_phys_off);
399		ltail++;
400	}
401
402	while (__atomic_load_n(&rbdr->tail, __ATOMIC_RELAXED) != next_tail)
403		rte_pause();
404
405	__atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
406	nicvf_addr_write(door, to_fill);
407	return to_fill;
408}
409
410static inline int32_t __hot
411nicvf_rx_pkts_to_process(struct nicvf_rxq *rxq, uint16_t nb_pkts,
412			 int32_t available_space)
413{
414	if (unlikely(available_space < nb_pkts))
415		rxq->available_space = nicvf_addr_read(rxq->cq_status)
416						& NICVF_CQ_CQE_COUNT_MASK;
417
418	return RTE_MIN(nb_pkts, available_space);
419}
420
421static inline void __hot
422nicvf_rx_offload(cqe_rx_word0_t cqe_rx_w0, cqe_rx_word2_t cqe_rx_w2,
423		 struct rte_mbuf *pkt)
424{
425	if (likely(cqe_rx_w0.rss_alg)) {
426		pkt->hash.rss = cqe_rx_w2.rss_tag;
427		pkt->ol_flags |= PKT_RX_RSS_HASH;
428	}
429}
430
431uint16_t __hot
432nicvf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
433{
434	uint32_t i, to_process;
435	struct cqe_rx_t *cqe_rx;
436	struct rte_mbuf *pkt;
437	cqe_rx_word0_t cqe_rx_w0;
438	cqe_rx_word1_t cqe_rx_w1;
439	cqe_rx_word2_t cqe_rx_w2;
440	cqe_rx_word3_t cqe_rx_w3;
441	struct nicvf_rxq *rxq = rx_queue;
442	union cq_entry_t *desc = rxq->desc;
443	const uint64_t cqe_mask = rxq->qlen_mask;
444	uint64_t rb0_ptr, mbuf_phys_off = rxq->mbuf_phys_off;
445	uint32_t cqe_head = rxq->head & cqe_mask;
446	int32_t available_space = rxq->available_space;
447	uint8_t port_id = rxq->port_id;
448	const uint8_t rbptr_offset = rxq->rbptr_offset;
449
450	to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
451
452	for (i = 0; i < to_process; i++) {
453		rte_prefetch_non_temporal(&desc[cqe_head + 2]);
454		cqe_rx = (struct cqe_rx_t *)&desc[cqe_head];
455		NICVF_RX_ASSERT(((struct cq_entry_type_t *)cqe_rx)->cqe_type
456						 == CQE_TYPE_RX);
457
458		NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
459		NICVF_LOAD_PAIR(cqe_rx_w2.u64, cqe_rx_w3.u64, &cqe_rx->word2);
460		rb0_ptr = *((uint64_t *)cqe_rx + rbptr_offset);
461		pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
462				(rb0_ptr - cqe_rx_w1.align_pad, mbuf_phys_off);
463
464		pkt->ol_flags = 0;
465		pkt->port = port_id;
466		pkt->data_len = cqe_rx_w3.rb0_sz;
467		pkt->data_off = RTE_PKTMBUF_HEADROOM + cqe_rx_w1.align_pad;
468		pkt->nb_segs = 1;
469		pkt->pkt_len = cqe_rx_w3.rb0_sz;
470		pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
471
472		nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
473		rte_mbuf_refcnt_set(pkt, 1);
474		rx_pkts[i] = pkt;
475		cqe_head = (cqe_head + 1) & cqe_mask;
476		nicvf_prefetch_store_keep(pkt);
477	}
478
479	if (likely(to_process)) {
480		rxq->available_space -= to_process;
481		rxq->head = cqe_head;
482		nicvf_addr_write(rxq->cq_door, to_process);
483		rxq->recv_buffers += to_process;
484	}
485	if (rxq->recv_buffers > rxq->rx_free_thresh) {
486		rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
487		NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
488	}
489
490	return to_process;
491}
492
493static inline uint16_t __hot
494nicvf_process_cq_mseg_entry(struct cqe_rx_t *cqe_rx,
495			uint64_t mbuf_phys_off, uint8_t port_id,
496			struct rte_mbuf **rx_pkt, uint8_t rbptr_offset)
497{
498	struct rte_mbuf *pkt, *seg, *prev;
499	cqe_rx_word0_t cqe_rx_w0;
500	cqe_rx_word1_t cqe_rx_w1;
501	cqe_rx_word2_t cqe_rx_w2;
502	uint16_t *rb_sz, nb_segs, seg_idx;
503	uint64_t *rb_ptr;
504
505	NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
506	NICVF_RX_ASSERT(cqe_rx_w0.cqe_type == CQE_TYPE_RX);
507	cqe_rx_w2 = cqe_rx->word2;
508	rb_sz = &cqe_rx->word3.rb0_sz;
509	rb_ptr = (uint64_t *)cqe_rx + rbptr_offset;
510	nb_segs = cqe_rx_w0.rb_cnt;
511	pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
512			(rb_ptr[0] - cqe_rx_w1.align_pad, mbuf_phys_off);
513
514	pkt->ol_flags = 0;
515	pkt->port = port_id;
516	pkt->data_off = RTE_PKTMBUF_HEADROOM + cqe_rx_w1.align_pad;
517	pkt->nb_segs = nb_segs;
518	pkt->pkt_len = cqe_rx_w1.pkt_len;
519	pkt->data_len = rb_sz[nicvf_frag_num(0)];
520	rte_mbuf_refcnt_set(pkt, 1);
521	pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
522	nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
523
524	*rx_pkt = pkt;
525	prev = pkt;
526	for (seg_idx = 1; seg_idx < nb_segs; seg_idx++) {
527		seg = (struct rte_mbuf *)nicvf_mbuff_phy2virt
528			(rb_ptr[seg_idx], mbuf_phys_off);
529
530		prev->next = seg;
531		seg->data_len = rb_sz[nicvf_frag_num(seg_idx)];
532		seg->port = port_id;
533		seg->data_off = RTE_PKTMBUF_HEADROOM;
534		rte_mbuf_refcnt_set(seg, 1);
535
536		prev = seg;
537	}
538	prev->next = NULL;
539	return nb_segs;
540}
541
542uint16_t __hot
543nicvf_recv_pkts_multiseg(void *rx_queue, struct rte_mbuf **rx_pkts,
544			 uint16_t nb_pkts)
545{
546	union cq_entry_t *cq_entry;
547	struct cqe_rx_t *cqe_rx;
548	struct nicvf_rxq *rxq = rx_queue;
549	union cq_entry_t *desc = rxq->desc;
550	const uint64_t cqe_mask = rxq->qlen_mask;
551	uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
552	uint32_t i, to_process, cqe_head, buffers_consumed = 0;
553	int32_t available_space = rxq->available_space;
554	uint16_t nb_segs;
555	const uint8_t port_id = rxq->port_id;
556	const uint8_t rbptr_offset = rxq->rbptr_offset;
557
558	cqe_head = rxq->head & cqe_mask;
559	to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
560
561	for (i = 0; i < to_process; i++) {
562		rte_prefetch_non_temporal(&desc[cqe_head + 2]);
563		cq_entry = &desc[cqe_head];
564		cqe_rx = (struct cqe_rx_t *)cq_entry;
565		nb_segs = nicvf_process_cq_mseg_entry(cqe_rx, mbuf_phys_off,
566				port_id, rx_pkts + i, rbptr_offset);
567		buffers_consumed += nb_segs;
568		cqe_head = (cqe_head + 1) & cqe_mask;
569		nicvf_prefetch_store_keep(rx_pkts[i]);
570	}
571
572	if (likely(to_process)) {
573		rxq->available_space -= to_process;
574		rxq->head = cqe_head;
575		nicvf_addr_write(rxq->cq_door, to_process);
576		rxq->recv_buffers += buffers_consumed;
577	}
578	if (rxq->recv_buffers > rxq->rx_free_thresh) {
579		rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
580		NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
581	}
582
583	return to_process;
584}
585
586uint32_t
587nicvf_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
588{
589	struct nicvf_rxq *rxq;
590
591	rxq = dev->data->rx_queues[queue_idx];
592	return nicvf_addr_read(rxq->cq_status) & NICVF_CQ_CQE_COUNT_MASK;
593}
594
595uint32_t
596nicvf_dev_rbdr_refill(struct rte_eth_dev *dev, uint16_t queue_idx)
597{
598	struct nicvf_rxq *rxq;
599	uint32_t to_process;
600	uint32_t rx_free;
601
602	rxq = dev->data->rx_queues[queue_idx];
603	to_process = rxq->recv_buffers;
604	while (rxq->recv_buffers > 0) {
605		rx_free = RTE_MIN(rxq->recv_buffers, NICVF_MAX_RX_FREE_THRESH);
606		rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rx_free);
607	}
608
609	assert(rxq->recv_buffers == 0);
610	return to_process;
611}
612