rte_memcpy_32.h revision 8b25d1ad
1/*
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2015 RehiveTech. All rights reserved.
5 *
6 *   Redistribution and use in source and binary forms, with or without
7 *   modification, are permitted provided that the following conditions
8 *   are met:
9 *
10 *     * Redistributions of source code must retain the above copyright
11 *       notice, this list of conditions and the following disclaimer.
12 *     * Redistributions in binary form must reproduce the above copyright
13 *       notice, this list of conditions and the following disclaimer in
14 *       the documentation and/or other materials provided with the
15 *       distribution.
16 *     * Neither the name of RehiveTech nor the names of its
17 *       contributors may be used to endorse or promote products derived
18 *       from this software without specific prior written permission.
19 *
20 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _RTE_MEMCPY_ARM32_H_
34#define _RTE_MEMCPY_ARM32_H_
35
36#include <stdint.h>
37#include <string.h>
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include "generic/rte_memcpy.h"
44
45#ifdef RTE_ARCH_ARM_NEON_MEMCPY
46
47#ifndef RTE_MACHINE_CPUFLAG_NEON
48#error "Cannot optimize memcpy by NEON as the CPU seems to not support this"
49#endif
50
51/* ARM NEON Intrinsics are used to copy data */
52#include <arm_neon.h>
53
54static inline void
55rte_mov16(uint8_t *dst, const uint8_t *src)
56{
57	vst1q_u8(dst, vld1q_u8(src));
58}
59
60static inline void
61rte_mov32(uint8_t *dst, const uint8_t *src)
62{
63	asm volatile (
64		"vld1.8 {d0-d3}, [%0]\n\t"
65		"vst1.8 {d0-d3}, [%1]\n\t"
66		: "+r" (src), "+r" (dst)
67		: : "memory", "d0", "d1", "d2", "d3");
68}
69
70static inline void
71rte_mov48(uint8_t *dst, const uint8_t *src)
72{
73	asm volatile (
74		"vld1.8 {d0-d3}, [%0]!\n\t"
75		"vld1.8 {d4-d5}, [%0]\n\t"
76		"vst1.8 {d0-d3}, [%1]!\n\t"
77		"vst1.8 {d4-d5}, [%1]\n\t"
78		: "+r" (src), "+r" (dst)
79		:
80		: "memory", "d0", "d1", "d2", "d3", "d4", "d5");
81}
82
83static inline void
84rte_mov64(uint8_t *dst, const uint8_t *src)
85{
86	asm volatile (
87		"vld1.8 {d0-d3}, [%0]!\n\t"
88		"vld1.8 {d4-d7}, [%0]\n\t"
89		"vst1.8 {d0-d3}, [%1]!\n\t"
90		"vst1.8 {d4-d7}, [%1]\n\t"
91		: "+r" (src), "+r" (dst)
92		:
93		: "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7");
94}
95
96static inline void
97rte_mov128(uint8_t *dst, const uint8_t *src)
98{
99	asm volatile ("pld [%0, #64]" : : "r" (src));
100	asm volatile (
101		"vld1.8 {d0-d3},   [%0]!\n\t"
102		"vld1.8 {d4-d7},   [%0]!\n\t"
103		"vld1.8 {d8-d11},  [%0]!\n\t"
104		"vld1.8 {d12-d15}, [%0]\n\t"
105		"vst1.8 {d0-d3},   [%1]!\n\t"
106		"vst1.8 {d4-d7},   [%1]!\n\t"
107		"vst1.8 {d8-d11},  [%1]!\n\t"
108		"vst1.8 {d12-d15}, [%1]\n\t"
109		: "+r" (src), "+r" (dst)
110		:
111		: "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
112		"d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15");
113}
114
115static inline void
116rte_mov256(uint8_t *dst, const uint8_t *src)
117{
118	asm volatile ("pld [%0,  #64]" : : "r" (src));
119	asm volatile ("pld [%0, #128]" : : "r" (src));
120	asm volatile ("pld [%0, #192]" : : "r" (src));
121	asm volatile ("pld [%0, #256]" : : "r" (src));
122	asm volatile ("pld [%0, #320]" : : "r" (src));
123	asm volatile ("pld [%0, #384]" : : "r" (src));
124	asm volatile ("pld [%0, #448]" : : "r" (src));
125	asm volatile (
126		"vld1.8 {d0-d3},   [%0]!\n\t"
127		"vld1.8 {d4-d7},   [%0]!\n\t"
128		"vld1.8 {d8-d11},  [%0]!\n\t"
129		"vld1.8 {d12-d15}, [%0]!\n\t"
130		"vld1.8 {d16-d19}, [%0]!\n\t"
131		"vld1.8 {d20-d23}, [%0]!\n\t"
132		"vld1.8 {d24-d27}, [%0]!\n\t"
133		"vld1.8 {d28-d31}, [%0]\n\t"
134		"vst1.8 {d0-d3},   [%1]!\n\t"
135		"vst1.8 {d4-d7},   [%1]!\n\t"
136		"vst1.8 {d8-d11},  [%1]!\n\t"
137		"vst1.8 {d12-d15}, [%1]!\n\t"
138		"vst1.8 {d16-d19}, [%1]!\n\t"
139		"vst1.8 {d20-d23}, [%1]!\n\t"
140		"vst1.8 {d24-d27}, [%1]!\n\t"
141		"vst1.8 {d28-d31}, [%1]!\n\t"
142		: "+r" (src), "+r" (dst)
143		:
144		: "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
145		"d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
146		"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
147		"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31");
148}
149
150#define rte_memcpy(dst, src, n)              \
151	({ (__builtin_constant_p(n)) ?       \
152	memcpy((dst), (src), (n)) :          \
153	rte_memcpy_func((dst), (src), (n)); })
154
155static inline void *
156rte_memcpy_func(void *dst, const void *src, size_t n)
157{
158	void *ret = dst;
159
160	/* We can't copy < 16 bytes using XMM registers so do it manually. */
161	if (n < 16) {
162		if (n & 0x01) {
163			*(uint8_t *)dst = *(const uint8_t *)src;
164			dst = (uint8_t *)dst + 1;
165			src = (const uint8_t *)src + 1;
166		}
167		if (n & 0x02) {
168			*(uint16_t *)dst = *(const uint16_t *)src;
169			dst = (uint16_t *)dst + 1;
170			src = (const uint16_t *)src + 1;
171		}
172		if (n & 0x04) {
173			*(uint32_t *)dst = *(const uint32_t *)src;
174			dst = (uint32_t *)dst + 1;
175			src = (const uint32_t *)src + 1;
176		}
177		if (n & 0x08) {
178			/* ARMv7 can not handle unaligned access to long long
179			 * (uint64_t). Therefore two uint32_t operations are
180			 * used.
181			 */
182			*(uint32_t *)dst = *(const uint32_t *)src;
183			dst = (uint32_t *)dst + 1;
184			src = (const uint32_t *)src + 1;
185			*(uint32_t *)dst = *(const uint32_t *)src;
186		}
187		return ret;
188	}
189
190	/* Special fast cases for <= 128 bytes */
191	if (n <= 32) {
192		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
193		rte_mov16((uint8_t *)dst - 16 + n,
194			(const uint8_t *)src - 16 + n);
195		return ret;
196	}
197
198	if (n <= 64) {
199		rte_mov32((uint8_t *)dst, (const uint8_t *)src);
200		rte_mov32((uint8_t *)dst - 32 + n,
201			(const uint8_t *)src - 32 + n);
202		return ret;
203	}
204
205	if (n <= 128) {
206		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
207		rte_mov64((uint8_t *)dst - 64 + n,
208			(const uint8_t *)src - 64 + n);
209		return ret;
210	}
211
212	/*
213	 * For large copies > 128 bytes. This combination of 256, 64 and 16 byte
214	 * copies was found to be faster than doing 128 and 32 byte copies as
215	 * well.
216	 */
217	for ( ; n >= 256; n -= 256) {
218		rte_mov256((uint8_t *)dst, (const uint8_t *)src);
219		dst = (uint8_t *)dst + 256;
220		src = (const uint8_t *)src + 256;
221	}
222
223	/*
224	 * We split the remaining bytes (which will be less than 256) into
225	 * 64byte (2^6) chunks.
226	 * Using incrementing integers in the case labels of a switch statement
227	 * enourages the compiler to use a jump table. To get incrementing
228	 * integers, we shift the 2 relevant bits to the LSB position to first
229	 * get decrementing integers, and then subtract.
230	 */
231	switch (3 - (n >> 6)) {
232	case 0x00:
233		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
234		n -= 64;
235		dst = (uint8_t *)dst + 64;
236		src = (const uint8_t *)src + 64;      /* fallthrough */
237	case 0x01:
238		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
239		n -= 64;
240		dst = (uint8_t *)dst + 64;
241		src = (const uint8_t *)src + 64;      /* fallthrough */
242	case 0x02:
243		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
244		n -= 64;
245		dst = (uint8_t *)dst + 64;
246		src = (const uint8_t *)src + 64;      /* fallthrough */
247	default:
248		break;
249	}
250
251	/*
252	 * We split the remaining bytes (which will be less than 64) into
253	 * 16byte (2^4) chunks, using the same switch structure as above.
254	 */
255	switch (3 - (n >> 4)) {
256	case 0x00:
257		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
258		n -= 16;
259		dst = (uint8_t *)dst + 16;
260		src = (const uint8_t *)src + 16;      /* fallthrough */
261	case 0x01:
262		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
263		n -= 16;
264		dst = (uint8_t *)dst + 16;
265		src = (const uint8_t *)src + 16;      /* fallthrough */
266	case 0x02:
267		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
268		n -= 16;
269		dst = (uint8_t *)dst + 16;
270		src = (const uint8_t *)src + 16;      /* fallthrough */
271	default:
272		break;
273	}
274
275	/* Copy any remaining bytes, without going beyond end of buffers */
276	if (n != 0)
277		rte_mov16((uint8_t *)dst - 16 + n,
278			(const uint8_t *)src - 16 + n);
279	return ret;
280}
281
282#else
283
284static inline void
285rte_mov16(uint8_t *dst, const uint8_t *src)
286{
287	memcpy(dst, src, 16);
288}
289
290static inline void
291rte_mov32(uint8_t *dst, const uint8_t *src)
292{
293	memcpy(dst, src, 32);
294}
295
296static inline void
297rte_mov48(uint8_t *dst, const uint8_t *src)
298{
299	memcpy(dst, src, 48);
300}
301
302static inline void
303rte_mov64(uint8_t *dst, const uint8_t *src)
304{
305	memcpy(dst, src, 64);
306}
307
308static inline void
309rte_mov128(uint8_t *dst, const uint8_t *src)
310{
311	memcpy(dst, src, 128);
312}
313
314static inline void
315rte_mov256(uint8_t *dst, const uint8_t *src)
316{
317	memcpy(dst, src, 256);
318}
319
320static inline void *
321rte_memcpy(void *dst, const void *src, size_t n)
322{
323	return memcpy(dst, src, n);
324}
325
326#endif /* RTE_ARCH_ARM_NEON_MEMCPY */
327
328#ifdef __cplusplus
329}
330#endif
331
332#endif /* _RTE_MEMCPY_ARM32_H_ */
333