rte_cycles.h revision 3d9b7210
1/*
2 *   BSD LICENSE
3 *
4 *   Copyright (C) IBM Corporation 2014.
5 *
6 *   Redistribution and use in source and binary forms, with or without
7 *   modification, are permitted provided that the following conditions
8 *   are met:
9 *
10 *     * Redistributions of source code must retain the above copyright
11 *       notice, this list of conditions and the following disclaimer.
12 *     * Redistributions in binary form must reproduce the above copyright
13 *       notice, this list of conditions and the following disclaimer in
14 *       the documentation and/or other materials provided with the
15 *       distribution.
16 *     * Neither the name of IBM Corporation nor the names of its
17 *       contributors may be used to endorse or promote products derived
18 *       from this software without specific prior written permission.
19 *
20 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31*/
32
33#ifndef _RTE_CYCLES_PPC_64_H_
34#define _RTE_CYCLES_PPC_64_H_
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include "generic/rte_cycles.h"
41
42#include <rte_byteorder.h>
43#include <rte_common.h>
44
45/**
46 * Read the time base register.
47 *
48 * @return
49 *   The time base for this lcore.
50 */
51static inline uint64_t
52rte_rdtsc(void)
53{
54	union {
55		uint64_t tsc_64;
56		RTE_STD_C11
57		struct {
58#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
59			uint32_t hi_32;
60			uint32_t lo_32;
61#else
62			uint32_t lo_32;
63			uint32_t hi_32;
64#endif
65		};
66	} tsc;
67	uint32_t tmp;
68
69	asm volatile(
70			"0:\n"
71			"mftbu   %[hi32]\n"
72			"mftb    %[lo32]\n"
73			"mftbu   %[tmp]\n"
74			"cmpw    %[tmp],%[hi32]\n"
75			"bne     0b\n"
76			: [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32),
77			[tmp] "=r"(tmp)
78		    );
79	return tsc.tsc_64;
80}
81
82static inline uint64_t
83rte_rdtsc_precise(void)
84{
85	rte_mb();
86	return rte_rdtsc();
87}
88
89static inline uint64_t
90rte_get_tsc_cycles(void) { return rte_rdtsc(); }
91
92#ifdef __cplusplus
93}
94#endif
95
96#endif /* _RTE_CYCLES_PPC_64_H_ */
97