ixgbe.h revision f7a9461e
1/*******************************************************************************
2
3  Intel 10 Gigabit PCI Express Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19  The full GNU General Public License is included in this distribution in
20  the file called "LICENSE.GPL".
21
22  Contact Information:
23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#ifndef IXGBE_NO_LRO
32#include <net/tcp.h>
33#endif
34
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#ifdef HAVE_IRQ_AFFINITY_HINT
38#include <linux/cpumask.h>
39#endif /* HAVE_IRQ_AFFINITY_HINT */
40#include <linux/vmalloc.h>
41
42#ifdef SIOCETHTOOL
43#include <linux/ethtool.h>
44#endif
45#ifdef NETIF_F_HW_VLAN_TX
46#include <linux/if_vlan.h>
47#endif
48#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
49#define IXGBE_DCA
50#include <linux/dca.h>
51#endif
52#include "ixgbe_dcb.h"
53
54#include "kcompat.h"
55
56#ifdef HAVE_SCTP
57#include <linux/sctp.h>
58#endif
59
60#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
61#define IXGBE_FCOE
62#include "ixgbe_fcoe.h"
63#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
64
65#if defined(CONFIG_PTP_1588_CLOCK) || defined(CONFIG_PTP_1588_CLOCK_MODULE)
66#define HAVE_IXGBE_PTP
67#endif
68
69#include "ixgbe_api.h"
70
71#define PFX "ixgbe: "
72#define DPRINTK(nlevel, klevel, fmt, args...) \
73	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
74	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
75		__func__ , ## args)))
76
77/* TX/RX descriptor defines */
78#define IXGBE_DEFAULT_TXD		512
79#define IXGBE_DEFAULT_TX_WORK		256
80#define IXGBE_MAX_TXD			4096
81#define IXGBE_MIN_TXD			64
82
83#define IXGBE_DEFAULT_RXD		512
84#define IXGBE_DEFAULT_RX_WORK		256
85#define IXGBE_MAX_RXD			4096
86#define IXGBE_MIN_RXD			64
87
88
89/* flow control */
90#define IXGBE_MIN_FCRTL			0x40
91#define IXGBE_MAX_FCRTL			0x7FF80
92#define IXGBE_MIN_FCRTH			0x600
93#define IXGBE_MAX_FCRTH			0x7FFF0
94#define IXGBE_DEFAULT_FCPAUSE		0xFFFF
95#define IXGBE_MIN_FCPAUSE		0
96#define IXGBE_MAX_FCPAUSE		0xFFFF
97
98/* Supported Rx Buffer Sizes */
99#define IXGBE_RXBUFFER_512	512    /* Used for packet split */
100#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
101#define IXGBE_RXBUFFER_1536	1536
102#define IXGBE_RXBUFFER_2K	2048
103#define IXGBE_RXBUFFER_3K	3072
104#define IXGBE_RXBUFFER_4K	4096
105#define IXGBE_RXBUFFER_7K	7168
106#define IXGBE_RXBUFFER_8K	8192
107#define IXGBE_RXBUFFER_15K	15360
108#endif /* CONFIG_IXGBE_DISABLE_PACKET_SPLIT */
109#define IXGBE_MAX_RXBUFFER	16384  /* largest size for single descriptor */
110
111/*
112 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
113 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
114 * this adds up to 512 bytes of extra data meaning the smallest allocation
115 * we could have is 1K.
116 * i.e. RXBUFFER_512 --> size-1024 slab
117 */
118#define IXGBE_RX_HDR_SIZE	IXGBE_RXBUFFER_512
119
120#define MAXIMUM_ETHERNET_VLAN_SIZE	(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
121
122/* How many Rx Buffers do we bundle into one write to the hardware ? */
123#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */
124
125#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
126#define IXGBE_TX_FLAGS_HW_VLAN		(u32)(1 << 1)
127#define IXGBE_TX_FLAGS_SW_VLAN		(u32)(1 << 2)
128#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 3)
129#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 4)
130#define IXGBE_TX_FLAGS_FCOE		(u32)(1 << 5)
131#define IXGBE_TX_FLAGS_FSO		(u32)(1 << 6)
132#define IXGBE_TX_FLAGS_TXSW		(u32)(1 << 7)
133#define IXGBE_TX_FLAGS_TSTAMP		(u32)(1 << 8)
134#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
135#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK	0xe0000000
136#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT	29
137#define IXGBE_TX_FLAGS_VLAN_SHIFT	16
138
139#define IXGBE_MAX_RX_DESC_POLL		10
140
141#define IXGBE_MAX_VF_MC_ENTRIES		30
142#define IXGBE_MAX_VF_FUNCTIONS		64
143#define IXGBE_MAX_VFTA_ENTRIES		128
144#define MAX_EMULATION_MAC_ADDRS		16
145#define IXGBE_MAX_PF_MACVLANS		15
146#define IXGBE_82599_VF_DEVICE_ID	0x10ED
147#define IXGBE_X540_VF_DEVICE_ID		0x1515
148
149#ifdef CONFIG_PCI_IOV
150#define VMDQ_P(p)	((p) + adapter->num_vfs)
151#else
152#define VMDQ_P(p)	(p)
153#endif
154
155#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter)	\
156	{							\
157		u32 current_counter = IXGBE_READ_REG(hw, reg);	\
158		if (current_counter < last_counter)		\
159			counter += 0x100000000LL;		\
160		last_counter = current_counter;			\
161		counter &= 0xFFFFFFFF00000000LL;		\
162		counter |= current_counter;			\
163	}
164
165#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
166	{								 \
167		u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb);	 \
168		u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb);	 \
169		u64 current_counter = (current_counter_msb << 32) |	 \
170			current_counter_lsb;				 \
171		if (current_counter < last_counter)			 \
172			counter += 0x1000000000LL;			 \
173		last_counter = current_counter;				 \
174		counter &= 0xFFFFFFF000000000LL;			 \
175		counter |= current_counter;				 \
176	}
177
178struct vf_stats {
179	u64 gprc;
180	u64 gorc;
181	u64 gptc;
182	u64 gotc;
183	u64 mprc;
184};
185
186struct vf_data_storage {
187	unsigned char vf_mac_addresses[ETH_ALEN];
188	u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
189	u16 num_vf_mc_hashes;
190	u16 default_vf_vlan_id;
191	u16 vlans_enabled;
192	bool clear_to_send;
193	struct vf_stats vfstats;
194	struct vf_stats last_vfstats;
195	struct vf_stats saved_rst_vfstats;
196	bool pf_set_mac;
197	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
198	u16 pf_qos;
199	u16 tx_rate;
200	u16 vlan_count;
201	u8 spoofchk_enabled;
202	struct pci_dev *vfdev;
203};
204
205struct vf_macvlans {
206	struct list_head l;
207	int vf;
208	bool free;
209	bool is_macvlan;
210	u8 vf_macvlan[ETH_ALEN];
211};
212
213#ifndef IXGBE_NO_LRO
214#define IXGBE_LRO_MAX		32	/*Maximum number of LRO descriptors*/
215#define IXGBE_LRO_GLOBAL	10
216
217struct ixgbe_lro_stats {
218	u32 flushed;
219	u32 coal;
220};
221
222/*
223 * ixgbe_lro_header - header format to be aggregated by LRO
224 * @iph: IP header without options
225 * @tcp: TCP header
226 * @ts:  Optional TCP timestamp data in TCP options
227 *
228 * This structure relies on the check above that verifies that the header
229 * is IPv4 and does not contain any options.
230 */
231struct ixgbe_lrohdr {
232	struct iphdr iph;
233	struct tcphdr th;
234	__be32 ts[0];
235};
236
237struct ixgbe_lro_list {
238	struct sk_buff_head active;
239	struct ixgbe_lro_stats stats;
240};
241
242#endif /* IXGBE_NO_LRO */
243#define IXGBE_MAX_TXD_PWR	14
244#define IXGBE_MAX_DATA_PER_TXD	(1 << IXGBE_MAX_TXD_PWR)
245
246/* Tx Descriptors needed, worst case */
247#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
248#ifdef MAX_SKB_FRAGS
249#define DESC_NEEDED	((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
250#else
251#define DESC_NEEDED	4
252#endif
253
254/* wrapper around a pointer to a socket buffer,
255 * so a DMA handle can be stored along with the buffer */
256struct ixgbe_tx_buffer {
257	union ixgbe_adv_tx_desc *next_to_watch;
258	unsigned long time_stamp;
259	struct sk_buff *skb;
260	unsigned int bytecount;
261	unsigned short gso_segs;
262	__be16 protocol;
263	DEFINE_DMA_UNMAP_ADDR(dma);
264	DEFINE_DMA_UNMAP_LEN(len);
265	u32 tx_flags;
266};
267
268struct ixgbe_rx_buffer {
269	struct sk_buff *skb;
270	dma_addr_t dma;
271#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
272	struct page *page;
273	unsigned int page_offset;
274#endif
275};
276
277struct ixgbe_queue_stats {
278	u64 packets;
279	u64 bytes;
280};
281
282struct ixgbe_tx_queue_stats {
283	u64 restart_queue;
284	u64 tx_busy;
285	u64 tx_done_old;
286};
287
288struct ixgbe_rx_queue_stats {
289	u64 rsc_count;
290	u64 rsc_flush;
291	u64 non_eop_descs;
292	u64 alloc_rx_page_failed;
293	u64 alloc_rx_buff_failed;
294	u64 csum_err;
295};
296
297enum ixgbe_ring_state_t {
298	__IXGBE_TX_FDIR_INIT_DONE,
299	__IXGBE_TX_DETECT_HANG,
300	__IXGBE_HANG_CHECK_ARMED,
301	__IXGBE_RX_RSC_ENABLED,
302#ifndef HAVE_NDO_SET_FEATURES
303	__IXGBE_RX_CSUM_ENABLED,
304#endif
305	__IXGBE_RX_CSUM_UDP_ZERO_ERR,
306#ifdef IXGBE_FCOE
307	__IXGBE_RX_FCOE_BUFSZ,
308#endif
309};
310
311#define check_for_tx_hang(ring) \
312	test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
313#define set_check_for_tx_hang(ring) \
314	set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
315#define clear_check_for_tx_hang(ring) \
316	clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
317#ifndef IXGBE_NO_HW_RSC
318#define ring_is_rsc_enabled(ring) \
319	test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
320#else
321#define ring_is_rsc_enabled(ring)	false
322#endif
323#define set_ring_rsc_enabled(ring) \
324	set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
325#define clear_ring_rsc_enabled(ring) \
326	clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
327#define netdev_ring(ring) (ring->netdev)
328#define ring_queue_index(ring) (ring->queue_index)
329
330
331struct ixgbe_ring {
332	struct ixgbe_ring *next;	/* pointer to next ring in q_vector */
333	struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
334	struct net_device *netdev;	/* netdev ring belongs to */
335	struct device *dev;		/* device for DMA mapping */
336	void *desc;			/* descriptor ring memory */
337	union {
338		struct ixgbe_tx_buffer *tx_buffer_info;
339		struct ixgbe_rx_buffer *rx_buffer_info;
340	};
341	unsigned long state;
342	u8 __iomem *tail;
343	dma_addr_t dma;			/* phys. address of descriptor ring */
344	unsigned int size;		/* length in bytes */
345
346	u16 count;			/* amount of descriptors */
347
348	u8 queue_index; /* needed for multiqueue queue management */
349	u8 reg_idx;			/* holds the special value that gets
350					 * the hardware register offset
351					 * associated with this ring, which is
352					 * different for DCB and RSS modes
353					 */
354	u16 next_to_use;
355	u16 next_to_clean;
356
357	union {
358#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
359		u16 rx_buf_len;
360#else
361		u16 next_to_alloc;
362#endif
363		struct {
364			u8 atr_sample_rate;
365			u8 atr_count;
366		};
367	};
368
369	u8 dcb_tc;
370	struct ixgbe_queue_stats stats;
371	union {
372		struct ixgbe_tx_queue_stats tx_stats;
373		struct ixgbe_rx_queue_stats rx_stats;
374	};
375} ____cacheline_internodealigned_in_smp;
376
377enum ixgbe_ring_f_enum {
378	RING_F_NONE = 0,
379	RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
380	RING_F_RSS,
381	RING_F_FDIR,
382#ifdef IXGBE_FCOE
383	RING_F_FCOE,
384#endif /* IXGBE_FCOE */
385	RING_F_ARRAY_SIZE  /* must be last in enum set */
386};
387
388#define IXGBE_MAX_DCB_INDICES	8
389#define IXGBE_MAX_RSS_INDICES	16
390#define IXGBE_MAX_VMDQ_INDICES	64
391#define IXGBE_MAX_FDIR_INDICES	64
392#ifdef IXGBE_FCOE
393#define IXGBE_MAX_FCOE_INDICES	8
394#define MAX_RX_QUEUES	(IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
395#define MAX_TX_QUEUES	(IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
396#else
397#define MAX_RX_QUEUES	IXGBE_MAX_FDIR_INDICES
398#define MAX_TX_QUEUES	IXGBE_MAX_FDIR_INDICES
399#endif /* IXGBE_FCOE */
400struct ixgbe_ring_feature {
401	int indices;
402	int mask;
403};
404
405#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
406/*
407 * FCoE requires that all Rx buffers be over 2200 bytes in length.  Since
408 * this is twice the size of a half page we need to double the page order
409 * for FCoE enabled Rx queues.
410 */
411#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
412static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
413{
414	return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
415}
416#else
417#define ixgbe_rx_pg_order(_ring) 0
418#endif
419#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
420#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
421
422#endif
423struct ixgbe_ring_container {
424	struct ixgbe_ring *ring;	/* pointer to linked list of rings */
425	unsigned int total_bytes;	/* total bytes processed this int */
426	unsigned int total_packets;	/* total packets processed this int */
427	u16 work_limit;			/* total work allowed per interrupt */
428	u8 count;			/* total number of rings in vector */
429	u8 itr;				/* current ITR setting for ring */
430};
431
432/* iterator for handling rings in ring container */
433#define ixgbe_for_each_ring(pos, head) \
434	for (pos = (head).ring; pos != NULL; pos = pos->next)
435
436#define MAX_RX_PACKET_BUFFERS	((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
437				 ? 8 : 1)
438#define MAX_TX_PACKET_BUFFERS	MAX_RX_PACKET_BUFFERS
439
440/* MAX_MSIX_Q_VECTORS of these are allocated,
441 * but we only use one per queue-specific vector.
442 */
443struct ixgbe_q_vector {
444	struct ixgbe_adapter *adapter;
445	int cpu;	/* CPU for DCA */
446	u16 v_idx;	/* index of q_vector within array, also used for
447			 * finding the bit in EICR and friends that
448			 * represents the vector for this ring */
449	u16 itr;	/* Interrupt throttle rate written to EITR */
450	struct ixgbe_ring_container rx, tx;
451
452#ifdef CONFIG_IXGBE_NAPI
453	struct napi_struct napi;
454#endif
455#ifndef HAVE_NETDEV_NAPI_LIST
456	struct net_device poll_dev;
457#endif
458#ifdef HAVE_IRQ_AFFINITY_HINT
459	cpumask_t affinity_mask;
460#endif
461#ifndef IXGBE_NO_LRO
462	struct ixgbe_lro_list lrolist;   /* LRO list for queue vector*/
463#endif
464	int numa_node;
465	char name[IFNAMSIZ + 9];
466
467	/* for dynamic allocation of rings associated with this q_vector */
468	struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
469};
470
471/*
472 * microsecond values for various ITR rates shifted by 2 to fit itr register
473 * with the first 3 bits reserved 0
474 */
475#define IXGBE_MIN_RSC_ITR	24
476#define IXGBE_100K_ITR		40
477#define IXGBE_20K_ITR		200
478#define IXGBE_16K_ITR		248
479#define IXGBE_10K_ITR		400
480#define IXGBE_8K_ITR		500
481
482/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
483static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
484					const u32 stat_err_bits)
485{
486	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
487}
488
489/* ixgbe_desc_unused - calculate if we have unused descriptors */
490static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
491{
492	u16 ntc = ring->next_to_clean;
493	u16 ntu = ring->next_to_use;
494
495	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
496}
497
498#define IXGBE_RX_DESC(R, i)	\
499	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
500#define IXGBE_TX_DESC(R, i)	\
501	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
502#define IXGBE_TX_CTXTDESC(R, i)	\
503	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
504
505#define IXGBE_MAX_JUMBO_FRAME_SIZE	16128
506#ifdef IXGBE_FCOE
507/* use 3K as the baby jumbo frame size for FCoE */
508#define IXGBE_FCOE_JUMBO_FRAME_SIZE	3072
509#endif /* IXGBE_FCOE */
510
511#define TCP_TIMER_VECTOR	0
512#define OTHER_VECTOR	1
513#define NON_Q_VECTORS	(OTHER_VECTOR + TCP_TIMER_VECTOR)
514
515#define IXGBE_MAX_MSIX_Q_VECTORS_82599	64
516#define IXGBE_MAX_MSIX_Q_VECTORS_82598	16
517
518struct ixgbe_mac_addr {
519	u8 addr[ETH_ALEN];
520	u16 queue;
521	u16 state; /* bitmask */
522};
523#define IXGBE_MAC_STATE_DEFAULT		0x1
524#define IXGBE_MAC_STATE_MODIFIED	0x2
525#define IXGBE_MAC_STATE_IN_USE		0x4
526
527#ifdef IXGBE_PROCFS
528struct ixgbe_therm_proc_data {
529	struct ixgbe_hw *hw;
530	struct ixgbe_thermal_diode_data *sensor_data;
531};
532
533#endif /* IXGBE_PROCFS */
534
535/*
536 * Only for array allocations in our adapter struct.  On 82598, there will be
537 * unused entries in the array, but that's not a big deal.  Also, in 82599,
538 * we can actually assign 64 queue vectors based on our extended-extended
539 * interrupt registers.  This is different than 82598, which is limited to 16.
540 */
541#define MAX_MSIX_Q_VECTORS	IXGBE_MAX_MSIX_Q_VECTORS_82599
542#define MAX_MSIX_COUNT		IXGBE_MAX_MSIX_VECTORS_82599
543
544#define MIN_MSIX_Q_VECTORS	1
545#define MIN_MSIX_COUNT		(MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
546
547/* default to trying for four seconds */
548#define IXGBE_TRY_LINK_TIMEOUT	(4 * HZ)
549
550/* board specific private data structure */
551struct ixgbe_adapter {
552#ifdef NETIF_F_HW_VLAN_TX
553#ifdef HAVE_VLAN_RX_REGISTER
554	struct vlan_group *vlgrp; /* must be first, see ixgbe_receive_skb */
555#else
556	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
557#endif
558#endif /* NETIF_F_HW_VLAN_TX */
559	/* OS defined structs */
560	struct net_device *netdev;
561	struct pci_dev *pdev;
562
563	unsigned long state;
564
565	/* Some features need tri-state capability,
566	 * thus the additional *_CAPABLE flags.
567	 */
568	u32 flags;
569#define IXGBE_FLAG_MSI_CAPABLE			(u32)(1 << 0)
570#define IXGBE_FLAG_MSI_ENABLED			(u32)(1 << 1)
571#define IXGBE_FLAG_MSIX_CAPABLE			(u32)(1 << 2)
572#define IXGBE_FLAG_MSIX_ENABLED			(u32)(1 << 3)
573#ifndef IXGBE_NO_LLI
574#define IXGBE_FLAG_LLI_PUSH			(u32)(1 << 4)
575#endif
576#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 8)
577#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
578#define IXGBE_FLAG_DCA_ENABLED			(u32)(1 << 9)
579#define IXGBE_FLAG_DCA_CAPABLE			(u32)(1 << 10)
580#define IXGBE_FLAG_DCA_ENABLED_DATA		(u32)(1 << 11)
581#else
582#define IXGBE_FLAG_DCA_ENABLED			(u32)0
583#define IXGBE_FLAG_DCA_CAPABLE			(u32)0
584#define IXGBE_FLAG_DCA_ENABLED_DATA             (u32)0
585#endif
586#define IXGBE_FLAG_MQ_CAPABLE			(u32)(1 << 12)
587#define IXGBE_FLAG_DCB_ENABLED			(u32)(1 << 13)
588#define IXGBE_FLAG_DCB_CAPABLE			(u32)(1 << 14)
589#define IXGBE_FLAG_RSS_ENABLED			(u32)(1 << 15)
590#define IXGBE_FLAG_RSS_CAPABLE			(u32)(1 << 16)
591#define IXGBE_FLAG_VMDQ_ENABLED			(u32)(1 << 18)
592#define IXGBE_FLAG_FAN_FAIL_CAPABLE		(u32)(1 << 19)
593#define IXGBE_FLAG_NEED_LINK_UPDATE		(u32)(1 << 20)
594#define IXGBE_FLAG_NEED_LINK_CONFIG		(u32)(1 << 21)
595#define IXGBE_FLAG_FDIR_HASH_CAPABLE		(u32)(1 << 22)
596#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE		(u32)(1 << 23)
597#ifdef IXGBE_FCOE
598#define IXGBE_FLAG_FCOE_CAPABLE			(u32)(1 << 24)
599#define IXGBE_FLAG_FCOE_ENABLED			(u32)(1 << 25)
600#endif /* IXGBE_FCOE */
601#define IXGBE_FLAG_SRIOV_CAPABLE		(u32)(1 << 26)
602#define IXGBE_FLAG_SRIOV_ENABLED		(u32)(1 << 27)
603#define IXGBE_FLAG_SRIOV_REPLICATION_ENABLE	(u32)(1 << 28)
604#define IXGBE_FLAG_SRIOV_L2SWITCH_ENABLE	(u32)(1 << 29)
605#define IXGBE_FLAG_SRIOV_L2LOOPBACK_ENABLE	(u32)(1 << 30)
606#define IXGBE_FLAG_RX_BB_CAPABLE		(u32)(1 << 31)
607
608	u32 flags2;
609#ifndef IXGBE_NO_HW_RSC
610#define IXGBE_FLAG2_RSC_CAPABLE			(u32)(1)
611#define IXGBE_FLAG2_RSC_ENABLED			(u32)(1 << 1)
612#else
613#define IXGBE_FLAG2_RSC_CAPABLE			0
614#define IXGBE_FLAG2_RSC_ENABLED			0
615#endif
616#define IXGBE_FLAG2_VMDQ_DEFAULT_OVERRIDE	(u32)(1 << 2)
617#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE		(u32)(1 << 4)
618#define IXGBE_FLAG2_TEMP_SENSOR_EVENT		(u32)(1 << 5)
619#define IXGBE_FLAG2_SEARCH_FOR_SFP		(u32)(1 << 6)
620#define IXGBE_FLAG2_SFP_NEEDS_RESET		(u32)(1 << 7)
621#define IXGBE_FLAG2_RESET_REQUESTED		(u32)(1 << 8)
622#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT	(u32)(1 << 9)
623#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP		(u32)(1 << 10)
624#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP		(u32)(1 << 11)
625#define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED      (u32)(1 << 12)
626
627	/* Tx fast path data */
628	int num_tx_queues;
629	u16 tx_itr_setting;
630	u16 tx_work_limit;
631
632	/* Rx fast path data */
633	int num_rx_queues;
634	u16 rx_itr_setting;
635	u16 rx_work_limit;
636
637	/* TX */
638	struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
639
640	u64 restart_queue;
641	u64 lsc_int;
642	u32 tx_timeout_count;
643
644	/* RX */
645	struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
646	int num_rx_pools;		/* == num_rx_queues in 82598 */
647	int num_rx_queues_per_pool;	/* 1 if 82598, can be many if 82599 */
648	u64 hw_csum_rx_error;
649	u64 hw_rx_no_dma_resources;
650	u64 rsc_total_count;
651	u64 rsc_total_flush;
652	u64 non_eop_descs;
653#ifndef CONFIG_IXGBE_NAPI
654	u64 rx_dropped_backlog;		/* count drops from rx intr handler */
655#endif
656	u32 alloc_rx_page_failed;
657	u32 alloc_rx_buff_failed;
658
659	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
660
661#ifdef HAVE_DCBNL_IEEE
662	struct ieee_pfc *ixgbe_ieee_pfc;
663	struct ieee_ets *ixgbe_ieee_ets;
664#endif
665	struct ixgbe_dcb_config dcb_cfg;
666	struct ixgbe_dcb_config temp_dcb_cfg;
667	u8 dcb_set_bitmap;
668	u8 dcbx_cap;
669#ifndef HAVE_MQPRIO
670	u8 tc;
671#endif
672	enum ixgbe_fc_mode last_lfc_mode;
673
674	int num_msix_vectors;
675	int max_msix_q_vectors;         /* true count of q_vectors for device */
676	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
677	struct msix_entry *msix_entries;
678
679#ifndef HAVE_NETDEV_STATS_IN_NETDEV
680	struct net_device_stats net_stats;
681#endif
682#ifndef IXGBE_NO_LRO
683	struct ixgbe_lro_stats lro_stats;
684#endif
685
686#ifdef ETHTOOL_TEST
687	u32 test_icr;
688	struct ixgbe_ring test_tx_ring;
689	struct ixgbe_ring test_rx_ring;
690#endif
691
692	/* structs defined in ixgbe_hw.h */
693	struct ixgbe_hw hw;
694	u16 msg_enable;
695	struct ixgbe_hw_stats stats;
696#ifndef IXGBE_NO_LLI
697	u32 lli_port;
698	u32 lli_size;
699	u32 lli_etype;
700	u32 lli_vlan_pri;
701#endif /* IXGBE_NO_LLI */
702
703	u32 *config_space;
704	u64 tx_busy;
705	unsigned int tx_ring_count;
706	unsigned int rx_ring_count;
707
708	u32 link_speed;
709	bool link_up;
710	unsigned long link_check_timeout;
711
712	struct timer_list service_timer;
713	struct work_struct service_task;
714
715	struct hlist_head fdir_filter_list;
716	unsigned long fdir_overflow; /* number of times ATR was backed off */
717	union ixgbe_atr_input fdir_mask;
718	int fdir_filter_count;
719	u32 fdir_pballoc;
720	u32 atr_sample_rate;
721	spinlock_t fdir_perfect_lock;
722
723#ifdef IXGBE_FCOE
724	struct ixgbe_fcoe fcoe;
725#endif /* IXGBE_FCOE */
726	u32 wol;
727
728	u16 bd_number;
729
730	char eeprom_id[32];
731	u16 eeprom_cap;
732	bool netdev_registered;
733	u32 interrupt_event;
734#ifdef HAVE_ETHTOOL_SET_PHYS_ID
735	u32 led_reg;
736#endif
737
738	DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
739	unsigned int num_vfs;
740	struct vf_data_storage *vfinfo;
741	int vf_rate_link_speed;
742	struct vf_macvlans vf_mvs;
743	struct vf_macvlans *mv_list;
744#ifdef CONFIG_PCI_IOV
745	u32 timer_event_accumulator;
746	u32 vferr_refcount;
747#endif
748	struct ixgbe_mac_addr *mac_table;
749#ifdef IXGBE_SYSFS
750	struct kobject *info_kobj;
751	struct kobject *therm_kobj[IXGBE_MAX_SENSORS];
752#else /* IXGBE_SYSFS */
753#ifdef IXGBE_PROCFS
754	struct proc_dir_entry *eth_dir;
755	struct proc_dir_entry *info_dir;
756	struct proc_dir_entry *therm_dir[IXGBE_MAX_SENSORS];
757	struct ixgbe_therm_proc_data therm_data[IXGBE_MAX_SENSORS];
758#endif /* IXGBE_PROCFS */
759#endif /* IXGBE_SYSFS */
760};
761
762struct ixgbe_fdir_filter {
763	struct  hlist_node fdir_node;
764	union ixgbe_atr_input filter;
765	u16 sw_idx;
766	u16 action;
767};
768
769enum ixgbe_state_t {
770	__IXGBE_TESTING,
771	__IXGBE_RESETTING,
772	__IXGBE_DOWN,
773	__IXGBE_SERVICE_SCHED,
774	__IXGBE_IN_SFP_INIT,
775};
776
777struct ixgbe_cb {
778#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
779	union {				/* Union defining head/tail partner */
780		struct sk_buff *head;
781		struct sk_buff *tail;
782	};
783#endif
784	dma_addr_t dma;
785#ifndef IXGBE_NO_LRO
786	__be32	tsecr;			/* timestamp echo response */
787	u32	tsval;			/* timestamp value in host order */
788	u32	next_seq;		/* next expected sequence number */
789	u16	free;			/* 65521 minus total size */
790	u16	mss;			/* size of data portion of packet */
791#endif /* IXGBE_NO_LRO */
792#ifdef HAVE_VLAN_RX_REGISTER
793	u16	vid;			/* VLAN tag */
794#endif
795	u16	append_cnt;		/* number of skb's appended */
796#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
797	bool	page_released;
798#endif
799};
800#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
801
802#ifdef IXGBE_SYSFS
803void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
804int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
805#endif /* IXGBE_SYSFS */
806#ifdef IXGBE_PROCFS
807void ixgbe_procfs_exit(struct ixgbe_adapter *adapter);
808int ixgbe_procfs_init(struct ixgbe_adapter *adapter);
809int ixgbe_procfs_topdir_init(void);
810void ixgbe_procfs_topdir_exit(void);
811#endif /* IXGBE_PROCFS */
812
813extern struct dcbnl_rtnl_ops dcbnl_ops;
814extern int ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max);
815
816extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
817
818/* needed by ixgbe_main.c */
819extern int ixgbe_validate_mac_addr(u8 *mc_addr);
820extern void ixgbe_check_options(struct ixgbe_adapter *adapter);
821extern void ixgbe_assign_netdev_ops(struct net_device *netdev);
822
823/* needed by ixgbe_ethtool.c */
824extern char ixgbe_driver_name[];
825extern const char ixgbe_driver_version[];
826
827extern void ixgbe_up(struct ixgbe_adapter *adapter);
828extern void ixgbe_down(struct ixgbe_adapter *adapter);
829extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
830extern void ixgbe_reset(struct ixgbe_adapter *adapter);
831extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
832extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
833extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
834extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
835extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
836extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,
837				    struct ixgbe_ring *);
838extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,
839				    struct ixgbe_ring *);
840extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
841extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
842extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
843extern bool ixgbe_is_ixgbe(struct pci_dev *pcidev);
844extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
845					 struct ixgbe_adapter *,
846					 struct ixgbe_ring *);
847extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
848					     struct ixgbe_tx_buffer *);
849extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
850extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
851				   struct ixgbe_ring *);
852extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
853			       struct ixgbe_ring *);
854extern void ixgbe_set_rx_mode(struct net_device *netdev);
855extern int ixgbe_write_mc_addr_list(struct net_device *netdev);
856extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
857#ifdef IXGBE_FCOE
858extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
859#endif /* IXGBE_FCOE */
860extern void ixgbe_do_reset(struct net_device *netdev);
861extern void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector);
862extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
863				   struct ixgbe_ring *);
864extern void ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter);
865extern void ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter);
866#ifdef ETHTOOL_OPS_COMPAT
867extern int ethtool_ioctl(struct ifreq *ifr);
868#endif
869
870#ifdef IXGBE_FCOE
871extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
872extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
873		     struct ixgbe_tx_buffer *first,
874		     u8 *hdr_len);
875extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
876extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
877			  union ixgbe_adv_rx_desc *rx_desc,
878			  struct sk_buff *skb);
879extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
880			      struct scatterlist *sgl, unsigned int sgc);
881#ifdef HAVE_NETDEV_OPS_FCOE_DDP_TARGET
882extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
883				 struct scatterlist *sgl, unsigned int sgc);
884#endif /* HAVE_NETDEV_OPS_FCOE_DDP_TARGET */
885extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
886#ifdef HAVE_NETDEV_OPS_FCOE_ENABLE
887extern int ixgbe_fcoe_enable(struct net_device *netdev);
888extern int ixgbe_fcoe_disable(struct net_device *netdev);
889#endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */
890#ifdef CONFIG_DCB
891#ifdef HAVE_DCBNL_OPS_GETAPP
892extern u8 ixgbe_fcoe_getapp(struct net_device *netdev);
893#endif /* HAVE_DCBNL_OPS_GETAPP */
894extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
895#endif /* CONFIG_DCB */
896#ifdef HAVE_NETDEV_OPS_FCOE_GETWWN
897extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
898#endif
899#endif /* IXGBE_FCOE */
900
901#ifdef CONFIG_DCB
902#ifdef HAVE_DCBNL_IEEE
903s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame);
904#endif /* HAVE_DCBNL_IEEE */
905#endif /* CONFIG_DCB */
906
907extern void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring);
908#ifndef ETHTOOL_GLINKSETTINGS
909extern int ixgbe_get_settings(struct net_device *netdev,
910			      struct ethtool_cmd *ecmd);
911#endif
912extern int ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,
913			    struct net_device *netdev, unsigned int vfn);
914extern void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
915extern int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
916				u8 *addr, u16 queue);
917extern int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
918				u8 *addr, u16 queue);
919extern int ixgbe_available_rars(struct ixgbe_adapter *adapter);
920#ifndef HAVE_VLAN_RX_REGISTER
921extern void ixgbe_vlan_mode(struct net_device *, u32);
922#endif
923#ifndef ixgbe_get_netdev_tc_txq
924#define ixgbe_get_netdev_tc_txq(dev, tc) (&dev->tc_to_txq[tc])
925#endif
926extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
927#endif /* _IXGBE_H_ */
928