ixgbe_common.c revision 3d9b7210
1/*******************************************************************************
2
3  Intel 10 Gigabit PCI Express Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19  The full GNU General Public License is included in this distribution in
20  the file called "LICENSE.GPL".
21
22  Contact Information:
23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "ixgbe_common.h"
29#include "ixgbe_phy.h"
30#include "ixgbe_api.h"
31
32static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
33static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
34static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
35static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
36static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
37static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
38					u16 count);
39static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
40static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
41static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
42static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
43
44static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
45static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
46					 u16 *san_mac_offset);
47static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
48					     u16 words, u16 *data);
49static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
50					      u16 words, u16 *data);
51static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
52						 u16 offset);
53
54/**
55 *  ixgbe_init_ops_generic - Inits function ptrs
56 *  @hw: pointer to the hardware structure
57 *
58 *  Initialize the function pointers.
59 **/
60s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
61{
62	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
63	struct ixgbe_mac_info *mac = &hw->mac;
64	u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
65
66	/* EEPROM */
67	eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
68	/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
69	if (eec & IXGBE_EEC_PRES) {
70		eeprom->ops.read = &ixgbe_read_eerd_generic;
71		eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
72	} else {
73		eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
74		eeprom->ops.read_buffer =
75				 &ixgbe_read_eeprom_buffer_bit_bang_generic;
76	}
77	eeprom->ops.write = &ixgbe_write_eeprom_generic;
78	eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
79	eeprom->ops.validate_checksum =
80				      &ixgbe_validate_eeprom_checksum_generic;
81	eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
82	eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
83
84	/* MAC */
85	mac->ops.init_hw = &ixgbe_init_hw_generic;
86	mac->ops.reset_hw = NULL;
87	mac->ops.start_hw = &ixgbe_start_hw_generic;
88	mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
89	mac->ops.get_media_type = NULL;
90	mac->ops.get_supported_physical_layer = NULL;
91	mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
92	mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
93	mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
94	mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
95	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
96	mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
97	mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
98
99	/* LEDs */
100	mac->ops.led_on = &ixgbe_led_on_generic;
101	mac->ops.led_off = &ixgbe_led_off_generic;
102	mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
103	mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
104
105	/* RAR, Multicast, VLAN */
106	mac->ops.set_rar = &ixgbe_set_rar_generic;
107	mac->ops.clear_rar = &ixgbe_clear_rar_generic;
108	mac->ops.insert_mac_addr = NULL;
109	mac->ops.set_vmdq = NULL;
110	mac->ops.clear_vmdq = NULL;
111	mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
112	mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
113	mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
114	mac->ops.enable_mc = &ixgbe_enable_mc_generic;
115	mac->ops.disable_mc = &ixgbe_disable_mc_generic;
116	mac->ops.clear_vfta = NULL;
117	mac->ops.set_vfta = NULL;
118	mac->ops.set_vlvf = NULL;
119	mac->ops.init_uta_tables = NULL;
120
121	/* Flow Control */
122	mac->ops.fc_enable = &ixgbe_fc_enable_generic;
123
124	/* Link */
125	mac->ops.get_link_capabilities = NULL;
126	mac->ops.setup_link = NULL;
127	mac->ops.check_link = NULL;
128
129	return 0;
130}
131
132/**
133 *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
134 *  control
135 *  @hw: pointer to hardware structure
136 *
137 *  There are several phys that do not support autoneg flow control. This
138 *  function check the device id to see if the associated phy supports
139 *  autoneg flow control.
140 **/
141static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
142{
143
144	switch (hw->device_id) {
145	case IXGBE_DEV_ID_X540T:
146		return 0;
147	case IXGBE_DEV_ID_82599_T3_LOM:
148		return 0;
149	default:
150		return IXGBE_ERR_FC_NOT_SUPPORTED;
151	}
152}
153
154/**
155 *  ixgbe_setup_fc - Set up flow control
156 *  @hw: pointer to hardware structure
157 *
158 *  Called at init time to set up flow control.
159 **/
160static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
161{
162	s32 ret_val = 0;
163	u32 reg = 0, reg_bp = 0;
164	u16 reg_cu = 0;
165
166	/*
167	 * Validate the requested mode.  Strict IEEE mode does not allow
168	 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
169	 */
170	if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
171		hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
172		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
173		goto out;
174	}
175
176	/*
177	 * 10gig parts do not have a word in the EEPROM to determine the
178	 * default flow control setting, so we explicitly set it to full.
179	 */
180	if (hw->fc.requested_mode == ixgbe_fc_default)
181		hw->fc.requested_mode = ixgbe_fc_full;
182
183	/*
184	 * Set up the 1G and 10G flow control advertisement registers so the
185	 * HW will be able to do fc autoneg once the cable is plugged in.  If
186	 * we link at 10G, the 1G advertisement is harmless and vice versa.
187	 */
188	switch (hw->phy.media_type) {
189	case ixgbe_media_type_fiber:
190	case ixgbe_media_type_backplane:
191		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
192		reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
193		break;
194	case ixgbe_media_type_copper:
195		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
196				     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
197		break;
198	default:
199		break;
200	}
201
202	/*
203	 * The possible values of fc.requested_mode are:
204	 * 0: Flow control is completely disabled
205	 * 1: Rx flow control is enabled (we can receive pause frames,
206	 *    but not send pause frames).
207	 * 2: Tx flow control is enabled (we can send pause frames but
208	 *    we do not support receiving pause frames).
209	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
210	 * other: Invalid.
211	 */
212	switch (hw->fc.requested_mode) {
213	case ixgbe_fc_none:
214		/* Flow control completely disabled by software override. */
215		reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
216		if (hw->phy.media_type == ixgbe_media_type_backplane)
217			reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
218				    IXGBE_AUTOC_ASM_PAUSE);
219		else if (hw->phy.media_type == ixgbe_media_type_copper)
220			reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
221		break;
222	case ixgbe_fc_tx_pause:
223		/*
224		 * Tx Flow control is enabled, and Rx Flow control is
225		 * disabled by software override.
226		 */
227		reg |= IXGBE_PCS1GANA_ASM_PAUSE;
228		reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
229		if (hw->phy.media_type == ixgbe_media_type_backplane) {
230			reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
231			reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
232		} else if (hw->phy.media_type == ixgbe_media_type_copper) {
233			reg_cu |= IXGBE_TAF_ASM_PAUSE;
234			reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
235		}
236		break;
237	case ixgbe_fc_rx_pause:
238		/*
239		 * Rx Flow control is enabled and Tx Flow control is
240		 * disabled by software override. Since there really
241		 * isn't a way to advertise that we are capable of RX
242		 * Pause ONLY, we will advertise that we support both
243		 * symmetric and asymmetric Rx PAUSE, as such we fall
244		 * through to the fc_full statement.  Later, we will
245		 * disable the adapter's ability to send PAUSE frames.
246		 */
247	case ixgbe_fc_full:
248		/* Flow control (both Rx and Tx) is enabled by SW override. */
249		reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
250		if (hw->phy.media_type == ixgbe_media_type_backplane)
251			reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
252				  IXGBE_AUTOC_ASM_PAUSE;
253		else if (hw->phy.media_type == ixgbe_media_type_copper)
254			reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
255		break;
256	default:
257		hw_dbg(hw, "Flow control param set incorrectly\n");
258		ret_val = IXGBE_ERR_CONFIG;
259		goto out;
260		break;
261	}
262
263	if (hw->mac.type != ixgbe_mac_X540) {
264		/*
265		 * Enable auto-negotiation between the MAC & PHY;
266		 * the MAC will advertise clause 37 flow control.
267		 */
268		IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
269		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
270
271		/* Disable AN timeout */
272		if (hw->fc.strict_ieee)
273			reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
274
275		IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
276		hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
277	}
278
279	/*
280	 * AUTOC restart handles negotiation of 1G and 10G on backplane
281	 * and copper. There is no need to set the PCS1GCTL register.
282	 *
283	 */
284	if (hw->phy.media_type == ixgbe_media_type_backplane) {
285		reg_bp |= IXGBE_AUTOC_AN_RESTART;
286		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
287	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
288		    (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
289		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
290				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
291	}
292
293	hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
294out:
295	return ret_val;
296}
297
298/**
299 *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
300 *  @hw: pointer to hardware structure
301 *
302 *  Starts the hardware by filling the bus info structure and media type, clears
303 *  all on chip counters, initializes receive address registers, multicast
304 *  table, VLAN filter table, calls routine to set up link and flow control
305 *  settings, and leaves transmit and receive units disabled and uninitialized
306 **/
307s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
308{
309	s32 ret_val;
310	u32 ctrl_ext;
311
312	/* Set the media type */
313	hw->phy.media_type = hw->mac.ops.get_media_type(hw);
314
315	/* PHY ops initialization must be done in reset_hw() */
316
317	/* Clear the VLAN filter table */
318	hw->mac.ops.clear_vfta(hw);
319
320	/* Clear statistics registers */
321	hw->mac.ops.clear_hw_cntrs(hw);
322
323	/* Set No Snoop Disable */
324	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
325	ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
326	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
327	IXGBE_WRITE_FLUSH(hw);
328
329	/* Setup flow control */
330	ret_val = ixgbe_setup_fc(hw);
331	if (ret_val != 0)
332		goto out;
333
334	/* Clear adapter stopped flag */
335	hw->adapter_stopped = false;
336
337out:
338	return ret_val;
339}
340
341/**
342 *  ixgbe_start_hw_gen2 - Init sequence for common device family
343 *  @hw: pointer to hw structure
344 *
345 * Performs the init sequence common to the second generation
346 * of 10 GbE devices.
347 * Devices in the second generation:
348 *     82599
349 *     X540
350 **/
351s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
352{
353	u32 i;
354	u32 regval;
355
356	/* Clear the rate limiters */
357	for (i = 0; i < hw->mac.max_tx_queues; i++) {
358		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
359		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
360	}
361	IXGBE_WRITE_FLUSH(hw);
362
363	/* Disable relaxed ordering */
364	for (i = 0; i < hw->mac.max_tx_queues; i++) {
365		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
366		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
367		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
368	}
369
370	for (i = 0; i < hw->mac.max_rx_queues; i++) {
371		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
372		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
373			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
374		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
375	}
376
377	return 0;
378}
379
380/**
381 *  ixgbe_init_hw_generic - Generic hardware initialization
382 *  @hw: pointer to hardware structure
383 *
384 *  Initialize the hardware by resetting the hardware, filling the bus info
385 *  structure and media type, clears all on chip counters, initializes receive
386 *  address registers, multicast table, VLAN filter table, calls routine to set
387 *  up link and flow control settings, and leaves transmit and receive units
388 *  disabled and uninitialized
389 **/
390s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
391{
392	s32 status;
393
394	/* Reset the hardware */
395	status = hw->mac.ops.reset_hw(hw);
396
397	if (status == 0) {
398		/* Start the HW */
399		status = hw->mac.ops.start_hw(hw);
400	}
401
402	return status;
403}
404
405/**
406 *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
407 *  @hw: pointer to hardware structure
408 *
409 *  Clears all hardware statistics counters by reading them from the hardware
410 *  Statistics counters are clear on read.
411 **/
412s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
413{
414	u16 i = 0;
415
416	IXGBE_READ_REG(hw, IXGBE_CRCERRS);
417	IXGBE_READ_REG(hw, IXGBE_ILLERRC);
418	IXGBE_READ_REG(hw, IXGBE_ERRBC);
419	IXGBE_READ_REG(hw, IXGBE_MSPDC);
420	for (i = 0; i < 8; i++)
421		IXGBE_READ_REG(hw, IXGBE_MPC(i));
422
423	IXGBE_READ_REG(hw, IXGBE_MLFC);
424	IXGBE_READ_REG(hw, IXGBE_MRFC);
425	IXGBE_READ_REG(hw, IXGBE_RLEC);
426	IXGBE_READ_REG(hw, IXGBE_LXONTXC);
427	IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
428	if (hw->mac.type >= ixgbe_mac_82599EB) {
429		IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
430		IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
431	} else {
432		IXGBE_READ_REG(hw, IXGBE_LXONRXC);
433		IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
434	}
435
436	for (i = 0; i < 8; i++) {
437		IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
438		IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
439		if (hw->mac.type >= ixgbe_mac_82599EB) {
440			IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
441			IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
442		} else {
443			IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
444			IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
445		}
446	}
447	if (hw->mac.type >= ixgbe_mac_82599EB)
448		for (i = 0; i < 8; i++)
449			IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
450	IXGBE_READ_REG(hw, IXGBE_PRC64);
451	IXGBE_READ_REG(hw, IXGBE_PRC127);
452	IXGBE_READ_REG(hw, IXGBE_PRC255);
453	IXGBE_READ_REG(hw, IXGBE_PRC511);
454	IXGBE_READ_REG(hw, IXGBE_PRC1023);
455	IXGBE_READ_REG(hw, IXGBE_PRC1522);
456	IXGBE_READ_REG(hw, IXGBE_GPRC);
457	IXGBE_READ_REG(hw, IXGBE_BPRC);
458	IXGBE_READ_REG(hw, IXGBE_MPRC);
459	IXGBE_READ_REG(hw, IXGBE_GPTC);
460	IXGBE_READ_REG(hw, IXGBE_GORCL);
461	IXGBE_READ_REG(hw, IXGBE_GORCH);
462	IXGBE_READ_REG(hw, IXGBE_GOTCL);
463	IXGBE_READ_REG(hw, IXGBE_GOTCH);
464	if (hw->mac.type == ixgbe_mac_82598EB)
465		for (i = 0; i < 8; i++)
466			IXGBE_READ_REG(hw, IXGBE_RNBC(i));
467	IXGBE_READ_REG(hw, IXGBE_RUC);
468	IXGBE_READ_REG(hw, IXGBE_RFC);
469	IXGBE_READ_REG(hw, IXGBE_ROC);
470	IXGBE_READ_REG(hw, IXGBE_RJC);
471	IXGBE_READ_REG(hw, IXGBE_MNGPRC);
472	IXGBE_READ_REG(hw, IXGBE_MNGPDC);
473	IXGBE_READ_REG(hw, IXGBE_MNGPTC);
474	IXGBE_READ_REG(hw, IXGBE_TORL);
475	IXGBE_READ_REG(hw, IXGBE_TORH);
476	IXGBE_READ_REG(hw, IXGBE_TPR);
477	IXGBE_READ_REG(hw, IXGBE_TPT);
478	IXGBE_READ_REG(hw, IXGBE_PTC64);
479	IXGBE_READ_REG(hw, IXGBE_PTC127);
480	IXGBE_READ_REG(hw, IXGBE_PTC255);
481	IXGBE_READ_REG(hw, IXGBE_PTC511);
482	IXGBE_READ_REG(hw, IXGBE_PTC1023);
483	IXGBE_READ_REG(hw, IXGBE_PTC1522);
484	IXGBE_READ_REG(hw, IXGBE_MPTC);
485	IXGBE_READ_REG(hw, IXGBE_BPTC);
486	for (i = 0; i < 16; i++) {
487		IXGBE_READ_REG(hw, IXGBE_QPRC(i));
488		IXGBE_READ_REG(hw, IXGBE_QPTC(i));
489		if (hw->mac.type >= ixgbe_mac_82599EB) {
490			IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
491			IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
492			IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
493			IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
494			IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
495		} else {
496			IXGBE_READ_REG(hw, IXGBE_QBRC(i));
497			IXGBE_READ_REG(hw, IXGBE_QBTC(i));
498		}
499	}
500
501	if (hw->mac.type == ixgbe_mac_X540) {
502		if (hw->phy.id == 0)
503			ixgbe_identify_phy(hw);
504		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
505				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
506		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
507				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
508		hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
509				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
510		hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
511				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
512	}
513
514	return 0;
515}
516
517/**
518 *  ixgbe_read_pba_string_generic - Reads part number string from EEPROM
519 *  @hw: pointer to hardware structure
520 *  @pba_num: stores the part number string from the EEPROM
521 *  @pba_num_size: part number string buffer length
522 *
523 *  Reads the part number string from the EEPROM.
524 **/
525s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
526				  u32 pba_num_size)
527{
528	s32 ret_val;
529	u16 data;
530	u16 pba_ptr;
531	u16 offset;
532	u16 length;
533
534	if (pba_num == NULL) {
535		hw_dbg(hw, "PBA string buffer was null\n");
536		return IXGBE_ERR_INVALID_ARGUMENT;
537	}
538
539	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
540	if (ret_val) {
541		hw_dbg(hw, "NVM Read Error\n");
542		return ret_val;
543	}
544
545	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
546	if (ret_val) {
547		hw_dbg(hw, "NVM Read Error\n");
548		return ret_val;
549	}
550
551	/*
552	 * if data is not ptr guard the PBA must be in legacy format which
553	 * means pba_ptr is actually our second data word for the PBA number
554	 * and we can decode it into an ascii string
555	 */
556	if (data != IXGBE_PBANUM_PTR_GUARD) {
557		hw_dbg(hw, "NVM PBA number is not stored as string\n");
558
559		/* we will need 11 characters to store the PBA */
560		if (pba_num_size < 11) {
561			hw_dbg(hw, "PBA string buffer too small\n");
562			return IXGBE_ERR_NO_SPACE;
563		}
564
565		/* extract hex string from data and pba_ptr */
566		pba_num[0] = (data >> 12) & 0xF;
567		pba_num[1] = (data >> 8) & 0xF;
568		pba_num[2] = (data >> 4) & 0xF;
569		pba_num[3] = data & 0xF;
570		pba_num[4] = (pba_ptr >> 12) & 0xF;
571		pba_num[5] = (pba_ptr >> 8) & 0xF;
572		pba_num[6] = '-';
573		pba_num[7] = 0;
574		pba_num[8] = (pba_ptr >> 4) & 0xF;
575		pba_num[9] = pba_ptr & 0xF;
576
577		/* put a null character on the end of our string */
578		pba_num[10] = '\0';
579
580		/* switch all the data but the '-' to hex char */
581		for (offset = 0; offset < 10; offset++) {
582			if (pba_num[offset] < 0xA)
583				pba_num[offset] += '0';
584			else if (pba_num[offset] < 0x10)
585				pba_num[offset] += 'A' - 0xA;
586		}
587
588		return 0;
589	}
590
591	ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
592	if (ret_val) {
593		hw_dbg(hw, "NVM Read Error\n");
594		return ret_val;
595	}
596
597	if (length == 0xFFFF || length == 0) {
598		hw_dbg(hw, "NVM PBA number section invalid length\n");
599		return IXGBE_ERR_PBA_SECTION;
600	}
601
602	/* check if pba_num buffer is big enough */
603	if (pba_num_size  < (((u32)length * 2) - 1)) {
604		hw_dbg(hw, "PBA string buffer too small\n");
605		return IXGBE_ERR_NO_SPACE;
606	}
607
608	/* trim pba length from start of string */
609	pba_ptr++;
610	length--;
611
612	for (offset = 0; offset < length; offset++) {
613		ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
614		if (ret_val) {
615			hw_dbg(hw, "NVM Read Error\n");
616			return ret_val;
617		}
618		pba_num[offset * 2] = (u8)(data >> 8);
619		pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
620	}
621	pba_num[offset * 2] = '\0';
622
623	return 0;
624}
625
626/**
627 *  ixgbe_get_mac_addr_generic - Generic get MAC address
628 *  @hw: pointer to hardware structure
629 *  @mac_addr: Adapter MAC address
630 *
631 *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
632 *  A reset of the adapter must be performed prior to calling this function
633 *  in order for the MAC address to have been loaded from the EEPROM into RAR0
634 **/
635s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
636{
637	u32 rar_high;
638	u32 rar_low;
639	u16 i;
640
641	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
642	rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
643
644	for (i = 0; i < 4; i++)
645		mac_addr[i] = (u8)(rar_low >> (i*8));
646
647	for (i = 0; i < 2; i++)
648		mac_addr[i+4] = (u8)(rar_high >> (i*8));
649
650	return 0;
651}
652
653/**
654 *  ixgbe_get_bus_info_generic - Generic set PCI bus info
655 *  @hw: pointer to hardware structure
656 *
657 *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
658 **/
659s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
660{
661	struct ixgbe_mac_info *mac = &hw->mac;
662	u16 link_status;
663
664	hw->bus.type = ixgbe_bus_type_pci_express;
665
666	/* Get the negotiated link width and speed from PCI config space */
667	link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
668
669	switch (link_status & IXGBE_PCI_LINK_WIDTH) {
670	case IXGBE_PCI_LINK_WIDTH_1:
671		hw->bus.width = ixgbe_bus_width_pcie_x1;
672		break;
673	case IXGBE_PCI_LINK_WIDTH_2:
674		hw->bus.width = ixgbe_bus_width_pcie_x2;
675		break;
676	case IXGBE_PCI_LINK_WIDTH_4:
677		hw->bus.width = ixgbe_bus_width_pcie_x4;
678		break;
679	case IXGBE_PCI_LINK_WIDTH_8:
680		hw->bus.width = ixgbe_bus_width_pcie_x8;
681		break;
682	default:
683		hw->bus.width = ixgbe_bus_width_unknown;
684		break;
685	}
686
687	switch (link_status & IXGBE_PCI_LINK_SPEED) {
688	case IXGBE_PCI_LINK_SPEED_2500:
689		hw->bus.speed = ixgbe_bus_speed_2500;
690		break;
691	case IXGBE_PCI_LINK_SPEED_5000:
692		hw->bus.speed = ixgbe_bus_speed_5000;
693		break;
694	case IXGBE_PCI_LINK_SPEED_8000:
695		hw->bus.speed = ixgbe_bus_speed_8000;
696		break;
697	default:
698		hw->bus.speed = ixgbe_bus_speed_unknown;
699		break;
700	}
701
702	mac->ops.set_lan_id(hw);
703
704	return 0;
705}
706
707/**
708 *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
709 *  @hw: pointer to the HW structure
710 *
711 *  Determines the LAN function id by reading memory-mapped registers
712 *  and swaps the port value if requested.
713 **/
714void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
715{
716	struct ixgbe_bus_info *bus = &hw->bus;
717	u32 reg;
718
719	reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
720	bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
721	bus->lan_id = bus->func;
722
723	/* check for a port swap */
724	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
725	if (reg & IXGBE_FACTPS_LFS)
726		bus->func ^= 0x1;
727}
728
729/**
730 *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
731 *  @hw: pointer to hardware structure
732 *
733 *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
734 *  disables transmit and receive units. The adapter_stopped flag is used by
735 *  the shared code and drivers to determine if the adapter is in a stopped
736 *  state and should not touch the hardware.
737 **/
738s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
739{
740	u32 reg_val;
741	u16 i;
742
743	/*
744	 * Set the adapter_stopped flag so other driver functions stop touching
745	 * the hardware
746	 */
747	hw->adapter_stopped = true;
748
749	/* Disable the receive unit */
750	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
751
752	/* Clear interrupt mask to stop interrupts from being generated */
753	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
754
755	/* Clear any pending interrupts, flush previous writes */
756	IXGBE_READ_REG(hw, IXGBE_EICR);
757
758	/* Disable the transmit unit.  Each queue must be disabled. */
759	for (i = 0; i < hw->mac.max_tx_queues; i++)
760		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
761
762	/* Disable the receive unit by stopping each queue */
763	for (i = 0; i < hw->mac.max_rx_queues; i++) {
764		reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
765		reg_val &= ~IXGBE_RXDCTL_ENABLE;
766		reg_val |= IXGBE_RXDCTL_SWFLSH;
767		IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
768	}
769
770	/* flush all queues disables */
771	IXGBE_WRITE_FLUSH(hw);
772	msleep(2);
773
774	/*
775	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
776	 * access and verify no pending requests
777	 */
778	return ixgbe_disable_pcie_master(hw);
779}
780
781/**
782 *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
783 *  @hw: pointer to hardware structure
784 *  @index: led number to turn on
785 **/
786s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
787{
788	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
789
790	/* To turn on the LED, set mode to ON. */
791	led_reg &= ~IXGBE_LED_MODE_MASK(index);
792	led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
793	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
794	IXGBE_WRITE_FLUSH(hw);
795
796	return 0;
797}
798
799/**
800 *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
801 *  @hw: pointer to hardware structure
802 *  @index: led number to turn off
803 **/
804s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
805{
806	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
807
808	/* To turn off the LED, set mode to OFF. */
809	led_reg &= ~IXGBE_LED_MODE_MASK(index);
810	led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
811	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
812	IXGBE_WRITE_FLUSH(hw);
813
814	return 0;
815}
816
817/**
818 *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
819 *  @hw: pointer to hardware structure
820 *
821 *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
822 *  ixgbe_hw struct in order to set up EEPROM access.
823 **/
824s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
825{
826	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
827	u32 eec;
828	u16 eeprom_size;
829
830	if (eeprom->type == ixgbe_eeprom_uninitialized) {
831		eeprom->type = ixgbe_eeprom_none;
832		/* Set default semaphore delay to 10ms which is a well
833		 * tested value */
834		eeprom->semaphore_delay = 10;
835		/* Clear EEPROM page size, it will be initialized as needed */
836		eeprom->word_page_size = 0;
837
838		/*
839		 * Check for EEPROM present first.
840		 * If not present leave as none
841		 */
842		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
843		if (eec & IXGBE_EEC_PRES) {
844			eeprom->type = ixgbe_eeprom_spi;
845
846			/*
847			 * SPI EEPROM is assumed here.  This code would need to
848			 * change if a future EEPROM is not SPI.
849			 */
850			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
851					    IXGBE_EEC_SIZE_SHIFT);
852			eeprom->word_size = 1 << (eeprom_size +
853					     IXGBE_EEPROM_WORD_SIZE_SHIFT);
854		}
855
856		if (eec & IXGBE_EEC_ADDR_SIZE)
857			eeprom->address_bits = 16;
858		else
859			eeprom->address_bits = 8;
860		hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
861			  "%d\n", eeprom->type, eeprom->word_size,
862			  eeprom->address_bits);
863	}
864
865	return 0;
866}
867
868/**
869 *  ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
870 *  @hw: pointer to hardware structure
871 *  @offset: offset within the EEPROM to write
872 *  @words: number of word(s)
873 *  @data: 16 bit word(s) to write to EEPROM
874 *
875 *  Reads 16 bit word(s) from EEPROM through bit-bang method
876 **/
877s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
878					       u16 words, u16 *data)
879{
880	s32 status = 0;
881	u16 i, count;
882
883	hw->eeprom.ops.init_params(hw);
884
885	if (words == 0) {
886		status = IXGBE_ERR_INVALID_ARGUMENT;
887		goto out;
888	}
889
890	if (offset + words > hw->eeprom.word_size) {
891		status = IXGBE_ERR_EEPROM;
892		goto out;
893	}
894
895	/*
896	 * The EEPROM page size cannot be queried from the chip. We do lazy
897	 * initialization. It is worth to do that when we write large buffer.
898	 */
899	if ((hw->eeprom.word_page_size == 0) &&
900	    (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
901		ixgbe_detect_eeprom_page_size_generic(hw, offset);
902
903	/*
904	 * We cannot hold synchronization semaphores for too long
905	 * to avoid other entity starvation. However it is more efficient
906	 * to read in bursts than synchronizing access for each word.
907	 */
908	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
909		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
910			IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
911		status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
912							    count, &data[i]);
913
914		if (status != 0)
915			break;
916	}
917
918out:
919	return status;
920}
921
922/**
923 *  ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
924 *  @hw: pointer to hardware structure
925 *  @offset: offset within the EEPROM to be written to
926 *  @words: number of word(s)
927 *  @data: 16 bit word(s) to be written to the EEPROM
928 *
929 *  If ixgbe_eeprom_update_checksum is not called after this function, the
930 *  EEPROM will most likely contain an invalid checksum.
931 **/
932static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
933					      u16 words, u16 *data)
934{
935	s32 status;
936	u16 word;
937	u16 page_size;
938	u16 i;
939	u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
940
941	/* Prepare the EEPROM for writing  */
942	status = ixgbe_acquire_eeprom(hw);
943
944	if (status == 0) {
945		if (ixgbe_ready_eeprom(hw) != 0) {
946			ixgbe_release_eeprom(hw);
947			status = IXGBE_ERR_EEPROM;
948		}
949	}
950
951	if (status == 0) {
952		for (i = 0; i < words; i++) {
953			ixgbe_standby_eeprom(hw);
954
955			/*  Send the WRITE ENABLE command (8 bit opcode )  */
956			ixgbe_shift_out_eeprom_bits(hw,
957						   IXGBE_EEPROM_WREN_OPCODE_SPI,
958						   IXGBE_EEPROM_OPCODE_BITS);
959
960			ixgbe_standby_eeprom(hw);
961
962			/*
963			 * Some SPI eeproms use the 8th address bit embedded
964			 * in the opcode
965			 */
966			if ((hw->eeprom.address_bits == 8) &&
967			    ((offset + i) >= 128))
968				write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
969
970			/* Send the Write command (8-bit opcode + addr) */
971			ixgbe_shift_out_eeprom_bits(hw, write_opcode,
972						    IXGBE_EEPROM_OPCODE_BITS);
973			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
974						    hw->eeprom.address_bits);
975
976			page_size = hw->eeprom.word_page_size;
977
978			/* Send the data in burst via SPI*/
979			do {
980				word = data[i];
981				word = (word >> 8) | (word << 8);
982				ixgbe_shift_out_eeprom_bits(hw, word, 16);
983
984				if (page_size == 0)
985					break;
986
987				/* do not wrap around page */
988				if (((offset + i) & (page_size - 1)) ==
989				    (page_size - 1))
990					break;
991			} while (++i < words);
992
993			ixgbe_standby_eeprom(hw);
994			msleep(10);
995		}
996		/* Done with writing - release the EEPROM */
997		ixgbe_release_eeprom(hw);
998	}
999
1000	return status;
1001}
1002
1003/**
1004 *  ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1005 *  @hw: pointer to hardware structure
1006 *  @offset: offset within the EEPROM to be written to
1007 *  @data: 16 bit word to be written to the EEPROM
1008 *
1009 *  If ixgbe_eeprom_update_checksum is not called after this function, the
1010 *  EEPROM will most likely contain an invalid checksum.
1011 **/
1012s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1013{
1014	s32 status;
1015
1016	hw->eeprom.ops.init_params(hw);
1017
1018	if (offset >= hw->eeprom.word_size) {
1019		status = IXGBE_ERR_EEPROM;
1020		goto out;
1021	}
1022
1023	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1024
1025out:
1026	return status;
1027}
1028
1029/**
1030 *  ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1031 *  @hw: pointer to hardware structure
1032 *  @offset: offset within the EEPROM to be read
1033 *  @data: read 16 bit words(s) from EEPROM
1034 *  @words: number of word(s)
1035 *
1036 *  Reads 16 bit word(s) from EEPROM through bit-bang method
1037 **/
1038s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1039					      u16 words, u16 *data)
1040{
1041	s32 status = 0;
1042	u16 i, count;
1043
1044	hw->eeprom.ops.init_params(hw);
1045
1046	if (words == 0) {
1047		status = IXGBE_ERR_INVALID_ARGUMENT;
1048		goto out;
1049	}
1050
1051	if (offset + words > hw->eeprom.word_size) {
1052		status = IXGBE_ERR_EEPROM;
1053		goto out;
1054	}
1055
1056	/*
1057	 * We cannot hold synchronization semaphores for too long
1058	 * to avoid other entity starvation. However it is more efficient
1059	 * to read in bursts than synchronizing access for each word.
1060	 */
1061	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1062		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1063			IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1064
1065		status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1066							   count, &data[i]);
1067
1068		if (status != 0)
1069			break;
1070	}
1071
1072out:
1073	return status;
1074}
1075
1076/**
1077 *  ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1078 *  @hw: pointer to hardware structure
1079 *  @offset: offset within the EEPROM to be read
1080 *  @words: number of word(s)
1081 *  @data: read 16 bit word(s) from EEPROM
1082 *
1083 *  Reads 16 bit word(s) from EEPROM through bit-bang method
1084 **/
1085static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1086					     u16 words, u16 *data)
1087{
1088	s32 status;
1089	u16 word_in;
1090	u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1091	u16 i;
1092
1093	/* Prepare the EEPROM for reading  */
1094	status = ixgbe_acquire_eeprom(hw);
1095
1096	if (status == 0) {
1097		if (ixgbe_ready_eeprom(hw) != 0) {
1098			ixgbe_release_eeprom(hw);
1099			status = IXGBE_ERR_EEPROM;
1100		}
1101	}
1102
1103	if (status == 0) {
1104		for (i = 0; i < words; i++) {
1105			ixgbe_standby_eeprom(hw);
1106			/*
1107			 * Some SPI eeproms use the 8th address bit embedded
1108			 * in the opcode
1109			 */
1110			if ((hw->eeprom.address_bits == 8) &&
1111			    ((offset + i) >= 128))
1112				read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1113
1114			/* Send the READ command (opcode + addr) */
1115			ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1116						    IXGBE_EEPROM_OPCODE_BITS);
1117			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1118						    hw->eeprom.address_bits);
1119
1120			/* Read the data. */
1121			word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1122			data[i] = (word_in >> 8) | (word_in << 8);
1123		}
1124
1125		/* End this read operation */
1126		ixgbe_release_eeprom(hw);
1127	}
1128
1129	return status;
1130}
1131
1132/**
1133 *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1134 *  @hw: pointer to hardware structure
1135 *  @offset: offset within the EEPROM to be read
1136 *  @data: read 16 bit value from EEPROM
1137 *
1138 *  Reads 16 bit value from EEPROM through bit-bang method
1139 **/
1140s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1141				       u16 *data)
1142{
1143	s32 status;
1144
1145	hw->eeprom.ops.init_params(hw);
1146
1147	if (offset >= hw->eeprom.word_size) {
1148		status = IXGBE_ERR_EEPROM;
1149		goto out;
1150	}
1151
1152	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1153
1154out:
1155	return status;
1156}
1157
1158/**
1159 *  ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1160 *  @hw: pointer to hardware structure
1161 *  @offset: offset of word in the EEPROM to read
1162 *  @words: number of word(s)
1163 *  @data: 16 bit word(s) from the EEPROM
1164 *
1165 *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
1166 **/
1167s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1168				   u16 words, u16 *data)
1169{
1170	u32 eerd;
1171	s32 status = 0;
1172	u32 i;
1173
1174	hw->eeprom.ops.init_params(hw);
1175
1176	if (words == 0) {
1177		status = IXGBE_ERR_INVALID_ARGUMENT;
1178		goto out;
1179	}
1180
1181	if (offset >= hw->eeprom.word_size) {
1182		status = IXGBE_ERR_EEPROM;
1183		goto out;
1184	}
1185
1186	for (i = 0; i < words; i++) {
1187		eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1188		       IXGBE_EEPROM_RW_REG_START;
1189
1190		IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1191		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1192
1193		if (status == 0) {
1194			data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1195				   IXGBE_EEPROM_RW_REG_DATA);
1196		} else {
1197			hw_dbg(hw, "Eeprom read timed out\n");
1198			goto out;
1199		}
1200	}
1201out:
1202	return status;
1203}
1204
1205/**
1206 *  ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1207 *  @hw: pointer to hardware structure
1208 *  @offset: offset within the EEPROM to be used as a scratch pad
1209 *
1210 *  Discover EEPROM page size by writing marching data at given offset.
1211 *  This function is called only when we are writing a new large buffer
1212 *  at given offset so the data would be overwritten anyway.
1213 **/
1214static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1215						 u16 offset)
1216{
1217	u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1218	s32 status = 0;
1219	u16 i;
1220
1221	for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1222		data[i] = i;
1223
1224	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1225	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1226					     IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1227	hw->eeprom.word_page_size = 0;
1228	if (status != 0)
1229		goto out;
1230
1231	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1232	if (status != 0)
1233		goto out;
1234
1235	/*
1236	 * When writing in burst more than the actual page size
1237	 * EEPROM address wraps around current page.
1238	 */
1239	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1240
1241	hw_dbg(hw, "Detected EEPROM page size = %d words.",
1242		  hw->eeprom.word_page_size);
1243out:
1244	return status;
1245}
1246
1247/**
1248 *  ixgbe_read_eerd_generic - Read EEPROM word using EERD
1249 *  @hw: pointer to hardware structure
1250 *  @offset: offset of  word in the EEPROM to read
1251 *  @data: word read from the EEPROM
1252 *
1253 *  Reads a 16 bit word from the EEPROM using the EERD register.
1254 **/
1255s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1256{
1257	return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1258}
1259
1260/**
1261 *  ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1262 *  @hw: pointer to hardware structure
1263 *  @offset: offset of  word in the EEPROM to write
1264 *  @words: number of word(s)
1265 *  @data: word(s) write to the EEPROM
1266 *
1267 *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
1268 **/
1269s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1270				    u16 words, u16 *data)
1271{
1272	u32 eewr;
1273	s32 status = 0;
1274	u16 i;
1275
1276	hw->eeprom.ops.init_params(hw);
1277
1278	if (words == 0) {
1279		status = IXGBE_ERR_INVALID_ARGUMENT;
1280		goto out;
1281	}
1282
1283	if (offset >= hw->eeprom.word_size) {
1284		status = IXGBE_ERR_EEPROM;
1285		goto out;
1286	}
1287
1288	for (i = 0; i < words; i++) {
1289		eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1290			(data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1291			IXGBE_EEPROM_RW_REG_START;
1292
1293		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1294		if (status != 0) {
1295			hw_dbg(hw, "Eeprom write EEWR timed out\n");
1296			goto out;
1297		}
1298
1299		IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1300
1301		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1302		if (status != 0) {
1303			hw_dbg(hw, "Eeprom write EEWR timed out\n");
1304			goto out;
1305		}
1306	}
1307
1308out:
1309	return status;
1310}
1311
1312/**
1313 *  ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1314 *  @hw: pointer to hardware structure
1315 *  @offset: offset of  word in the EEPROM to write
1316 *  @data: word write to the EEPROM
1317 *
1318 *  Write a 16 bit word to the EEPROM using the EEWR register.
1319 **/
1320s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1321{
1322	return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1323}
1324
1325/**
1326 *  ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1327 *  @hw: pointer to hardware structure
1328 *  @ee_reg: EEPROM flag for polling
1329 *
1330 *  Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1331 *  read or write is done respectively.
1332 **/
1333s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1334{
1335	u32 i;
1336	u32 reg;
1337	s32 status = IXGBE_ERR_EEPROM;
1338
1339	for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1340		if (ee_reg == IXGBE_NVM_POLL_READ)
1341			reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1342		else
1343			reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1344
1345		if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1346			status = 0;
1347			break;
1348		}
1349		udelay(5);
1350	}
1351	return status;
1352}
1353
1354/**
1355 *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1356 *  @hw: pointer to hardware structure
1357 *
1358 *  Prepares EEPROM for access using bit-bang method. This function should
1359 *  be called before issuing a command to the EEPROM.
1360 **/
1361static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1362{
1363	s32 status = 0;
1364	u32 eec;
1365	u32 i;
1366
1367	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1368	    != 0)
1369		status = IXGBE_ERR_SWFW_SYNC;
1370
1371	if (status == 0) {
1372		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1373
1374		/* Request EEPROM Access */
1375		eec |= IXGBE_EEC_REQ;
1376		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1377
1378		for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1379			eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1380			if (eec & IXGBE_EEC_GNT)
1381				break;
1382			udelay(5);
1383		}
1384
1385		/* Release if grant not acquired */
1386		if (!(eec & IXGBE_EEC_GNT)) {
1387			eec &= ~IXGBE_EEC_REQ;
1388			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1389			hw_dbg(hw, "Could not acquire EEPROM grant\n");
1390
1391			hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1392			status = IXGBE_ERR_EEPROM;
1393		}
1394
1395		/* Setup EEPROM for Read/Write */
1396		if (status == 0) {
1397			/* Clear CS and SK */
1398			eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1399			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1400			IXGBE_WRITE_FLUSH(hw);
1401			udelay(1);
1402		}
1403	}
1404	return status;
1405}
1406
1407/**
1408 *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
1409 *  @hw: pointer to hardware structure
1410 *
1411 *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1412 **/
1413static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1414{
1415	s32 status = IXGBE_ERR_EEPROM;
1416	u32 timeout = 2000;
1417	u32 i;
1418	u32 swsm;
1419
1420	/* Get SMBI software semaphore between device drivers first */
1421	for (i = 0; i < timeout; i++) {
1422		/*
1423		 * If the SMBI bit is 0 when we read it, then the bit will be
1424		 * set and we have the semaphore
1425		 */
1426		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1427		if (!(swsm & IXGBE_SWSM_SMBI)) {
1428			status = 0;
1429			break;
1430		}
1431		udelay(50);
1432	}
1433
1434	if (i == timeout) {
1435		hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1436			 "not granted.\n");
1437		/*
1438		 * this release is particularly important because our attempts
1439		 * above to get the semaphore may have succeeded, and if there
1440		 * was a timeout, we should unconditionally clear the semaphore
1441		 * bits to free the driver to make progress
1442		 */
1443		ixgbe_release_eeprom_semaphore(hw);
1444
1445		udelay(50);
1446		/*
1447		 * one last try
1448		 * If the SMBI bit is 0 when we read it, then the bit will be
1449		 * set and we have the semaphore
1450		 */
1451		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1452		if (!(swsm & IXGBE_SWSM_SMBI))
1453			status = 0;
1454	}
1455
1456	/* Now get the semaphore between SW/FW through the SWESMBI bit */
1457	if (status == 0) {
1458		for (i = 0; i < timeout; i++) {
1459			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1460
1461			/* Set the SW EEPROM semaphore bit to request access */
1462			swsm |= IXGBE_SWSM_SWESMBI;
1463			IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1464
1465			/*
1466			 * If we set the bit successfully then we got the
1467			 * semaphore.
1468			 */
1469			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1470			if (swsm & IXGBE_SWSM_SWESMBI)
1471				break;
1472
1473			udelay(50);
1474		}
1475
1476		/*
1477		 * Release semaphores and return error if SW EEPROM semaphore
1478		 * was not granted because we don't have access to the EEPROM
1479		 */
1480		if (i >= timeout) {
1481			hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1482				 "not granted.\n");
1483			ixgbe_release_eeprom_semaphore(hw);
1484			status = IXGBE_ERR_EEPROM;
1485		}
1486	} else {
1487		hw_dbg(hw, "Software semaphore SMBI between device drivers "
1488			 "not granted.\n");
1489	}
1490
1491	return status;
1492}
1493
1494/**
1495 *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
1496 *  @hw: pointer to hardware structure
1497 *
1498 *  This function clears hardware semaphore bits.
1499 **/
1500static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1501{
1502	u32 swsm;
1503
1504	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1505
1506	/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1507	swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1508	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1509	IXGBE_WRITE_FLUSH(hw);
1510}
1511
1512/**
1513 *  ixgbe_ready_eeprom - Polls for EEPROM ready
1514 *  @hw: pointer to hardware structure
1515 **/
1516static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1517{
1518	s32 status = 0;
1519	u16 i;
1520	u8 spi_stat_reg;
1521
1522	/*
1523	 * Read "Status Register" repeatedly until the LSB is cleared.  The
1524	 * EEPROM will signal that the command has been completed by clearing
1525	 * bit 0 of the internal status register.  If it's not cleared within
1526	 * 5 milliseconds, then error out.
1527	 */
1528	for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1529		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1530					    IXGBE_EEPROM_OPCODE_BITS);
1531		spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1532		if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1533			break;
1534
1535		udelay(5);
1536		ixgbe_standby_eeprom(hw);
1537	};
1538
1539	/*
1540	 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1541	 * devices (and only 0-5mSec on 5V devices)
1542	 */
1543	if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1544		hw_dbg(hw, "SPI EEPROM Status error\n");
1545		status = IXGBE_ERR_EEPROM;
1546	}
1547
1548	return status;
1549}
1550
1551/**
1552 *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1553 *  @hw: pointer to hardware structure
1554 **/
1555static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1556{
1557	u32 eec;
1558
1559	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1560
1561	/* Toggle CS to flush commands */
1562	eec |= IXGBE_EEC_CS;
1563	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1564	IXGBE_WRITE_FLUSH(hw);
1565	udelay(1);
1566	eec &= ~IXGBE_EEC_CS;
1567	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1568	IXGBE_WRITE_FLUSH(hw);
1569	udelay(1);
1570}
1571
1572/**
1573 *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1574 *  @hw: pointer to hardware structure
1575 *  @data: data to send to the EEPROM
1576 *  @count: number of bits to shift out
1577 **/
1578static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1579					u16 count)
1580{
1581	u32 eec;
1582	u32 mask;
1583	u32 i;
1584
1585	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1586
1587	/*
1588	 * Mask is used to shift "count" bits of "data" out to the EEPROM
1589	 * one bit at a time.  Determine the starting bit based on count
1590	 */
1591	mask = 0x01 << (count - 1);
1592
1593	for (i = 0; i < count; i++) {
1594		/*
1595		 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1596		 * "1", and then raising and then lowering the clock (the SK
1597		 * bit controls the clock input to the EEPROM).  A "0" is
1598		 * shifted out to the EEPROM by setting "DI" to "0" and then
1599		 * raising and then lowering the clock.
1600		 */
1601		if (data & mask)
1602			eec |= IXGBE_EEC_DI;
1603		else
1604			eec &= ~IXGBE_EEC_DI;
1605
1606		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1607		IXGBE_WRITE_FLUSH(hw);
1608
1609		udelay(1);
1610
1611		ixgbe_raise_eeprom_clk(hw, &eec);
1612		ixgbe_lower_eeprom_clk(hw, &eec);
1613
1614		/*
1615		 * Shift mask to signify next bit of data to shift in to the
1616		 * EEPROM
1617		 */
1618		mask = mask >> 1;
1619	};
1620
1621	/* We leave the "DI" bit set to "0" when we leave this routine. */
1622	eec &= ~IXGBE_EEC_DI;
1623	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1624	IXGBE_WRITE_FLUSH(hw);
1625}
1626
1627/**
1628 *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1629 *  @hw: pointer to hardware structure
1630 **/
1631static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1632{
1633	u32 eec;
1634	u32 i;
1635	u16 data = 0;
1636
1637	/*
1638	 * In order to read a register from the EEPROM, we need to shift
1639	 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1640	 * the clock input to the EEPROM (setting the SK bit), and then reading
1641	 * the value of the "DO" bit.  During this "shifting in" process the
1642	 * "DI" bit should always be clear.
1643	 */
1644	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1645
1646	eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1647
1648	for (i = 0; i < count; i++) {
1649		data = data << 1;
1650		ixgbe_raise_eeprom_clk(hw, &eec);
1651
1652		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1653
1654		eec &= ~(IXGBE_EEC_DI);
1655		if (eec & IXGBE_EEC_DO)
1656			data |= 1;
1657
1658		ixgbe_lower_eeprom_clk(hw, &eec);
1659	}
1660
1661	return data;
1662}
1663
1664/**
1665 *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1666 *  @hw: pointer to hardware structure
1667 *  @eec: EEC register's current value
1668 **/
1669static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1670{
1671	/*
1672	 * Raise the clock input to the EEPROM
1673	 * (setting the SK bit), then delay
1674	 */
1675	*eec = *eec | IXGBE_EEC_SK;
1676	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1677	IXGBE_WRITE_FLUSH(hw);
1678	udelay(1);
1679}
1680
1681/**
1682 *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1683 *  @hw: pointer to hardware structure
1684 *  @eecd: EECD's current value
1685 **/
1686static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1687{
1688	/*
1689	 * Lower the clock input to the EEPROM (clearing the SK bit), then
1690	 * delay
1691	 */
1692	*eec = *eec & ~IXGBE_EEC_SK;
1693	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1694	IXGBE_WRITE_FLUSH(hw);
1695	udelay(1);
1696}
1697
1698/**
1699 *  ixgbe_release_eeprom - Release EEPROM, release semaphores
1700 *  @hw: pointer to hardware structure
1701 **/
1702static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1703{
1704	u32 eec;
1705
1706	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1707
1708	eec |= IXGBE_EEC_CS;  /* Pull CS high */
1709	eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1710
1711	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1712	IXGBE_WRITE_FLUSH(hw);
1713
1714	udelay(1);
1715
1716	/* Stop requesting EEPROM access */
1717	eec &= ~IXGBE_EEC_REQ;
1718	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1719
1720	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1721
1722	/* Delay before attempt to obtain semaphore again to allow FW access */
1723	msleep(hw->eeprom.semaphore_delay);
1724}
1725
1726/**
1727 *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1728 *  @hw: pointer to hardware structure
1729 **/
1730u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1731{
1732	u16 i;
1733	u16 j;
1734	u16 checksum = 0;
1735	u16 length = 0;
1736	u16 pointer = 0;
1737	u16 word = 0;
1738
1739	/* Include 0x0-0x3F in the checksum */
1740	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1741		if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1742			hw_dbg(hw, "EEPROM read failed\n");
1743			break;
1744		}
1745		checksum += word;
1746	}
1747
1748	/* Include all data from pointers except for the fw pointer */
1749	for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1750		hw->eeprom.ops.read(hw, i, &pointer);
1751
1752		/* Make sure the pointer seems valid */
1753		if (pointer != 0xFFFF && pointer != 0) {
1754			hw->eeprom.ops.read(hw, pointer, &length);
1755
1756			if (length != 0xFFFF && length != 0) {
1757				for (j = pointer+1; j <= pointer+length; j++) {
1758					hw->eeprom.ops.read(hw, j, &word);
1759					checksum += word;
1760				}
1761			}
1762		}
1763	}
1764
1765	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1766
1767	return checksum;
1768}
1769
1770/**
1771 *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1772 *  @hw: pointer to hardware structure
1773 *  @checksum_val: calculated checksum
1774 *
1775 *  Performs checksum calculation and validates the EEPROM checksum.  If the
1776 *  caller does not need checksum_val, the value can be NULL.
1777 **/
1778s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1779					   u16 *checksum_val)
1780{
1781	s32 status;
1782	u16 checksum;
1783	u16 read_checksum = 0;
1784
1785	/*
1786	 * Read the first word from the EEPROM. If this times out or fails, do
1787	 * not continue or we could be in for a very long wait while every
1788	 * EEPROM read fails
1789	 */
1790	status = hw->eeprom.ops.read(hw, 0, &checksum);
1791
1792	if (status == 0) {
1793		checksum = hw->eeprom.ops.calc_checksum(hw);
1794
1795		hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1796
1797		/*
1798		 * Verify read checksum from EEPROM is the same as
1799		 * calculated checksum
1800		 */
1801		if (read_checksum != checksum)
1802			status = IXGBE_ERR_EEPROM_CHECKSUM;
1803
1804		/* If the user cares, return the calculated checksum */
1805		if (checksum_val)
1806			*checksum_val = checksum;
1807	} else {
1808		hw_dbg(hw, "EEPROM read failed\n");
1809	}
1810
1811	return status;
1812}
1813
1814/**
1815 *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1816 *  @hw: pointer to hardware structure
1817 **/
1818s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1819{
1820	s32 status;
1821	u16 checksum;
1822
1823	/*
1824	 * Read the first word from the EEPROM. If this times out or fails, do
1825	 * not continue or we could be in for a very long wait while every
1826	 * EEPROM read fails
1827	 */
1828	status = hw->eeprom.ops.read(hw, 0, &checksum);
1829
1830	if (status == 0) {
1831		checksum = hw->eeprom.ops.calc_checksum(hw);
1832		status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1833					      checksum);
1834	} else {
1835		hw_dbg(hw, "EEPROM read failed\n");
1836	}
1837
1838	return status;
1839}
1840
1841/**
1842 *  ixgbe_validate_mac_addr - Validate MAC address
1843 *  @mac_addr: pointer to MAC address.
1844 *
1845 *  Tests a MAC address to ensure it is a valid Individual Address
1846 **/
1847s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1848{
1849	s32 status = 0;
1850
1851	/* Make sure it is not a multicast address */
1852	if (IXGBE_IS_MULTICAST(mac_addr)) {
1853		hw_dbg(hw, "MAC address is multicast\n");
1854		status = IXGBE_ERR_INVALID_MAC_ADDR;
1855	/* Not a broadcast address */
1856	} else if (IXGBE_IS_BROADCAST(mac_addr)) {
1857		hw_dbg(hw, "MAC address is broadcast\n");
1858		status = IXGBE_ERR_INVALID_MAC_ADDR;
1859	/* Reject the zero address */
1860	} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1861		   mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1862		hw_dbg(hw, "MAC address is all zeros\n");
1863		status = IXGBE_ERR_INVALID_MAC_ADDR;
1864	}
1865	return status;
1866}
1867
1868/**
1869 *  ixgbe_set_rar_generic - Set Rx address register
1870 *  @hw: pointer to hardware structure
1871 *  @index: Receive address register to write
1872 *  @addr: Address to put into receive address register
1873 *  @vmdq: VMDq "set" or "pool" index
1874 *  @enable_addr: set flag that address is active
1875 *
1876 *  Puts an ethernet address into a receive address register.
1877 **/
1878s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1879			  u32 enable_addr)
1880{
1881	u32 rar_low, rar_high;
1882	u32 rar_entries = hw->mac.num_rar_entries;
1883
1884	/* Make sure we are using a valid rar index range */
1885	if (index >= rar_entries) {
1886		hw_dbg(hw, "RAR index %d is out of range.\n", index);
1887		return IXGBE_ERR_INVALID_ARGUMENT;
1888	}
1889
1890	/* setup VMDq pool selection before this RAR gets enabled */
1891	hw->mac.ops.set_vmdq(hw, index, vmdq);
1892
1893	/*
1894	 * HW expects these in little endian so we reverse the byte
1895	 * order from network order (big endian) to little endian
1896	 */
1897	rar_low = ((u32)addr[0] |
1898		   ((u32)addr[1] << 8) |
1899		   ((u32)addr[2] << 16) |
1900		   ((u32)addr[3] << 24));
1901	/*
1902	 * Some parts put the VMDq setting in the extra RAH bits,
1903	 * so save everything except the lower 16 bits that hold part
1904	 * of the address and the address valid bit.
1905	 */
1906	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1907	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1908	rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1909
1910	if (enable_addr != 0)
1911		rar_high |= IXGBE_RAH_AV;
1912
1913	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1914	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1915
1916	return 0;
1917}
1918
1919/**
1920 *  ixgbe_clear_rar_generic - Remove Rx address register
1921 *  @hw: pointer to hardware structure
1922 *  @index: Receive address register to write
1923 *
1924 *  Clears an ethernet address from a receive address register.
1925 **/
1926s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1927{
1928	u32 rar_high;
1929	u32 rar_entries = hw->mac.num_rar_entries;
1930
1931	/* Make sure we are using a valid rar index range */
1932	if (index >= rar_entries) {
1933		hw_dbg(hw, "RAR index %d is out of range.\n", index);
1934		return IXGBE_ERR_INVALID_ARGUMENT;
1935	}
1936
1937	/*
1938	 * Some parts put the VMDq setting in the extra RAH bits,
1939	 * so save everything except the lower 16 bits that hold part
1940	 * of the address and the address valid bit.
1941	 */
1942	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1943	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1944
1945	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1946	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1947
1948	/* clear VMDq pool/queue selection for this RAR */
1949	hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1950
1951	return 0;
1952}
1953
1954/**
1955 *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1956 *  @hw: pointer to hardware structure
1957 *
1958 *  Places the MAC address in receive address register 0 and clears the rest
1959 *  of the receive address registers. Clears the multicast table. Assumes
1960 *  the receiver is in reset when the routine is called.
1961 **/
1962s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1963{
1964	u32 i;
1965	u32 rar_entries = hw->mac.num_rar_entries;
1966
1967	/*
1968	 * If the current mac address is valid, assume it is a software override
1969	 * to the permanent address.
1970	 * Otherwise, use the permanent address from the eeprom.
1971	 */
1972	if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1973	    IXGBE_ERR_INVALID_MAC_ADDR) {
1974		/* Get the MAC address from the RAR0 for later reference */
1975		hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1976
1977		hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1978			  hw->mac.addr[0], hw->mac.addr[1],
1979			  hw->mac.addr[2]);
1980		hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1981			  hw->mac.addr[4], hw->mac.addr[5]);
1982	} else {
1983		/* Setup the receive address. */
1984		hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1985		hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1986			  hw->mac.addr[0], hw->mac.addr[1],
1987			  hw->mac.addr[2]);
1988		hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1989			  hw->mac.addr[4], hw->mac.addr[5]);
1990
1991		hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1992
1993		/* clear VMDq pool/queue selection for RAR 0 */
1994		hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1995	}
1996	hw->addr_ctrl.overflow_promisc = 0;
1997
1998	hw->addr_ctrl.rar_used_count = 1;
1999
2000	/* Zero out the other receive addresses. */
2001	hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
2002	for (i = 1; i < rar_entries; i++) {
2003		IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2004		IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2005	}
2006
2007	/* Clear the MTA */
2008	hw->addr_ctrl.mta_in_use = 0;
2009	IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2010
2011	hw_dbg(hw, " Clearing MTA\n");
2012	for (i = 0; i < hw->mac.mcft_size; i++)
2013		IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2014
2015	ixgbe_init_uta_tables(hw);
2016
2017	return 0;
2018}
2019
2020/**
2021 *  ixgbe_add_uc_addr - Adds a secondary unicast address.
2022 *  @hw: pointer to hardware structure
2023 *  @addr: new address
2024 *
2025 *  Adds it to unused receive address register or goes into promiscuous mode.
2026 **/
2027void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2028{
2029	u32 rar_entries = hw->mac.num_rar_entries;
2030	u32 rar;
2031
2032	hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2033		  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2034
2035	/*
2036	 * Place this address in the RAR if there is room,
2037	 * else put the controller into promiscuous mode
2038	 */
2039	if (hw->addr_ctrl.rar_used_count < rar_entries) {
2040		rar = hw->addr_ctrl.rar_used_count;
2041		hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2042		hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
2043		hw->addr_ctrl.rar_used_count++;
2044	} else {
2045		hw->addr_ctrl.overflow_promisc++;
2046	}
2047
2048	hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
2049}
2050
2051/**
2052 *  ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2053 *  @hw: pointer to hardware structure
2054 *  @addr_list: the list of new addresses
2055 *  @addr_count: number of addresses
2056 *  @next: iterator function to walk the address list
2057 *
2058 *  The given list replaces any existing list.  Clears the secondary addrs from
2059 *  receive address registers.  Uses unused receive address registers for the
2060 *  first secondary addresses, and falls back to promiscuous mode as needed.
2061 *
2062 *  Drivers using secondary unicast addresses must set user_set_promisc when
2063 *  manually putting the device into promiscuous mode.
2064 **/
2065s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2066				      u32 addr_count, ixgbe_mc_addr_itr next)
2067{
2068	u8 *addr;
2069	u32 i;
2070	u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2071	u32 uc_addr_in_use;
2072	u32 fctrl;
2073	u32 vmdq;
2074
2075	/*
2076	 * Clear accounting of old secondary address list,
2077	 * don't count RAR[0]
2078	 */
2079	uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2080	hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2081	hw->addr_ctrl.overflow_promisc = 0;
2082
2083	/* Zero out the other receive addresses */
2084	hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2085	for (i = 0; i < uc_addr_in_use; i++) {
2086		IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2087		IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2088	}
2089
2090	/* Add the new addresses */
2091	for (i = 0; i < addr_count; i++) {
2092		hw_dbg(hw, " Adding the secondary addresses:\n");
2093		addr = next(hw, &addr_list, &vmdq);
2094		ixgbe_add_uc_addr(hw, addr, vmdq);
2095	}
2096
2097	if (hw->addr_ctrl.overflow_promisc) {
2098		/* enable promisc if not already in overflow or set by user */
2099		if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2100			hw_dbg(hw, " Entering address overflow promisc mode\n");
2101			fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2102			fctrl |= IXGBE_FCTRL_UPE;
2103			IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2104		}
2105	} else {
2106		/* only disable if set by overflow, not by user */
2107		if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2108			hw_dbg(hw, " Leaving address overflow promisc mode\n");
2109			fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2110			fctrl &= ~IXGBE_FCTRL_UPE;
2111			IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2112		}
2113	}
2114
2115	hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2116	return 0;
2117}
2118
2119/**
2120 *  ixgbe_mta_vector - Determines bit-vector in multicast table to set
2121 *  @hw: pointer to hardware structure
2122 *  @mc_addr: the multicast address
2123 *
2124 *  Extracts the 12 bits, from a multicast address, to determine which
2125 *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
2126 *  incoming rx multicast addresses, to determine the bit-vector to check in
2127 *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2128 *  by the MO field of the MCSTCTRL. The MO field is set during initialization
2129 *  to mc_filter_type.
2130 **/
2131static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2132{
2133	u32 vector = 0;
2134
2135	switch (hw->mac.mc_filter_type) {
2136	case 0:   /* use bits [47:36] of the address */
2137		vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2138		break;
2139	case 1:   /* use bits [46:35] of the address */
2140		vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2141		break;
2142	case 2:   /* use bits [45:34] of the address */
2143		vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2144		break;
2145	case 3:   /* use bits [43:32] of the address */
2146		vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2147		break;
2148	default:  /* Invalid mc_filter_type */
2149		hw_dbg(hw, "MC filter type param set incorrectly\n");
2150		break;
2151	}
2152
2153	/* vector can only be 12-bits or boundary will be exceeded */
2154	vector &= 0xFFF;
2155	return vector;
2156}
2157
2158/**
2159 *  ixgbe_set_mta - Set bit-vector in multicast table
2160 *  @hw: pointer to hardware structure
2161 *  @hash_value: Multicast address hash value
2162 *
2163 *  Sets the bit-vector in the multicast table.
2164 **/
2165void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2166{
2167	u32 vector;
2168	u32 vector_bit;
2169	u32 vector_reg;
2170
2171	hw->addr_ctrl.mta_in_use++;
2172
2173	vector = ixgbe_mta_vector(hw, mc_addr);
2174	hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2175
2176	/*
2177	 * The MTA is a register array of 128 32-bit registers. It is treated
2178	 * like an array of 4096 bits.  We want to set bit
2179	 * BitArray[vector_value]. So we figure out what register the bit is
2180	 * in, read it, OR in the new bit, then write back the new value.  The
2181	 * register is determined by the upper 7 bits of the vector value and
2182	 * the bit within that register are determined by the lower 5 bits of
2183	 * the value.
2184	 */
2185	vector_reg = (vector >> 5) & 0x7F;
2186	vector_bit = vector & 0x1F;
2187	hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2188}
2189
2190/**
2191 *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2192 *  @hw: pointer to hardware structure
2193 *  @mc_addr_list: the list of new multicast addresses
2194 *  @mc_addr_count: number of addresses
2195 *  @next: iterator function to walk the multicast address list
2196 *  @clear: flag, when set clears the table beforehand
2197 *
2198 *  When the clear flag is set, the given list replaces any existing list.
2199 *  Hashes the given addresses into the multicast table.
2200 **/
2201s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2202				      u32 mc_addr_count, ixgbe_mc_addr_itr next,
2203				      bool clear)
2204{
2205	u32 i;
2206	u32 vmdq;
2207
2208	/*
2209	 * Set the new number of MC addresses that we are being requested to
2210	 * use.
2211	 */
2212	hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2213	hw->addr_ctrl.mta_in_use = 0;
2214
2215	/* Clear mta_shadow */
2216	if (clear) {
2217		hw_dbg(hw, " Clearing MTA\n");
2218		memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2219	}
2220
2221	/* Update mta_shadow */
2222	for (i = 0; i < mc_addr_count; i++) {
2223		hw_dbg(hw, " Adding the multicast addresses:\n");
2224		ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2225	}
2226
2227	/* Enable mta */
2228	for (i = 0; i < hw->mac.mcft_size; i++)
2229		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2230				      hw->mac.mta_shadow[i]);
2231
2232	if (hw->addr_ctrl.mta_in_use > 0)
2233		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2234				IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2235
2236	hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2237	return 0;
2238}
2239
2240/**
2241 *  ixgbe_enable_mc_generic - Enable multicast address in RAR
2242 *  @hw: pointer to hardware structure
2243 *
2244 *  Enables multicast address in RAR and the use of the multicast hash table.
2245 **/
2246s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2247{
2248	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2249
2250	if (a->mta_in_use > 0)
2251		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2252				hw->mac.mc_filter_type);
2253
2254	return 0;
2255}
2256
2257/**
2258 *  ixgbe_disable_mc_generic - Disable multicast address in RAR
2259 *  @hw: pointer to hardware structure
2260 *
2261 *  Disables multicast address in RAR and the use of the multicast hash table.
2262 **/
2263s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2264{
2265	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2266
2267	if (a->mta_in_use > 0)
2268		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2269
2270	return 0;
2271}
2272
2273/**
2274 *  ixgbe_fc_enable_generic - Enable flow control
2275 *  @hw: pointer to hardware structure
2276 *
2277 *  Enable flow control according to the current settings.
2278 **/
2279s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2280{
2281	s32 ret_val = 0;
2282	u32 mflcn_reg, fccfg_reg;
2283	u32 reg;
2284	u32 fcrtl, fcrth;
2285	int i;
2286
2287	/* Validate the water mark configuration */
2288	if (!hw->fc.pause_time) {
2289		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2290		goto out;
2291	}
2292
2293	/* Low water mark of zero causes XOFF floods */
2294	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2295		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2296		    hw->fc.high_water[i]) {
2297			if (!hw->fc.low_water[i] ||
2298			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2299				hw_dbg(hw, "Invalid water mark configuration\n");
2300				ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2301				goto out;
2302			}
2303		}
2304	}
2305
2306	/* Negotiate the fc mode to use */
2307	ixgbe_fc_autoneg(hw);
2308
2309	/* Disable any previous flow control settings */
2310	mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2311	mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2312
2313	fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2314	fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2315
2316	/*
2317	 * The possible values of fc.current_mode are:
2318	 * 0: Flow control is completely disabled
2319	 * 1: Rx flow control is enabled (we can receive pause frames,
2320	 *    but not send pause frames).
2321	 * 2: Tx flow control is enabled (we can send pause frames but
2322	 *    we do not support receiving pause frames).
2323	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2324	 * other: Invalid.
2325	 */
2326	switch (hw->fc.current_mode) {
2327	case ixgbe_fc_none:
2328		/*
2329		 * Flow control is disabled by software override or autoneg.
2330		 * The code below will actually disable it in the HW.
2331		 */
2332		break;
2333	case ixgbe_fc_rx_pause:
2334		/*
2335		 * Rx Flow control is enabled and Tx Flow control is
2336		 * disabled by software override. Since there really
2337		 * isn't a way to advertise that we are capable of RX
2338		 * Pause ONLY, we will advertise that we support both
2339		 * symmetric and asymmetric Rx PAUSE.  Later, we will
2340		 * disable the adapter's ability to send PAUSE frames.
2341		 */
2342		mflcn_reg |= IXGBE_MFLCN_RFCE;
2343		break;
2344	case ixgbe_fc_tx_pause:
2345		/*
2346		 * Tx Flow control is enabled, and Rx Flow control is
2347		 * disabled by software override.
2348		 */
2349		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2350		break;
2351	case ixgbe_fc_full:
2352		/* Flow control (both Rx and Tx) is enabled by SW override. */
2353		mflcn_reg |= IXGBE_MFLCN_RFCE;
2354		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2355		break;
2356	default:
2357		hw_dbg(hw, "Flow control param set incorrectly\n");
2358		ret_val = IXGBE_ERR_CONFIG;
2359		goto out;
2360		break;
2361	}
2362
2363	/* Set 802.3x based flow control settings. */
2364	mflcn_reg |= IXGBE_MFLCN_DPF;
2365	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2366	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2367
2368
2369	/* Set up and enable Rx high/low water mark thresholds, enable XON. */
2370	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2371		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2372		    hw->fc.high_water[i]) {
2373			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2374			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2375			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2376		} else {
2377			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2378			/*
2379			 * In order to prevent Tx hangs when the internal Tx
2380			 * switch is enabled we must set the high water mark
2381			 * to the maximum FCRTH value.  This allows the Tx
2382			 * switch to function even under heavy Rx workloads.
2383			 */
2384			fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2385		}
2386
2387		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2388	}
2389
2390	/* Configure pause time (2 TCs per register) */
2391	reg = hw->fc.pause_time * 0x00010001;
2392	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2393		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2394
2395	/* Configure flow control refresh threshold value */
2396	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2397
2398out:
2399	return ret_val;
2400}
2401
2402/**
2403 *  ixgbe_negotiate_fc - Negotiate flow control
2404 *  @hw: pointer to hardware structure
2405 *  @adv_reg: flow control advertised settings
2406 *  @lp_reg: link partner's flow control settings
2407 *  @adv_sym: symmetric pause bit in advertisement
2408 *  @adv_asm: asymmetric pause bit in advertisement
2409 *  @lp_sym: symmetric pause bit in link partner advertisement
2410 *  @lp_asm: asymmetric pause bit in link partner advertisement
2411 *
2412 *  Find the intersection between advertised settings and link partner's
2413 *  advertised settings
2414 **/
2415static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2416			      u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2417{
2418	if ((!(adv_reg)) ||  (!(lp_reg)))
2419		return IXGBE_ERR_FC_NOT_NEGOTIATED;
2420
2421	if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2422		/*
2423		 * Now we need to check if the user selected Rx ONLY
2424		 * of pause frames.  In this case, we had to advertise
2425		 * FULL flow control because we could not advertise RX
2426		 * ONLY. Hence, we must now check to see if we need to
2427		 * turn OFF the TRANSMISSION of PAUSE frames.
2428		 */
2429		if (hw->fc.requested_mode == ixgbe_fc_full) {
2430			hw->fc.current_mode = ixgbe_fc_full;
2431			hw_dbg(hw, "Flow Control = FULL.\n");
2432		} else {
2433			hw->fc.current_mode = ixgbe_fc_rx_pause;
2434			hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2435		}
2436	} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2437		   (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2438		hw->fc.current_mode = ixgbe_fc_tx_pause;
2439		hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2440	} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2441		   !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2442		hw->fc.current_mode = ixgbe_fc_rx_pause;
2443		hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2444	} else {
2445		hw->fc.current_mode = ixgbe_fc_none;
2446		hw_dbg(hw, "Flow Control = NONE.\n");
2447	}
2448	return 0;
2449}
2450
2451/**
2452 *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2453 *  @hw: pointer to hardware structure
2454 *
2455 *  Enable flow control according on 1 gig fiber.
2456 **/
2457static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2458{
2459	u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2460	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2461
2462	/*
2463	 * On multispeed fiber at 1g, bail out if
2464	 * - link is up but AN did not complete, or if
2465	 * - link is up and AN completed but timed out
2466	 */
2467
2468	linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2469	if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2470	    (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2471		goto out;
2472
2473	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2474	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2475
2476	ret_val =  ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2477				      pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2478				      IXGBE_PCS1GANA_ASM_PAUSE,
2479				      IXGBE_PCS1GANA_SYM_PAUSE,
2480				      IXGBE_PCS1GANA_ASM_PAUSE);
2481
2482out:
2483	return ret_val;
2484}
2485
2486/**
2487 *  ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2488 *  @hw: pointer to hardware structure
2489 *
2490 *  Enable flow control according to IEEE clause 37.
2491 **/
2492static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2493{
2494	u32 links2, anlp1_reg, autoc_reg, links;
2495	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2496
2497	/*
2498	 * On backplane, bail out if
2499	 * - backplane autoneg was not completed, or if
2500	 * - we are 82599 and link partner is not AN enabled
2501	 */
2502	links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2503	if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2504		goto out;
2505
2506	if (hw->mac.type == ixgbe_mac_82599EB) {
2507		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2508		if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2509			goto out;
2510	}
2511	/*
2512	 * Read the 10g AN autoc and LP ability registers and resolve
2513	 * local flow control settings accordingly
2514	 */
2515	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2516	anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2517
2518	ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2519		anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2520		IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2521
2522out:
2523	return ret_val;
2524}
2525
2526/**
2527 *  ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2528 *  @hw: pointer to hardware structure
2529 *
2530 *  Enable flow control according to IEEE clause 37.
2531 **/
2532static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2533{
2534	u16 technology_ability_reg = 0;
2535	u16 lp_technology_ability_reg = 0;
2536
2537	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2538			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2539			     &technology_ability_reg);
2540	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2541			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2542			     &lp_technology_ability_reg);
2543
2544	return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2545				  (u32)lp_technology_ability_reg,
2546				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2547				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2548}
2549
2550/**
2551 *  ixgbe_fc_autoneg - Configure flow control
2552 *  @hw: pointer to hardware structure
2553 *
2554 *  Compares our advertised flow control capabilities to those advertised by
2555 *  our link partner, and determines the proper flow control mode to use.
2556 **/
2557void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2558{
2559	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2560	ixgbe_link_speed speed;
2561	bool link_up;
2562
2563	/*
2564	 * AN should have completed when the cable was plugged in.
2565	 * Look for reasons to bail out.  Bail out if:
2566	 * - FC autoneg is disabled, or if
2567	 * - link is not up.
2568	 */
2569	if (hw->fc.disable_fc_autoneg)
2570		goto out;
2571
2572	hw->mac.ops.check_link(hw, &speed, &link_up, false);
2573	if (!link_up)
2574		goto out;
2575
2576	switch (hw->phy.media_type) {
2577	/* Autoneg flow control on fiber adapters */
2578	case ixgbe_media_type_fiber:
2579		if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2580			ret_val = ixgbe_fc_autoneg_fiber(hw);
2581		break;
2582
2583	/* Autoneg flow control on backplane adapters */
2584	case ixgbe_media_type_backplane:
2585		ret_val = ixgbe_fc_autoneg_backplane(hw);
2586		break;
2587
2588	/* Autoneg flow control on copper adapters */
2589	case ixgbe_media_type_copper:
2590		if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2591			ret_val = ixgbe_fc_autoneg_copper(hw);
2592		break;
2593
2594	default:
2595		break;
2596	}
2597
2598out:
2599	if (ret_val == 0) {
2600		hw->fc.fc_was_autonegged = true;
2601	} else {
2602		hw->fc.fc_was_autonegged = false;
2603		hw->fc.current_mode = hw->fc.requested_mode;
2604	}
2605}
2606
2607/**
2608 *  ixgbe_disable_pcie_master - Disable PCI-express master access
2609 *  @hw: pointer to hardware structure
2610 *
2611 *  Disables PCI-Express master access and verifies there are no pending
2612 *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2613 *  bit hasn't caused the master requests to be disabled, else 0
2614 *  is returned signifying master requests disabled.
2615 **/
2616s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2617{
2618	s32 status = 0;
2619	u32 i;
2620
2621	/* Always set this bit to ensure any future transactions are blocked */
2622	IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2623
2624	/* Exit if master requets are blocked */
2625	if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2626		goto out;
2627
2628	/* Poll for master request bit to clear */
2629	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2630		udelay(100);
2631		if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2632			goto out;
2633	}
2634
2635	/*
2636	 * Two consecutive resets are required via CTRL.RST per datasheet
2637	 * 5.2.5.3.2 Master Disable.  We set a flag to inform the reset routine
2638	 * of this need.  The first reset prevents new master requests from
2639	 * being issued by our device.  We then must wait 1usec or more for any
2640	 * remaining completions from the PCIe bus to trickle in, and then reset
2641	 * again to clear out any effects they may have had on our device.
2642	 */
2643	hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2644	hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2645
2646	/*
2647	 * Before proceeding, make sure that the PCIe block does not have
2648	 * transactions pending.
2649	 */
2650	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2651		udelay(100);
2652		if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2653		    IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2654			goto out;
2655	}
2656
2657	hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2658	status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2659
2660out:
2661	return status;
2662}
2663
2664/**
2665 *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2666 *  @hw: pointer to hardware structure
2667 *  @mask: Mask to specify which semaphore to acquire
2668 *
2669 *  Acquires the SWFW semaphore through the GSSR register for the specified
2670 *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2671 **/
2672s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2673{
2674	u32 gssr;
2675	u32 swmask = mask;
2676	u32 fwmask = mask << 5;
2677	s32 timeout = 200;
2678
2679	while (timeout) {
2680		/*
2681		 * SW EEPROM semaphore bit is used for access to all
2682		 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2683		 */
2684		if (ixgbe_get_eeprom_semaphore(hw))
2685			return IXGBE_ERR_SWFW_SYNC;
2686
2687		gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2688		if (!(gssr & (fwmask | swmask)))
2689			break;
2690
2691		/*
2692		 * Firmware currently using resource (fwmask) or other software
2693		 * thread currently using resource (swmask)
2694		 */
2695		ixgbe_release_eeprom_semaphore(hw);
2696		msleep(5);
2697		timeout--;
2698	}
2699
2700	if (!timeout) {
2701		hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2702		return IXGBE_ERR_SWFW_SYNC;
2703	}
2704
2705	gssr |= swmask;
2706	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2707
2708	ixgbe_release_eeprom_semaphore(hw);
2709	return 0;
2710}
2711
2712/**
2713 *  ixgbe_release_swfw_sync - Release SWFW semaphore
2714 *  @hw: pointer to hardware structure
2715 *  @mask: Mask to specify which semaphore to release
2716 *
2717 *  Releases the SWFW semaphore through the GSSR register for the specified
2718 *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2719 **/
2720void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2721{
2722	u32 gssr;
2723	u32 swmask = mask;
2724
2725	ixgbe_get_eeprom_semaphore(hw);
2726
2727	gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2728	gssr &= ~swmask;
2729	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2730
2731	ixgbe_release_eeprom_semaphore(hw);
2732}
2733
2734/**
2735 *  ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2736 *  @hw: pointer to hardware structure
2737 *
2738 *  Stops the receive data path and waits for the HW to internally empty
2739 *  the Rx security block
2740 **/
2741s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2742{
2743#define IXGBE_MAX_SECRX_POLL 40
2744
2745	int i;
2746	int secrxreg;
2747
2748	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2749	secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2750	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2751	for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2752		secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2753		if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2754			break;
2755		else
2756			/* Use interrupt-safe sleep just in case */
2757			udelay(1000);
2758	}
2759
2760	/* For informational purposes only */
2761	if (i >= IXGBE_MAX_SECRX_POLL)
2762		hw_dbg(hw, "Rx unit being enabled before security "
2763			 "path fully disabled.  Continuing with init.\n");
2764
2765	return 0;
2766}
2767
2768/**
2769 *  ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2770 *  @hw: pointer to hardware structure
2771 *
2772 *  Enables the receive data path.
2773 **/
2774s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2775{
2776	int secrxreg;
2777
2778	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2779	secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2780	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2781	IXGBE_WRITE_FLUSH(hw);
2782
2783	return 0;
2784}
2785
2786/**
2787 *  ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2788 *  @hw: pointer to hardware structure
2789 *  @regval: register value to write to RXCTRL
2790 *
2791 *  Enables the Rx DMA unit
2792 **/
2793s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2794{
2795	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2796
2797	return 0;
2798}
2799
2800/**
2801 *  ixgbe_blink_led_start_generic - Blink LED based on index.
2802 *  @hw: pointer to hardware structure
2803 *  @index: led number to blink
2804 **/
2805s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2806{
2807	ixgbe_link_speed speed = 0;
2808	bool link_up = 0;
2809	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2810	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2811
2812	/*
2813	 * Link must be up to auto-blink the LEDs;
2814	 * Force it if link is down.
2815	 */
2816	hw->mac.ops.check_link(hw, &speed, &link_up, false);
2817
2818	if (!link_up) {
2819		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2820		autoc_reg |= IXGBE_AUTOC_FLU;
2821		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2822		IXGBE_WRITE_FLUSH(hw);
2823		msleep(10);
2824	}
2825
2826	led_reg &= ~IXGBE_LED_MODE_MASK(index);
2827	led_reg |= IXGBE_LED_BLINK(index);
2828	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2829	IXGBE_WRITE_FLUSH(hw);
2830
2831	return 0;
2832}
2833
2834/**
2835 *  ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2836 *  @hw: pointer to hardware structure
2837 *  @index: led number to stop blinking
2838 **/
2839s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2840{
2841	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2842	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2843
2844	autoc_reg &= ~IXGBE_AUTOC_FLU;
2845	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2846	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2847
2848	led_reg &= ~IXGBE_LED_MODE_MASK(index);
2849	led_reg &= ~IXGBE_LED_BLINK(index);
2850	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2851	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2852	IXGBE_WRITE_FLUSH(hw);
2853
2854	return 0;
2855}
2856
2857/**
2858 *  ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2859 *  @hw: pointer to hardware structure
2860 *  @san_mac_offset: SAN MAC address offset
2861 *
2862 *  This function will read the EEPROM location for the SAN MAC address
2863 *  pointer, and returns the value at that location.  This is used in both
2864 *  get and set mac_addr routines.
2865 **/
2866static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2867					 u16 *san_mac_offset)
2868{
2869	/*
2870	 * First read the EEPROM pointer to see if the MAC addresses are
2871	 * available.
2872	 */
2873	hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2874
2875	return 0;
2876}
2877
2878/**
2879 *  ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2880 *  @hw: pointer to hardware structure
2881 *  @san_mac_addr: SAN MAC address
2882 *
2883 *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
2884 *  per-port, so set_lan_id() must be called before reading the addresses.
2885 *  set_lan_id() is called by identify_sfp(), but this cannot be relied
2886 *  upon for non-SFP connections, so we must call it here.
2887 **/
2888s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2889{
2890	u16 san_mac_data, san_mac_offset;
2891	u8 i;
2892
2893	/*
2894	 * First read the EEPROM pointer to see if the MAC addresses are
2895	 * available.  If they're not, no point in calling set_lan_id() here.
2896	 */
2897	ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2898
2899	if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2900		/*
2901		 * No addresses available in this EEPROM.  It's not an
2902		 * error though, so just wipe the local address and return.
2903		 */
2904		for (i = 0; i < 6; i++)
2905			san_mac_addr[i] = 0xFF;
2906
2907		goto san_mac_addr_out;
2908	}
2909
2910	/* make sure we know which port we need to program */
2911	hw->mac.ops.set_lan_id(hw);
2912	/* apply the port offset to the address offset */
2913	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2914			 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2915	for (i = 0; i < 3; i++) {
2916		hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2917		san_mac_addr[i * 2] = (u8)(san_mac_data);
2918		san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2919		san_mac_offset++;
2920	}
2921
2922san_mac_addr_out:
2923	return 0;
2924}
2925
2926/**
2927 *  ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2928 *  @hw: pointer to hardware structure
2929 *  @san_mac_addr: SAN MAC address
2930 *
2931 *  Write a SAN MAC address to the EEPROM.
2932 **/
2933s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2934{
2935	s32 status = 0;
2936	u16 san_mac_data, san_mac_offset;
2937	u8 i;
2938
2939	/* Look for SAN mac address pointer.  If not defined, return */
2940	ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2941
2942	if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2943		status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2944		goto san_mac_addr_out;
2945	}
2946
2947	/* Make sure we know which port we need to write */
2948	hw->mac.ops.set_lan_id(hw);
2949	/* Apply the port offset to the address offset */
2950	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2951			 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2952
2953	for (i = 0; i < 3; i++) {
2954		san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2955		san_mac_data |= (u16)(san_mac_addr[i * 2]);
2956		hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2957		san_mac_offset++;
2958	}
2959
2960san_mac_addr_out:
2961	return status;
2962}
2963
2964/**
2965 *  ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2966 *  @hw: pointer to hardware structure
2967 *
2968 *  Read PCIe configuration space, and get the MSI-X vector count from
2969 *  the capabilities table.
2970 **/
2971u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2972{
2973	u16 msix_count = 1;
2974	u16 max_msix_count;
2975	u16 pcie_offset;
2976
2977	switch (hw->mac.type) {
2978	case ixgbe_mac_82598EB:
2979		pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2980		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2981		break;
2982	case ixgbe_mac_82599EB:
2983	case ixgbe_mac_X540:
2984		pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2985		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2986		break;
2987	default:
2988		return msix_count;
2989	}
2990
2991	msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
2992	msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2993
2994	/* MSI-X count is zero-based in HW */
2995	msix_count++;
2996
2997	if (msix_count > max_msix_count)
2998		msix_count = max_msix_count;
2999
3000	return msix_count;
3001}
3002
3003/**
3004 *  ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3005 *  @hw: pointer to hardware structure
3006 *  @addr: Address to put into receive address register
3007 *  @vmdq: VMDq pool to assign
3008 *
3009 *  Puts an ethernet address into a receive address register, or
3010 *  finds the rar that it is aleady in; adds to the pool list
3011 **/
3012s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3013{
3014	static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3015	u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3016	u32 rar;
3017	u32 rar_low, rar_high;
3018	u32 addr_low, addr_high;
3019
3020	/* swap bytes for HW little endian */
3021	addr_low  = addr[0] | (addr[1] << 8)
3022			    | (addr[2] << 16)
3023			    | (addr[3] << 24);
3024	addr_high = addr[4] | (addr[5] << 8);
3025
3026	/*
3027	 * Either find the mac_id in rar or find the first empty space.
3028	 * rar_highwater points to just after the highest currently used
3029	 * rar in order to shorten the search.  It grows when we add a new
3030	 * rar to the top.
3031	 */
3032	for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3033		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3034
3035		if (((IXGBE_RAH_AV & rar_high) == 0)
3036		    && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3037			first_empty_rar = rar;
3038		} else if ((rar_high & 0xFFFF) == addr_high) {
3039			rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3040			if (rar_low == addr_low)
3041				break;    /* found it already in the rars */
3042		}
3043	}
3044
3045	if (rar < hw->mac.rar_highwater) {
3046		/* already there so just add to the pool bits */
3047		ixgbe_set_vmdq(hw, rar, vmdq);
3048	} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3049		/* stick it into first empty RAR slot we found */
3050		rar = first_empty_rar;
3051		ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3052	} else if (rar == hw->mac.rar_highwater) {
3053		/* add it to the top of the list and inc the highwater mark */
3054		ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3055		hw->mac.rar_highwater++;
3056	} else if (rar >= hw->mac.num_rar_entries) {
3057		return IXGBE_ERR_INVALID_MAC_ADDR;
3058	}
3059
3060	/*
3061	 * If we found rar[0], make sure the default pool bit (we use pool 0)
3062	 * remains cleared to be sure default pool packets will get delivered
3063	 */
3064	if (rar == 0)
3065		ixgbe_clear_vmdq(hw, rar, 0);
3066
3067	return rar;
3068}
3069
3070/**
3071 *  ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3072 *  @hw: pointer to hardware struct
3073 *  @rar: receive address register index to disassociate
3074 *  @vmdq: VMDq pool index to remove from the rar
3075 **/
3076s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3077{
3078	u32 mpsar_lo, mpsar_hi;
3079	u32 rar_entries = hw->mac.num_rar_entries;
3080
3081	/* Make sure we are using a valid rar index range */
3082	if (rar >= rar_entries) {
3083		hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3084		return IXGBE_ERR_INVALID_ARGUMENT;
3085	}
3086
3087	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3088	mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3089
3090	if (!mpsar_lo && !mpsar_hi)
3091		goto done;
3092
3093	if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3094		if (mpsar_lo) {
3095			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3096			mpsar_lo = 0;
3097		}
3098		if (mpsar_hi) {
3099			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3100			mpsar_hi = 0;
3101		}
3102	} else if (vmdq < 32) {
3103		mpsar_lo &= ~(1 << vmdq);
3104		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3105	} else {
3106		mpsar_hi &= ~(1 << (vmdq - 32));
3107		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3108	}
3109
3110	/* was that the last pool using this rar? */
3111	if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3112		hw->mac.ops.clear_rar(hw, rar);
3113done:
3114	return 0;
3115}
3116
3117/**
3118 *  ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3119 *  @hw: pointer to hardware struct
3120 *  @rar: receive address register index to associate with a VMDq index
3121 *  @vmdq: VMDq pool index
3122 **/
3123s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3124{
3125	u32 mpsar;
3126	u32 rar_entries = hw->mac.num_rar_entries;
3127
3128	/* Make sure we are using a valid rar index range */
3129	if (rar >= rar_entries) {
3130		hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3131		return IXGBE_ERR_INVALID_ARGUMENT;
3132	}
3133
3134	if (vmdq < 32) {
3135		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3136		mpsar |= 1 << vmdq;
3137		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3138	} else {
3139		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3140		mpsar |= 1 << (vmdq - 32);
3141		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3142	}
3143	return 0;
3144}
3145
3146/**
3147 *  This function should only be involved in the IOV mode.
3148 *  In IOV mode, Default pool is next pool after the number of
3149 *  VFs advertized and not 0.
3150 *  MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3151 *
3152 *  ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3153 *  @hw: pointer to hardware struct
3154 *  @vmdq: VMDq pool index
3155 **/
3156s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3157{
3158	u32 mpsar;
3159	u32 rar = hw->mac.san_mac_rar_index;
3160
3161	if (vmdq < 32) {
3162		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3163		mpsar |= 1 << vmdq;
3164		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3165	} else {
3166		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3167		mpsar |= 1 << (vmdq - 32);
3168		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3169	}
3170
3171	return 0;
3172}
3173
3174/**
3175 *  ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3176 *  @hw: pointer to hardware structure
3177 **/
3178s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3179{
3180	int i;
3181
3182	hw_dbg(hw, " Clearing UTA\n");
3183
3184	for (i = 0; i < 128; i++)
3185		IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3186
3187	return 0;
3188}
3189
3190/**
3191 *  ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3192 *  @hw: pointer to hardware structure
3193 *  @vlan: VLAN id to write to VLAN filter
3194 *
3195 *  return the VLVF index where this VLAN id should be placed
3196 *
3197 **/
3198s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3199{
3200	u32 bits = 0;
3201	u32 first_empty_slot = 0;
3202	s32 regindex;
3203
3204	/* short cut the special case */
3205	if (vlan == 0)
3206		return 0;
3207
3208	/*
3209	  * Search for the vlan id in the VLVF entries. Save off the first empty
3210	  * slot found along the way
3211	  */
3212	for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3213		bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3214		if (!bits && !(first_empty_slot))
3215			first_empty_slot = regindex;
3216		else if ((bits & 0x0FFF) == vlan)
3217			break;
3218	}
3219
3220	/*
3221	  * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3222	  * in the VLVF. Else use the first empty VLVF register for this
3223	  * vlan id.
3224	  */
3225	if (regindex >= IXGBE_VLVF_ENTRIES) {
3226		if (first_empty_slot)
3227			regindex = first_empty_slot;
3228		else {
3229			hw_dbg(hw, "No space in VLVF.\n");
3230			regindex = IXGBE_ERR_NO_SPACE;
3231		}
3232	}
3233
3234	return regindex;
3235}
3236
3237/**
3238 *  ixgbe_set_vfta_generic - Set VLAN filter table
3239 *  @hw: pointer to hardware structure
3240 *  @vlan: VLAN id to write to VLAN filter
3241 *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
3242 *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
3243 *
3244 *  Turn on/off specified VLAN in the VLAN filter table.
3245 **/
3246s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3247			   bool vlan_on)
3248{
3249	s32 regindex;
3250	u32 bitindex;
3251	u32 vfta;
3252	u32 targetbit;
3253	s32 ret_val = 0;
3254	bool vfta_changed = false;
3255
3256	if (vlan > 4095)
3257		return IXGBE_ERR_PARAM;
3258
3259	/*
3260	 * this is a 2 part operation - first the VFTA, then the
3261	 * VLVF and VLVFB if VT Mode is set
3262	 * We don't write the VFTA until we know the VLVF part succeeded.
3263	 */
3264
3265	/* Part 1
3266	 * The VFTA is a bitstring made up of 128 32-bit registers
3267	 * that enable the particular VLAN id, much like the MTA:
3268	 *    bits[11-5]: which register
3269	 *    bits[4-0]:  which bit in the register
3270	 */
3271	regindex = (vlan >> 5) & 0x7F;
3272	bitindex = vlan & 0x1F;
3273	targetbit = (1 << bitindex);
3274	vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3275
3276	if (vlan_on) {
3277		if (!(vfta & targetbit)) {
3278			vfta |= targetbit;
3279			vfta_changed = true;
3280		}
3281	} else {
3282		if ((vfta & targetbit)) {
3283			vfta &= ~targetbit;
3284			vfta_changed = true;
3285		}
3286	}
3287
3288	/* Part 2
3289	 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3290	 */
3291	ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3292					 &vfta_changed);
3293	if (ret_val != 0)
3294		return ret_val;
3295
3296	if (vfta_changed)
3297		IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3298
3299	return 0;
3300}
3301
3302/**
3303 *  ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3304 *  @hw: pointer to hardware structure
3305 *  @vlan: VLAN id to write to VLAN filter
3306 *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
3307 *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
3308 *  @vfta_changed: pointer to boolean flag which indicates whether VFTA
3309 *                 should be changed
3310 *
3311 *  Turn on/off specified bit in VLVF table.
3312 **/
3313s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3314			    bool vlan_on, bool *vfta_changed)
3315{
3316	u32 vt;
3317
3318	if (vlan > 4095)
3319		return IXGBE_ERR_PARAM;
3320
3321	/* If VT Mode is set
3322	 *   Either vlan_on
3323	 *     make sure the vlan is in VLVF
3324	 *     set the vind bit in the matching VLVFB
3325	 *   Or !vlan_on
3326	 *     clear the pool bit and possibly the vind
3327	 */
3328	vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3329	if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3330		s32 vlvf_index;
3331		u32 bits;
3332
3333		vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3334		if (vlvf_index < 0)
3335			return vlvf_index;
3336
3337		if (vlan_on) {
3338			/* set the pool bit */
3339			if (vind < 32) {
3340				bits = IXGBE_READ_REG(hw,
3341						IXGBE_VLVFB(vlvf_index * 2));
3342				bits |= (1 << vind);
3343				IXGBE_WRITE_REG(hw,
3344						IXGBE_VLVFB(vlvf_index * 2),
3345						bits);
3346			} else {
3347				bits = IXGBE_READ_REG(hw,
3348					IXGBE_VLVFB((vlvf_index * 2) + 1));
3349				bits |= (1 << (vind - 32));
3350				IXGBE_WRITE_REG(hw,
3351					IXGBE_VLVFB((vlvf_index * 2) + 1),
3352					bits);
3353			}
3354		} else {
3355			/* clear the pool bit */
3356			if (vind < 32) {
3357				bits = IXGBE_READ_REG(hw,
3358						IXGBE_VLVFB(vlvf_index * 2));
3359				bits &= ~(1 << vind);
3360				IXGBE_WRITE_REG(hw,
3361						IXGBE_VLVFB(vlvf_index * 2),
3362						bits);
3363				bits |= IXGBE_READ_REG(hw,
3364					IXGBE_VLVFB((vlvf_index * 2) + 1));
3365			} else {
3366				bits = IXGBE_READ_REG(hw,
3367					IXGBE_VLVFB((vlvf_index * 2) + 1));
3368				bits &= ~(1 << (vind - 32));
3369				IXGBE_WRITE_REG(hw,
3370					IXGBE_VLVFB((vlvf_index * 2) + 1),
3371					bits);
3372				bits |= IXGBE_READ_REG(hw,
3373						IXGBE_VLVFB(vlvf_index * 2));
3374			}
3375		}
3376
3377		/*
3378		 * If there are still bits set in the VLVFB registers
3379		 * for the VLAN ID indicated we need to see if the
3380		 * caller is requesting that we clear the VFTA entry bit.
3381		 * If the caller has requested that we clear the VFTA
3382		 * entry bit but there are still pools/VFs using this VLAN
3383		 * ID entry then ignore the request.  We're not worried
3384		 * about the case where we're turning the VFTA VLAN ID
3385		 * entry bit on, only when requested to turn it off as
3386		 * there may be multiple pools and/or VFs using the
3387		 * VLAN ID entry.  In that case we cannot clear the
3388		 * VFTA bit until all pools/VFs using that VLAN ID have also
3389		 * been cleared.  This will be indicated by "bits" being
3390		 * zero.
3391		 */
3392		if (bits) {
3393			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3394					(IXGBE_VLVF_VIEN | vlan));
3395			if ((!vlan_on) && (vfta_changed != NULL)) {
3396				/* someone wants to clear the vfta entry
3397				 * but some pools/VFs are still using it.
3398				 * Ignore it. */
3399				*vfta_changed = false;
3400			}
3401		} else
3402			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3403	}
3404
3405	return 0;
3406}
3407
3408/**
3409 *  ixgbe_clear_vfta_generic - Clear VLAN filter table
3410 *  @hw: pointer to hardware structure
3411 *
3412 *  Clears the VLAN filer table, and the VMDq index associated with the filter
3413 **/
3414s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3415{
3416	u32 offset;
3417
3418	for (offset = 0; offset < hw->mac.vft_size; offset++)
3419		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3420
3421	for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3422		IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3423		IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3424		IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3425	}
3426
3427	return 0;
3428}
3429
3430/**
3431 *  ixgbe_check_mac_link_generic - Determine link and speed status
3432 *  @hw: pointer to hardware structure
3433 *  @speed: pointer to link speed
3434 *  @link_up: true when link is up
3435 *  @link_up_wait_to_complete: bool used to wait for link up or not
3436 *
3437 *  Reads the links register to determine if link is up and the current speed
3438 **/
3439s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3440				 bool *link_up, bool link_up_wait_to_complete)
3441{
3442	u32 links_reg, links_orig;
3443	u32 i;
3444
3445	/* clear the old state */
3446	links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3447
3448	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3449
3450	if (links_orig != links_reg) {
3451		hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3452			  links_orig, links_reg);
3453	}
3454
3455	if (link_up_wait_to_complete) {
3456		for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3457			if (links_reg & IXGBE_LINKS_UP) {
3458				*link_up = true;
3459				break;
3460			} else {
3461				*link_up = false;
3462			}
3463			msleep(100);
3464			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3465		}
3466	} else {
3467		if (links_reg & IXGBE_LINKS_UP)
3468			*link_up = true;
3469		else
3470			*link_up = false;
3471	}
3472
3473	if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3474	    IXGBE_LINKS_SPEED_10G_82599)
3475		*speed = IXGBE_LINK_SPEED_10GB_FULL;
3476	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3477		 IXGBE_LINKS_SPEED_1G_82599)
3478		*speed = IXGBE_LINK_SPEED_1GB_FULL;
3479	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3480		 IXGBE_LINKS_SPEED_100_82599)
3481		*speed = IXGBE_LINK_SPEED_100_FULL;
3482	else
3483		*speed = IXGBE_LINK_SPEED_UNKNOWN;
3484
3485	return 0;
3486}
3487
3488/**
3489 *  ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3490 *  the EEPROM
3491 *  @hw: pointer to hardware structure
3492 *  @wwnn_prefix: the alternative WWNN prefix
3493 *  @wwpn_prefix: the alternative WWPN prefix
3494 *
3495 *  This function will read the EEPROM from the alternative SAN MAC address
3496 *  block to check the support for the alternative WWNN/WWPN prefix support.
3497 **/
3498s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3499				 u16 *wwpn_prefix)
3500{
3501	u16 offset, caps;
3502	u16 alt_san_mac_blk_offset;
3503
3504	/* clear output first */
3505	*wwnn_prefix = 0xFFFF;
3506	*wwpn_prefix = 0xFFFF;
3507
3508	/* check if alternative SAN MAC is supported */
3509	hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3510			    &alt_san_mac_blk_offset);
3511
3512	if ((alt_san_mac_blk_offset == 0) ||
3513	    (alt_san_mac_blk_offset == 0xFFFF))
3514		goto wwn_prefix_out;
3515
3516	/* check capability in alternative san mac address block */
3517	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3518	hw->eeprom.ops.read(hw, offset, &caps);
3519	if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3520		goto wwn_prefix_out;
3521
3522	/* get the corresponding prefix for WWNN/WWPN */
3523	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3524	hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3525
3526	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3527	hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3528
3529wwn_prefix_out:
3530	return 0;
3531}
3532
3533/**
3534 *  ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3535 *  @hw: pointer to hardware structure
3536 *  @bs: the fcoe boot status
3537 *
3538 *  This function will read the FCOE boot status from the iSCSI FCOE block
3539 **/
3540s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3541{
3542	u16 offset, caps, flags;
3543	s32 status;
3544
3545	/* clear output first */
3546	*bs = ixgbe_fcoe_bootstatus_unavailable;
3547
3548	/* check if FCOE IBA block is present */
3549	offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3550	status = hw->eeprom.ops.read(hw, offset, &caps);
3551	if (status != 0)
3552		goto out;
3553
3554	if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3555		goto out;
3556
3557	/* check if iSCSI FCOE block is populated */
3558	status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3559	if (status != 0)
3560		goto out;
3561
3562	if ((offset == 0) || (offset == 0xFFFF))
3563		goto out;
3564
3565	/* read fcoe flags in iSCSI FCOE block */
3566	offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3567	status = hw->eeprom.ops.read(hw, offset, &flags);
3568	if (status != 0)
3569		goto out;
3570
3571	if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3572		*bs = ixgbe_fcoe_bootstatus_enabled;
3573	else
3574		*bs = ixgbe_fcoe_bootstatus_disabled;
3575
3576out:
3577	return status;
3578}
3579
3580/**
3581 *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3582 *  @hw: pointer to hardware structure
3583 *  @enable: enable or disable switch for anti-spoofing
3584 *  @pf: Physical Function pool - do not enable anti-spoofing for the PF
3585 *
3586 **/
3587void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3588{
3589	int j;
3590	int pf_target_reg = pf >> 3;
3591	int pf_target_shift = pf % 8;
3592	u32 pfvfspoof = 0;
3593
3594	if (hw->mac.type == ixgbe_mac_82598EB)
3595		return;
3596
3597	if (enable)
3598		pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3599
3600	/*
3601	 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3602	 * MAC anti-spoof enables in each register array element.
3603	 */
3604	for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3605		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3606
3607	/* If not enabling anti-spoofing then done */
3608	if (!enable)
3609		return;
3610
3611	/*
3612	 * The PF should be allowed to spoof so that it can support
3613	 * emulation mode NICs.  Reset the bit assigned to the PF
3614	 */
3615	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3616	pfvfspoof ^= (1 << pf_target_shift);
3617	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3618}
3619
3620/**
3621 *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3622 *  @hw: pointer to hardware structure
3623 *  @enable: enable or disable switch for VLAN anti-spoofing
3624 *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3625 *
3626 **/
3627void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3628{
3629	int vf_target_reg = vf >> 3;
3630	int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3631	u32 pfvfspoof;
3632
3633	if (hw->mac.type == ixgbe_mac_82598EB)
3634		return;
3635
3636	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3637	if (enable)
3638		pfvfspoof |= (1 << vf_target_shift);
3639	else
3640		pfvfspoof &= ~(1 << vf_target_shift);
3641	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3642}
3643
3644/**
3645 *  ixgbe_get_device_caps_generic - Get additional device capabilities
3646 *  @hw: pointer to hardware structure
3647 *  @device_caps: the EEPROM word with the extra device capabilities
3648 *
3649 *  This function will read the EEPROM location for the device capabilities,
3650 *  and return the word through device_caps.
3651 **/
3652s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3653{
3654	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3655
3656	return 0;
3657}
3658
3659/**
3660 *  ixgbe_calculate_checksum - Calculate checksum for buffer
3661 *  @buffer: pointer to EEPROM
3662 *  @length: size of EEPROM to calculate a checksum for
3663 *  Calculates the checksum for some buffer on a specified length.  The
3664 *  checksum calculated is returned.
3665 **/
3666static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3667{
3668	u32 i;
3669	u8 sum = 0;
3670
3671	if (!buffer)
3672		return 0;
3673	for (i = 0; i < length; i++)
3674		sum += buffer[i];
3675
3676	return (u8) (0 - sum);
3677}
3678
3679/**
3680 *  ixgbe_host_interface_command - Issue command to manageability block
3681 *  @hw: pointer to the HW structure
3682 *  @buffer: contains the command to write and where the return status will
3683 *   be placed
3684 *  @length: length of buffer, must be multiple of 4 bytes
3685 *
3686 *  Communicates with the manageability block.  On success return 0
3687 *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3688 **/
3689static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3690					u32 length)
3691{
3692	u32 hicr, i, bi;
3693	u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3694	u8 buf_len, dword_len;
3695
3696	s32 ret_val = 0;
3697
3698	if (length == 0 || length & 0x3 ||
3699	    length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3700		hw_dbg(hw, "Buffer length failure.\n");
3701		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3702		goto out;
3703	}
3704
3705	/* Check that the host interface is enabled. */
3706	hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3707	if ((hicr & IXGBE_HICR_EN) == 0) {
3708		hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3709		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3710		goto out;
3711	}
3712
3713	/* Calculate length in DWORDs */
3714	dword_len = length >> 2;
3715
3716	/*
3717	 * The device driver writes the relevant command block
3718	 * into the ram area.
3719	 */
3720	for (i = 0; i < dword_len; i++)
3721		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3722				      i, IXGBE_CPU_TO_LE32(buffer[i]));
3723
3724	/* Setting this bit tells the ARC that a new command is pending. */
3725	IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3726
3727	for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3728		hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3729		if (!(hicr & IXGBE_HICR_C))
3730			break;
3731		msleep(1);
3732	}
3733
3734	/* Check command successful completion. */
3735	if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3736	    (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3737		hw_dbg(hw, "Command has failed with no status valid.\n");
3738		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3739		goto out;
3740	}
3741
3742	/* Calculate length in DWORDs */
3743	dword_len = hdr_size >> 2;
3744
3745	/* first pull in the header so we know the buffer length */
3746	for (bi = 0; bi < dword_len; bi++) {
3747		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3748		IXGBE_LE32_TO_CPUS(&buffer[bi]);
3749	}
3750
3751	/* If there is any thing in data position pull it in */
3752	buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3753	if (buf_len == 0)
3754		goto out;
3755
3756	if (length < (buf_len + hdr_size)) {
3757		hw_dbg(hw, "Buffer not large enough for reply message.\n");
3758		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3759		goto out;
3760	}
3761
3762	/* Calculate length in DWORDs, add 3 for odd lengths */
3763	dword_len = (buf_len + 3) >> 2;
3764
3765	/* Pull in the rest of the buffer (bi is where we left off)*/
3766	for (; bi <= dword_len; bi++) {
3767		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3768		IXGBE_LE32_TO_CPUS(&buffer[bi]);
3769	}
3770
3771out:
3772	return ret_val;
3773}
3774
3775/**
3776 *  ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3777 *  @hw: pointer to the HW structure
3778 *  @maj: driver version major number
3779 *  @min: driver version minor number
3780 *  @build: driver version build number
3781 *  @sub: driver version sub build number
3782 *
3783 *  Sends driver version number to firmware through the manageability
3784 *  block.  On success return 0
3785 *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3786 *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3787 **/
3788s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3789				 u8 build, u8 sub)
3790{
3791	struct ixgbe_hic_drv_info fw_cmd;
3792	int i;
3793	s32 ret_val = 0;
3794
3795	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
3796	    != 0) {
3797		ret_val = IXGBE_ERR_SWFW_SYNC;
3798		goto out;
3799	}
3800
3801	fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3802	fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3803	fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3804	fw_cmd.port_num = (u8)hw->bus.func;
3805	fw_cmd.ver_maj = maj;
3806	fw_cmd.ver_min = min;
3807	fw_cmd.ver_build = build;
3808	fw_cmd.ver_sub = sub;
3809	fw_cmd.hdr.checksum = 0;
3810	fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3811				(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3812	fw_cmd.pad = 0;
3813	fw_cmd.pad2 = 0;
3814
3815	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3816		ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3817						       sizeof(fw_cmd));
3818		if (ret_val != 0)
3819			continue;
3820
3821		if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3822		    FW_CEM_RESP_STATUS_SUCCESS)
3823			ret_val = 0;
3824		else
3825			ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3826
3827		break;
3828	}
3829
3830	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3831out:
3832	return ret_val;
3833}
3834
3835/**
3836 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
3837 * @hw: pointer to hardware structure
3838 * @num_pb: number of packet buffers to allocate
3839 * @headroom: reserve n KB of headroom
3840 * @strategy: packet buffer allocation strategy
3841 **/
3842void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
3843			     int strategy)
3844{
3845	u32 pbsize = hw->mac.rx_pb_size;
3846	int i = 0;
3847	u32 rxpktsize, txpktsize, txpbthresh;
3848
3849	/* Reserve headroom */
3850	pbsize -= headroom;
3851
3852	if (!num_pb)
3853		num_pb = 1;
3854
3855	/* Divide remaining packet buffer space amongst the number of packet
3856	 * buffers requested using supplied strategy.
3857	 */
3858	switch (strategy) {
3859	case PBA_STRATEGY_WEIGHTED:
3860		/* ixgbe_dcb_pba_80_48 strategy weight first half of packet
3861		 * buffer with 5/8 of the packet buffer space.
3862		 */
3863		rxpktsize = (pbsize * 5) / (num_pb * 4);
3864		pbsize -= rxpktsize * (num_pb / 2);
3865		rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3866		for (; i < (num_pb / 2); i++)
3867			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3868		/* Fall through to configure remaining packet buffers */
3869	case PBA_STRATEGY_EQUAL:
3870		rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3871		for (; i < num_pb; i++)
3872			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3873		break;
3874	default:
3875		break;
3876	}
3877
3878	/* Only support an equally distributed Tx packet buffer strategy. */
3879	txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3880	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3881	for (i = 0; i < num_pb; i++) {
3882		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3883		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3884	}
3885
3886	/* Clear unused TCs, if any, to zero buffer size*/
3887	for (; i < IXGBE_MAX_PB; i++) {
3888		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3889		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3890		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3891	}
3892}
3893
3894/**
3895 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3896 * @hw: pointer to the hardware structure
3897 *
3898 * The 82599 and x540 MACs can experience issues if TX work is still pending
3899 * when a reset occurs.  This function prevents this by flushing the PCIe
3900 * buffers on the system.
3901 **/
3902void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3903{
3904	u32 gcr_ext, hlreg0;
3905
3906	/*
3907	 * If double reset is not requested then all transactions should
3908	 * already be clear and as such there is no work to do
3909	 */
3910	if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3911		return;
3912
3913	/*
3914	 * Set loopback enable to prevent any transmits from being sent
3915	 * should the link come up.  This assumes that the RXCTRL.RXEN bit
3916	 * has already been cleared.
3917	 */
3918	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3919	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3920
3921	/* initiate cleaning flow for buffers in the PCIe transaction layer */
3922	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3923	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3924			gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3925
3926	/* Flush all writes and allow 20usec for all transactions to clear */
3927	IXGBE_WRITE_FLUSH(hw);
3928	udelay(20);
3929
3930	/* restore previous register values */
3931	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3932	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3933}
3934
3935static const u8 ixgbe_emc_temp_data[4] = {
3936	IXGBE_EMC_INTERNAL_DATA,
3937	IXGBE_EMC_DIODE1_DATA,
3938	IXGBE_EMC_DIODE2_DATA,
3939	IXGBE_EMC_DIODE3_DATA
3940};
3941static const u8 ixgbe_emc_therm_limit[4] = {
3942	IXGBE_EMC_INTERNAL_THERM_LIMIT,
3943	IXGBE_EMC_DIODE1_THERM_LIMIT,
3944	IXGBE_EMC_DIODE2_THERM_LIMIT,
3945	IXGBE_EMC_DIODE3_THERM_LIMIT
3946};
3947
3948/**
3949 *  ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3950 *  @hw: pointer to hardware structure
3951 *  @data: pointer to the thermal sensor data structure
3952 *
3953 *  Returns the thermal sensor data structure
3954 **/
3955s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3956{
3957	s32 status = 0;
3958	u16 ets_offset;
3959	u16 ets_cfg;
3960	u16 ets_sensor;
3961	u8  num_sensors;
3962	u8  sensor_index;
3963	u8  sensor_location;
3964	u8  i;
3965	struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3966
3967	/* Only support thermal sensors attached to 82599 physical port 0 */
3968	if ((hw->mac.type != ixgbe_mac_82599EB) ||
3969	    (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3970		status = IXGBE_NOT_IMPLEMENTED;
3971		goto out;
3972	}
3973
3974	status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
3975	if (status)
3976		goto out;
3977
3978	if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
3979		status = IXGBE_NOT_IMPLEMENTED;
3980		goto out;
3981	}
3982
3983	status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
3984	if (status)
3985		goto out;
3986
3987	if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
3988		!= IXGBE_ETS_TYPE_EMC) {
3989		status = IXGBE_NOT_IMPLEMENTED;
3990		goto out;
3991	}
3992
3993	num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3994	if (num_sensors > IXGBE_MAX_SENSORS)
3995		num_sensors = IXGBE_MAX_SENSORS;
3996
3997	for (i = 0; i < num_sensors; i++) {
3998		status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3999					     &ets_sensor);
4000		if (status)
4001			goto out;
4002
4003		sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4004				IXGBE_ETS_DATA_INDEX_SHIFT);
4005		sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4006				   IXGBE_ETS_DATA_LOC_SHIFT);
4007
4008		if (sensor_location != 0) {
4009			status = hw->phy.ops.read_i2c_byte(hw,
4010					ixgbe_emc_temp_data[sensor_index],
4011					IXGBE_I2C_THERMAL_SENSOR_ADDR,
4012					&data->sensor[i].temp);
4013			if (status)
4014				goto out;
4015		}
4016	}
4017out:
4018	return status;
4019}
4020
4021/**
4022 *  ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4023 *  @hw: pointer to hardware structure
4024 *
4025 *  Inits the thermal sensor thresholds according to the NVM map
4026 *  and save off the threshold and location values into mac.thermal_sensor_data
4027 **/
4028s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4029{
4030	s32 status = 0;
4031	u16 ets_offset;
4032	u16 ets_cfg;
4033	u16 ets_sensor;
4034	u8  low_thresh_delta;
4035	u8  num_sensors;
4036	u8  sensor_index;
4037	u8  sensor_location;
4038	u8  therm_limit;
4039	u8  i;
4040	struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4041
4042	memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4043
4044	/* Only support thermal sensors attached to 82599 physical port 0 */
4045	if ((hw->mac.type != ixgbe_mac_82599EB) ||
4046	    (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4047		return IXGBE_NOT_IMPLEMENTED;
4048
4049	hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4050	if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4051		return IXGBE_NOT_IMPLEMENTED;
4052
4053	hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4054	if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4055		!= IXGBE_ETS_TYPE_EMC)
4056		return IXGBE_NOT_IMPLEMENTED;
4057
4058	low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4059			     IXGBE_ETS_LTHRES_DELTA_SHIFT);
4060	num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4061
4062	for (i = 0; i < num_sensors; i++) {
4063		hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
4064		sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4065				IXGBE_ETS_DATA_INDEX_SHIFT);
4066		sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4067				   IXGBE_ETS_DATA_LOC_SHIFT);
4068		therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4069
4070		hw->phy.ops.write_i2c_byte(hw,
4071			ixgbe_emc_therm_limit[sensor_index],
4072			IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4073
4074		if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4075			data->sensor[i].location = sensor_location;
4076			data->sensor[i].caution_thresh = therm_limit;
4077			data->sensor[i].max_op_thresh = therm_limit -
4078							low_thresh_delta;
4079		}
4080	}
4081	return status;
4082}
4083