1aa97dd1cSKonstantin Ananyev/*
2aa97dd1cSKonstantin Ananyev * Copyright (c) 2016  Intel Corporation.
3aa97dd1cSKonstantin Ananyev * Licensed under the Apache License, Version 2.0 (the "License");
4aa97dd1cSKonstantin Ananyev * you may not use this file except in compliance with the License.
5aa97dd1cSKonstantin Ananyev * You may obtain a copy of the License at:
6aa97dd1cSKonstantin Ananyev *
7aa97dd1cSKonstantin Ananyev *     http://www.apache.org/licenses/LICENSE-2.0
8aa97dd1cSKonstantin Ananyev *
9aa97dd1cSKonstantin Ananyev * Unless required by applicable law or agreed to in writing, software
10aa97dd1cSKonstantin Ananyev * distributed under the License is distributed on an "AS IS" BASIS,
11aa97dd1cSKonstantin Ananyev * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12aa97dd1cSKonstantin Ananyev * See the License for the specific language governing permissions and
13aa97dd1cSKonstantin Ananyev * limitations under the License.
14aa97dd1cSKonstantin Ananyev */
15aa97dd1cSKonstantin Ananyev
16aa97dd1cSKonstantin Ananyev#ifndef PORT_H_
17aa97dd1cSKonstantin Ananyev#define PORT_H_
18aa97dd1cSKonstantin Ananyev
19aa97dd1cSKonstantin Ananyevstatic void
20aa97dd1cSKonstantin Ananyevprepare_hash_key(struct netbe_port *uprt, uint8_t key_size, uint16_t family)
21aa97dd1cSKonstantin Ananyev{
22aa97dd1cSKonstantin Ananyev	uint32_t align_nb_q;
23aa97dd1cSKonstantin Ananyev
24aa97dd1cSKonstantin Ananyev	align_nb_q = rte_align32pow2(uprt->nb_lcore);
25aa97dd1cSKonstantin Ananyev	memset(uprt->hash_key, 0, RSS_HASH_KEY_LENGTH);
26aa97dd1cSKonstantin Ananyev	uprt->hash_key_size = key_size;
27aa97dd1cSKonstantin Ananyev	if (family == AF_INET)
28aa97dd1cSKonstantin Ananyev		uprt->hash_key[RSS_HASH_KEY_DEST_PORT_LOC_IPV4] = align_nb_q;
29aa97dd1cSKonstantin Ananyev	else
30aa97dd1cSKonstantin Ananyev		uprt->hash_key[RSS_HASH_KEY_DEST_PORT_LOC_IPV6] = align_nb_q;
31aa97dd1cSKonstantin Ananyev}
32aa97dd1cSKonstantin Ananyev
33aa97dd1cSKonstantin Ananyevstatic int
34aa97dd1cSKonstantin Ananyevupdate_rss_conf(struct netbe_port *uprt,
35aa97dd1cSKonstantin Ananyev	const struct rte_eth_dev_info *dev_info,
36aa97dd1cSKonstantin Ananyev	struct rte_eth_conf *port_conf, uint32_t proto)
37aa97dd1cSKonstantin Ananyev{
38aa97dd1cSKonstantin Ananyev	uint8_t hash_key_size;
39aa97dd1cSKonstantin Ananyev
40aa97dd1cSKonstantin Ananyev	if (uprt->nb_lcore > 1) {
41aa97dd1cSKonstantin Ananyev		if (dev_info->hash_key_size > 0)
42aa97dd1cSKonstantin Ananyev			hash_key_size = dev_info->hash_key_size;
43aa97dd1cSKonstantin Ananyev		else {
44aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
45aa97dd1cSKonstantin Ananyev				"%s: dev_info did not provide a valid hash "
46aa97dd1cSKonstantin Ananyev				"key size\n", __func__);
47aa97dd1cSKonstantin Ananyev			return -EINVAL;
48aa97dd1cSKonstantin Ananyev		}
49aa97dd1cSKonstantin Ananyev
50aa97dd1cSKonstantin Ananyev		if (uprt->ipv4 != INADDR_ANY &&
51aa97dd1cSKonstantin Ananyev				memcmp(&uprt->ipv6, &in6addr_any,
52aa97dd1cSKonstantin Ananyev				sizeof(uprt->ipv6)) != 0) {
53aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
54aa97dd1cSKonstantin Ananyev				"%s: RSS for both IPv4 and IPv6 not "
55aa97dd1cSKonstantin Ananyev				"supported!\n", __func__);
56aa97dd1cSKonstantin Ananyev			return -EINVAL;
57aa97dd1cSKonstantin Ananyev		} else if (uprt->ipv4 != INADDR_ANY) {
58aa97dd1cSKonstantin Ananyev			prepare_hash_key(uprt, hash_key_size, AF_INET);
59aa97dd1cSKonstantin Ananyev		} else if (memcmp(&uprt->ipv6, &in6addr_any, sizeof(uprt->ipv6))
60aa97dd1cSKonstantin Ananyev				!= 0) {
61aa97dd1cSKonstantin Ananyev			prepare_hash_key(uprt, hash_key_size, AF_INET6);
62aa97dd1cSKonstantin Ananyev		} else {
63aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
64aa97dd1cSKonstantin Ananyev				"%s: No IPv4 or IPv6 address is found!\n",
65aa97dd1cSKonstantin Ananyev				__func__);
66aa97dd1cSKonstantin Ananyev			return -EINVAL;
67aa97dd1cSKonstantin Ananyev		}
68aa97dd1cSKonstantin Ananyev		port_conf->rxmode.mq_mode = ETH_MQ_RX_RSS;
69aa97dd1cSKonstantin Ananyev		if (proto == TLE_PROTO_TCP)
70aa97dd1cSKonstantin Ananyev			port_conf->rx_adv_conf.rss_conf.rss_hf = ETH_RSS_TCP;
71aa97dd1cSKonstantin Ananyev		else
72aa97dd1cSKonstantin Ananyev			port_conf->rx_adv_conf.rss_conf.rss_hf = ETH_RSS_UDP;
73aa97dd1cSKonstantin Ananyev		port_conf->rx_adv_conf.rss_conf.rss_key_len = hash_key_size;
74aa97dd1cSKonstantin Ananyev		port_conf->rx_adv_conf.rss_conf.rss_key = uprt->hash_key;
75aa97dd1cSKonstantin Ananyev	}
76aa97dd1cSKonstantin Ananyev
77aa97dd1cSKonstantin Ananyev	return 0;
78aa97dd1cSKonstantin Ananyev}
79aa97dd1cSKonstantin Ananyev
80aa97dd1cSKonstantin Ananyevstatic uint32_t
81aa97dd1cSKonstantin Ananyevqidx_from_hash_index(uint32_t hash, uint32_t align_nb_q)
82aa97dd1cSKonstantin Ananyev{
83aa97dd1cSKonstantin Ananyev	uint32_t i, nb_bit, q;
84aa97dd1cSKonstantin Ananyev
85aa97dd1cSKonstantin Ananyev	nb_bit = (sizeof(uint32_t) * CHAR_BIT) - __builtin_clz(align_nb_q - 1);
86aa97dd1cSKonstantin Ananyev	q = (hash & 1);
87aa97dd1cSKonstantin Ananyev	for (i = 1; i < nb_bit; i++) {
88aa97dd1cSKonstantin Ananyev		hash >>= 1;
89aa97dd1cSKonstantin Ananyev		q <<= 1;
90aa97dd1cSKonstantin Ananyev		q |= (hash & 1);
91aa97dd1cSKonstantin Ananyev	}
92aa97dd1cSKonstantin Ananyev
93aa97dd1cSKonstantin Ananyev	return q;
94aa97dd1cSKonstantin Ananyev}
95aa97dd1cSKonstantin Ananyev
96aa97dd1cSKonstantin Ananyevstatic int
97aa97dd1cSKonstantin Ananyevupdate_rss_reta(struct netbe_port *uprt,
98aa97dd1cSKonstantin Ananyev	const struct rte_eth_dev_info *dev_info)
99aa97dd1cSKonstantin Ananyev{
100aa97dd1cSKonstantin Ananyev	struct rte_eth_rss_reta_entry64 reta_conf[RSS_RETA_CONF_ARRAY_SIZE];
101aa97dd1cSKonstantin Ananyev	int32_t i, rc, align_nb_q;
102aa97dd1cSKonstantin Ananyev	int32_t q_index, idx, shift;
103aa97dd1cSKonstantin Ananyev
104aa97dd1cSKonstantin Ananyev	if (uprt->nb_lcore > 1) {
105aa97dd1cSKonstantin Ananyev		if (dev_info->reta_size == 0) {
106aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
107aa97dd1cSKonstantin Ananyev				"%s: Redirection table size 0 is invalid for "
108aa97dd1cSKonstantin Ananyev				"RSS\n", __func__);
109aa97dd1cSKonstantin Ananyev			return -EINVAL;
110aa97dd1cSKonstantin Ananyev		}
111aa97dd1cSKonstantin Ananyev		RTE_LOG(NOTICE, USER1,
112aa97dd1cSKonstantin Ananyev			"%s: The reta size of port %d is %u\n",
113aa97dd1cSKonstantin Ananyev			__func__, uprt->id, dev_info->reta_size);
114aa97dd1cSKonstantin Ananyev
115aa97dd1cSKonstantin Ananyev		if (dev_info->reta_size > ETH_RSS_RETA_SIZE_512) {
116aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
117aa97dd1cSKonstantin Ananyev				"%s: More than %u entries of Reta not supported\n",
118aa97dd1cSKonstantin Ananyev				__func__, ETH_RSS_RETA_SIZE_512);
119aa97dd1cSKonstantin Ananyev			return -EINVAL;
120aa97dd1cSKonstantin Ananyev		}
121aa97dd1cSKonstantin Ananyev
122aa97dd1cSKonstantin Ananyev		memset(reta_conf, 0, sizeof(reta_conf));
123aa97dd1cSKonstantin Ananyev		align_nb_q = rte_align32pow2(uprt->nb_lcore);
124aa97dd1cSKonstantin Ananyev		for (i = 0; i < align_nb_q; i++) {
125aa97dd1cSKonstantin Ananyev			q_index = qidx_from_hash_index(i, align_nb_q) %
126aa97dd1cSKonstantin Ananyev						uprt->nb_lcore;
127aa97dd1cSKonstantin Ananyev
128aa97dd1cSKonstantin Ananyev			idx = i / RTE_RETA_GROUP_SIZE;
129aa97dd1cSKonstantin Ananyev			shift = i % RTE_RETA_GROUP_SIZE;
130aa97dd1cSKonstantin Ananyev			reta_conf[idx].mask |= (1ULL << shift);
131aa97dd1cSKonstantin Ananyev			reta_conf[idx].reta[shift] = q_index;
132aa97dd1cSKonstantin Ananyev			RTE_LOG(NOTICE, USER1,
133aa97dd1cSKonstantin Ananyev				"%s: port=%u RSS reta conf: hash=%u, q=%u\n",
134aa97dd1cSKonstantin Ananyev				__func__, uprt->id, i, q_index);
135aa97dd1cSKonstantin Ananyev		}
136aa97dd1cSKonstantin Ananyev
137aa97dd1cSKonstantin Ananyev		rc = rte_eth_dev_rss_reta_update(uprt->id,
138aa97dd1cSKonstantin Ananyev				reta_conf, dev_info->reta_size);
139aa97dd1cSKonstantin Ananyev		if (rc != 0) {
140aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
141aa97dd1cSKonstantin Ananyev				"%s: Bad redirection table parameter, "
142aa97dd1cSKonstantin Ananyev				"rc = %d\n", __func__, rc);
143aa97dd1cSKonstantin Ananyev			return rc;
144aa97dd1cSKonstantin Ananyev		}
145aa97dd1cSKonstantin Ananyev	}
146aa97dd1cSKonstantin Ananyev
147aa97dd1cSKonstantin Ananyev	return 0;
148aa97dd1cSKonstantin Ananyev}
149aa97dd1cSKonstantin Ananyev
150aa97dd1cSKonstantin Ananyev/*
151aa97dd1cSKonstantin Ananyev * Initilise DPDK port.
152aa97dd1cSKonstantin Ananyev * In current version, multi-queue per port is used.
153aa97dd1cSKonstantin Ananyev */
154aa97dd1cSKonstantin Ananyevstatic int
155aa97dd1cSKonstantin Ananyevport_init(struct netbe_port *uprt, uint32_t proto)
156aa97dd1cSKonstantin Ananyev{
157aa97dd1cSKonstantin Ananyev	int32_t rc;
158aa97dd1cSKonstantin Ananyev	struct rte_eth_conf port_conf;
159aa97dd1cSKonstantin Ananyev	struct rte_eth_dev_info dev_info;
160aa97dd1cSKonstantin Ananyev
161aa97dd1cSKonstantin Ananyev	rte_eth_dev_info_get(uprt->id, &dev_info);
162aa97dd1cSKonstantin Ananyev	if ((dev_info.rx_offload_capa & uprt->rx_offload) != uprt->rx_offload) {
163aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1,
164aa97dd1cSKonstantin Ananyev			"port#%u supported/requested RX offloads don't match, "
1655c795f7bSKonstantin Ananyev			"supported: %#" PRIx64 ", requested: %#" PRIx64 ";\n",
1665c795f7bSKonstantin Ananyev			uprt->id, (uint64_t)dev_info.rx_offload_capa,
1675c795f7bSKonstantin Ananyev			(uint64_t)uprt->rx_offload);
168aa97dd1cSKonstantin Ananyev		return -EINVAL;
169aa97dd1cSKonstantin Ananyev	}
170aa97dd1cSKonstantin Ananyev	if ((dev_info.tx_offload_capa & uprt->tx_offload) != uprt->tx_offload) {
171aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1,
172aa97dd1cSKonstantin Ananyev			"port#%u supported/requested TX offloads don't match, "
1735c795f7bSKonstantin Ananyev			"supported: %#" PRIx64 ", requested: %#" PRIx64 ";\n",
1745c795f7bSKonstantin Ananyev			uprt->id, (uint64_t)dev_info.tx_offload_capa,
1755c795f7bSKonstantin Ananyev			(uint64_t)uprt->tx_offload);
176aa97dd1cSKonstantin Ananyev		return -EINVAL;
177aa97dd1cSKonstantin Ananyev	}
178aa97dd1cSKonstantin Ananyev
179aa97dd1cSKonstantin Ananyev	port_conf = port_conf_default;
180aa97dd1cSKonstantin Ananyev	if ((uprt->rx_offload & RX_CSUM_OFFLOAD) != 0) {
181aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1, "%s(%u): enabling RX csum offload;\n",
182aa97dd1cSKonstantin Ananyev			__func__, uprt->id);
183cecfc87fSJianfeng Tan		port_conf.rxmode.offloads |= uprt->rx_offload & RX_CSUM_OFFLOAD;
184aa97dd1cSKonstantin Ananyev	}
185aa97dd1cSKonstantin Ananyev	port_conf.rxmode.max_rx_pkt_len = uprt->mtu + ETHER_CRC_LEN;
18636d90e3aSMohammad Abdul Awal	if (port_conf.rxmode.max_rx_pkt_len > ETHER_MAX_LEN)
187cecfc87fSJianfeng Tan		port_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
188aa97dd1cSKonstantin Ananyev
189aa97dd1cSKonstantin Ananyev	rc = update_rss_conf(uprt, &dev_info, &port_conf, proto);
190aa97dd1cSKonstantin Ananyev	if (rc != 0)
191aa97dd1cSKonstantin Ananyev		return rc;
192aa97dd1cSKonstantin Ananyev
193cecfc87fSJianfeng Tan	port_conf.txmode.offloads = uprt->tx_offload;
194cecfc87fSJianfeng Tan
195aa97dd1cSKonstantin Ananyev	rc = rte_eth_dev_configure(uprt->id, uprt->nb_lcore, uprt->nb_lcore,
196aa97dd1cSKonstantin Ananyev			&port_conf);
197aa97dd1cSKonstantin Ananyev	RTE_LOG(NOTICE, USER1,
198aa97dd1cSKonstantin Ananyev		"%s: rte_eth_dev_configure(prt_id=%u, nb_rxq=%u, nb_txq=%u) "
199aa97dd1cSKonstantin Ananyev		"returns %d;\n", __func__, uprt->id, uprt->nb_lcore,
200aa97dd1cSKonstantin Ananyev		uprt->nb_lcore, rc);
201aa97dd1cSKonstantin Ananyev	if (rc != 0)
202aa97dd1cSKonstantin Ananyev		return rc;
203aa97dd1cSKonstantin Ananyev
204aa97dd1cSKonstantin Ananyev	return 0;
205aa97dd1cSKonstantin Ananyev}
206aa97dd1cSKonstantin Ananyev
207aa97dd1cSKonstantin Ananyevstatic int
208aa97dd1cSKonstantin Ananyevqueue_init(struct netbe_port *uprt, struct rte_mempool *mp)
209aa97dd1cSKonstantin Ananyev{
210aa97dd1cSKonstantin Ananyev	int32_t socket, rc;
211aa97dd1cSKonstantin Ananyev	uint16_t q;
2125b873e3bSKonstantin Ananyev	uint32_t nb_rxd, nb_txd;
213aa97dd1cSKonstantin Ananyev	struct rte_eth_dev_info dev_info;
214aa97dd1cSKonstantin Ananyev
215aa97dd1cSKonstantin Ananyev	rte_eth_dev_info_get(uprt->id, &dev_info);
216aa97dd1cSKonstantin Ananyev
217aa97dd1cSKonstantin Ananyev	socket = rte_eth_dev_socket_id(uprt->id);
218aa97dd1cSKonstantin Ananyev
219aa97dd1cSKonstantin Ananyev	dev_info.default_rxconf.rx_drop_en = 1;
220aa97dd1cSKonstantin Ananyev
2215b873e3bSKonstantin Ananyev	nb_rxd = RTE_MIN(RX_RING_SIZE, dev_info.rx_desc_lim.nb_max);
2225b873e3bSKonstantin Ananyev	nb_txd = RTE_MIN(TX_RING_SIZE, dev_info.tx_desc_lim.nb_max);
2235b873e3bSKonstantin Ananyev
2245b873e3bSKonstantin Ananyev	dev_info.default_txconf.tx_free_thresh = nb_txd / 2;
225aa97dd1cSKonstantin Ananyev
226aa97dd1cSKonstantin Ananyev	for (q = 0; q < uprt->nb_lcore; q++) {
2275b873e3bSKonstantin Ananyev		rc = rte_eth_rx_queue_setup(uprt->id, q, nb_rxd,
228aa97dd1cSKonstantin Ananyev			socket, &dev_info.default_rxconf, mp);
229aa97dd1cSKonstantin Ananyev		if (rc < 0) {
230aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
231aa97dd1cSKonstantin Ananyev				"%s: rx queue=%u setup failed with error "
232aa97dd1cSKonstantin Ananyev				"code: %d\n", __func__, q, rc);
233aa97dd1cSKonstantin Ananyev			return rc;
234aa97dd1cSKonstantin Ananyev		}
235aa97dd1cSKonstantin Ananyev	}
236aa97dd1cSKonstantin Ananyev
237aa97dd1cSKonstantin Ananyev	for (q = 0; q < uprt->nb_lcore; q++) {
2385b873e3bSKonstantin Ananyev		rc = rte_eth_tx_queue_setup(uprt->id, q, nb_txd,
239aa97dd1cSKonstantin Ananyev			socket, &dev_info.default_txconf);
240aa97dd1cSKonstantin Ananyev		if (rc < 0) {
241aa97dd1cSKonstantin Ananyev			RTE_LOG(ERR, USER1,
242aa97dd1cSKonstantin Ananyev				"%s: tx queue=%u setup failed with error "
243aa97dd1cSKonstantin Ananyev				"code: %d\n", __func__, q, rc);
244aa97dd1cSKonstantin Ananyev			return rc;
245aa97dd1cSKonstantin Ananyev		}
246aa97dd1cSKonstantin Ananyev	}
247aa97dd1cSKonstantin Ananyev	return 0;
248aa97dd1cSKonstantin Ananyev}
249aa97dd1cSKonstantin Ananyev
250aa97dd1cSKonstantin Ananyev/*
251aa97dd1cSKonstantin Ananyev * Check that lcore is enabled, not master, and not in use already.
252aa97dd1cSKonstantin Ananyev */
253aa97dd1cSKonstantin Ananyevstatic int
254aa97dd1cSKonstantin Ananyevcheck_lcore(uint32_t lc)
255aa97dd1cSKonstantin Ananyev{
256aa97dd1cSKonstantin Ananyev	if (rte_lcore_is_enabled(lc) == 0) {
257aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1, "lcore %u is not enabled\n", lc);
258aa97dd1cSKonstantin Ananyev		return -EINVAL;
259aa97dd1cSKonstantin Ananyev	}
260aa97dd1cSKonstantin Ananyev	if (rte_eal_get_lcore_state(lc) == RUNNING) {
261aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1, "lcore %u already running %p\n",
262aa97dd1cSKonstantin Ananyev			lc, lcore_config[lc].f);
263aa97dd1cSKonstantin Ananyev		return -EINVAL;
264aa97dd1cSKonstantin Ananyev	}
265aa97dd1cSKonstantin Ananyev	return 0;
266aa97dd1cSKonstantin Ananyev}
267aa97dd1cSKonstantin Ananyev
268aa97dd1cSKonstantin Ananyevstatic void
269aa97dd1cSKonstantin Ananyevlog_netbe_prt(const struct netbe_port *uprt)
270aa97dd1cSKonstantin Ananyev{
271aa97dd1cSKonstantin Ananyev	uint32_t i;
272aa97dd1cSKonstantin Ananyev	char corelist[2 * RTE_MAX_LCORE + 1];
273aa97dd1cSKonstantin Ananyev	char hashkey[2 * RSS_HASH_KEY_LENGTH];
274aa97dd1cSKonstantin Ananyev
275aa97dd1cSKonstantin Ananyev	memset(corelist, 0, sizeof(corelist));
276aa97dd1cSKonstantin Ananyev	memset(hashkey, 0, sizeof(hashkey));
277aa97dd1cSKonstantin Ananyev	for (i = 0; i < uprt->nb_lcore; i++)
278aa97dd1cSKonstantin Ananyev		if (i < uprt->nb_lcore - 1)
279aa97dd1cSKonstantin Ananyev			sprintf(corelist + (2 * i), "%u,", uprt->lcore_id[i]);
280aa97dd1cSKonstantin Ananyev		else
281aa97dd1cSKonstantin Ananyev			sprintf(corelist + (2 * i), "%u", uprt->lcore_id[i]);
282aa97dd1cSKonstantin Ananyev
283aa97dd1cSKonstantin Ananyev	for (i = 0; i < uprt->hash_key_size; i++)
284aa97dd1cSKonstantin Ananyev		sprintf(hashkey + (2 * i), "%02x", uprt->hash_key[i]);
285aa97dd1cSKonstantin Ananyev
286aa97dd1cSKonstantin Ananyev	RTE_LOG(NOTICE, USER1,
287aa97dd1cSKonstantin Ananyev		"uprt %p = <id = %u, lcore = <%s>, mtu = %u, "
2885c795f7bSKonstantin Ananyev		"rx_offload = %#" PRIx64 ", tx_offload = %#" PRIx64 ",\n"
289aa97dd1cSKonstantin Ananyev		"ipv4 = %#x, "
290aa97dd1cSKonstantin Ananyev		"ipv6 = %04hx:%04hx:%04hx:%04hx:%04hx:%04hx:%04hx:%04hx, "
291aa97dd1cSKonstantin Ananyev		"mac = %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx>;\n"
292aa97dd1cSKonstantin Ananyev		"hashkey = %s;\n",
293aa97dd1cSKonstantin Ananyev		uprt, uprt->id, corelist,
294aa97dd1cSKonstantin Ananyev		uprt->mtu, uprt->rx_offload, uprt->tx_offload,
295aa97dd1cSKonstantin Ananyev		uprt->ipv4,
296aa97dd1cSKonstantin Ananyev		uprt->ipv6.s6_addr16[0], uprt->ipv6.s6_addr16[1],
297aa97dd1cSKonstantin Ananyev		uprt->ipv6.s6_addr16[2], uprt->ipv6.s6_addr16[3],
298aa97dd1cSKonstantin Ananyev		uprt->ipv6.s6_addr16[4], uprt->ipv6.s6_addr16[5],
299aa97dd1cSKonstantin Ananyev		uprt->ipv6.s6_addr16[6], uprt->ipv6.s6_addr16[7],
300aa97dd1cSKonstantin Ananyev		uprt->mac.addr_bytes[0], uprt->mac.addr_bytes[1],
301aa97dd1cSKonstantin Ananyev		uprt->mac.addr_bytes[2], uprt->mac.addr_bytes[3],
302aa97dd1cSKonstantin Ananyev		uprt->mac.addr_bytes[4], uprt->mac.addr_bytes[5],
303aa97dd1cSKonstantin Ananyev		hashkey);
304aa97dd1cSKonstantin Ananyev}
305aa97dd1cSKonstantin Ananyev
306aa97dd1cSKonstantin Ananyevstatic void
307aa97dd1cSKonstantin Ananyevlog_netbe_cfg(const struct netbe_cfg *ucfg)
308aa97dd1cSKonstantin Ananyev{
309aa97dd1cSKonstantin Ananyev	uint32_t i;
310aa97dd1cSKonstantin Ananyev
311aa97dd1cSKonstantin Ananyev	RTE_LOG(NOTICE, USER1,
312aa97dd1cSKonstantin Ananyev		"ucfg @ %p, prt_num = %u\n", ucfg, ucfg->prt_num);
313aa97dd1cSKonstantin Ananyev
314aa97dd1cSKonstantin Ananyev	for (i = 0; i != ucfg->prt_num; i++)
315aa97dd1cSKonstantin Ananyev		log_netbe_prt(ucfg->prt + i);
316aa97dd1cSKonstantin Ananyev}
317aa97dd1cSKonstantin Ananyev
318aa97dd1cSKonstantin Ananyevstatic int
31974a56517SMariusz Drostpool_init(uint32_t sid, uint32_t mpool_buf_num)
320aa97dd1cSKonstantin Ananyev{
321aa97dd1cSKonstantin Ananyev	int32_t rc;
322aa97dd1cSKonstantin Ananyev	struct rte_mempool *mp;
323aa97dd1cSKonstantin Ananyev	char name[RTE_MEMPOOL_NAMESIZE];
324aa97dd1cSKonstantin Ananyev
325aa97dd1cSKonstantin Ananyev	snprintf(name, sizeof(name), "MP%u", sid);
32674a56517SMariusz Drost	mp = rte_pktmbuf_pool_create(name, mpool_buf_num, MPOOL_CACHE_SIZE, 0,
327aa97dd1cSKonstantin Ananyev		RTE_MBUF_DEFAULT_BUF_SIZE, sid - 1);
328aa97dd1cSKonstantin Ananyev	if (mp == NULL) {
329aa97dd1cSKonstantin Ananyev		rc = -rte_errno;
330aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1, "%s(%d) failed with error code: %d\n",
331aa97dd1cSKonstantin Ananyev			__func__, sid - 1, rc);
332aa97dd1cSKonstantin Ananyev		return rc;
333aa97dd1cSKonstantin Ananyev	}
334aa97dd1cSKonstantin Ananyev
335aa97dd1cSKonstantin Ananyev	mpool[sid] = mp;
336aa97dd1cSKonstantin Ananyev	return 0;
337aa97dd1cSKonstantin Ananyev}
338aa97dd1cSKonstantin Ananyev
339aa97dd1cSKonstantin Ananyevstatic int
34074a56517SMariusz Drostfrag_pool_init(uint32_t sid, uint32_t mpool_buf_num)
341aa97dd1cSKonstantin Ananyev{
342aa97dd1cSKonstantin Ananyev	int32_t rc;
343aa97dd1cSKonstantin Ananyev	struct rte_mempool *frag_mp;
344aa97dd1cSKonstantin Ananyev	char frag_name[RTE_MEMPOOL_NAMESIZE];
345aa97dd1cSKonstantin Ananyev
346aa97dd1cSKonstantin Ananyev	snprintf(frag_name, sizeof(frag_name), "frag_MP%u", sid);
34774a56517SMariusz Drost	frag_mp = rte_pktmbuf_pool_create(frag_name, mpool_buf_num,
348aa97dd1cSKonstantin Ananyev		MPOOL_CACHE_SIZE, 0, FRAG_MBUF_BUF_SIZE, sid - 1);
349aa97dd1cSKonstantin Ananyev	if (frag_mp == NULL) {
350aa97dd1cSKonstantin Ananyev		rc = -rte_errno;
351aa97dd1cSKonstantin Ananyev		RTE_LOG(ERR, USER1, "%s(%d) failed with error code: %d\n",
352aa97dd1cSKonstantin Ananyev			__func__, sid - 1, rc);
353aa97dd1cSKonstantin Ananyev		return rc;
354aa97dd1cSKonstantin Ananyev	}
355aa97dd1cSKonstantin Ananyev
356aa97dd1cSKonstantin Ananyev	frag_mpool[sid] = frag_mp;
357aa97dd1cSKonstantin Ananyev	return 0;
358aa97dd1cSKonstantin Ananyev}
359aa97dd1cSKonstantin Ananyev
360aa97dd1cSKonstantin Ananyevstatic struct netbe_lcore *
361aa97dd1cSKonstantin Ananyevfind_initilized_lcore(struct netbe_cfg *cfg, uint32_t lc_num)
362aa97dd1cSKonstantin Ananyev{
363aa97dd1cSKonstantin Ananyev	uint32_t i;
364aa97dd1cSKonstantin Ananyev
365aa97dd1cSKonstantin Ananyev	for (i = 0; i < cfg->cpu_num; i++)
366aa97dd1cSKonstantin Ananyev		if (cfg->cpu[i].id == lc_num)
367aa97dd1cSKonstantin Ananyev			return &cfg->cpu[i];
368aa97dd1cSKonstantin Ananyev
369aa97dd1cSKonstantin Ananyev	return NULL;
370aa97dd1cSKonstantin Ananyev}
371aa97dd1cSKonstantin Ananyev
372aa97dd1cSKonstantin Ananyev/*
373aa97dd1cSKonstantin Ananyev * Setup all enabled ports.
374