1/*
2 * Copyright (c) 2005 Topspin Communications.  All rights reserved.
3 * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
4 * Copyright (c) 2005 PathScale, Inc.  All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses.  You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 *     Redistribution and use in source and binary forms, with or
13 *     without modification, are permitted provided that the following
14 *     conditions are met:
15 *
16 *      - Redistributions of source code must retain the above
17 *        copyright notice, this list of conditions and the following
18 *        disclaimer.
19 *
20 *      - Redistributions in binary form must reproduce the above
21 *        copyright notice, this list of conditions and the following
22 *        disclaimer in the documentation and/or other materials
23 *        provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef KERN_ABI_EXP_H
36#define KERN_ABI_EXP_H
37
38#include <infiniband/kern-abi.h>
39
40/*
41 * This file must be kept in sync with the kernel's version of
42 * drivers/infiniband/include/ib_user_verbs_exp.h
43 */
44
45enum {
46	IB_USER_VERBS_EXP_CMD_FIRST = 64
47};
48
49enum {
50	IB_USER_VERBS_EXP_CMD_CREATE_QP,
51	IB_USER_VERBS_EXP_CMD_MODIFY_CQ,
52	IB_USER_VERBS_EXP_CMD_MODIFY_QP,
53	IB_USER_VERBS_EXP_CMD_CREATE_CQ,
54	IB_USER_VERBS_EXP_CMD_QUERY_DEVICE,
55	IB_USER_VERBS_EXP_CMD_CREATE_DCT,
56	IB_USER_VERBS_EXP_CMD_DESTROY_DCT,
57	IB_USER_VERBS_EXP_CMD_QUERY_DCT,
58	IB_USER_VERBS_EXP_CMD_ARM_DCT,
59	IB_USER_VERBS_EXP_CMD_CREATE_MR,
60	IB_USER_VERBS_EXP_CMD_QUERY_MKEY,
61	IB_USER_VERBS_EXP_CMD_REG_MR,
62	IB_USER_VERBS_EXP_CMD_PREFETCH_MR,
63	IB_USER_VERBS_EXP_CMD_REREG_MR,
64	IB_USER_VERBS_EXP_CMD_CREATE_WQ,
65	IB_USER_VERBS_EXP_CMD_MODIFY_WQ,
66	IB_USER_VERBS_EXP_CMD_DESTROY_WQ,
67	IB_USER_VERBS_EXP_CMD_CREATE_RWQ_IND_TBL,
68	IB_USER_VERBS_EXP_CMD_DESTROY_RWQ_IND_TBL,
69	IB_USER_VERBS_EXP_CMD_CREATE_FLOW,
70};
71
72enum {
73	IB_USER_VERBS_CMD_EXP_CREATE_WQ =
74			IB_USER_VERBS_EXP_CMD_CREATE_WQ +
75			IB_USER_VERBS_EXP_CMD_FIRST,
76	IB_USER_VERBS_CMD_EXP_MODIFY_WQ =
77			IB_USER_VERBS_EXP_CMD_MODIFY_WQ +
78			IB_USER_VERBS_EXP_CMD_FIRST,
79	IB_USER_VERBS_CMD_EXP_DESTROY_WQ =
80			IB_USER_VERBS_EXP_CMD_DESTROY_WQ +
81			IB_USER_VERBS_EXP_CMD_FIRST,
82	IB_USER_VERBS_CMD_EXP_CREATE_RWQ_IND_TBL =
83			IB_USER_VERBS_EXP_CMD_CREATE_RWQ_IND_TBL +
84			IB_USER_VERBS_EXP_CMD_FIRST,
85	IB_USER_VERBS_CMD_EXP_DESTROY_RWQ_IND_TBL =
86			IB_USER_VERBS_EXP_CMD_DESTROY_RWQ_IND_TBL +
87			IB_USER_VERBS_EXP_CMD_FIRST,
88	/*
89	 * Set commands that didn't exist to -1 so our compile-time
90	 * trick opcodes in IBV_INIT_CMD() doesn't break.
91	 */
92	IB_USER_VERBS_CMD_EXP_CREATE_WQ_V2 = -1,
93	IB_USER_VERBS_CMD_EXP_MODIFY_WQ_V2 = -1,
94	IB_USER_VERBS_CMD_EXP_DESTROY_WQ_V2 = -1,
95	IB_USER_VERBS_CMD_EXP_CREATE_RWQ_IND_TBL_V2 = -1,
96	IB_USER_VERBS_CMD_EXP_DESTROY_RWQ_IND_TBL_V2 = -1,
97};
98
99enum ibv_exp_create_qp_comp_mask {
100	IBV_EXP_CREATE_QP_CAP_FLAGS          = (1ULL << 0),
101	IBV_EXP_CREATE_QP_INL_RECV           = (1ULL << 1),
102	IBV_EXP_CREATE_QP_QPG                = (1ULL << 2),
103	IBV_EXP_CREATE_QP_MAX_INL_KLMS	     = (1ULL << 3)
104};
105
106struct ibv_create_qpg_init_attrib {
107	__u32 tss_child_count;
108	__u32 rss_child_count;
109};
110
111struct ibv_create_qpg {
112	__u32 qpg_type;
113	union {
114		struct {
115			__u32 parent_handle;
116			__u32 reserved;
117		};
118		struct ibv_create_qpg_init_attrib parent_attrib;
119	};
120	__u32 reserved2;
121};
122
123enum ibv_exp_create_qp_kernel_flags {
124	IBV_EXP_CREATE_QP_KERNEL_FLAGS = IBV_EXP_QP_CREATE_CROSS_CHANNEL  |
125					 IBV_EXP_QP_CREATE_MANAGED_SEND   |
126					 IBV_EXP_QP_CREATE_MANAGED_RECV   |
127					 IBV_EXP_QP_CREATE_ATOMIC_BE_REPLY |
128					 IBV_EXP_QP_CREATE_RX_END_PADDING |
129					 IBV_EXP_QP_CREATE_SCATTER_FCS
130};
131
132struct ibv_exp_create_qp {
133	struct ex_hdr hdr;
134	__u64 comp_mask;
135	__u64 user_handle;
136	__u32 pd_handle;
137	__u32 send_cq_handle;
138	__u32 recv_cq_handle;
139	__u32 srq_handle;
140	__u32 max_send_wr;
141	__u32 max_recv_wr;
142	__u32 max_send_sge;
143	__u32 max_recv_sge;
144	__u32 max_inline_data;
145	__u8  sq_sig_all;
146	__u8  qp_type;
147	__u8  is_srq;
148	__u8  reserved;
149	__u64 qp_cap_flags;
150	__u32 max_inl_recv;
151	__u32 reserved1;
152	struct ibv_create_qpg qpg;
153	__u64 max_inl_send_klms;
154	struct {
155		__u64 rx_hash_fields_mask;
156		__u32 rwq_ind_tbl_handle;
157		__u8 rx_hash_function;
158		__u8 rx_hash_key_len;
159		__u8 rx_hash_key[128];
160		__u16 reserved;
161	} rx_hash_info;
162	__u8 port_num;
163	__u8 reserved_2[7];
164	__u64 driver_data[0];
165};
166
167enum ibv_exp_create_qp_resp_comp_mask {
168	IBV_EXP_CREATE_QP_RESP_INL_RECV       = (1ULL << 0),
169};
170
171struct ibv_exp_create_qp_resp {
172	__u64 comp_mask;
173	__u32 qp_handle;
174	__u32 qpn;
175	__u32 max_send_wr;
176	__u32 max_recv_wr;
177	__u32 max_send_sge;
178	__u32 max_recv_sge;
179	__u32 max_inline_data;
180	__u32 max_inl_recv;
181};
182
183struct ibv_exp_umr_caps_resp {
184	__u32 max_klm_list_size;
185	__u32 max_send_wqe_inline_klms;
186	__u32 max_umr_recursion_depth;
187	__u32 max_umr_stride_dimension;
188};
189
190struct ibv_exp_odp_caps_resp {
191	__u64	general_odp_caps;
192	struct {
193		__u32	rc_odp_caps;
194		__u32	uc_odp_caps;
195		__u32	ud_odp_caps;
196		__u32	dc_odp_caps;
197		__u32	xrc_odp_caps;
198		__u32	raw_eth_odp_caps;
199	} per_transport_caps;
200};
201
202struct ibv_exp_query_device {
203	struct ex_hdr hdr;
204	__u64 comp_mask;
205	__u64 driver_data[0];
206};
207
208struct ibv_exp_rx_hash_caps_resp {
209	__u32	max_rwq_indirection_tables;
210	__u32	max_rwq_indirection_table_size;
211	__u64	supported_packet_fields;
212	__u32	supported_qps;
213	__u8	supported_hash_functions;
214	__u8	reserved[3];
215};
216
217struct ibv_exp_mp_rq_caps_resp {
218	__u32	supported_qps; /* use ibv_exp_supported_qp_types */
219	__u32	allowed_shifts; /* use ibv_exp_mp_rq_shifts */
220	__u8	min_single_wqe_log_num_of_strides;
221	__u8	max_single_wqe_log_num_of_strides;
222	__u8	min_single_stride_log_num_of_bytes;
223	__u8	max_single_stride_log_num_of_bytes;
224	__u32	reserved;
225};
226
227struct ibv_exp_ec_caps_resp {
228        __u32        max_ec_data_vector_count;
229        __u32        max_ec_calc_inflight_calcs;
230};
231
232struct ibv_exp_masked_atomic_caps {
233	__u32 max_fa_bit_boundary;
234	__u32 log_max_atomic_inline;
235	__u64 masked_log_atomic_arg_sizes;
236	__u64 masked_log_atomic_arg_sizes_network_endianness;
237};
238
239struct ibv_exp_lso_caps_resp {
240	__u32 max_tso;
241	__u32 supported_qpts;
242};
243
244struct ibv_exp_packet_pacing_caps_resp {
245	__u32 qp_rate_limit_min;
246	__u32 qp_rate_limit_max; /* In kbps */
247	__u32 supported_qpts;
248	__u32 reserved;
249};
250
251struct ibv_exp_query_device_resp {
252	__u64 comp_mask;
253	__u64 fw_ver;
254	__u64 node_guid;
255	__u64 sys_image_guid;
256	__u64 max_mr_size;
257	__u64 page_size_cap;
258	__u32 vendor_id;
259	__u32 vendor_part_id;
260	__u32 hw_ver;
261	__u32 max_qp;
262	__u32 max_qp_wr;
263	__u32 device_cap_flags;
264	__u32 max_sge;
265	__u32 max_sge_rd;
266	__u32 max_cq;
267	__u32 max_cqe;
268	__u32 max_mr;
269	__u32 max_pd;
270	__u32 max_qp_rd_atom;
271	__u32 max_ee_rd_atom;
272	__u32 max_res_rd_atom;
273	__u32 max_qp_init_rd_atom;
274	__u32 max_ee_init_rd_atom;
275	__u32 exp_atomic_cap;
276	__u32 max_ee;
277	__u32 max_rdd;
278	__u32 max_mw;
279	__u32 max_raw_ipv6_qp;
280	__u32 max_raw_ethy_qp;
281	__u32 max_mcast_grp;
282	__u32 max_mcast_qp_attach;
283	__u32 max_total_mcast_qp_attach;
284	__u32 max_ah;
285	__u32 max_fmr;
286	__u32 max_map_per_fmr;
287	__u32 max_srq;
288	__u32 max_srq_wr;
289	__u32 max_srq_sge;
290	__u16 max_pkeys;
291	__u8  local_ca_ack_delay;
292	__u8  phys_port_cnt;
293	__u8  reserved[4];
294	__u64 timestamp_mask;
295	__u64 hca_core_clock;
296	__u64 device_cap_flags2;
297	__u32 dc_rd_req;
298	__u32 dc_rd_res;
299	__u32 inline_recv_sz;
300	__u32 max_rss_tbl_sz;
301	__u64 log_atomic_arg_sizes;
302	__u32 max_fa_bit_boundary;
303	__u32 log_max_atomic_inline;
304	struct ibv_exp_umr_caps_resp umr_caps;
305	struct ibv_exp_odp_caps_resp odp_caps;
306	__u32 max_dct;
307	__u32 max_ctx_res_domain;
308	struct ibv_exp_rx_hash_caps_resp rx_hash;
309	__u32 max_wq_type_rq;
310	__u32 max_device_ctx;
311	struct ibv_exp_mp_rq_caps_resp mp_rq_caps;
312	__u16 wq_vlan_offloads_cap;
313	__u8 reserved1[2];
314	__u32 ec_w_mask;
315	struct ibv_exp_ec_caps_resp ec_caps;
316	struct ibv_exp_masked_atomic_caps masked_atomic_caps;
317	__u16 rx_pad_end_addr_align;
318	__u8 reserved2[6];
319	struct ibv_exp_lso_caps_resp tso_caps;
320	struct ibv_exp_packet_pacing_caps_resp packet_pacing_caps;
321};
322
323struct ibv_exp_create_dct {
324	struct ex_hdr hdr;
325	__u64 comp_mask;
326	__u64 user_handle;
327	__u32 pd_handle;
328	__u32 cq_handle;
329	__u32 srq_handle;
330	__u32 access_flags;
331	__u64 dc_key;
332	__u32 flow_label;
333	__u8  min_rnr_timer;
334	__u8  tclass;
335	__u8  port;
336	__u8  pkey_index;
337	__u8  gid_index;
338	__u8  hop_limit;
339	__u8  mtu;
340	__u8  rsvd0;
341	__u32 create_flags;
342	__u32 inline_size;
343	__u32 rsvd1;
344	__u64 driver_data[0];
345};
346
347struct ibv_exp_create_dct_resp {
348	__u32 dct_handle;
349	__u32 dct_num;
350	__u32 inline_size;
351	__u32 rsvd;
352};
353
354struct ibv_exp_destroy_dct {
355	struct ex_hdr hdr;
356	__u64 comp_mask;
357	__u32 dct_handle;
358	__u32 rsvd;
359	__u64 driver_data[0];
360};
361
362struct ibv_exp_destroy_dct_resp {
363	__u32	events_reported;
364	__u32	reserved;
365};
366
367struct ibv_exp_query_dct {
368	struct ex_hdr hdr;
369	__u64 comp_mask;
370	__u32 dct_handle;
371	__u32 reserved;
372	__u64 driver_data[0];
373};
374
375struct ibv_exp_query_dct_resp {
376	__u64	dc_key;
377	__u32	access_flags;
378	__u32	flow_label;
379	__u32	key_violations;
380	__u8	port;
381	__u8	min_rnr_timer;
382	__u8	tclass;
383	__u8	mtu;
384	__u8	pkey_index;
385	__u8	gid_index;
386	__u8	hop_limit;
387	__u8	state;
388	__u32	rsvd;
389	__u64	driver_data[0];
390};
391
392struct ibv_exp_arm_dct {
393	struct ex_hdr hdr;
394	__u64 comp_mask;
395	__u32 dct_handle;
396	__u32 reserved;
397	__u64 driver_data[0];
398};
399
400struct ibv_exp_arm_dct_resp {
401	__u64	reserved;
402};
403
404struct ibv_exp_modify_cq {
405	struct ex_hdr hdr;
406	__u32 cq_handle;
407	__u32 attr_mask;
408	__u16 cq_count;
409	__u16 cq_period;
410	__u32 cq_cap_flags;
411	__u32 comp_mask;
412	__u32 rsvd;
413};
414
415struct ibv_exp_modify_qp {
416	struct ex_hdr hdr;
417	__u32 comp_mask;
418	struct ibv_qp_dest dest;
419	struct ibv_qp_dest alt_dest;
420	__u32 qp_handle;
421	__u32 attr_mask;
422	__u32 qkey;
423	__u32 rq_psn;
424	__u32 sq_psn;
425	__u32 dest_qp_num;
426	__u32 qp_access_flags;
427	__u16 pkey_index;
428	__u16 alt_pkey_index;
429	__u8  qp_state;
430	__u8  cur_qp_state;
431	__u8  path_mtu;
432	__u8  path_mig_state;
433	__u8  en_sqd_async_notify;
434	__u8  max_rd_atomic;
435	__u8  max_dest_rd_atomic;
436	__u8  min_rnr_timer;
437	__u8  port_num;
438	__u8  timeout;
439	__u8  retry_cnt;
440	__u8  rnr_retry;
441	__u8  alt_port_num;
442	__u8  alt_timeout;
443	__u8  reserved[6];
444	__u64 dct_key;
445	__u32 exp_attr_mask;
446	__u32 flow_entropy;
447	__u32 rate_limit;
448	__u32 reserved1;
449	__u64 driver_data[0];
450};
451
452enum ibv_exp_create_cq_comp_mask {
453	IBV_EXP_CREATE_CQ_CAP_FLAGS	= (uint64_t)1 << 0,
454};
455
456struct ibv_exp_create_cq {
457	struct ex_hdr hdr;
458	__u64 comp_mask;
459	__u64 user_handle;
460	__u32 cqe;
461	__u32 comp_vector;
462	__s32 comp_channel;
463	__u32 reserved;
464	__u64 create_flags;
465	__u64 driver_data[0];
466};
467
468struct ibv_exp_create_mr {
469	struct ex_hdr hdr;
470	__u64 comp_mask;
471	__u32 pd_handle;
472	__u32 max_klm_list_size;
473	__u64 exp_access_flags;
474	__u32 create_flags;
475	__u32 reserved;
476	__u64 driver_data[0];
477};
478
479struct ibv_exp_create_mr_resp {
480	__u64 comp_mask;
481	__u32 handle;
482	__u32 lkey;
483	__u32 rkey;
484	__u32 reserved;
485	__u64 driver_data[0];
486};
487
488struct ibv_exp_query_mkey {
489	struct ex_hdr hdr;
490	__u64 comp_mask;
491	__u32 handle;
492	__u32 lkey;
493	__u32 rkey;
494	__u32 reserved;
495	__u64 driver_data[0];
496};
497
498struct ibv_exp_query_mkey_resp {
499	__u64 comp_mask;
500	__u32 max_klm_list_size;
501	__u32 reserved;
502	__u64 driver_data[0];
503};
504
505enum ibv_exp_reg_mr_comp_mask {
506	IBV_EXP_REG_MR_EXP_ACCESS_FLAGS = 1ULL << 0,
507};
508
509struct ibv_exp_reg_mr {
510	struct ex_hdr hdr;
511	__u64 start;
512	__u64 length;
513	__u64 hca_va;
514	__u32 pd_handle;
515	__u32 reserved;
516	__u64 exp_access_flags;
517	__u64 comp_mask;
518};
519
520struct ibv_exp_prefetch_mr {
521	struct ex_hdr hdr;
522	__u64 comp_mask;
523	__u32 mr_handle;
524	__u32 flags;
525	__u64 start;
526	__u64 length;
527};
528
529struct ibv_exp_reg_mr_resp {
530	__u32 mr_handle;
531	__u32 lkey;
532	__u32 rkey;
533	__u32 reserved;
534	__u64 comp_mask;
535};
536
537struct ibv_exp_rereg_mr {
538	struct ex_hdr hdr;
539	__u32 comp_mask;
540	__u32 mr_handle;
541	__u32 flags;
542	__u32 reserved;
543	__u64 start;
544	__u64 length;
545	__u64 hca_va;
546	__u32 pd_handle;
547	__u32 access_flags;
548};
549
550struct ibv_exp_rereg_mr_resp {
551	__u32 comp_mask;
552	__u32 lkey;
553	__u32 rkey;
554	__u32 reserved;
555};
556
557struct ibv_exp_cmd_wq_mp_rq {
558	__u32 use_shift; /* use ibv_exp_mp_rq_shifts */
559	__u8  single_wqe_log_num_of_strides;
560	__u8  single_stride_log_num_of_bytes;
561	__u16 reserved;
562};
563
564enum ibv_exp_cmd_create_wq_comp_mask {
565	IBV_EXP_CMD_CREATE_WQ_MP_RQ		= 1 << 0,
566	IBV_EXP_CMD_CREATE_WQ_VLAN_OFFLOADS	= 1 << 1,
567	IBV_EXP_CMD_CREATE_WQ_FLAGS		= 1 << 2,
568};
569
570struct ibv_exp_create_wq {
571	struct ex_hdr hdr;
572	__u32 comp_mask; /* enum ibv_exp_cmd_create_wq_comp_mask */
573	__u32 wq_type; /* enum ibv_exp_wq_type */
574	__u64 user_handle;
575	__u32 pd_handle;
576	__u32 cq_handle;
577	__u32 max_recv_wr;
578	__u32 max_recv_sge;
579};
580
581struct ibv_exp_create_wq_resp {
582	__u32 comp_mask;
583	__u32 response_length;
584	__u32 wq_handle;
585	__u32 max_recv_wr;
586	__u32 max_recv_sge;
587	__u32 wqn;
588};
589
590struct ib_exp_destroy_wq {
591	struct ex_hdr hdr;
592	__u32 comp_mask;
593	__u32 wq_handle;
594};
595
596struct ibv_destroy_wq_resp {
597	__u32 comp_mask;
598	__u32 response_length;
599	__u32 events_reported;
600	__u32 reserved;
601};
602
603struct ib_exp_modify_wq  {
604	struct ex_hdr hdr;
605	__u32 comp_mask;
606	__u32 wq_handle;
607	__u32 wq_state;
608	__u32 curr_wq_state;
609};
610
611struct ibv_exp_create_rwq_ind_table {
612	struct ex_hdr hdr;
613	__u32 comp_mask;
614	__u32 log_ind_tbl_size;
615	/* Following are wq handles based on log_ind_tbl_size, must be 64 bytes aligned.
616	 * __u32 wq_handle1
617	 * __u32 wq_handle2
618	 */
619};
620
621struct ibv_exp_create_rwq_ind_table_resp {
622	__u32 comp_mask;
623	__u32 response_length;
624	__u32 ind_tbl_handle;
625	__u32 ind_tbl_num;
626};
627
628struct ibv_exp_destroy_rwq_ind_table {
629	struct ex_hdr hdr;
630	__u32 comp_mask;
631	__u32 ind_tbl_handle;
632};
633
634struct ibv_exp_kern_ipv6_filter {
635	__u8 src_ip[16];
636	__u8 dst_ip[16];
637};
638
639struct ibv_exp_kern_spec_ipv6 {
640	__u32  type;
641	__u16  size;
642	__u16 reserved;
643	struct ibv_exp_kern_ipv6_filter val;
644	struct ibv_exp_kern_ipv6_filter mask;
645};
646
647struct ibv_exp_kern_ipv6_ext_filter {
648	__u8 src_ip[16];
649	__u8 dst_ip[16];
650	__u32 flow_label;
651	__u8  next_hdr;
652	__u8  traffic_class;
653	__u8  hop_limit;
654	__u8  reserved;
655};
656
657struct ibv_exp_kern_spec_ipv6_ext {
658	__u32  type;
659	__u16  size;
660	__u16 reserved;
661	struct ibv_exp_kern_ipv6_ext_filter val;
662	struct ibv_exp_kern_ipv6_ext_filter mask;
663};
664
665struct ibv_exp_kern_ipv4_ext_filter {
666	__u32 src_ip;
667	__u32 dst_ip;
668	__u8  proto;
669	__u8  tos;
670	__u8  ttl;
671	__u8  flags;
672};
673
674struct ibv_exp_kern_spec_ipv4_ext {
675	__u32  type;
676	__u16  size;
677	__u16 reserved;
678	struct ibv_exp_kern_ipv4_ext_filter val;
679	struct ibv_exp_kern_ipv4_ext_filter mask;
680};
681
682struct ibv_exp_kern_tunnel_filter {
683	__u32 tunnel_id;
684};
685
686struct ibv_exp_kern_spec_tunnel {
687	__u32  type;
688	__u16  size;
689	__u16 reserved;
690	struct ibv_exp_kern_tunnel_filter val;
691	struct ibv_exp_kern_tunnel_filter mask;
692};
693
694struct ibv_exp_kern_spec_action_tag {
695	__u32  type;
696	__u16  size;
697	__u16 reserved;
698	__u32 tag_id;
699	__u32 reserved1;
700};
701
702struct ibv_exp_kern_spec {
703	union {
704		struct {
705			__u32 type;
706			__u16 size;
707			__u16 reserved;
708		} hdr;
709		struct ibv_kern_spec_ib ib;
710		struct ibv_kern_spec_eth eth;
711		struct ibv_kern_spec_ipv4 ipv4;
712		struct ibv_exp_kern_spec_ipv4_ext ipv4_ext;
713		struct ibv_kern_spec_tcp_udp tcp_udp;
714		struct ibv_exp_kern_spec_ipv6 ipv6;
715		struct ibv_exp_kern_spec_ipv6_ext ipv6_ext;
716		struct ibv_exp_kern_spec_tunnel tunnel;
717		struct ibv_exp_kern_spec_action_tag flow_tag;
718	};
719};
720#endif /* KERN_ABI_EXP_H */
721