1/*-
2 * GPL LICENSE SUMMARY
3 *
4 *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 *
6 *   This program is free software; you can redistribute it and/or modify
7 *   it under the terms of version 2 of the GNU General Public License as
8 *   published by the Free Software Foundation.
9 *
10 *   This program is distributed in the hope that it will be useful, but
11 *   WITHOUT ANY WARRANTY; without even the implied warranty of
12 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13 *   General Public License for more details.
14 *
15 *   You should have received a copy of the GNU General Public License
16 *   along with this program; if not, write to the Free Software
17 *   Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *   The full GNU General Public License is included in this distribution
19 *   in the file called LICENSE.GPL.
20 *
21 *   Contact Information:
22 *   Intel Corporation
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/device.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/uio_driver.h>
31#include <linux/io.h>
32#include <linux/msi.h>
33#include <linux/version.h>
34#include <linux/slab.h>
35
36#ifdef CONFIG_XEN_DOM0
37#include <xen/xen.h>
38#endif
39#include "rte_pci_dev_features.h"
40
41#include "compat.h"
42
43/**
44 * A structure describing the private information for a uio device.
45 */
46struct rte_uio_pci_dev {
47	struct uio_info info;
48	struct pci_dev *pdev;
49	enum rte_intr_mode mode;
50};
51
52static char *intr_mode;
53static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
54
55/* sriov sysfs */
56static ssize_t
57show_max_vfs(struct device *dev, struct device_attribute *attr,
58	     char *buf)
59{
60	return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
61}
62
63static ssize_t
64store_max_vfs(struct device *dev, struct device_attribute *attr,
65	      const char *buf, size_t count)
66{
67	int err = 0;
68	unsigned long max_vfs;
69	struct pci_dev *pdev = to_pci_dev(dev);
70
71	if (0 != kstrtoul(buf, 0, &max_vfs))
72		return -EINVAL;
73
74	if (0 == max_vfs)
75		pci_disable_sriov(pdev);
76	else if (0 == pci_num_vf(pdev))
77		err = pci_enable_sriov(pdev, max_vfs);
78	else /* do nothing if change max_vfs number */
79		err = -EINVAL;
80
81	return err ? err : count;
82}
83
84#ifdef RTE_PCI_CONFIG
85static ssize_t
86show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
87{
88	dev_info(dev, "Deprecated\n");
89
90	return 0;
91}
92
93static ssize_t
94store_extended_tag(struct device *dev,
95		   struct device_attribute *attr,
96		   const char *buf,
97		   size_t count)
98{
99	dev_info(dev, "Deprecated\n");
100
101	return 0;
102}
103
104static ssize_t
105show_max_read_request_size(struct device *dev,
106			   struct device_attribute *attr,
107			   char *buf)
108{
109	dev_info(dev, "Deprecated\n");
110
111	return 0;
112}
113
114static ssize_t
115store_max_read_request_size(struct device *dev,
116			    struct device_attribute *attr,
117			    const char *buf,
118			    size_t count)
119{
120	dev_info(dev, "Deprecated\n");
121
122	return 0;
123}
124#endif
125
126static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
127#ifdef RTE_PCI_CONFIG
128static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
129	store_extended_tag);
130static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
131	show_max_read_request_size, store_max_read_request_size);
132#endif
133
134static struct attribute *dev_attrs[] = {
135	&dev_attr_max_vfs.attr,
136#ifdef RTE_PCI_CONFIG
137	&dev_attr_extended_tag.attr,
138	&dev_attr_max_read_request_size.attr,
139#endif
140	NULL,
141};
142
143static const struct attribute_group dev_attr_grp = {
144	.attrs = dev_attrs,
145};
146/*
147 * It masks the msix on/off of generating MSI-X messages.
148 */
149static void
150igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
151{
152	u32 mask_bits = desc->masked;
153	unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
154						PCI_MSIX_ENTRY_VECTOR_CTRL;
155
156	if (state != 0)
157		mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
158	else
159		mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
160
161	if (mask_bits != desc->masked) {
162		writel(mask_bits, desc->mask_base + offset);
163		readl(desc->mask_base);
164		desc->masked = mask_bits;
165	}
166}
167
168/**
169 * This is the irqcontrol callback to be registered to uio_info.
170 * It can be used to disable/enable interrupt from user space processes.
171 *
172 * @param info
173 *  pointer to uio_info.
174 * @param irq_state
175 *  state value. 1 to enable interrupt, 0 to disable interrupt.
176 *
177 * @return
178 *  - On success, 0.
179 *  - On failure, a negative value.
180 */
181static int
182igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
183{
184	struct rte_uio_pci_dev *udev = info->priv;
185	struct pci_dev *pdev = udev->pdev;
186
187	pci_cfg_access_lock(pdev);
188	if (udev->mode == RTE_INTR_MODE_LEGACY)
189		pci_intx(pdev, !!irq_state);
190
191	else if (udev->mode == RTE_INTR_MODE_MSIX) {
192		struct msi_desc *desc;
193
194#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
195		list_for_each_entry(desc, &pdev->msi_list, list)
196			igbuio_msix_mask_irq(desc, irq_state);
197#else
198		list_for_each_entry(desc, &pdev->dev.msi_list, list)
199			igbuio_msix_mask_irq(desc, irq_state);
200#endif
201	}
202	pci_cfg_access_unlock(pdev);
203
204	return 0;
205}
206
207/**
208 * This is interrupt handler which will check if the interrupt is for the right device.
209 * If yes, disable it here and will be enable later.
210 */
211static irqreturn_t
212igbuio_pci_irqhandler(int irq, struct uio_info *info)
213{
214	struct rte_uio_pci_dev *udev = info->priv;
215
216	/* Legacy mode need to mask in hardware */
217	if (udev->mode == RTE_INTR_MODE_LEGACY &&
218	    !pci_check_and_mask_intx(udev->pdev))
219		return IRQ_NONE;
220
221	/* Message signal mode, no share IRQ and automasked */
222	return IRQ_HANDLED;
223}
224
225#ifdef CONFIG_XEN_DOM0
226static int
227igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
228{
229	int idx;
230
231	idx = (int)vma->vm_pgoff;
232	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
233#ifdef HAVE_PTE_MASK_PAGE_IOMAP
234	vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
235#endif
236
237	return remap_pfn_range(vma,
238			vma->vm_start,
239			info->mem[idx].addr >> PAGE_SHIFT,
240			vma->vm_end - vma->vm_start,
241			vma->vm_page_prot);
242}
243
244/**
245 * This is uio device mmap method which will use igbuio mmap for Xen
246 * Dom0 environment.
247 */
248static int
249igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
250{
251	int idx;
252
253	if (vma->vm_pgoff >= MAX_UIO_MAPS)
254		return -EINVAL;
255
256	if (info->mem[vma->vm_pgoff].size == 0)
257		return -EINVAL;
258
259	idx = (int)vma->vm_pgoff;
260	switch (info->mem[idx].memtype) {
261	case UIO_MEM_PHYS:
262		return igbuio_dom0_mmap_phys(info, vma);
263	case UIO_MEM_LOGICAL:
264	case UIO_MEM_VIRTUAL:
265	default:
266		return -EINVAL;
267	}
268}
269#endif
270
271/* Remap pci resources described by bar #pci_bar in uio resource n. */
272static int
273igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
274		       int n, int pci_bar, const char *name)
275{
276	unsigned long addr, len;
277	void *internal_addr;
278
279	if (n >= ARRAY_SIZE(info->mem))
280		return -EINVAL;
281
282	addr = pci_resource_start(dev, pci_bar);
283	len = pci_resource_len(dev, pci_bar);
284	if (addr == 0 || len == 0)
285		return -1;
286	internal_addr = ioremap(addr, len);
287	if (internal_addr == NULL)
288		return -1;
289	info->mem[n].name = name;
290	info->mem[n].addr = addr;
291	info->mem[n].internal_addr = internal_addr;
292	info->mem[n].size = len;
293	info->mem[n].memtype = UIO_MEM_PHYS;
294	return 0;
295}
296
297/* Get pci port io resources described by bar #pci_bar in uio resource n. */
298static int
299igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
300		int n, int pci_bar, const char *name)
301{
302	unsigned long addr, len;
303
304	if (n >= ARRAY_SIZE(info->port))
305		return -EINVAL;
306
307	addr = pci_resource_start(dev, pci_bar);
308	len = pci_resource_len(dev, pci_bar);
309	if (addr == 0 || len == 0)
310		return -EINVAL;
311
312	info->port[n].name = name;
313	info->port[n].start = addr;
314	info->port[n].size = len;
315	info->port[n].porttype = UIO_PORT_X86;
316
317	return 0;
318}
319
320/* Unmap previously ioremap'd resources */
321static void
322igbuio_pci_release_iomem(struct uio_info *info)
323{
324	int i;
325
326	for (i = 0; i < MAX_UIO_MAPS; i++) {
327		if (info->mem[i].internal_addr)
328			iounmap(info->mem[i].internal_addr);
329	}
330}
331
332static int
333igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
334{
335	int i, iom, iop, ret;
336	unsigned long flags;
337	static const char *bar_names[PCI_STD_RESOURCE_END + 1]  = {
338		"BAR0",
339		"BAR1",
340		"BAR2",
341		"BAR3",
342		"BAR4",
343		"BAR5",
344	};
345
346	iom = 0;
347	iop = 0;
348
349	for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
350		if (pci_resource_len(dev, i) != 0 &&
351				pci_resource_start(dev, i) != 0) {
352			flags = pci_resource_flags(dev, i);
353			if (flags & IORESOURCE_MEM) {
354				ret = igbuio_pci_setup_iomem(dev, info, iom,
355							     i, bar_names[i]);
356				if (ret != 0)
357					return ret;
358				iom++;
359			} else if (flags & IORESOURCE_IO) {
360				ret = igbuio_pci_setup_ioport(dev, info, iop,
361							      i, bar_names[i]);
362				if (ret != 0)
363					return ret;
364				iop++;
365			}
366		}
367	}
368
369	return (iom != 0) ? ret : -ENOENT;
370}
371
372#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
373static int __devinit
374#else
375static int
376#endif
377igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
378{
379	struct rte_uio_pci_dev *udev;
380	struct msix_entry msix_entry;
381	int err;
382
383	udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
384	if (!udev)
385		return -ENOMEM;
386
387	/*
388	 * enable device: ask low-level code to enable I/O and
389	 * memory
390	 */
391	err = pci_enable_device(dev);
392	if (err != 0) {
393		dev_err(&dev->dev, "Cannot enable PCI device\n");
394		goto fail_free;
395	}
396
397	/*
398	 * reserve device's PCI memory regions for use by this
399	 * module
400	 */
401	err = pci_request_regions(dev, "igb_uio");
402	if (err != 0) {
403		dev_err(&dev->dev, "Cannot request regions\n");
404		goto fail_disable;
405	}
406
407	/* enable bus mastering on the device */
408	pci_set_master(dev);
409
410	/* remap IO memory */
411	err = igbuio_setup_bars(dev, &udev->info);
412	if (err != 0)
413		goto fail_release_iomem;
414
415	/* set 64-bit DMA mask */
416	err = pci_set_dma_mask(dev,  DMA_BIT_MASK(64));
417	if (err != 0) {
418		dev_err(&dev->dev, "Cannot set DMA mask\n");
419		goto fail_release_iomem;
420	}
421
422	err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
423	if (err != 0) {
424		dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
425		goto fail_release_iomem;
426	}
427
428	/* fill uio infos */
429	udev->info.name = "igb_uio";
430	udev->info.version = "0.1";
431	udev->info.handler = igbuio_pci_irqhandler;
432	udev->info.irqcontrol = igbuio_pci_irqcontrol;
433#ifdef CONFIG_XEN_DOM0
434	/* check if the driver run on Xen Dom0 */
435	if (xen_initial_domain())
436		udev->info.mmap = igbuio_dom0_pci_mmap;
437#endif
438	udev->info.priv = udev;
439	udev->pdev = dev;
440
441	switch (igbuio_intr_mode_preferred) {
442	case RTE_INTR_MODE_MSIX:
443		/* Only 1 msi-x vector needed */
444		msix_entry.entry = 0;
445		if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
446			dev_dbg(&dev->dev, "using MSI-X");
447			udev->info.irq = msix_entry.vector;
448			udev->mode = RTE_INTR_MODE_MSIX;
449			break;
450		}
451		/* fall back to INTX */
452	case RTE_INTR_MODE_LEGACY:
453		if (pci_intx_mask_supported(dev)) {
454			dev_dbg(&dev->dev, "using INTX");
455			udev->info.irq_flags = IRQF_SHARED;
456			udev->info.irq = dev->irq;
457			udev->mode = RTE_INTR_MODE_LEGACY;
458			break;
459		}
460		dev_notice(&dev->dev, "PCI INTX mask not supported\n");
461		/* fall back to no IRQ */
462	case RTE_INTR_MODE_NONE:
463		udev->mode = RTE_INTR_MODE_NONE;
464		udev->info.irq = 0;
465		break;
466
467	default:
468		dev_err(&dev->dev, "invalid IRQ mode %u",
469			igbuio_intr_mode_preferred);
470		err = -EINVAL;
471		goto fail_release_iomem;
472	}
473
474	err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
475	if (err != 0)
476		goto fail_release_iomem;
477
478	/* register uio driver */
479	err = uio_register_device(&dev->dev, &udev->info);
480	if (err != 0)
481		goto fail_remove_group;
482
483	pci_set_drvdata(dev, udev);
484
485	dev_info(&dev->dev, "uio device registered with irq %lx\n",
486		 udev->info.irq);
487
488	return 0;
489
490fail_remove_group:
491	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
492fail_release_iomem:
493	igbuio_pci_release_iomem(&udev->info);
494	if (udev->mode == RTE_INTR_MODE_MSIX)
495		pci_disable_msix(udev->pdev);
496	pci_release_regions(dev);
497fail_disable:
498	pci_disable_device(dev);
499fail_free:
500	kfree(udev);
501
502	return err;
503}
504
505static void
506igbuio_pci_remove(struct pci_dev *dev)
507{
508	struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
509
510	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
511	uio_unregister_device(&udev->info);
512	igbuio_pci_release_iomem(&udev->info);
513	if (udev->mode == RTE_INTR_MODE_MSIX)
514		pci_disable_msix(dev);
515	pci_release_regions(dev);
516	pci_disable_device(dev);
517	pci_set_drvdata(dev, NULL);
518	kfree(udev);
519}
520
521static int
522igbuio_config_intr_mode(char *intr_str)
523{
524	if (!intr_str) {
525		pr_info("Use MSIX interrupt by default\n");
526		return 0;
527	}
528
529	if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
530		igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
531		pr_info("Use MSIX interrupt\n");
532	} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
533		igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
534		pr_info("Use legacy interrupt\n");
535	} else {
536		pr_info("Error: bad parameter - %s\n", intr_str);
537		return -EINVAL;
538	}
539
540	return 0;
541}
542
543static struct pci_driver igbuio_pci_driver = {
544	.name = "igb_uio",
545	.id_table = NULL,
546	.probe = igbuio_pci_probe,
547	.remove = igbuio_pci_remove,
548};
549
550static int __init
551igbuio_pci_init_module(void)
552{
553	int ret;
554
555	ret = igbuio_config_intr_mode(intr_mode);
556	if (ret < 0)
557		return ret;
558
559	return pci_register_driver(&igbuio_pci_driver);
560}
561
562static void __exit
563igbuio_pci_exit_module(void)
564{
565	pci_unregister_driver(&igbuio_pci_driver);
566}
567
568module_init(igbuio_pci_init_module);
569module_exit(igbuio_pci_exit_module);
570
571module_param(intr_mode, charp, S_IRUGO);
572MODULE_PARM_DESC(intr_mode,
573"igb_uio interrupt mode (default=msix):\n"
574"    " RTE_INTR_MODE_MSIX_NAME "       Use MSIX interrupt\n"
575"    " RTE_INTR_MODE_LEGACY_NAME "     Use Legacy interrupt\n"
576"\n");
577
578MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
579MODULE_LICENSE("GPL");
580MODULE_AUTHOR("Intel Corporation");
581