1/*-
2 * Copyright (c) 2007-2013 Broadcom Corporation.
3 *
4 * Eric Davis        <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano     <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
11 * www.qlogic.com
12 *
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
14 */
15
16#define BNX2X_DRIVER_VERSION "1.78.18"
17
18#include "bnx2x.h"
19#include "bnx2x_vfpf.h"
20#include "ecore_sp.h"
21#include "ecore_init.h"
22#include "ecore_init_ops.h"
23
24#include "rte_version.h"
25
26#include <sys/types.h>
27#include <sys/stat.h>
28#include <fcntl.h>
29#include <zlib.h>
30
31#define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32#define BNX2X_PMD_VERSION_MAJOR 1
33#define BNX2X_PMD_VERSION_MINOR 0
34#define BNX2X_PMD_VERSION_REVISION 5
35#define BNX2X_PMD_VERSION_PATCH 1
36
37static inline const char *
38bnx2x_pmd_version(void)
39{
40	static char version[32];
41
42	snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
43			BNX2X_PMD_VER_PREFIX,
44			BNX2X_DRIVER_VERSION,
45			BNX2X_PMD_VERSION_MAJOR,
46			BNX2X_PMD_VERSION_MINOR,
47			BNX2X_PMD_VERSION_REVISION,
48			BNX2X_PMD_VERSION_PATCH);
49
50	return version;
51}
52
53static z_stream zlib_stream;
54
55#define EVL_VLID_MASK 0x0FFF
56
57#define BNX2X_DEF_SB_ATT_IDX 0x0001
58#define BNX2X_DEF_SB_IDX     0x0002
59
60/*
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
63 */
64#define FLR_WAIT_USEC     10000	/* 10 msecs */
65#define FLR_WAIT_INTERVAL 50	/* usecs */
66#define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)	/* 200 */
67
68struct pbf_pN_buf_regs {
69	int pN;
70	uint32_t init_crd;
71	uint32_t crd;
72	uint32_t crd_freed;
73};
74
75struct pbf_pN_cmd_regs {
76	int pN;
77	uint32_t lines_occup;
78	uint32_t lines_freed;
79};
80
81/* resources needed for unloading a previously loaded device */
82
83#define BNX2X_PREV_WAIT_NEEDED 1
84rte_spinlock_t bnx2x_prev_mtx;
85struct bnx2x_prev_list_node {
86	LIST_ENTRY(bnx2x_prev_list_node) node;
87	uint8_t bus;
88	uint8_t slot;
89	uint8_t path;
90	uint8_t aer;
91	uint8_t undi;
92};
93
94static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95	= LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96
97static int load_count[2][3] = { { 0 } };
98	/* per-path: 0-common, 1-port0, 2-port1 */
99
100static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101				uint8_t cmng_type);
102static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104			      uint8_t port);
105static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110				     uint8_t print);
111static void bnx2x_int_disable(struct bnx2x_softc *sc);
112static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115				 struct bnx2x_fastpath *fp,
116				 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117static void bnx2x_link_report(struct bnx2x_softc *sc);
118void bnx2x_link_status_update(struct bnx2x_softc *sc);
119static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120static void bnx2x_free_mem(struct bnx2x_softc *sc);
121static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123static __attribute__ ((noinline))
124int bnx2x_nic_load(struct bnx2x_softc *sc);
125
126static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
128static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
129static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
130			 uint8_t storm, uint16_t index, uint8_t op,
131			 uint8_t update);
132
133int bnx2x_test_bit(int nr, volatile unsigned long *addr)
134{
135	int res;
136
137	mb();
138	res = ((*addr) & (1UL << nr)) != 0;
139	mb();
140	return res;
141}
142
143void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144{
145	__sync_fetch_and_or(addr, (1UL << nr));
146}
147
148void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149{
150	__sync_fetch_and_and(addr, ~(1UL << nr));
151}
152
153int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154{
155	unsigned long mask = (1UL << nr);
156	return __sync_fetch_and_and(addr, ~mask) & mask;
157}
158
159int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160{
161	return __sync_val_compare_and_swap(addr, old, new);
162}
163
164int
165bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
166	      const char *msg, uint32_t align)
167{
168	char mz_name[RTE_MEMZONE_NAMESIZE];
169	const struct rte_memzone *z;
170
171	dma->sc = sc;
172	if (IS_PF(sc))
173		sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
174			rte_get_timer_cycles());
175	else
176		sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
177			rte_get_timer_cycles());
178
179	/* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
180	z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
181					SOCKET_ID_ANY,
182					0, align);
183	if (z == NULL) {
184		PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
185		return -ENOMEM;
186	}
187	dma->paddr = (uint64_t) z->phys_addr;
188	dma->vaddr = z->addr;
189
190	PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
191
192	return 0;
193}
194
195static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196{
197	uint32_t lock_status;
198	uint32_t resource_bit = (1 << resource);
199	int func = SC_FUNC(sc);
200	uint32_t hw_lock_control_reg;
201	int cnt;
202
203	PMD_INIT_FUNC_TRACE();
204
205	/* validate the resource is within range */
206	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
207		PMD_DRV_LOG(NOTICE,
208			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
209			    resource);
210		return -1;
211	}
212
213	if (func <= 5) {
214		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
215	} else {
216		hw_lock_control_reg =
217		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
218	}
219
220	/* validate the resource is not already taken */
221	lock_status = REG_RD(sc, hw_lock_control_reg);
222	if (lock_status & resource_bit) {
223		PMD_DRV_LOG(NOTICE,
224			    "resource in use (status 0x%x bit 0x%x)",
225			    lock_status, resource_bit);
226		return -1;
227	}
228
229	/* try every 5ms for 5 seconds */
230	for (cnt = 0; cnt < 1000; cnt++) {
231		REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
232		lock_status = REG_RD(sc, hw_lock_control_reg);
233		if (lock_status & resource_bit) {
234			return 0;
235		}
236		DELAY(5000);
237	}
238
239	PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
240	return -1;
241}
242
243static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
244{
245	uint32_t lock_status;
246	uint32_t resource_bit = (1 << resource);
247	int func = SC_FUNC(sc);
248	uint32_t hw_lock_control_reg;
249
250	PMD_INIT_FUNC_TRACE();
251
252	/* validate the resource is within range */
253	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254		PMD_DRV_LOG(NOTICE,
255			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
256			    resource);
257		return -1;
258	}
259
260	if (func <= 5) {
261		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
262	} else {
263		hw_lock_control_reg =
264		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
265	}
266
267	/* validate the resource is currently taken */
268	lock_status = REG_RD(sc, hw_lock_control_reg);
269	if (!(lock_status & resource_bit)) {
270		PMD_DRV_LOG(NOTICE,
271			    "resource not in use (status 0x%x bit 0x%x)",
272			    lock_status, resource_bit);
273		return -1;
274	}
275
276	REG_WR(sc, hw_lock_control_reg, resource_bit);
277	return 0;
278}
279
280/* copy command into DMAE command memory and set DMAE command Go */
281void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
282{
283	uint32_t cmd_offset;
284	uint32_t i;
285
286	cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
287	for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
288		REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
289	}
290
291	REG_WR(sc, dmae_reg_go_c[idx], 1);
292}
293
294uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
295{
296	return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
297			  DMAE_COMMAND_C_TYPE_ENABLE);
298}
299
300uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
301{
302	return opcode & ~DMAE_COMMAND_SRC_RESET;
303}
304
305uint32_t
306bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
307		uint8_t with_comp, uint8_t comp_type)
308{
309	uint32_t opcode = 0;
310
311	opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
312		   (dst_type << DMAE_COMMAND_DST_SHIFT));
313
314	opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
315
316	opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
317
318	opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
319		   (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
320
321	opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
322
323#ifdef __BIG_ENDIAN
324	opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
325#else
326	opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
327#endif
328
329	if (with_comp) {
330		opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
331	}
332
333	return opcode;
334}
335
336static void
337bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
338			uint8_t src_type, uint8_t dst_type)
339{
340	memset(dmae, 0, sizeof(struct dmae_command));
341
342	/* set the opcode */
343	dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
344				       TRUE, DMAE_COMP_PCI);
345
346	/* fill in the completion parameters */
347	dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
348	dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
349	dmae->comp_val = DMAE_COMP_VAL;
350}
351
352/* issue a DMAE command over the init channel and wait for completion */
353static int
354bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
355{
356	uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
357	int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
358
359	/* reset completion */
360	*wb_comp = 0;
361
362	/* post the command on the channel used for initializations */
363	bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
364
365	/* wait for completion */
366	DELAY(500);
367
368	while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
369		if (!timeout ||
370		    (sc->recovery_state != BNX2X_RECOVERY_DONE &&
371		     sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
372			PMD_DRV_LOG(INFO, "DMAE timeout!");
373			return DMAE_TIMEOUT;
374		}
375
376		timeout--;
377		DELAY(50);
378	}
379
380	if (*wb_comp & DMAE_PCI_ERR_FLAG) {
381		PMD_DRV_LOG(INFO, "DMAE PCI error!");
382		return DMAE_PCI_ERROR;
383	}
384
385	return 0;
386}
387
388void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
389{
390	struct dmae_command dmae;
391	uint32_t *data;
392	uint32_t i;
393	int rc;
394
395	if (!sc->dmae_ready) {
396		data = BNX2X_SP(sc, wb_data[0]);
397
398		for (i = 0; i < len32; i++) {
399			data[i] = REG_RD(sc, (src_addr + (i * 4)));
400		}
401
402		return;
403	}
404
405	/* set opcode and fixed command fields */
406	bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
407
408	/* fill in addresses and len */
409	dmae.src_addr_lo = (src_addr >> 2);	/* GRC addr has dword resolution */
410	dmae.src_addr_hi = 0;
411	dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
412	dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
413	dmae.len = len32;
414
415	/* issue the command and wait for completion */
416	if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
417		rte_panic("DMAE failed (%d)", rc);
418	};
419}
420
421void
422bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
423	       uint32_t len32)
424{
425	struct dmae_command dmae;
426	int rc;
427
428	if (!sc->dmae_ready) {
429		ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
430		return;
431	}
432
433	/* set opcode and fixed command fields */
434	bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
435
436	/* fill in addresses and len */
437	dmae.src_addr_lo = U64_LO(dma_addr);
438	dmae.src_addr_hi = U64_HI(dma_addr);
439	dmae.dst_addr_lo = (dst_addr >> 2);	/* GRC addr has dword resolution */
440	dmae.dst_addr_hi = 0;
441	dmae.len = len32;
442
443	/* issue the command and wait for completion */
444	if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
445		rte_panic("DMAE failed (%d)", rc);
446	}
447}
448
449static void
450bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
451			uint32_t addr, uint32_t len)
452{
453	uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
454	uint32_t offset = 0;
455
456	while (len > dmae_wr_max) {
457		bnx2x_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
458			       (addr + offset),	/* dst GRC address */
459			       dmae_wr_max);
460		offset += (dmae_wr_max * 4);
461		len -= dmae_wr_max;
462	}
463
464	bnx2x_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
465		       (addr + offset),	/* dst GRC address */
466		       len);
467}
468
469void
470bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
471		       uint32_t cid)
472{
473	/* ustorm cxt validation */
474	cxt->ustorm_ag_context.cdu_usage =
475	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
476				   CDU_REGION_NUMBER_UCM_AG,
477				   ETH_CONNECTION_TYPE);
478	/* xcontext validation */
479	cxt->xstorm_ag_context.cdu_reserved =
480	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
481				   CDU_REGION_NUMBER_XCM_AG,
482				   ETH_CONNECTION_TYPE);
483}
484
485static void
486bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
487			    uint8_t sb_index, uint8_t ticks)
488{
489	uint32_t addr =
490	    (BAR_CSTRORM_INTMEM +
491	     CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
492
493	REG_WR8(sc, addr, ticks);
494}
495
496static void
497bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
498			    uint8_t sb_index, uint8_t disable)
499{
500	uint32_t enable_flag =
501	    (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
502	uint32_t addr =
503	    (BAR_CSTRORM_INTMEM +
504	     CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
505	uint8_t flags;
506
507	/* clear and set */
508	flags = REG_RD8(sc, addr);
509	flags &= ~HC_INDEX_DATA_HC_ENABLED;
510	flags |= enable_flag;
511	REG_WR8(sc, addr, flags);
512}
513
514void
515bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
516			     uint8_t sb_index, uint8_t disable, uint16_t usec)
517{
518	uint8_t ticks = (usec / 4);
519
520	bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
521
522	disable = (disable) ? 1 : ((usec) ? 0 : 1);
523	bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
524}
525
526uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
527{
528	return REG_RD(sc, reg_addr);
529}
530
531void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
532{
533	REG_WR(sc, reg_addr, val);
534}
535
536void
537elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
538		   __rte_unused const elink_log_id_t elink_log_id, ...)
539{
540	PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
541}
542
543static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
544{
545	uint32_t spio_reg;
546
547	/* Only 2 SPIOs are configurable */
548	if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
549		PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
550		return -1;
551	}
552
553	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
554
555	/* read SPIO and mask except the float bits */
556	spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
557
558	switch (mode) {
559	case MISC_SPIO_OUTPUT_LOW:
560		/* clear FLOAT and set CLR */
561		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
562		spio_reg |= (spio << MISC_SPIO_CLR_POS);
563		break;
564
565	case MISC_SPIO_OUTPUT_HIGH:
566		/* clear FLOAT and set SET */
567		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
568		spio_reg |= (spio << MISC_SPIO_SET_POS);
569		break;
570
571	case MISC_SPIO_INPUT_HI_Z:
572		/* set FLOAT */
573		spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
574		break;
575
576	default:
577		break;
578	}
579
580	REG_WR(sc, MISC_REG_SPIO, spio_reg);
581	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
582
583	return 0;
584}
585
586static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
587{
588	/* The GPIO should be swapped if swap register is set and active */
589	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
590			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
591	int gpio_shift = gpio_num;
592	if (gpio_port)
593		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
594
595	uint32_t gpio_mask = (1 << gpio_shift);
596	uint32_t gpio_reg;
597
598	if (gpio_num > MISC_REGISTERS_GPIO_3) {
599		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
600		return -1;
601	}
602
603	/* read GPIO value */
604	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
605
606	/* get the requested pin value */
607	return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
608}
609
610static int
611bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
612{
613	/* The GPIO should be swapped if swap register is set and active */
614	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
615			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
616	int gpio_shift = gpio_num;
617	if (gpio_port)
618		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
619
620	uint32_t gpio_mask = (1 << gpio_shift);
621	uint32_t gpio_reg;
622
623	if (gpio_num > MISC_REGISTERS_GPIO_3) {
624		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
625		return -1;
626	}
627
628	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
629
630	/* read GPIO and mask except the float bits */
631	gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
632
633	switch (mode) {
634	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
635		/* clear FLOAT and set CLR */
636		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
637		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
638		break;
639
640	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
641		/* clear FLOAT and set SET */
642		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
643		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
644		break;
645
646	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
647		/* set FLOAT */
648		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
649		break;
650
651	default:
652		break;
653	}
654
655	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
656	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
657
658	return 0;
659}
660
661static int
662bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
663{
664	uint32_t gpio_reg;
665
666	/* any port swapping should be handled by caller */
667
668	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
669
670	/* read GPIO and mask except the float bits */
671	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
672	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
673	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
674	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
675
676	switch (mode) {
677	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
678		/* set CLR */
679		gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
680		break;
681
682	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
683		/* set SET */
684		gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
685		break;
686
687	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
688		/* set FLOAT */
689		gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
690		break;
691
692	default:
693		PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
694		bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
695		return -1;
696	}
697
698	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
699	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
700
701	return 0;
702}
703
704static int
705bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
706		   uint8_t port)
707{
708	/* The GPIO should be swapped if swap register is set and active */
709	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
710			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
711	int gpio_shift = gpio_num;
712	if (gpio_port)
713		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714
715	uint32_t gpio_mask = (1 << gpio_shift);
716	uint32_t gpio_reg;
717
718	if (gpio_num > MISC_REGISTERS_GPIO_3) {
719		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
720		return -1;
721	}
722
723	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
724
725	/* read GPIO int */
726	gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
727
728	switch (mode) {
729	case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
730		/* clear SET and set CLR */
731		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
732		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
733		break;
734
735	case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
736		/* clear CLR and set SET */
737		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
738		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
739		break;
740
741	default:
742		break;
743	}
744
745	REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
746	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
747
748	return 0;
749}
750
751uint32_t
752elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753{
754	return bnx2x_gpio_read(sc, gpio_num, port);
755}
756
757uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
758			    uint8_t port)
759{
760	return bnx2x_gpio_write(sc, gpio_num, mode, port);
761}
762
763uint8_t
764elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
765			 uint8_t mode /* 0=low 1=high */ )
766{
767	return bnx2x_gpio_mult_write(sc, pins, mode);
768}
769
770uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
771				uint8_t port)
772{
773	return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
774}
775
776void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777{
778	REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
779		    (SC_FUNC(sc) * sizeof(uint32_t))), 1);
780}
781
782/* send the MCP a request, block until there is a reply */
783uint32_t
784elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785{
786	int mb_idx = SC_FW_MB_IDX(sc);
787	uint32_t seq;
788	uint32_t rc = 0;
789	uint32_t cnt = 1;
790	uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
791
792	seq = ++sc->fw_seq;
793	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
794	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
795
796	PMD_DRV_LOG(DEBUG,
797		    "wrote command 0x%08x to FW MB param 0x%08x",
798		    (command | seq), param);
799
800	/* Let the FW do it's magic. GIve it up to 5 seconds... */
801	do {
802		DELAY(delay * 1000);
803		rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
804	} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805
806	/* is this a reply to our command? */
807	if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
808		rc &= FW_MSG_CODE_MASK;
809	} else {
810		/* Ruh-roh! */
811		PMD_DRV_LOG(NOTICE, "FW failed to respond!");
812		rc = 0;
813	}
814
815	return rc;
816}
817
818static uint32_t
819bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820{
821	return elink_cb_fw_command(sc, command, param);
822}
823
824static void
825__storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
826			   phys_addr_t mapping)
827{
828	REG_WR(sc, addr, U64_LO(mapping));
829	REG_WR(sc, (addr + 4), U64_HI(mapping));
830}
831
832static void
833storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
834		      uint16_t abs_fid)
835{
836	uint32_t addr = (XSEM_REG_FAST_MEMORY +
837			 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
838	__storm_memset_dma_mapping(sc, addr, mapping);
839}
840
841static void
842storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843{
844	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845		pf_id);
846	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847		pf_id);
848	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849		pf_id);
850	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
851		pf_id);
852}
853
854static void
855storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856{
857	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858		enable);
859	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860		enable);
861	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862		enable);
863	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
864		enable);
865}
866
867static void
868storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
869		     uint16_t pfid)
870{
871	uint32_t addr;
872	size_t size;
873
874	addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
875	size = sizeof(struct event_ring_data);
876	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
877}
878
879static void
880storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881{
882	uint32_t addr = (BAR_CSTRORM_INTMEM +
883			 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
884	REG_WR16(sc, addr, eq_prod);
885}
886
887/*
888 * Post a slowpath command.
889 *
890 * A slowpath command is used to propogate a configuration change through
891 * the controller in a controlled manner, allowing each STORM processor and
892 * other H/W blocks to phase in the change.  The commands sent on the
893 * slowpath are referred to as ramrods.  Depending on the ramrod used the
894 * completion of the ramrod will occur in different ways.  Here's a
895 * breakdown of ramrods and how they complete:
896 *
897 * RAMROD_CMD_ID_ETH_PORT_SETUP
898 *   Used to setup the leading connection on a port.  Completes on the
899 *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 *
901 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
902 *   Used to setup an additional connection on a port.  Completes on the
903 *   RCQ of the multi-queue/RSS connection being initialized.
904 *
905 * RAMROD_CMD_ID_ETH_STAT_QUERY
906 *   Used to force the storm processors to update the statistics database
907 *   in host memory.  This ramrod is send on the leading connection CID and
908 *   completes as an index increment of the CSTORM on the default status
909 *   block.
910 *
911 * RAMROD_CMD_ID_ETH_UPDATE
912 *   Used to update the state of the leading connection, usually to udpate
913 *   the RSS indirection table.  Completes on the RCQ of the leading
914 *   connection. (Not currently used under FreeBSD until OS support becomes
915 *   available.)
916 *
917 * RAMROD_CMD_ID_ETH_HALT
918 *   Used when tearing down a connection prior to driver unload.  Completes
919 *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
920 *   use this on the leading connection.
921 *
922 * RAMROD_CMD_ID_ETH_SET_MAC
923 *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
924 *   the RCQ of the leading connection.
925 *
926 * RAMROD_CMD_ID_ETH_CFC_DEL
927 *   Used when tearing down a conneciton prior to driver unload.  Completes
928 *   on the RCQ of the leading connection (since the current connection
929 *   has been completely removed from controller memory).
930 *
931 * RAMROD_CMD_ID_ETH_PORT_DEL
932 *   Used to tear down the leading connection prior to driver unload,
933 *   typically fp[0].  Completes as an index increment of the CSTORM on the
934 *   default status block.
935 *
936 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
937 *   Used for connection offload.  Completes on the RCQ of the multi-queue
938 *   RSS connection that is being offloaded.  (Not currently used under
939 *   FreeBSD.)
940 *
941 * There can only be one command pending per function.
942 *
943 * Returns:
944 *   0 = Success, !0 = Failure.
945 */
946
947/* must be called under the spq lock */
948static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949{
950	struct eth_spe *next_spe = sc->spq_prod_bd;
951
952	if (sc->spq_prod_bd == sc->spq_last_bd) {
953		/* wrap back to the first eth_spq */
954		sc->spq_prod_bd = sc->spq;
955		sc->spq_prod_idx = 0;
956	} else {
957		sc->spq_prod_bd++;
958		sc->spq_prod_idx++;
959	}
960
961	return next_spe;
962}
963
964/* must be called under the spq lock */
965static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966{
967	int func = SC_FUNC(sc);
968
969	/*
970	 * Make sure that BD data is updated before writing the producer.
971	 * BD data is written to the memory, the producer is read from the
972	 * memory, thus we need a full memory barrier to ensure the ordering.
973	 */
974	mb();
975
976	REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
977		 sc->spq_prod_idx);
978
979	mb();
980}
981
982/**
983 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 *
985 * @cmd:      command to check
986 * @cmd_type: command type
987 */
988static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989{
990	if ((cmd_type == NONE_CONNECTION_TYPE) ||
991	    (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
992	    (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
993	    (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
994	    (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
995	    (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
996	    (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
997		return TRUE;
998	} else {
999		return FALSE;
1000	}
1001}
1002
1003/**
1004 * bnx2x_sp_post - place a single command on an SP ring
1005 *
1006 * @sc:         driver handle
1007 * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008 * @cid:        SW CID the command is related to
1009 * @data_hi:    command private data address (high 32 bits)
1010 * @data_lo:    command private data address (low 32 bits)
1011 * @cmd_type:   command type (e.g. NONE, ETH)
1012 *
1013 * SP data is handled as if it's always an address pair, thus data fields are
1014 * not swapped to little endian in upper functions. Instead this function swaps
1015 * data as if it's two uint32 fields.
1016 */
1017int
1018bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019	    uint32_t data_lo, int cmd_type)
1020{
1021	struct eth_spe *spe;
1022	uint16_t type;
1023	int common;
1024
1025	common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027	if (common) {
1028		if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029			PMD_DRV_LOG(INFO, "EQ ring is full!");
1030			return -1;
1031		}
1032	} else {
1033		if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034			PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035			return -1;
1036		}
1037	}
1038
1039	spe = bnx2x_sp_get_next(sc);
1040
1041	/* CID needs port number to be encoded int it */
1042	spe->hdr.conn_and_cmd_data =
1043	    htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045	type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047	/* TBD: Check if it works for VFs */
1048	type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049		 SPE_HDR_FUNCTION_ID);
1050
1051	spe->hdr.type = htole16(type);
1052
1053	spe->data.update_data_addr.hi = htole32(data_hi);
1054	spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056	/*
1057	 * It's ok if the actual decrement is issued towards the memory
1058	 * somewhere between the lock and unlock. Thus no more explict
1059	 * memory barrier is needed.
1060	 */
1061	if (common) {
1062		atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063	} else {
1064		atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065	}
1066
1067	PMD_DRV_LOG(DEBUG,
1068		    "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069		    "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070		    sc->spq_prod_idx,
1071		    (uint32_t) U64_HI(sc->spq_dma.paddr),
1072		    (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073				(uint8_t *) sc->spq_prod_bd -
1074				(uint8_t *) sc->spq), command, common,
1075		    HW_CID(sc, cid), data_hi, data_lo, type,
1076		    atomic_load_acq_long(&sc->cq_spq_left),
1077		    atomic_load_acq_long(&sc->eq_spq_left));
1078
1079	bnx2x_sp_prod_update(sc);
1080
1081	return 0;
1082}
1083
1084static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085{
1086	SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087		 sc->fw_drv_pulse_wr_seq);
1088}
1089
1090static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091{
1092	uint16_t hw_cons;
1093	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095	if (unlikely(!txq)) {
1096		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097		return 0;
1098	}
1099
1100	mb();			/* status block fields can change */
1101	hw_cons = le16toh(*fp->tx_cons_sb);
1102	return hw_cons != txq->tx_pkt_head;
1103}
1104
1105static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106{
1107	/* expand this for multi-cos if ever supported */
1108	return bnx2x_tx_queue_has_work(fp);
1109}
1110
1111static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112{
1113	uint16_t rx_cq_cons_sb;
1114	struct bnx2x_rx_queue *rxq;
1115	rxq = fp->sc->rx_queues[fp->index];
1116	if (unlikely(!rxq)) {
1117		PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118		return 0;
1119	}
1120
1121	mb();			/* status block fields can change */
1122	rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123	if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124		     MAX_RCQ_ENTRIES(rxq)))
1125		rx_cq_cons_sb++;
1126	return rxq->rx_cq_head != rx_cq_cons_sb;
1127}
1128
1129static void
1130bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131	     union eth_rx_cqe *rr_cqe)
1132{
1133#ifdef RTE_LIBRTE_BNX2X_DEBUG
1134	int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135#endif
1136	int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1137	enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1138	struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1139
1140	PMD_DRV_LOG(DEBUG,
1141		    "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1142		    fp->index, cid, command, sc->state,
1143		    rr_cqe->ramrod_cqe.ramrod_type);
1144
1145	switch (command) {
1146	case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1147		PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1148		drv_cmd = ECORE_Q_CMD_UPDATE;
1149		break;
1150
1151	case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1152		PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1153		drv_cmd = ECORE_Q_CMD_SETUP;
1154		break;
1155
1156	case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1157		PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1158		drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1159		break;
1160
1161	case (RAMROD_CMD_ID_ETH_HALT):
1162		PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1163		drv_cmd = ECORE_Q_CMD_HALT;
1164		break;
1165
1166	case (RAMROD_CMD_ID_ETH_TERMINATE):
1167		PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1168		drv_cmd = ECORE_Q_CMD_TERMINATE;
1169		break;
1170
1171	case (RAMROD_CMD_ID_ETH_EMPTY):
1172		PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1173		drv_cmd = ECORE_Q_CMD_EMPTY;
1174		break;
1175
1176	default:
1177		PMD_DRV_LOG(DEBUG,
1178			    "ERROR: unexpected MC reply (%d)"
1179			    "on fp[%d]", command, fp->index);
1180		return;
1181	}
1182
1183	if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1184	    q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185		/*
1186		 * q_obj->complete_cmd() failure means that this was
1187		 * an unexpected completion.
1188		 *
1189		 * In this case we don't want to increase the sc->spq_left
1190		 * because apparently we haven't sent this command the first
1191		 * place.
1192		 */
1193		// rte_panic("Unexpected SP completion");
1194		return;
1195	}
1196
1197	atomic_add_acq_long(&sc->cq_spq_left, 1);
1198
1199	PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1200		    atomic_load_acq_long(&sc->cq_spq_left));
1201}
1202
1203static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204{
1205	struct bnx2x_rx_queue *rxq;
1206	uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1207	uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208
1209	rxq = sc->rx_queues[fp->index];
1210	if (!rxq) {
1211		PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1212		return 0;
1213	}
1214
1215	/* CQ "next element" is of the size of the regular element */
1216	hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1217	if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1218		     USABLE_RCQ_ENTRIES_PER_PAGE)) {
1219		hw_cq_cons++;
1220	}
1221
1222	bd_cons = rxq->rx_bd_head;
1223	bd_prod = rxq->rx_bd_tail;
1224	bd_prod_fw = bd_prod;
1225	sw_cq_cons = rxq->rx_cq_head;
1226	sw_cq_prod = rxq->rx_cq_tail;
1227
1228	/*
1229	 * Memory barrier necessary as speculative reads of the rx
1230	 * buffer can be ahead of the index in the status block
1231	 */
1232	rmb();
1233
1234	while (sw_cq_cons != hw_cq_cons) {
1235		union eth_rx_cqe *cqe;
1236		struct eth_fast_path_rx_cqe *cqe_fp;
1237		uint8_t cqe_fp_flags;
1238		enum eth_rx_cqe_type cqe_fp_type;
1239
1240		comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1241		bd_prod = RX_BD(bd_prod, rxq);
1242		bd_cons = RX_BD(bd_cons, rxq);
1243
1244		cqe = &rxq->cq_ring[comp_ring_cons];
1245		cqe_fp = &cqe->fast_path_cqe;
1246		cqe_fp_flags = cqe_fp->type_error_flags;
1247		cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248
1249		/* is this a slowpath msg? */
1250		if (CQE_TYPE_SLOW(cqe_fp_type)) {
1251			bnx2x_sp_event(sc, fp, cqe);
1252			goto next_cqe;
1253		}
1254
1255		/* is this an error packet? */
1256		if (unlikely(cqe_fp_flags &
1257			     ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1258			PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1259				   cqe_fp_flags, sw_cq_cons);
1260			goto next_rx;
1261		}
1262
1263		PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1264
1265next_rx:
1266		bd_cons = NEXT_RX_BD(bd_cons);
1267		bd_prod = NEXT_RX_BD(bd_prod);
1268		bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1269
1270next_cqe:
1271		sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1272		sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273
1274	}			/* while work to do */
1275
1276	rxq->rx_bd_head = bd_cons;
1277	rxq->rx_bd_tail = bd_prod_fw;
1278	rxq->rx_cq_head = sw_cq_cons;
1279	rxq->rx_cq_tail = sw_cq_prod;
1280
1281	/* Update producers */
1282	bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283
1284	return sw_cq_cons != hw_cq_cons;
1285}
1286
1287static uint16_t
1288bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1289		uint16_t pkt_idx, uint16_t bd_idx)
1290{
1291	struct eth_tx_start_bd *tx_start_bd =
1292	    &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1293	uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1294	struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295
1296	if (likely(tx_mbuf != NULL)) {
1297		rte_pktmbuf_free_seg(tx_mbuf);
1298	} else {
1299		PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1300			   fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1301	}
1302
1303	txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1304	txq->nb_tx_avail += nbd;
1305
1306	while (nbd--)
1307		bd_idx = NEXT_TX_BD(bd_idx);
1308
1309	return bd_idx;
1310}
1311
1312/* processes transmit completions */
1313uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314{
1315	uint16_t bd_cons, hw_cons, sw_cons;
1316	__rte_unused uint16_t tx_bd_avail;
1317
1318	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319
1320	if (unlikely(!txq)) {
1321		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1322		return 0;
1323	}
1324
1325	bd_cons = txq->tx_bd_head;
1326	hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1327	sw_cons = txq->tx_pkt_head;
1328
1329	while (sw_cons != hw_cons) {
1330		bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1331		sw_cons++;
1332	}
1333
1334	txq->tx_pkt_head = sw_cons;
1335	txq->tx_bd_head = bd_cons;
1336
1337	tx_bd_avail = txq->nb_tx_avail;
1338
1339	PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1340		   "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1341		   fp->index, tx_bd_avail, hw_cons,
1342		   txq->tx_pkt_head, txq->tx_pkt_tail,
1343		   txq->tx_bd_head, txq->tx_bd_tail);
1344	return TRUE;
1345}
1346
1347static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348{
1349	struct bnx2x_fastpath *fp;
1350	int i, count;
1351
1352	/* wait until all TX fastpath tasks have completed */
1353	for (i = 0; i < sc->num_queues; i++) {
1354		fp = &sc->fp[i];
1355
1356		count = 1000;
1357
1358		while (bnx2x_has_tx_work(fp)) {
1359			bnx2x_txeof(sc, fp);
1360
1361			if (count == 0) {
1362				PMD_TX_LOG(ERR,
1363					   "Timeout waiting for fp[%d] "
1364					   "transmits to complete!", i);
1365				rte_panic("tx drain failure");
1366				return;
1367			}
1368
1369			count--;
1370			DELAY(1000);
1371			rmb();
1372		}
1373	}
1374
1375	return;
1376}
1377
1378static int
1379bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1380		 int mac_type, uint8_t wait_for_comp)
1381{
1382	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1383	int rc;
1384
1385	/* wait for completion of requested */
1386	if (wait_for_comp) {
1387		bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1388	}
1389
1390	/* Set the mac type of addresses we want to clear */
1391	bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392
1393	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394	if (rc < 0)
1395		PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1396
1397	return rc;
1398}
1399
1400static int
1401bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1402			unsigned long *rx_accept_flags,
1403			unsigned long *tx_accept_flags)
1404{
1405	/* Clear the flags first */
1406	*rx_accept_flags = 0;
1407	*tx_accept_flags = 0;
1408
1409	switch (rx_mode) {
1410	case BNX2X_RX_MODE_NONE:
1411		/*
1412		 * 'drop all' supersedes any accept flags that may have been
1413		 * passed to the function.
1414		 */
1415		break;
1416
1417	case BNX2X_RX_MODE_NORMAL:
1418		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1419		bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1420		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421
1422		/* internal switching mode */
1423		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1424		bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1425		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1426
1427		break;
1428
1429	case BNX2X_RX_MODE_ALLMULTI:
1430		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1431		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1432		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433
1434		/* internal switching mode */
1435		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1436		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1437		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1438
1439		break;
1440
1441	case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1442	case BNX2X_RX_MODE_PROMISC:
1443		/*
1444		 * According to deffinition of SI mode, iface in promisc mode
1445		 * should receive matched and unmatched (in resolution of port)
1446		 * unicast packets.
1447		 */
1448		bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1449		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1450		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1451		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1452
1453		/* internal switching mode */
1454		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1455		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456
1457		if (IS_MF_SI(sc)) {
1458			bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1459		} else {
1460			bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1461		}
1462
1463		break;
1464
1465	default:
1466		PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1467		return -1;
1468	}
1469
1470	/* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1471	if (rx_mode != BNX2X_RX_MODE_NONE) {
1472		bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1473		bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1474	}
1475
1476	return 0;
1477}
1478
1479static int
1480bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1481		  unsigned long rx_mode_flags,
1482		  unsigned long rx_accept_flags,
1483		  unsigned long tx_accept_flags, unsigned long ramrod_flags)
1484{
1485	struct ecore_rx_mode_ramrod_params ramrod_param;
1486	int rc;
1487
1488	memset(&ramrod_param, 0, sizeof(ramrod_param));
1489
1490	/* Prepare ramrod parameters */
1491	ramrod_param.cid = 0;
1492	ramrod_param.cl_id = cl_id;
1493	ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1494	ramrod_param.func_id = SC_FUNC(sc);
1495
1496	ramrod_param.pstate = &sc->sp_state;
1497	ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1498
1499	ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1500	ramrod_param.rdata_mapping =
1501	    (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1502	    bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1503
1504	ramrod_param.ramrod_flags = ramrod_flags;
1505	ramrod_param.rx_mode_flags = rx_mode_flags;
1506
1507	ramrod_param.rx_accept_flags = rx_accept_flags;
1508	ramrod_param.tx_accept_flags = tx_accept_flags;
1509
1510	rc = ecore_config_rx_mode(sc, &ramrod_param);
1511	if (rc < 0) {
1512		PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1513		return rc;
1514	}
1515
1516	return 0;
1517}
1518
1519int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1520{
1521	unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1522	unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523	int rc;
1524
1525	rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1526				   &tx_accept_flags);
1527	if (rc) {
1528		return rc;
1529	}
1530
1531	bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1532	bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1533	bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1534
1535	return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1536				 rx_accept_flags, tx_accept_flags,
1537				 ramrod_flags);
1538}
1539
1540/* returns the "mcp load_code" according to global load_count array */
1541static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1542{
1543	int path = SC_PATH(sc);
1544	int port = SC_PORT(sc);
1545
1546	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1547		    path, load_count[path][0], load_count[path][1],
1548		    load_count[path][2]);
1549
1550	load_count[path][0]++;
1551	load_count[path][1 + port]++;
1552	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1553		    path, load_count[path][0], load_count[path][1],
1554		    load_count[path][2]);
1555	if (load_count[path][0] == 1)
1556		return FW_MSG_CODE_DRV_LOAD_COMMON;
1557	else if (load_count[path][1 + port] == 1)
1558		return FW_MSG_CODE_DRV_LOAD_PORT;
1559	else
1560		return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561}
1562
1563/* returns the "mcp load_code" according to global load_count array */
1564static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1565{
1566	int port = SC_PORT(sc);
1567	int path = SC_PATH(sc);
1568
1569	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1570		    path, load_count[path][0], load_count[path][1],
1571		    load_count[path][2]);
1572	load_count[path][0]--;
1573	load_count[path][1 + port]--;
1574	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1575		    path, load_count[path][0], load_count[path][1],
1576		    load_count[path][2]);
1577	if (load_count[path][0] == 0) {
1578		return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1579	} else if (load_count[path][1 + port] == 0) {
1580		return FW_MSG_CODE_DRV_UNLOAD_PORT;
1581	} else {
1582		return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1583	}
1584}
1585
1586/* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1587static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1588{
1589	uint32_t reset_code = 0;
1590
1591	/* Select the UNLOAD request mode */
1592	if (unload_mode == UNLOAD_NORMAL) {
1593		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594	} else {
1595		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596	}
1597
1598	/* Send the request to the MCP */
1599	if (!BNX2X_NOMCP(sc)) {
1600		reset_code = bnx2x_fw_command(sc, reset_code, 0);
1601	} else {
1602		reset_code = bnx2x_nic_unload_no_mcp(sc);
1603	}
1604
1605	return reset_code;
1606}
1607
1608/* send UNLOAD_DONE command to the MCP */
1609static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1610{
1611	uint32_t reset_param =
1612	    keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1613
1614	/* Report UNLOAD_DONE to MCP */
1615	if (!BNX2X_NOMCP(sc)) {
1616		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1617	}
1618}
1619
1620static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1621{
1622	int tout = 50;
1623
1624	if (!sc->port.pmf) {
1625		return 0;
1626	}
1627
1628	/*
1629	 * (assumption: No Attention from MCP at this stage)
1630	 * PMF probably in the middle of TX disable/enable transaction
1631	 * 1. Sync IRS for default SB
1632	 * 2. Sync SP queue - this guarantees us that attention handling started
1633	 * 3. Wait, that TX disable/enable transaction completes
1634	 *
1635	 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1636	 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1637	 * received completion for the transaction the state is TX_STOPPED.
1638	 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1639	 * transaction.
1640	 */
1641
1642	while (ecore_func_get_state(sc, &sc->func_obj) !=
1643	       ECORE_F_STATE_STARTED && tout--) {
1644		DELAY(20000);
1645	}
1646
1647	if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1648		/*
1649		 * Failed to complete the transaction in a "good way"
1650		 * Force both transactions with CLR bit.
1651		 */
1652		struct ecore_func_state_params func_params = { NULL };
1653
1654		PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1655			    "Forcing STARTED-->TX_STOPPED-->STARTED");
1656
1657		func_params.f_obj = &sc->func_obj;
1658		bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1659
1660		/* STARTED-->TX_STOPPED */
1661		func_params.cmd = ECORE_F_CMD_TX_STOP;
1662		ecore_func_state_change(sc, &func_params);
1663
1664		/* TX_STOPPED-->STARTED */
1665		func_params.cmd = ECORE_F_CMD_TX_START;
1666		return ecore_func_state_change(sc, &func_params);
1667	}
1668
1669	return 0;
1670}
1671
1672static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1673{
1674	struct bnx2x_fastpath *fp = &sc->fp[index];
1675	struct ecore_queue_state_params q_params = { NULL };
1676	int rc;
1677
1678	PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1679
1680	q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1681	/* We want to wait for completion in this context */
1682	bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1683
1684	/* Stop the primary connection: */
1685
1686	/* ...halt the connection */
1687	q_params.cmd = ECORE_Q_CMD_HALT;
1688	rc = ecore_queue_state_change(sc, &q_params);
1689	if (rc) {
1690		return rc;
1691	}
1692
1693	/* ...terminate the connection */
1694	q_params.cmd = ECORE_Q_CMD_TERMINATE;
1695	memset(&q_params.params.terminate, 0,
1696	       sizeof(q_params.params.terminate));
1697	q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1698	rc = ecore_queue_state_change(sc, &q_params);
1699	if (rc) {
1700		return rc;
1701	}
1702
1703	/* ...delete cfc entry */
1704	q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1705	memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1706	q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1707	return ecore_queue_state_change(sc, &q_params);
1708}
1709
1710/* wait for the outstanding SP commands */
1711static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712{
1713	unsigned long tmp;
1714	int tout = 5000;	/* wait for 5 secs tops */
1715
1716	while (tout--) {
1717		mb();
1718		if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1719			return TRUE;
1720		}
1721
1722		DELAY(1000);
1723	}
1724
1725	mb();
1726
1727	tmp = atomic_load_acq_long(&sc->sp_state);
1728	if (tmp & mask) {
1729		PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1730			    "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1731		return FALSE;
1732	}
1733
1734	return FALSE;
1735}
1736
1737static int bnx2x_func_stop(struct bnx2x_softc *sc)
1738{
1739	struct ecore_func_state_params func_params = { NULL };
1740	int rc;
1741
1742	/* prepare parameters for function state transitions */
1743	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1744	func_params.f_obj = &sc->func_obj;
1745	func_params.cmd = ECORE_F_CMD_STOP;
1746
1747	/*
1748	 * Try to stop the function the 'good way'. If it fails (in case
1749	 * of a parity error during bnx2x_chip_cleanup()) and we are
1750	 * not in a debug mode, perform a state transaction in order to
1751	 * enable further HW_RESET transaction.
1752	 */
1753	rc = ecore_func_state_change(sc, &func_params);
1754	if (rc) {
1755		PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1756			    "Running a dry transaction");
1757		bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1758		return ecore_func_state_change(sc, &func_params);
1759	}
1760
1761	return 0;
1762}
1763
1764static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1765{
1766	struct ecore_func_state_params func_params = { NULL };
1767
1768	/* Prepare parameters for function state transitions */
1769	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1770
1771	func_params.f_obj = &sc->func_obj;
1772	func_params.cmd = ECORE_F_CMD_HW_RESET;
1773
1774	func_params.params.hw_init.load_phase = load_code;
1775
1776	return ecore_func_state_change(sc, &func_params);
1777}
1778
1779static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780{
1781	if (disable_hw) {
1782		/* prevent the HW from sending interrupts */
1783		bnx2x_int_disable(sc);
1784	}
1785}
1786
1787static void
1788bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1789{
1790	int port = SC_PORT(sc);
1791	struct ecore_mcast_ramrod_params rparam = { NULL };
1792	uint32_t reset_code;
1793	int i, rc = 0;
1794
1795	bnx2x_drain_tx_queues(sc);
1796
1797	/* give HW time to discard old tx messages */
1798	DELAY(1000);
1799
1800	/* Clean all ETH MACs */
1801	rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802			      FALSE);
1803	if (rc < 0) {
1804		PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1805	}
1806
1807	/* Clean up UC list  */
1808	rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1809			      TRUE);
1810	if (rc < 0) {
1811		PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1812	}
1813
1814	/* Disable LLH */
1815	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1816
1817	/* Set "drop all" to stop Rx */
1818
1819	/*
1820	 * We need to take the if_maddr_lock() here in order to prevent
1821	 * a race between the completion code and this code.
1822	 */
1823
1824	if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825		bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1826	} else {
1827		bnx2x_set_storm_rx_mode(sc);
1828	}
1829
1830	/* Clean up multicast configuration */
1831	rparam.mcast_obj = &sc->mcast_obj;
1832	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833	if (rc < 0) {
1834		PMD_DRV_LOG(NOTICE,
1835			    "Failed to send DEL MCAST command (%d)", rc);
1836	}
1837
1838	/*
1839	 * Send the UNLOAD_REQUEST to the MCP. This will return if
1840	 * this function should perform FUNCTION, PORT, or COMMON HW
1841	 * reset.
1842	 */
1843	reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844
1845	/*
1846	 * (assumption: No Attention from MCP at this stage)
1847	 * PMF probably in the middle of TX disable/enable transaction
1848	 */
1849	rc = bnx2x_func_wait_started(sc);
1850	if (rc) {
1851		PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1852	}
1853
1854	/*
1855	 * Close multi and leading connections
1856	 * Completions for ramrods are collected in a synchronous way
1857	 */
1858	for (i = 0; i < sc->num_queues; i++) {
1859		if (bnx2x_stop_queue(sc, i)) {
1860			goto unload_error;
1861		}
1862	}
1863
1864	/*
1865	 * If SP settings didn't get completed so far - something
1866	 * very wrong has happen.
1867	 */
1868	if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869		PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1870	}
1871
1872unload_error:
1873
1874	rc = bnx2x_func_stop(sc);
1875	if (rc) {
1876		PMD_DRV_LOG(NOTICE, "Function stop failed!");
1877	}
1878
1879	/* disable HW interrupts */
1880	bnx2x_int_disable_sync(sc, TRUE);
1881
1882	/* Reset the chip */
1883	rc = bnx2x_reset_hw(sc, reset_code);
1884	if (rc) {
1885		PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1886	}
1887
1888	/* Report UNLOAD_DONE to MCP */
1889	bnx2x_send_unload_done(sc, keep_link);
1890}
1891
1892static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1893{
1894	uint32_t val;
1895
1896	PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1897
1898	val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899	val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900		 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901	REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1902}
1903
1904/*
1905 * Cleans the object that have internal lists without sending
1906 * ramrods. Should be run when interrutps are disabled.
1907 */
1908static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1909{
1910	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911	struct ecore_mcast_ramrod_params rparam = { NULL };
1912	struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913	int rc;
1914
1915	/* Cleanup MACs' object first... */
1916
1917	/* Wait for completion of requested */
1918	bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919	/* Perform a dry cleanup */
1920	bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1921
1922	/* Clean ETH primary MAC */
1923	bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924	rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925				 &ramrod_flags);
1926	if (rc != 0) {
1927		PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1928	}
1929
1930	/* Cleanup UC list */
1931	vlan_mac_flags = 0;
1932	bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1934	if (rc != 0) {
1935		PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1936	}
1937
1938	/* Now clean mcast object... */
1939
1940	rparam.mcast_obj = &sc->mcast_obj;
1941	bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1942
1943	/* Add a DEL command... */
1944	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1945	if (rc < 0) {
1946		PMD_DRV_LOG(NOTICE,
1947			    "Failed to send DEL MCAST command (%d)", rc);
1948	}
1949
1950	/* now wait until all pending commands are cleared */
1951
1952	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1953	while (rc != 0) {
1954		if (rc < 0) {
1955			PMD_DRV_LOG(NOTICE,
1956				    "Failed to clean MCAST object (%d)", rc);
1957			return;
1958		}
1959
1960		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1961	}
1962}
1963
1964/* stop the controller */
1965__attribute__ ((noinline))
1966int
1967bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1968{
1969	uint8_t global = FALSE;
1970	uint32_t val;
1971
1972	PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1973
1974	/* stop the periodic callout */
1975	bnx2x_periodic_stop(sc);
1976
1977	/* mark driver as unloaded in shmem2 */
1978	if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1979		val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1980		SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1981			  val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982	}
1983
1984	if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1985	    (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1986		/*
1987		 * We can get here if the driver has been unloaded
1988		 * during parity error recovery and is either waiting for a
1989		 * leader to complete or for other functions to unload and
1990		 * then ifconfig down has been issued. In this case we want to
1991		 * unload and let other functions to complete a recovery
1992		 * process.
1993		 */
1994		sc->recovery_state = BNX2X_RECOVERY_DONE;
1995		sc->is_leader = 0;
1996		bnx2x_release_leader_lock(sc);
1997		mb();
1998
1999		PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2000		return -1;
2001	}
2002
2003	/*
2004	 * Nothing to do during unload if previous bnx2x_nic_load()
2005	 * did not completed succesfully - all resourses are released.
2006	 */
2007	if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2008		return 0;
2009	}
2010
2011	sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012	mb();
2013
2014	sc->rx_mode = BNX2X_RX_MODE_NONE;
2015	bnx2x_set_rx_mode(sc);
2016	mb();
2017
2018	if (IS_PF(sc)) {
2019		/* set ALWAYS_ALIVE bit in shmem */
2020		sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2021
2022		bnx2x_drv_pulse(sc);
2023
2024		bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2025		bnx2x_save_statistics(sc);
2026	}
2027
2028	/* wait till consumers catch up with producers in all queues */
2029	bnx2x_drain_tx_queues(sc);
2030
2031	/* if VF indicate to PF this function is going down (PF will delete sp
2032	 * elements and clear initializations
2033	 */
2034	if (IS_VF(sc)) {
2035		bnx2x_vf_unload(sc);
2036	} else if (unload_mode != UNLOAD_RECOVERY) {
2037		/* if this is a normal/close unload need to clean up chip */
2038		bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2039	} else {
2040		/* Send the UNLOAD_REQUEST to the MCP */
2041		bnx2x_send_unload_req(sc, unload_mode);
2042
2043		/*
2044		 * Prevent transactions to host from the functions on the
2045		 * engine that doesn't reset global blocks in case of global
2046		 * attention once gloabl blocks are reset and gates are opened
2047		 * (the engine which leader will perform the recovery
2048		 * last).
2049		 */
2050		if (!CHIP_IS_E1x(sc)) {
2051			bnx2x_pf_disable(sc);
2052		}
2053
2054		/* disable HW interrupts */
2055		bnx2x_int_disable_sync(sc, TRUE);
2056
2057		/* Report UNLOAD_DONE to MCP */
2058		bnx2x_send_unload_done(sc, FALSE);
2059	}
2060
2061	/*
2062	 * At this stage no more interrupts will arrive so we may safely clean
2063	 * the queue'able objects here in case they failed to get cleaned so far.
2064	 */
2065	if (IS_PF(sc)) {
2066		bnx2x_squeeze_objects(sc);
2067	}
2068
2069	/* There should be no more pending SP commands at this stage */
2070	sc->sp_state = 0;
2071
2072	sc->port.pmf = 0;
2073
2074	if (IS_PF(sc)) {
2075		bnx2x_free_mem(sc);
2076	}
2077
2078	bnx2x_free_fw_stats_mem(sc);
2079
2080	sc->state = BNX2X_STATE_CLOSED;
2081
2082	/*
2083	 * Check if there are pending parity attentions. If there are - set
2084	 * RECOVERY_IN_PROGRESS.
2085	 */
2086	if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2087		bnx2x_set_reset_in_progress(sc);
2088
2089		/* Set RESET_IS_GLOBAL if needed */
2090		if (global) {
2091			bnx2x_set_reset_global(sc);
2092		}
2093	}
2094
2095	/*
2096	 * The last driver must disable a "close the gate" if there is no
2097	 * parity attention or "process kill" pending.
2098	 */
2099	if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2100	    bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2101		bnx2x_disable_close_the_gate(sc);
2102	}
2103
2104	PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2105
2106	return 0;
2107}
2108
2109/*
2110 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2111 * visible to the controller.
2112 *
2113 * If an mbuf is submitted to this routine and cannot be given to the
2114 * controller (e.g. it has too many fragments) then the function may free
2115 * the mbuf and return to the caller.
2116 *
2117 * Returns:
2118 *     int: Number of TX BDs used for the mbuf
2119 *
2120 *   Note the side effect that an mbuf may be freed if it causes a problem.
2121 */
2122int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2123{
2124	struct eth_tx_start_bd *tx_start_bd;
2125	uint16_t bd_prod, pkt_prod;
2126	struct bnx2x_softc *sc;
2127	uint32_t nbds = 0;
2128
2129	sc = txq->sc;
2130	bd_prod = txq->tx_bd_tail;
2131	pkt_prod = txq->tx_pkt_tail;
2132
2133	txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2134
2135	tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2136
2137	tx_start_bd->addr =
2138	    rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2139	tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2140	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2141	tx_start_bd->general_data =
2142	    (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2143
2144	tx_start_bd->nbd = rte_cpu_to_le_16(2);
2145
2146	if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2147		tx_start_bd->vlan_or_ethertype =
2148		    rte_cpu_to_le_16(m0->vlan_tci);
2149		tx_start_bd->bd_flags.as_bitfield |=
2150		    (X_ETH_OUTBAND_VLAN <<
2151		     ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2152	} else {
2153		if (IS_PF(sc))
2154			tx_start_bd->vlan_or_ethertype =
2155			    rte_cpu_to_le_16(pkt_prod);
2156		else {
2157			struct ether_hdr *eh =
2158			    rte_pktmbuf_mtod(m0, struct ether_hdr *);
2159
2160			tx_start_bd->vlan_or_ethertype =
2161			    rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2162		}
2163	}
2164
2165	bd_prod = NEXT_TX_BD(bd_prod);
2166	if (IS_VF(sc)) {
2167		struct eth_tx_parse_bd_e2 *tx_parse_bd;
2168		const struct ether_hdr *eh =
2169		    rte_pktmbuf_mtod(m0, struct ether_hdr *);
2170		uint8_t mac_type = UNICAST_ADDRESS;
2171
2172		tx_parse_bd =
2173		    &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2174		if (is_multicast_ether_addr(&eh->d_addr)) {
2175			if (is_broadcast_ether_addr(&eh->d_addr))
2176				mac_type = BROADCAST_ADDRESS;
2177			else
2178				mac_type = MULTICAST_ADDRESS;
2179		}
2180		tx_parse_bd->parsing_data =
2181		    (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2182
2183		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2184			   &eh->d_addr.addr_bytes[0], 2);
2185		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2186			   &eh->d_addr.addr_bytes[2], 2);
2187		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2188			   &eh->d_addr.addr_bytes[4], 2);
2189		rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2190			   &eh->s_addr.addr_bytes[0], 2);
2191		rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2192			   &eh->s_addr.addr_bytes[2], 2);
2193		rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2194			   &eh->s_addr.addr_bytes[4], 2);
2195
2196		tx_parse_bd->data.mac_addr.dst_hi =
2197		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2198		tx_parse_bd->data.mac_addr.dst_mid =
2199		    rte_cpu_to_be_16(tx_parse_bd->data.
2200				     mac_addr.dst_mid);
2201		tx_parse_bd->data.mac_addr.dst_lo =
2202		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2203		tx_parse_bd->data.mac_addr.src_hi =
2204		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2205		tx_parse_bd->data.mac_addr.src_mid =
2206		    rte_cpu_to_be_16(tx_parse_bd->data.
2207				     mac_addr.src_mid);
2208		tx_parse_bd->data.mac_addr.src_lo =
2209		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2210
2211		PMD_TX_LOG(DEBUG,
2212			   "PBD dst %x %x %x src %x %x %x p_data %x",
2213			   tx_parse_bd->data.mac_addr.dst_hi,
2214			   tx_parse_bd->data.mac_addr.dst_mid,
2215			   tx_parse_bd->data.mac_addr.dst_lo,
2216			   tx_parse_bd->data.mac_addr.src_hi,
2217			   tx_parse_bd->data.mac_addr.src_mid,
2218			   tx_parse_bd->data.mac_addr.src_lo,
2219			   tx_parse_bd->parsing_data);
2220	}
2221
2222	PMD_TX_LOG(DEBUG,
2223		   "start bd: nbytes %d flags %x vlan %x",
2224		   tx_start_bd->nbytes,
2225		   tx_start_bd->bd_flags.as_bitfield,
2226		   tx_start_bd->vlan_or_ethertype);
2227
2228	bd_prod = NEXT_TX_BD(bd_prod);
2229	pkt_prod++;
2230
2231	if (TX_IDX(bd_prod) < 2)
2232		nbds++;
2233
2234	txq->nb_tx_avail -= 2;
2235	txq->tx_bd_tail = bd_prod;
2236	txq->tx_pkt_tail = pkt_prod;
2237
2238	return nbds + 2;
2239}
2240
2241static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2242{
2243	return L2_ILT_LINES(sc);
2244}
2245
2246static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2247{
2248	struct ilt_client_info *ilt_client;
2249	struct ecore_ilt *ilt = sc->ilt;
2250	uint16_t line = 0;
2251
2252	PMD_INIT_FUNC_TRACE();
2253
2254	ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2255
2256	/* CDU */
2257	ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2258	ilt_client->client_num = ILT_CLIENT_CDU;
2259	ilt_client->page_size = CDU_ILT_PAGE_SZ;
2260	ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2261	ilt_client->start = line;
2262	line += bnx2x_cid_ilt_lines(sc);
2263
2264	if (CNIC_SUPPORT(sc)) {
2265		line += CNIC_ILT_LINES;
2266	}
2267
2268	ilt_client->end = (line - 1);
2269
2270	/* QM */
2271	if (QM_INIT(sc->qm_cid_count)) {
2272		ilt_client = &ilt->clients[ILT_CLIENT_QM];
2273		ilt_client->client_num = ILT_CLIENT_QM;
2274		ilt_client->page_size = QM_ILT_PAGE_SZ;
2275		ilt_client->flags = 0;
2276		ilt_client->start = line;
2277
2278		/* 4 bytes for each cid */
2279		line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2280				     QM_ILT_PAGE_SZ);
2281
2282		ilt_client->end = (line - 1);
2283	}
2284
2285	if (CNIC_SUPPORT(sc)) {
2286		/* SRC */
2287		ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2288		ilt_client->client_num = ILT_CLIENT_SRC;
2289		ilt_client->page_size = SRC_ILT_PAGE_SZ;
2290		ilt_client->flags = 0;
2291		ilt_client->start = line;
2292		line += SRC_ILT_LINES;
2293		ilt_client->end = (line - 1);
2294
2295		/* TM */
2296		ilt_client = &ilt->clients[ILT_CLIENT_TM];
2297		ilt_client->client_num = ILT_CLIENT_TM;
2298		ilt_client->page_size = TM_ILT_PAGE_SZ;
2299		ilt_client->flags = 0;
2300		ilt_client->start = line;
2301		line += TM_ILT_LINES;
2302		ilt_client->end = (line - 1);
2303	}
2304
2305	assert((line <= ILT_MAX_LINES));
2306}
2307
2308static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2309{
2310	int i;
2311
2312	for (i = 0; i < sc->num_queues; i++) {
2313		/* get the Rx buffer size for RX frames */
2314		sc->fp[i].rx_buf_size =
2315		    (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2316	}
2317}
2318
2319int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2320{
2321
2322	sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2323
2324	return sc->ilt == NULL;
2325}
2326
2327static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2328{
2329	sc->ilt->lines = rte_calloc("",
2330				    sizeof(struct ilt_line), ILT_MAX_LINES,
2331				    RTE_CACHE_LINE_SIZE);
2332	return sc->ilt->lines == NULL;
2333}
2334
2335void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2336{
2337	rte_free(sc->ilt);
2338	sc->ilt = NULL;
2339}
2340
2341static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2342{
2343	if (sc->ilt->lines != NULL) {
2344		rte_free(sc->ilt->lines);
2345		sc->ilt->lines = NULL;
2346	}
2347}
2348
2349static void bnx2x_free_mem(struct bnx2x_softc *sc)
2350{
2351	uint32_t i;
2352
2353	for (i = 0; i < L2_ILT_LINES(sc); i++) {
2354		sc->context[i].vcxt = NULL;
2355		sc->context[i].size = 0;
2356	}
2357
2358	ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2359
2360	bnx2x_free_ilt_lines_mem(sc);
2361}
2362
2363static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2364{
2365	int context_size;
2366	int allocated;
2367	int i;
2368	char cdu_name[RTE_MEMZONE_NAMESIZE];
2369
2370	/*
2371	 * Allocate memory for CDU context:
2372	 * This memory is allocated separately and not in the generic ILT
2373	 * functions because CDU differs in few aspects:
2374	 * 1. There can be multiple entities allocating memory for context -
2375	 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2376	 * its own ILT lines.
2377	 * 2. Since CDU page-size is not a single 4KB page (which is the case
2378	 * for the other ILT clients), to be efficient we want to support
2379	 * allocation of sub-page-size in the last entry.
2380	 * 3. Context pointers are used by the driver to pass to FW / update
2381	 * the context (for the other ILT clients the pointers are used just to
2382	 * free the memory during unload).
2383	 */
2384	context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2385	for (i = 0, allocated = 0; allocated < context_size; i++) {
2386		sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2387					  (context_size - allocated));
2388
2389		snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2390		if (bnx2x_dma_alloc(sc, sc->context[i].size,
2391				  &sc->context[i].vcxt_dma,
2392				  cdu_name, BNX2X_PAGE_SIZE) != 0) {
2393			bnx2x_free_mem(sc);
2394			return -1;
2395		}
2396
2397		sc->context[i].vcxt =
2398		    (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2399
2400		allocated += sc->context[i].size;
2401	}
2402
2403	bnx2x_alloc_ilt_lines_mem(sc);
2404
2405	if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2406		PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2407		bnx2x_free_mem(sc);
2408		return -1;
2409	}
2410
2411	return 0;
2412}
2413
2414static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2415{
2416	sc->fw_stats_num = 0;
2417
2418	sc->fw_stats_req_size = 0;
2419	sc->fw_stats_req = NULL;
2420	sc->fw_stats_req_mapping = 0;
2421
2422	sc->fw_stats_data_size = 0;
2423	sc->fw_stats_data = NULL;
2424	sc->fw_stats_data_mapping = 0;
2425}
2426
2427static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2428{
2429	uint8_t num_queue_stats;
2430	int num_groups, vf_headroom = 0;
2431
2432	/* number of queues for statistics is number of eth queues */
2433	num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2434
2435	/*
2436	 * Total number of FW statistics requests =
2437	 *   1 for port stats + 1 for PF stats + num of queues
2438	 */
2439	sc->fw_stats_num = (2 + num_queue_stats);
2440
2441	/*
2442	 * Request is built from stats_query_header and an array of
2443	 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2444	 * rules. The real number or requests is configured in the
2445	 * stats_query_header.
2446	 */
2447	num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2448	if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2449		num_groups++;
2450
2451	sc->fw_stats_req_size =
2452	    (sizeof(struct stats_query_header) +
2453	     (num_groups * sizeof(struct stats_query_cmd_group)));
2454
2455	/*
2456	 * Data for statistics requests + stats_counter.
2457	 * stats_counter holds per-STORM counters that are incremented when
2458	 * STORM has finished with the current request. Memory for FCoE
2459	 * offloaded statistics are counted anyway, even if they will not be sent.
2460	 * VF stats are not accounted for here as the data of VF stats is stored
2461	 * in memory allocated by the VF, not here.
2462	 */
2463	sc->fw_stats_data_size =
2464	    (sizeof(struct stats_counter) +
2465	     sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2466	     /* sizeof(struct fcoe_statistics_params) + */
2467	     (sizeof(struct per_queue_stats) * num_queue_stats));
2468
2469	if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2470			  &sc->fw_stats_dma, "fw_stats",
2471			  RTE_CACHE_LINE_SIZE) != 0) {
2472		bnx2x_free_fw_stats_mem(sc);
2473		return -1;
2474	}
2475
2476	/* set up the shortcuts */
2477
2478	sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2479	sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2480
2481	sc->fw_stats_data =
2482	    (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2483					 sc->fw_stats_req_size);
2484	sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2485				     sc->fw_stats_req_size);
2486
2487	return 0;
2488}
2489
2490/*
2491 * Bits map:
2492 * 0-7  - Engine0 load counter.
2493 * 8-15 - Engine1 load counter.
2494 * 16   - Engine0 RESET_IN_PROGRESS bit.
2495 * 17   - Engine1 RESET_IN_PROGRESS bit.
2496 * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2497 *        function on the engine
2498 * 19   - Engine1 ONE_IS_LOADED.
2499 * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2500 *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2501 *        for just the one belonging to its engine).
2502 */
2503#define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2504#define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2505#define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2506#define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2507#define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2508#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2509#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2510#define BNX2X_GLOBAL_RESET_BIT      0x00040000
2511
2512/* set the GLOBAL_RESET bit, should be run under rtnl lock */
2513static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2514{
2515	uint32_t val;
2516	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2517	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2518	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2519	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2520}
2521
2522/* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2523static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2524{
2525	uint32_t val;
2526	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2527	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2528	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2529	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2530}
2531
2532/* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2533static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2534{
2535	return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2536}
2537
2538/* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2539static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2540{
2541	uint32_t val;
2542	uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2543	    BNX2X_PATH0_RST_IN_PROG_BIT;
2544
2545	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2546
2547	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548	/* Clear the bit */
2549	val &= ~bit;
2550	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2551
2552	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553}
2554
2555/* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2556static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2557{
2558	uint32_t val;
2559	uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2560	    BNX2X_PATH0_RST_IN_PROG_BIT;
2561
2562	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2563
2564	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2565	/* Set the bit */
2566	val |= bit;
2567	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2568
2569	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2570}
2571
2572/* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2573static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2574{
2575	uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2576	uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2577	    BNX2X_PATH0_RST_IN_PROG_BIT;
2578
2579	/* return false if bit is set */
2580	return (val & bit) ? FALSE : TRUE;
2581}
2582
2583/* get the load status for an engine, should be run under rtnl lock */
2584static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2585{
2586	uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2587	    BNX2X_PATH0_LOAD_CNT_MASK;
2588	uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2589	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2590	uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2591
2592	val = ((val & mask) >> shift);
2593
2594	return val != 0;
2595}
2596
2597/* set pf load mark */
2598static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2599{
2600	uint32_t val;
2601	uint32_t val1;
2602	uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2603	    BNX2X_PATH0_LOAD_CNT_MASK;
2604	uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2605	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2606
2607	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2608
2609	PMD_INIT_FUNC_TRACE();
2610
2611	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2612
2613	/* get the current counter value */
2614	val1 = ((val & mask) >> shift);
2615
2616	/* set bit of this PF */
2617	val1 |= (1 << SC_ABS_FUNC(sc));
2618
2619	/* clear the old value */
2620	val &= ~mask;
2621
2622	/* set the new one */
2623	val |= ((val1 << shift) & mask);
2624
2625	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2626
2627	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628}
2629
2630/* clear pf load mark */
2631static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2632{
2633	uint32_t val1, val;
2634	uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2635	    BNX2X_PATH0_LOAD_CNT_MASK;
2636	uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2637	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2638
2639	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2640	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2641
2642	/* get the current counter value */
2643	val1 = (val & mask) >> shift;
2644
2645	/* clear bit of that PF */
2646	val1 &= ~(1 << SC_ABS_FUNC(sc));
2647
2648	/* clear the old value */
2649	val &= ~mask;
2650
2651	/* set the new one */
2652	val |= ((val1 << shift) & mask);
2653
2654	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2655	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2656	return val1 != 0;
2657}
2658
2659/* send load requrest to mcp and analyze response */
2660static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2661{
2662	PMD_INIT_FUNC_TRACE();
2663
2664	/* init fw_seq */
2665	sc->fw_seq =
2666	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2667	     DRV_MSG_SEQ_NUMBER_MASK);
2668
2669	PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2670
2671#ifdef BNX2X_PULSE
2672	/* get the current FW pulse sequence */
2673	sc->fw_drv_pulse_wr_seq =
2674	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2675	     DRV_PULSE_SEQ_MASK);
2676#else
2677	/* set ALWAYS_ALIVE bit in shmem */
2678	sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2679	bnx2x_drv_pulse(sc);
2680#endif
2681
2682	/* load request */
2683	(*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2684				      DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2685
2686	/* if the MCP fails to respond we must abort */
2687	if (!(*load_code)) {
2688		PMD_DRV_LOG(NOTICE, "MCP response failure!");
2689		return -1;
2690	}
2691
2692	/* if MCP refused then must abort */
2693	if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2694		PMD_DRV_LOG(NOTICE, "MCP refused load request");
2695		return -1;
2696	}
2697
2698	return 0;
2699}
2700
2701/*
2702 * Check whether another PF has already loaded FW to chip. In virtualized
2703 * environments a pf from anoth VM may have already initialized the device
2704 * including loading FW.
2705 */
2706static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2707{
2708	uint32_t my_fw, loaded_fw;
2709
2710	/* is another pf loaded on this engine? */
2711	if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2712	    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2713		/* build my FW version dword */
2714		my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2715			 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2716			 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2717			 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2718
2719		/* read loaded FW from chip */
2720		loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2721		PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2722			    loaded_fw, my_fw);
2723
2724		/* abort nic load if version mismatch */
2725		if (my_fw != loaded_fw) {
2726			PMD_DRV_LOG(NOTICE,
2727				    "FW 0x%08x already loaded (mine is 0x%08x)",
2728				    loaded_fw, my_fw);
2729			return -1;
2730		}
2731	}
2732
2733	return 0;
2734}
2735
2736/* mark PMF if applicable */
2737static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2738{
2739	uint32_t ncsi_oem_data_addr;
2740
2741	PMD_INIT_FUNC_TRACE();
2742
2743	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2744	    (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2745	    (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2746		/*
2747		 * Barrier here for ordering between the writing to sc->port.pmf here
2748		 * and reading it from the periodic task.
2749		 */
2750		sc->port.pmf = 1;
2751		mb();
2752	} else {
2753		sc->port.pmf = 0;
2754	}
2755
2756	PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2757
2758	if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2759		if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2760			ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2761			if (ncsi_oem_data_addr) {
2762				REG_WR(sc,
2763				       (ncsi_oem_data_addr +
2764					offsetof(struct glob_ncsi_oem_data,
2765						 driver_version)), 0);
2766			}
2767		}
2768	}
2769}
2770
2771static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2772{
2773	int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2774	int abs_func;
2775	int vn;
2776
2777	if (BNX2X_NOMCP(sc)) {
2778		return;		/* what should be the default bvalue in this case */
2779	}
2780
2781	/*
2782	 * The formula for computing the absolute function number is...
2783	 * For 2 port configuration (4 functions per port):
2784	 *   abs_func = 2 * vn + SC_PORT + SC_PATH
2785	 * For 4 port configuration (2 functions per port):
2786	 *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2787	 */
2788	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2789		abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2790		if (abs_func >= E1H_FUNC_MAX) {
2791			break;
2792		}
2793		sc->devinfo.mf_info.mf_config[vn] =
2794		    MFCFG_RD(sc, func_mf_config[abs_func].config);
2795	}
2796
2797	if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2798	    FUNC_MF_CFG_FUNC_DISABLED) {
2799		PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2800		sc->flags |= BNX2X_MF_FUNC_DIS;
2801	} else {
2802		PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2803		sc->flags &= ~BNX2X_MF_FUNC_DIS;
2804	}
2805}
2806
2807/* acquire split MCP access lock register */
2808static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2809{
2810	uint32_t j, val;
2811
2812	for (j = 0; j < 1000; j++) {
2813		val = (1UL << 31);
2814		REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2815		val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2816		if (val & (1L << 31))
2817			break;
2818
2819		DELAY(5000);
2820	}
2821
2822	if (!(val & (1L << 31))) {
2823		PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2824		return -1;
2825	}
2826
2827	return 0;
2828}
2829
2830/* release split MCP access lock register */
2831static void bnx2x_release_alr(struct bnx2x_softc *sc)
2832{
2833	REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2834}
2835
2836static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2837{
2838	int port = SC_PORT(sc);
2839	uint32_t ext_phy_config;
2840
2841	/* mark the failure */
2842	ext_phy_config =
2843	    SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2844
2845	ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2846	ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2847	SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2848		 ext_phy_config);
2849
2850	/* log the failure */
2851	PMD_DRV_LOG(INFO,
2852		    "Fan Failure has caused the driver to shutdown "
2853		    "the card to prevent permanent damage. "
2854		    "Please contact OEM Support for assistance");
2855
2856	rte_panic("Schedule task to handle fan failure");
2857}
2858
2859/* this function is called upon a link interrupt */
2860static void bnx2x_link_attn(struct bnx2x_softc *sc)
2861{
2862	uint32_t pause_enabled = 0;
2863	struct host_port_stats *pstats;
2864	int cmng_fns;
2865
2866	/* Make sure that we are synced with the current statistics */
2867	bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2868
2869	elink_link_update(&sc->link_params, &sc->link_vars);
2870
2871	if (sc->link_vars.link_up) {
2872
2873		/* dropless flow control */
2874		if (sc->dropless_fc) {
2875			pause_enabled = 0;
2876
2877			if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2878				pause_enabled = 1;
2879			}
2880
2881			REG_WR(sc,
2882			       (BAR_USTRORM_INTMEM +
2883				USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2884			       pause_enabled);
2885		}
2886
2887		if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2888			pstats = BNX2X_SP(sc, port_stats);
2889			/* reset old mac stats */
2890			memset(&(pstats->mac_stx[0]), 0,
2891			       sizeof(struct mac_stx));
2892		}
2893
2894		if (sc->state == BNX2X_STATE_OPEN) {
2895			bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2896		}
2897	}
2898
2899	if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2900		cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2901
2902		if (cmng_fns != CMNG_FNS_NONE) {
2903			bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2904			storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2905		}
2906	}
2907
2908	bnx2x_link_report(sc);
2909
2910	if (IS_MF(sc)) {
2911		bnx2x_link_sync_notify(sc);
2912	}
2913}
2914
2915static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2916{
2917	int port = SC_PORT(sc);
2918	uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2919	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
2920	uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2921	    NIG_REG_MASK_INTERRUPT_PORT0;
2922	uint32_t aeu_mask;
2923	uint32_t nig_mask = 0;
2924	uint32_t reg_addr;
2925	uint32_t igu_acked;
2926	uint32_t cnt;
2927
2928	if (sc->attn_state & asserted) {
2929		PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2930	}
2931
2932	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2933
2934	aeu_mask = REG_RD(sc, aeu_addr);
2935
2936	aeu_mask &= ~(asserted & 0x3ff);
2937
2938	REG_WR(sc, aeu_addr, aeu_mask);
2939
2940	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2941
2942	sc->attn_state |= asserted;
2943
2944	if (asserted & ATTN_HARD_WIRED_MASK) {
2945		if (asserted & ATTN_NIG_FOR_FUNC) {
2946
2947			/* save nig interrupt mask */
2948			nig_mask = REG_RD(sc, nig_int_mask_addr);
2949
2950			/* If nig_mask is not set, no need to call the update function */
2951			if (nig_mask) {
2952				REG_WR(sc, nig_int_mask_addr, 0);
2953
2954				bnx2x_link_attn(sc);
2955			}
2956
2957			/* handle unicore attn? */
2958		}
2959
2960		if (asserted & ATTN_SW_TIMER_4_FUNC) {
2961			PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2962		}
2963
2964		if (asserted & GPIO_2_FUNC) {
2965			PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2966		}
2967
2968		if (asserted & GPIO_3_FUNC) {
2969			PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2970		}
2971
2972		if (asserted & GPIO_4_FUNC) {
2973			PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2974		}
2975
2976		if (port == 0) {
2977			if (asserted & ATTN_GENERAL_ATTN_1) {
2978				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2979				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2980			}
2981			if (asserted & ATTN_GENERAL_ATTN_2) {
2982				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2983				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2984			}
2985			if (asserted & ATTN_GENERAL_ATTN_3) {
2986				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2987				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2988			}
2989		} else {
2990			if (asserted & ATTN_GENERAL_ATTN_4) {
2991				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2992				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2993			}
2994			if (asserted & ATTN_GENERAL_ATTN_5) {
2995				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2996				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2997			}
2998			if (asserted & ATTN_GENERAL_ATTN_6) {
2999				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3000				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3001			}
3002		}
3003	}
3004	/* hardwired */
3005	if (sc->devinfo.int_block == INT_BLOCK_HC) {
3006		reg_addr =
3007		    (HC_REG_COMMAND_REG + port * 32 +
3008		     COMMAND_REG_ATTN_BITS_SET);
3009	} else {
3010		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3011	}
3012
3013	PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3014		    asserted,
3015		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3016		    reg_addr);
3017	REG_WR(sc, reg_addr, asserted);
3018
3019	/* now set back the mask */
3020	if (asserted & ATTN_NIG_FOR_FUNC) {
3021		/*
3022		 * Verify that IGU ack through BAR was written before restoring
3023		 * NIG mask. This loop should exit after 2-3 iterations max.
3024		 */
3025		if (sc->devinfo.int_block != INT_BLOCK_HC) {
3026			cnt = 0;
3027
3028			do {
3029				igu_acked =
3030				    REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3031			} while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3032				 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3033
3034			if (!igu_acked) {
3035				PMD_DRV_LOG(ERR,
3036					    "Failed to verify IGU ack on time");
3037			}
3038
3039			mb();
3040		}
3041
3042		REG_WR(sc, nig_int_mask_addr, nig_mask);
3043
3044	}
3045}
3046
3047static void
3048bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3049		     __rte_unused const char *blk)
3050{
3051	PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3052}
3053
3054static int
3055bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3056			      uint8_t print)
3057{
3058	uint32_t cur_bit = 0;
3059	int i = 0;
3060
3061	for (i = 0; sig; i++) {
3062		cur_bit = ((uint32_t) 0x1 << i);
3063		if (sig & cur_bit) {
3064			switch (cur_bit) {
3065			case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3066				if (print)
3067					bnx2x_print_next_block(sc, par_num++,
3068							     "BRB");
3069				break;
3070			case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3071				if (print)
3072					bnx2x_print_next_block(sc, par_num++,
3073							     "PARSER");
3074				break;
3075			case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3076				if (print)
3077					bnx2x_print_next_block(sc, par_num++,
3078							     "TSDM");
3079				break;
3080			case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3081				if (print)
3082					bnx2x_print_next_block(sc, par_num++,
3083							     "SEARCHER");
3084				break;
3085			case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3086				if (print)
3087					bnx2x_print_next_block(sc, par_num++,
3088							     "TCM");
3089				break;
3090			case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3091				if (print)
3092					bnx2x_print_next_block(sc, par_num++,
3093							     "TSEMI");
3094				break;
3095			case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3096				if (print)
3097					bnx2x_print_next_block(sc, par_num++,
3098							     "XPB");
3099				break;
3100			}
3101
3102			/* Clear the bit */
3103			sig &= ~cur_bit;
3104		}
3105	}
3106
3107	return par_num;
3108}
3109
3110static int
3111bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3112			      uint8_t * global, uint8_t print)
3113{
3114	int i = 0;
3115	uint32_t cur_bit = 0;
3116	for (i = 0; sig; i++) {
3117		cur_bit = ((uint32_t) 0x1 << i);
3118		if (sig & cur_bit) {
3119			switch (cur_bit) {
3120			case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3121				if (print)
3122					bnx2x_print_next_block(sc, par_num++,
3123							     "PBF");
3124				break;
3125			case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3126				if (print)
3127					bnx2x_print_next_block(sc, par_num++,
3128							     "QM");
3129				break;
3130			case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3131				if (print)
3132					bnx2x_print_next_block(sc, par_num++,
3133							     "TM");
3134				break;
3135			case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3136				if (print)
3137					bnx2x_print_next_block(sc, par_num++,
3138							     "XSDM");
3139				break;
3140			case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3141				if (print)
3142					bnx2x_print_next_block(sc, par_num++,
3143							     "XCM");
3144				break;
3145			case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3146				if (print)
3147					bnx2x_print_next_block(sc, par_num++,
3148							     "XSEMI");
3149				break;
3150			case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3151				if (print)
3152					bnx2x_print_next_block(sc, par_num++,
3153							     "DOORBELLQ");
3154				break;
3155			case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3156				if (print)
3157					bnx2x_print_next_block(sc, par_num++,
3158							     "NIG");
3159				break;
3160			case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3161				if (print)
3162					bnx2x_print_next_block(sc, par_num++,
3163							     "VAUX PCI CORE");
3164				*global = TRUE;
3165				break;
3166			case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3167				if (print)
3168					bnx2x_print_next_block(sc, par_num++,
3169							     "DEBUG");
3170				break;
3171			case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3172				if (print)
3173					bnx2x_print_next_block(sc, par_num++,
3174							     "USDM");
3175				break;
3176			case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3177				if (print)
3178					bnx2x_print_next_block(sc, par_num++,
3179							     "UCM");
3180				break;
3181			case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3182				if (print)
3183					bnx2x_print_next_block(sc, par_num++,
3184							     "USEMI");
3185				break;
3186			case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3187				if (print)
3188					bnx2x_print_next_block(sc, par_num++,
3189							     "UPB");
3190				break;
3191			case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3192				if (print)
3193					bnx2x_print_next_block(sc, par_num++,
3194							     "CSDM");
3195				break;
3196			case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3197				if (print)
3198					bnx2x_print_next_block(sc, par_num++,
3199							     "CCM");
3200				break;
3201			}
3202
3203			/* Clear the bit */
3204			sig &= ~cur_bit;
3205		}
3206	}
3207
3208	return par_num;
3209}
3210
3211static int
3212bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3213			      uint8_t print)
3214{
3215	uint32_t cur_bit = 0;
3216	int i = 0;
3217
3218	for (i = 0; sig; i++) {
3219		cur_bit = ((uint32_t) 0x1 << i);
3220		if (sig & cur_bit) {
3221			switch (cur_bit) {
3222			case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3223				if (print)
3224					bnx2x_print_next_block(sc, par_num++,
3225							     "CSEMI");
3226				break;
3227			case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3228				if (print)
3229					bnx2x_print_next_block(sc, par_num++,
3230							     "PXP");
3231				break;
3232			case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3233				if (print)
3234					bnx2x_print_next_block(sc, par_num++,
3235							     "PXPPCICLOCKCLIENT");
3236				break;
3237			case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3238				if (print)
3239					bnx2x_print_next_block(sc, par_num++,
3240							     "CFC");
3241				break;
3242			case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3243				if (print)
3244					bnx2x_print_next_block(sc, par_num++,
3245							     "CDU");
3246				break;
3247			case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3248				if (print)
3249					bnx2x_print_next_block(sc, par_num++,
3250							     "DMAE");
3251				break;
3252			case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3253				if (print)
3254					bnx2x_print_next_block(sc, par_num++,
3255							     "IGU");
3256				break;
3257			case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3258				if (print)
3259					bnx2x_print_next_block(sc, par_num++,
3260							     "MISC");
3261				break;
3262			}
3263
3264			/* Clear the bit */
3265			sig &= ~cur_bit;
3266		}
3267	}
3268
3269	return par_num;
3270}
3271
3272static int
3273bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3274			      uint8_t * global, uint8_t print)
3275{
3276	uint32_t cur_bit = 0;
3277	int i = 0;
3278
3279	for (i = 0; sig; i++) {
3280		cur_bit = ((uint32_t) 0x1 << i);
3281		if (sig & cur_bit) {
3282			switch (cur_bit) {
3283			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3284				if (print)
3285					bnx2x_print_next_block(sc, par_num++,
3286							     "MCP ROM");
3287				*global = TRUE;
3288				break;
3289			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3290				if (print)
3291					bnx2x_print_next_block(sc, par_num++,
3292							     "MCP UMP RX");
3293				*global = TRUE;
3294				break;
3295			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3296				if (print)
3297					bnx2x_print_next_block(sc, par_num++,
3298							     "MCP UMP TX");
3299				*global = TRUE;
3300				break;
3301			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3302				if (print)
3303					bnx2x_print_next_block(sc, par_num++,
3304							     "MCP SCPAD");
3305				*global = TRUE;
3306				break;
3307			}
3308
3309			/* Clear the bit */
3310			sig &= ~cur_bit;
3311		}
3312	}
3313
3314	return par_num;
3315}
3316
3317static int
3318bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3319			      uint8_t print)
3320{
3321	uint32_t cur_bit = 0;
3322	int i = 0;
3323
3324	for (i = 0; sig; i++) {
3325		cur_bit = ((uint32_t) 0x1 << i);
3326		if (sig & cur_bit) {
3327			switch (cur_bit) {
3328			case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3329				if (print)
3330					bnx2x_print_next_block(sc, par_num++,
3331							     "PGLUE_B");
3332				break;
3333			case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3334				if (print)
3335					bnx2x_print_next_block(sc, par_num++,
3336							     "ATC");
3337				break;
3338			}
3339
3340			/* Clear the bit */
3341			sig &= ~cur_bit;
3342		}
3343	}
3344
3345	return par_num;
3346}
3347
3348static uint8_t
3349bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3350		uint32_t * sig)
3351{
3352	int par_num = 0;
3353
3354	if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3355	    (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3356	    (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3357	    (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3358	    (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3359		PMD_DRV_LOG(ERR,
3360			    "Parity error: HW block parity attention:"
3361			    "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3362			    (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3363			    (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3364			    (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3365			    (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3366			    (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3367
3368		if (print)
3369			PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3370
3371		par_num =
3372		    bnx2x_check_blocks_with_parity0(sc, sig[0] &
3373						  HW_PRTY_ASSERT_SET_0,
3374						  par_num, print);
3375		par_num =
3376		    bnx2x_check_blocks_with_parity1(sc, sig[1] &
3377						  HW_PRTY_ASSERT_SET_1,
3378						  par_num, global, print);
3379		par_num =
3380		    bnx2x_check_blocks_with_parity2(sc, sig[2] &
3381						  HW_PRTY_ASSERT_SET_2,
3382						  par_num, print);
3383		par_num =
3384		    bnx2x_check_blocks_with_parity3(sc, sig[3] &
3385						  HW_PRTY_ASSERT_SET_3,
3386						  par_num, global, print);
3387		par_num =
3388		    bnx2x_check_blocks_with_parity4(sc, sig[4] &
3389						  HW_PRTY_ASSERT_SET_4,
3390						  par_num, print);
3391
3392		if (print)
3393			PMD_DRV_LOG(INFO, "");
3394
3395		return TRUE;
3396	}
3397
3398	return FALSE;
3399}
3400
3401static uint8_t
3402bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3403{
3404	struct attn_route attn = { {0} };
3405	int port = SC_PORT(sc);
3406
3407	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3408	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3409	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3410	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3411
3412	if (!CHIP_IS_E1x(sc))
3413		attn.sig[4] =
3414		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3415
3416	return bnx2x_parity_attn(sc, global, print, attn.sig);
3417}
3418
3419static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3420{
3421	uint32_t val;
3422
3423	if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3424		val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3425		PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3426		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3427			PMD_DRV_LOG(INFO,
3428				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3429		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3430			PMD_DRV_LOG(INFO,
3431				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3432		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3433			PMD_DRV_LOG(INFO,
3434				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3435		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3436			PMD_DRV_LOG(INFO,
3437				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3438		if (val &
3439		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3440			PMD_DRV_LOG(INFO,
3441				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3442		if (val &
3443		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3444			PMD_DRV_LOG(INFO,
3445				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3446		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3447			PMD_DRV_LOG(INFO,
3448				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3449		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3450			PMD_DRV_LOG(INFO,
3451				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3452		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3453			PMD_DRV_LOG(INFO,
3454				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3455	}
3456
3457	if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3458		val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3459		PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3460		if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3461			PMD_DRV_LOG(INFO,
3462				    "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3463		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3464			PMD_DRV_LOG(INFO,
3465				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3466		if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3467			PMD_DRV_LOG(INFO,
3468				    "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3469		if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3470			PMD_DRV_LOG(INFO,
3471				    "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3472		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3473			PMD_DRV_LOG(INFO,
3474				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3475		if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3476			PMD_DRV_LOG(INFO,
3477				    "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3478	}
3479
3480	if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3481		    AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3482		PMD_DRV_LOG(INFO,
3483			    "ERROR: FATAL parity attention set4 0x%08x",
3484			    (uint32_t) (attn &
3485					(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3486					 |
3487					 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3488	}
3489}
3490
3491static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3492{
3493	int port = SC_PORT(sc);
3494
3495	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3496}
3497
3498static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3499{
3500	int port = SC_PORT(sc);
3501
3502	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3503}
3504
3505/*
3506 * called due to MCP event (on pmf):
3507 *   reread new bandwidth configuration
3508 *   configure FW
3509 *   notify others function about the change
3510 */
3511static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3512{
3513	if (sc->link_vars.link_up) {
3514		bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3515		bnx2x_link_sync_notify(sc);
3516	}
3517
3518	storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3519}
3520
3521static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3522{
3523	bnx2x_config_mf_bw(sc);
3524	bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3525}
3526
3527static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3528{
3529	bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3530}
3531
3532#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3533
3534static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3535{
3536	struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3537
3538	strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3539		ETH_STAT_INFO_VERSION_LEN);
3540
3541	sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3542					      DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3543					      ether_stat->mac_local + MAC_PAD,
3544					      MAC_PAD, ETH_ALEN);
3545
3546	ether_stat->mtu_size = sc->mtu;
3547
3548	ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3549	ether_stat->promiscuous_mode = 0;	// (flags & PROMISC) ? 1 : 0;
3550
3551	ether_stat->txq_size = sc->tx_ring_size;
3552	ether_stat->rxq_size = sc->rx_ring_size;
3553}
3554
3555static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3556{
3557	enum drv_info_opcode op_code;
3558	uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3559
3560	/* if drv_info version supported by MFW doesn't match - send NACK */
3561	if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3562		bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3563		return;
3564	}
3565
3566	op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3567		   DRV_INFO_CONTROL_OP_CODE_SHIFT);
3568
3569	memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3570
3571	switch (op_code) {
3572	case ETH_STATS_OPCODE:
3573		bnx2x_drv_info_ether_stat(sc);
3574		break;
3575	case FCOE_STATS_OPCODE:
3576	case ISCSI_STATS_OPCODE:
3577	default:
3578		/* if op code isn't supported - send NACK */
3579		bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3580		return;
3581	}
3582
3583	/*
3584	 * If we got drv_info attn from MFW then these fields are defined in
3585	 * shmem2 for sure
3586	 */
3587	SHMEM2_WR(sc, drv_info_host_addr_lo,
3588		  U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589	SHMEM2_WR(sc, drv_info_host_addr_hi,
3590		  U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3591
3592	bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3593}
3594
3595static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3596{
3597	if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3598/*
3599 * This is the only place besides the function initialization
3600 * where the sc->flags can change so it is done without any
3601 * locks
3602 */
3603		if (sc->devinfo.
3604		    mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3605			PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3606			sc->flags |= BNX2X_MF_FUNC_DIS;
3607			bnx2x_e1h_disable(sc);
3608		} else {
3609			PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3610			sc->flags &= ~BNX2X_MF_FUNC_DIS;
3611			bnx2x_e1h_enable(sc);
3612		}
3613		dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3614	}
3615
3616	if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3617		bnx2x_config_mf_bw(sc);
3618		dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3619	}
3620
3621	/* Report results to MCP */
3622	if (dcc_event)
3623		bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3624	else
3625		bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3626}
3627
3628static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3629{
3630	int port = SC_PORT(sc);
3631	uint32_t val;
3632
3633	sc->port.pmf = 1;
3634
3635	/*
3636	 * We need the mb() to ensure the ordering between the writing to
3637	 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3638	 */
3639	mb();
3640
3641	/* enable nig attention */
3642	val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3643	if (sc->devinfo.int_block == INT_BLOCK_HC) {
3644		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3645		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3646	} else if (!CHIP_IS_E1x(sc)) {
3647		REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3648		REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3649	}
3650
3651	bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3652}
3653
3654static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3655{
3656	char last_idx;
3657	int i, rc = 0;
3658	__rte_unused uint32_t row0, row1, row2, row3;
3659
3660	/* XSTORM */
3661	last_idx =
3662	    REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3663	if (last_idx)
3664		PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3665
3666	/* print the asserts */
3667	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3668
3669		row0 =
3670		    REG_RD(sc,
3671			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3672		row1 =
3673		    REG_RD(sc,
3674			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3675			   4);
3676		row2 =
3677		    REG_RD(sc,
3678			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3679			   8);
3680		row3 =
3681		    REG_RD(sc,
3682			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3683			   12);
3684
3685		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3686			PMD_DRV_LOG(ERR,
3687				    "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3688				    i, row3, row2, row1, row0);
3689			rc++;
3690		} else {
3691			break;
3692		}
3693	}
3694
3695	/* TSTORM */
3696	last_idx =
3697	    REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3698	if (last_idx) {
3699		PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3700	}
3701
3702	/* print the asserts */
3703	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3704
3705		row0 =
3706		    REG_RD(sc,
3707			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3708		row1 =
3709		    REG_RD(sc,
3710			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3711			   4);
3712		row2 =
3713		    REG_RD(sc,
3714			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3715			   8);
3716		row3 =
3717		    REG_RD(sc,
3718			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3719			   12);
3720
3721		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3722			PMD_DRV_LOG(ERR,
3723				    "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3724				    i, row3, row2, row1, row0);
3725			rc++;
3726		} else {
3727			break;
3728		}
3729	}
3730
3731	/* CSTORM */
3732	last_idx =
3733	    REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3734	if (last_idx) {
3735		PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3736	}
3737
3738	/* print the asserts */
3739	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3740
3741		row0 =
3742		    REG_RD(sc,
3743			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3744		row1 =
3745		    REG_RD(sc,
3746			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3747			   4);
3748		row2 =
3749		    REG_RD(sc,
3750			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3751			   8);
3752		row3 =
3753		    REG_RD(sc,
3754			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3755			   12);
3756
3757		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3758			PMD_DRV_LOG(ERR,
3759				    "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3760				    i, row3, row2, row1, row0);
3761			rc++;
3762		} else {
3763			break;
3764		}
3765	}
3766
3767	/* USTORM */
3768	last_idx =
3769	    REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3770	if (last_idx) {
3771		PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3772	}
3773
3774	/* print the asserts */
3775	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3776
3777		row0 =
3778		    REG_RD(sc,
3779			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3780		row1 =
3781		    REG_RD(sc,
3782			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3783			   4);
3784		row2 =
3785		    REG_RD(sc,
3786			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3787			   8);
3788		row3 =
3789		    REG_RD(sc,
3790			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3791			   12);
3792
3793		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3794			PMD_DRV_LOG(ERR,
3795				    "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3796				    i, row3, row2, row1, row0);
3797			rc++;
3798		} else {
3799			break;
3800		}
3801	}
3802
3803	return rc;
3804}
3805
3806static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3807{
3808	int func = SC_FUNC(sc);
3809	uint32_t val;
3810
3811	if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3812
3813		if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3814
3815			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3816			bnx2x_read_mf_cfg(sc);
3817			sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3818			    MFCFG_RD(sc,
3819				     func_mf_config[SC_ABS_FUNC(sc)].config);
3820			val =
3821			    SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3822
3823			if (val & DRV_STATUS_DCC_EVENT_MASK)
3824				bnx2x_dcc_event(sc,
3825					      (val &
3826					       DRV_STATUS_DCC_EVENT_MASK));
3827
3828			if (val & DRV_STATUS_SET_MF_BW)
3829				bnx2x_set_mf_bw(sc);
3830
3831			if (val & DRV_STATUS_DRV_INFO_REQ)
3832				bnx2x_handle_drv_info_req(sc);
3833
3834			if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3835				bnx2x_pmf_update(sc);
3836
3837			if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3838				bnx2x_handle_eee_event(sc);
3839
3840			if (sc->link_vars.periodic_flags &
3841			    ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3842				/* sync with link */
3843				sc->link_vars.periodic_flags &=
3844				    ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3845				if (IS_MF(sc)) {
3846					bnx2x_link_sync_notify(sc);
3847				}
3848				bnx2x_link_report(sc);
3849			}
3850
3851			/*
3852			 * Always call it here: bnx2x_link_report() will
3853			 * prevent the link indication duplication.
3854			 */
3855			bnx2x_link_status_update(sc);
3856
3857		} else if (attn & BNX2X_MC_ASSERT_BITS) {
3858
3859			PMD_DRV_LOG(ERR, "MC assert!");
3860			bnx2x_mc_assert(sc);
3861			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3862			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3863			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3864			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3865			rte_panic("MC assert!");
3866
3867		} else if (attn & BNX2X_MCP_ASSERT) {
3868
3869			PMD_DRV_LOG(ERR, "MCP assert!");
3870			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3871
3872		} else {
3873			PMD_DRV_LOG(ERR,
3874				    "Unknown HW assert! (attn 0x%08x)", attn);
3875		}
3876	}
3877
3878	if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3879		PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3880		if (attn & BNX2X_GRC_TIMEOUT) {
3881			val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3882			PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3883		}
3884		if (attn & BNX2X_GRC_RSV) {
3885			val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3886			PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3887		}
3888		REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3889	}
3890}
3891
3892static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3893{
3894	int port = SC_PORT(sc);
3895	int reg_offset;
3896	uint32_t val0, mask0, val1, mask1;
3897	uint32_t val;
3898
3899	if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3900		val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3901		PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3902/* CFC error attention */
3903		if (val & 0x2) {
3904			PMD_DRV_LOG(ERR, "FATAL error from CFC");
3905		}
3906	}
3907
3908	if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3909		val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3910		PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3911/* RQ_USDMDP_FIFO_OVERFLOW */
3912		if (val & 0x18000) {
3913			PMD_DRV_LOG(ERR, "FATAL error from PXP");
3914		}
3915
3916		if (!CHIP_IS_E1x(sc)) {
3917			val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3918			PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3919		}
3920	}
3921#define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3922#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3923
3924	if (attn & AEU_PXP2_HW_INT_BIT) {
3925/*  CQ47854 workaround do not panic on
3926 *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3927 */
3928		if (!CHIP_IS_E1x(sc)) {
3929			mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3930			val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3931			mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3932			val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3933			/*
3934			 * If the olny PXP2_EOP_ERROR_BIT is set in
3935			 * STS0 and STS1 - clear it
3936			 *
3937			 * probably we lose additional attentions between
3938			 * STS0 and STS_CLR0, in this case user will not
3939			 * be notified about them
3940			 */
3941			if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3942			    !(val1 & mask1))
3943				val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3944
3945			/* print the register, since no one can restore it */
3946			PMD_DRV_LOG(ERR,
3947				    "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3948
3949			/*
3950			 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3951			 * then notify
3952			 */
3953			if (val0 & PXP2_EOP_ERROR_BIT) {
3954				PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3955
3956				/*
3957				 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3958				 * set then clear attention from PXP2 block without panic
3959				 */
3960				if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3961				    ((val1 & mask1) == 0))
3962					attn &= ~AEU_PXP2_HW_INT_BIT;
3963			}
3964		}
3965	}
3966
3967	if (attn & HW_INTERRUT_ASSERT_SET_2) {
3968		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3969			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3970
3971		val = REG_RD(sc, reg_offset);
3972		val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3973		REG_WR(sc, reg_offset, val);
3974
3975		PMD_DRV_LOG(ERR,
3976			    "FATAL HW block attention set2 0x%x",
3977			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3978		rte_panic("HW block attention set2");
3979	}
3980}
3981
3982static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3983{
3984	int port = SC_PORT(sc);
3985	int reg_offset;
3986	uint32_t val;
3987
3988	if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3989		val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3990		PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3991/* DORQ discard attention */
3992		if (val & 0x2) {
3993			PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3994		}
3995	}
3996
3997	if (attn & HW_INTERRUT_ASSERT_SET_1) {
3998		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3999			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4000
4001		val = REG_RD(sc, reg_offset);
4002		val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4003		REG_WR(sc, reg_offset, val);
4004
4005		PMD_DRV_LOG(ERR,
4006			    "FATAL HW block attention set1 0x%08x",
4007			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4008		rte_panic("HW block attention set1");
4009	}
4010}
4011
4012static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4013{
4014	int port = SC_PORT(sc);
4015	int reg_offset;
4016	uint32_t val;
4017
4018	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4019	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4020
4021	if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4022		val = REG_RD(sc, reg_offset);
4023		val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4024		REG_WR(sc, reg_offset, val);
4025
4026		PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4027
4028/* Fan failure attention */
4029		elink_hw_reset_phy(&sc->link_params);
4030		bnx2x_fan_failure(sc);
4031	}
4032
4033	if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4034		elink_handle_module_detect_int(&sc->link_params);
4035	}
4036
4037	if (attn & HW_INTERRUT_ASSERT_SET_0) {
4038		val = REG_RD(sc, reg_offset);
4039		val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4040		REG_WR(sc, reg_offset, val);
4041
4042		rte_panic("FATAL HW block attention set0 0x%lx",
4043			  (attn & HW_INTERRUT_ASSERT_SET_0));
4044	}
4045}
4046
4047static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4048{
4049	struct attn_route attn;
4050	struct attn_route *group_mask;
4051	int port = SC_PORT(sc);
4052	int index;
4053	uint32_t reg_addr;
4054	uint32_t val;
4055	uint32_t aeu_mask;
4056	uint8_t global = FALSE;
4057
4058	/*
4059	 * Need to take HW lock because MCP or other port might also
4060	 * try to handle this event.
4061	 */
4062	bnx2x_acquire_alr(sc);
4063
4064	if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4065		sc->recovery_state = BNX2X_RECOVERY_INIT;
4066
4067/* disable HW interrupts */
4068		bnx2x_int_disable(sc);
4069		bnx2x_release_alr(sc);
4070		return;
4071	}
4072
4073	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4074	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4075	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4076	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4077	if (!CHIP_IS_E1x(sc)) {
4078		attn.sig[4] =
4079		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4080	} else {
4081		attn.sig[4] = 0;
4082	}
4083
4084	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4085		if (deasserted & (1 << index)) {
4086			group_mask = &sc->attn_group[index];
4087
4088			bnx2x_attn_int_deasserted4(sc,
4089						 attn.
4090						 sig[4] & group_mask->sig[4]);
4091			bnx2x_attn_int_deasserted3(sc,
4092						 attn.
4093						 sig[3] & group_mask->sig[3]);
4094			bnx2x_attn_int_deasserted1(sc,
4095						 attn.
4096						 sig[1] & group_mask->sig[1]);
4097			bnx2x_attn_int_deasserted2(sc,
4098						 attn.
4099						 sig[2] & group_mask->sig[2]);
4100			bnx2x_attn_int_deasserted0(sc,
4101						 attn.
4102						 sig[0] & group_mask->sig[0]);
4103		}
4104	}
4105
4106	bnx2x_release_alr(sc);
4107
4108	if (sc->devinfo.int_block == INT_BLOCK_HC) {
4109		reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4110			    COMMAND_REG_ATTN_BITS_CLR);
4111	} else {
4112		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4113	}
4114
4115	val = ~deasserted;
4116	PMD_DRV_LOG(DEBUG,
4117		    "about to mask 0x%08x at %s addr 0x%08x", val,
4118		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4119		    reg_addr);
4120	REG_WR(sc, reg_addr, val);
4121
4122	if (~sc->attn_state & deasserted) {
4123		PMD_DRV_LOG(ERR, "IGU error");
4124	}
4125
4126	reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4127	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
4128
4129	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4130
4131	aeu_mask = REG_RD(sc, reg_addr);
4132
4133	aeu_mask |= (deasserted & 0x3ff);
4134
4135	REG_WR(sc, reg_addr, aeu_mask);
4136	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4137
4138	sc->attn_state &= ~deasserted;
4139}
4140
4141static void bnx2x_attn_int(struct bnx2x_softc *sc)
4142{
4143	/* read local copy of bits */
4144	uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4145	uint32_t attn_ack =
4146	    le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4147	uint32_t attn_state = sc->attn_state;
4148
4149	/* look for changed bits */
4150	uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4151	uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4152
4153	PMD_DRV_LOG(DEBUG,
4154		    "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4155		    attn_bits, attn_ack, asserted, deasserted);
4156
4157	if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4158		PMD_DRV_LOG(ERR, "BAD attention state");
4159	}
4160
4161	/* handle bits that were raised */
4162	if (asserted) {
4163		bnx2x_attn_int_asserted(sc, asserted);
4164	}
4165
4166	if (deasserted) {
4167		bnx2x_attn_int_deasserted(sc, deasserted);
4168	}
4169}
4170
4171static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4172{
4173	struct host_sp_status_block *def_sb = sc->def_sb;
4174	uint16_t rc = 0;
4175
4176	mb();			/* status block is written to by the chip */
4177
4178	if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4179		sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4180		rc |= BNX2X_DEF_SB_ATT_IDX;
4181	}
4182
4183	if (sc->def_idx != def_sb->sp_sb.running_index) {
4184		sc->def_idx = def_sb->sp_sb.running_index;
4185		rc |= BNX2X_DEF_SB_IDX;
4186	}
4187
4188	mb();
4189
4190	return rc;
4191}
4192
4193static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4194							  uint32_t cid)
4195{
4196	return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4197}
4198
4199static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4200{
4201	struct ecore_mcast_ramrod_params rparam;
4202	int rc;
4203
4204	memset(&rparam, 0, sizeof(rparam));
4205
4206	rparam.mcast_obj = &sc->mcast_obj;
4207
4208	/* clear pending state for the last command */
4209	sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4210
4211	/* if there are pending mcast commands - send them */
4212	if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4213		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4214		if (rc < 0) {
4215			PMD_DRV_LOG(INFO,
4216				    "Failed to send pending mcast commands (%d)",
4217				    rc);
4218		}
4219	}
4220}
4221
4222static void
4223bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4224{
4225	unsigned long ramrod_flags = 0;
4226	int rc = 0;
4227	uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4228	struct ecore_vlan_mac_obj *vlan_mac_obj;
4229
4230	/* always push next commands out, don't wait here */
4231	bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4232
4233	switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4234	case ECORE_FILTER_MAC_PENDING:
4235		PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4236		vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4237		break;
4238
4239	case ECORE_FILTER_MCAST_PENDING:
4240		PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4241		bnx2x_handle_mcast_eqe(sc);
4242		return;
4243
4244	default:
4245		PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4246			    elem->message.data.eth_event.echo);
4247		return;
4248	}
4249
4250	rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4251
4252	if (rc < 0) {
4253		PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4254	} else if (rc > 0) {
4255		PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4256	}
4257}
4258
4259static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4260{
4261	bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4262
4263	/* send rx_mode command again if was requested */
4264	if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4265		bnx2x_set_storm_rx_mode(sc);
4266	}
4267}
4268
4269static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4270{
4271	storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4272	wmb();			/* keep prod updates ordered */
4273}
4274
4275static void bnx2x_eq_int(struct bnx2x_softc *sc)
4276{
4277	uint16_t hw_cons, sw_cons, sw_prod;
4278	union event_ring_elem *elem;
4279	uint8_t echo;
4280	uint32_t cid;
4281	uint8_t opcode;
4282	int spqe_cnt = 0;
4283	struct ecore_queue_sp_obj *q_obj;
4284	struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4285	struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4286
4287	hw_cons = le16toh(*sc->eq_cons_sb);
4288
4289	/*
4290	 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4291	 * when we get to the next-page we need to adjust so the loop
4292	 * condition below will be met. The next element is the size of a
4293	 * regular element and hence incrementing by 1
4294	 */
4295	if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4296		hw_cons++;
4297	}
4298
4299	/*
4300	 * This function may never run in parallel with itself for a
4301	 * specific sc and no need for a read memory barrier here.
4302	 */
4303	sw_cons = sc->eq_cons;
4304	sw_prod = sc->eq_prod;
4305
4306	for (;
4307	     sw_cons != hw_cons;
4308	     sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4309
4310		elem = &sc->eq[EQ_DESC(sw_cons)];
4311
4312/* elem CID originates from FW, actually LE */
4313		cid = SW_CID(elem->message.data.cfc_del_event.cid);
4314		opcode = elem->message.opcode;
4315
4316/* handle eq element */
4317		switch (opcode) {
4318		case EVENT_RING_OPCODE_STAT_QUERY:
4319			PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4320				    sc->stats_comp++);
4321			/* nothing to do with stats comp */
4322			goto next_spqe;
4323
4324		case EVENT_RING_OPCODE_CFC_DEL:
4325			/* handle according to cid range */
4326			/* we may want to verify here that the sc state is HALTING */
4327			PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4328				    cid);
4329			q_obj = bnx2x_cid_to_q_obj(sc, cid);
4330			if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4331				break;
4332			}
4333			goto next_spqe;
4334
4335		case EVENT_RING_OPCODE_STOP_TRAFFIC:
4336			PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4337			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4338				break;
4339			}
4340			goto next_spqe;
4341
4342		case EVENT_RING_OPCODE_START_TRAFFIC:
4343			PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4344			if (f_obj->complete_cmd
4345			    (sc, f_obj, ECORE_F_CMD_TX_START)) {
4346				break;
4347			}
4348			goto next_spqe;
4349
4350		case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4351			echo = elem->message.data.function_update_event.echo;
4352			if (echo == SWITCH_UPDATE) {
4353				PMD_DRV_LOG(DEBUG,
4354					    "got FUNC_SWITCH_UPDATE ramrod");
4355				if (f_obj->complete_cmd(sc, f_obj,
4356							ECORE_F_CMD_SWITCH_UPDATE))
4357				{
4358					break;
4359				}
4360			} else {
4361				PMD_DRV_LOG(DEBUG,
4362					    "AFEX: ramrod completed FUNCTION_UPDATE");
4363				f_obj->complete_cmd(sc, f_obj,
4364						    ECORE_F_CMD_AFEX_UPDATE);
4365			}
4366			goto next_spqe;
4367
4368		case EVENT_RING_OPCODE_FORWARD_SETUP:
4369			q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4370			if (q_obj->complete_cmd(sc, q_obj,
4371						ECORE_Q_CMD_SETUP_TX_ONLY)) {
4372				break;
4373			}
4374			goto next_spqe;
4375
4376		case EVENT_RING_OPCODE_FUNCTION_START:
4377			PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4378			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4379				break;
4380			}
4381			goto next_spqe;
4382
4383		case EVENT_RING_OPCODE_FUNCTION_STOP:
4384			PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4385			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4386				break;
4387			}
4388			goto next_spqe;
4389		}
4390
4391		switch (opcode | sc->state) {
4392		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4393		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4394			cid =
4395			    elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4396			PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4397				    cid);
4398			rss_raw->clear_pending(rss_raw);
4399			break;
4400
4401		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4402		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4403		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4404		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4405		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4406		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4407			PMD_DRV_LOG(DEBUG,
4408				    "got (un)set mac ramrod");
4409			bnx2x_handle_classification_eqe(sc, elem);
4410			break;
4411
4412		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4413		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4414		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4415			PMD_DRV_LOG(DEBUG,
4416				    "got mcast ramrod");
4417			bnx2x_handle_mcast_eqe(sc);
4418			break;
4419
4420		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4421		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4422		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4423			PMD_DRV_LOG(DEBUG,
4424				    "got rx_mode ramrod");
4425			bnx2x_handle_rx_mode_eqe(sc);
4426			break;
4427
4428		default:
4429			/* unknown event log error and continue */
4430			PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4431				    elem->message.opcode, sc->state);
4432		}
4433
4434next_spqe:
4435		spqe_cnt++;
4436	}			/* for */
4437
4438	mb();
4439	atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4440
4441	sc->eq_cons = sw_cons;
4442	sc->eq_prod = sw_prod;
4443
4444	/* make sure that above mem writes were issued towards the memory */
4445	wmb();
4446
4447	/* update producer */
4448	bnx2x_update_eq_prod(sc, sc->eq_prod);
4449}
4450
4451static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4452{
4453	uint16_t status;
4454	int rc = 0;
4455
4456	/* what work needs to be performed? */
4457	status = bnx2x_update_dsb_idx(sc);
4458
4459	/* HW attentions */
4460	if (status & BNX2X_DEF_SB_ATT_IDX) {
4461		PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4462		bnx2x_attn_int(sc);
4463		status &= ~BNX2X_DEF_SB_ATT_IDX;
4464		rc = 1;
4465	}
4466
4467	/* SP events: STAT_QUERY and others */
4468	if (status & BNX2X_DEF_SB_IDX) {
4469/* handle EQ completions */
4470		PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4471		bnx2x_eq_int(sc);
4472		bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4473			   le16toh(sc->def_idx), IGU_INT_NOP, 1);
4474		status &= ~BNX2X_DEF_SB_IDX;
4475	}
4476
4477	/* if status is non zero then something went wrong */
4478	if (unlikely(status)) {
4479		PMD_DRV_LOG(INFO,
4480			    "Got an unknown SP interrupt! (0x%04x)", status);
4481	}
4482
4483	/* ack status block only if something was actually handled */
4484	bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4485		   le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4486
4487	return rc;
4488}
4489
4490static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4491{
4492	struct bnx2x_softc *sc = fp->sc;
4493	uint8_t more_rx = FALSE;
4494
4495	/* update the fastpath index */
4496	bnx2x_update_fp_sb_idx(fp);
4497
4498	if (scan_fp) {
4499		if (bnx2x_has_rx_work(fp)) {
4500			more_rx = bnx2x_rxeof(sc, fp);
4501		}
4502
4503		if (more_rx) {
4504			/* still more work to do */
4505			bnx2x_handle_fp_tq(fp, scan_fp);
4506			return;
4507		}
4508	}
4509
4510	bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4511		   le16toh(fp->fp_hc_idx), IGU_INT_DISABLE, 1);
4512}
4513
4514/*
4515 * Legacy interrupt entry point.
4516 *
4517 * Verifies that the controller generated the interrupt and
4518 * then calls a separate routine to handle the various
4519 * interrupt causes: link, RX, and TX.
4520 */
4521int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4522{
4523	struct bnx2x_fastpath *fp;
4524	uint32_t status, mask;
4525	int i, rc = 0;
4526
4527	/*
4528	 * 0 for ustorm, 1 for cstorm
4529	 * the bits returned from ack_int() are 0-15
4530	 * bit 0 = attention status block
4531	 * bit 1 = fast path status block
4532	 * a mask of 0x2 or more = tx/rx event
4533	 * a mask of 1 = slow path event
4534	 */
4535
4536	status = bnx2x_ack_int(sc);
4537
4538	/* the interrupt is not for us */
4539	if (unlikely(status == 0)) {
4540		return 0;
4541	}
4542
4543	PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4544	//bnx2x_dump_status_block(sc);
4545
4546	FOR_EACH_ETH_QUEUE(sc, i) {
4547		fp = &sc->fp[i];
4548		mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4549		if (status & mask) {
4550			bnx2x_handle_fp_tq(fp, scan_fp);
4551			status &= ~mask;
4552		}
4553	}
4554
4555	if (unlikely(status & 0x1)) {
4556		rc = bnx2x_handle_sp_tq(sc);
4557		status &= ~0x1;
4558	}
4559
4560	if (unlikely(status)) {
4561		PMD_DRV_LOG(WARNING,
4562			    "Unexpected fastpath status (0x%08x)!", status);
4563	}
4564
4565	return rc;
4566}
4567
4568static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4569static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4570static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4571static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4572static void bnx2x_reset_common(struct bnx2x_softc *sc);
4573static void bnx2x_reset_port(struct bnx2x_softc *sc);
4574static void bnx2x_reset_func(struct bnx2x_softc *sc);
4575static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4576static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4577
4578static struct
4579ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4580	.init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4581	.init_hw_cmn = bnx2x_init_hw_common,
4582	.init_hw_port = bnx2x_init_hw_port,
4583	.init_hw_func = bnx2x_init_hw_func,
4584
4585	.reset_hw_cmn = bnx2x_reset_common,
4586	.reset_hw_port = bnx2x_reset_port,
4587	.reset_hw_func = bnx2x_reset_func,
4588
4589	.init_fw = bnx2x_init_firmware,
4590	.release_fw = bnx2x_release_firmware,
4591};
4592
4593static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4594{
4595	sc->dmae_ready = 0;
4596
4597	PMD_INIT_FUNC_TRACE();
4598
4599	ecore_init_func_obj(sc,
4600			    &sc->func_obj,
4601			    BNX2X_SP(sc, func_rdata),
4602			    (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4603			    BNX2X_SP(sc, func_afex_rdata),
4604			    (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4605			    &bnx2x_func_sp_drv);
4606}
4607
4608static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4609{
4610	struct ecore_func_state_params func_params = { NULL };
4611	int rc;
4612
4613	PMD_INIT_FUNC_TRACE();
4614
4615	/* prepare the parameters for function state transitions */
4616	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4617
4618	func_params.f_obj = &sc->func_obj;
4619	func_params.cmd = ECORE_F_CMD_HW_INIT;
4620
4621	func_params.params.hw_init.load_phase = load_code;
4622
4623	/*
4624	 * Via a plethora of function pointers, we will eventually reach
4625	 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4626	 */
4627	rc = ecore_func_state_change(sc, &func_params);
4628
4629	return rc;
4630}
4631
4632static void
4633bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4634{
4635	uint32_t i;
4636
4637	if (!(len % 4) && !(addr % 4)) {
4638		for (i = 0; i < len; i += 4) {
4639			REG_WR(sc, (addr + i), fill);
4640		}
4641	} else {
4642		for (i = 0; i < len; i++) {
4643			REG_WR8(sc, (addr + i), fill);
4644		}
4645	}
4646}
4647
4648/* writes FP SP data to FW - data_size in dwords */
4649static void
4650bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4651		  uint32_t data_size)
4652{
4653	uint32_t index;
4654
4655	for (index = 0; index < data_size; index++) {
4656		REG_WR(sc,
4657		       (BAR_CSTRORM_INTMEM +
4658			CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4659			(sizeof(uint32_t) * index)), *(sb_data_p + index));
4660	}
4661}
4662
4663static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4664{
4665	struct hc_status_block_data_e2 sb_data_e2;
4666	struct hc_status_block_data_e1x sb_data_e1x;
4667	uint32_t *sb_data_p;
4668	uint32_t data_size = 0;
4669
4670	if (!CHIP_IS_E1x(sc)) {
4671		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4672		sb_data_e2.common.state = SB_DISABLED;
4673		sb_data_e2.common.p_func.vf_valid = FALSE;
4674		sb_data_p = (uint32_t *) & sb_data_e2;
4675		data_size = (sizeof(struct hc_status_block_data_e2) /
4676			     sizeof(uint32_t));
4677	} else {
4678		memset(&sb_data_e1x, 0,
4679		       sizeof(struct hc_status_block_data_e1x));
4680		sb_data_e1x.common.state = SB_DISABLED;
4681		sb_data_e1x.common.p_func.vf_valid = FALSE;
4682		sb_data_p = (uint32_t *) & sb_data_e1x;
4683		data_size = (sizeof(struct hc_status_block_data_e1x) /
4684			     sizeof(uint32_t));
4685	}
4686
4687	bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4688
4689	bnx2x_fill(sc,
4690		 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4691		 CSTORM_STATUS_BLOCK_SIZE);
4692	bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4693		 0, CSTORM_SYNC_BLOCK_SIZE);
4694}
4695
4696static void
4697bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4698		  struct hc_sp_status_block_data *sp_sb_data)
4699{
4700	uint32_t i;
4701
4702	for (i = 0;
4703	     i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4704	     i++) {
4705		REG_WR(sc,
4706		       (BAR_CSTRORM_INTMEM +
4707			CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4708			(i * sizeof(uint32_t))),
4709		       *((uint32_t *) sp_sb_data + i));
4710	}
4711}
4712
4713static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4714{
4715	struct hc_sp_status_block_data sp_sb_data;
4716
4717	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4718
4719	sp_sb_data.state = SB_DISABLED;
4720	sp_sb_data.p_func.vf_valid = FALSE;
4721
4722	bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4723
4724	bnx2x_fill(sc,
4725		 (BAR_CSTRORM_INTMEM +
4726		  CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4727		 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4728	bnx2x_fill(sc,
4729		 (BAR_CSTRORM_INTMEM +
4730		  CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4731		 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4732}
4733
4734static void
4735bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4736			     int igu_seg_id)
4737{
4738	hc_sm->igu_sb_id = igu_sb_id;
4739	hc_sm->igu_seg_id = igu_seg_id;
4740	hc_sm->timer_value = 0xFF;
4741	hc_sm->time_to_expire = 0xFFFFFFFF;
4742}
4743
4744static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4745{
4746	/* zero out state machine indices */
4747
4748	/* rx indices */
4749	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4750
4751	/* tx indices */
4752	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4753	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4754	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4755	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4756
4757	/* map indices */
4758
4759	/* rx indices */
4760	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4761	    (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4762
4763	/* tx indices */
4764	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4765	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4767	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4769	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4771	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772}
4773
4774static void
4775bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4776	    uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4777{
4778	struct hc_status_block_data_e2 sb_data_e2;
4779	struct hc_status_block_data_e1x sb_data_e1x;
4780	struct hc_status_block_sm *hc_sm_p;
4781	uint32_t *sb_data_p;
4782	int igu_seg_id;
4783	int data_size;
4784
4785	if (CHIP_INT_MODE_IS_BC(sc)) {
4786		igu_seg_id = HC_SEG_ACCESS_NORM;
4787	} else {
4788		igu_seg_id = IGU_SEG_ACCESS_NORM;
4789	}
4790
4791	bnx2x_zero_fp_sb(sc, fw_sb_id);
4792
4793	if (!CHIP_IS_E1x(sc)) {
4794		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4795		sb_data_e2.common.state = SB_ENABLED;
4796		sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4797		sb_data_e2.common.p_func.vf_id = vfid;
4798		sb_data_e2.common.p_func.vf_valid = vf_valid;
4799		sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4800		sb_data_e2.common.same_igu_sb_1b = TRUE;
4801		sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4802		sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4803		hc_sm_p = sb_data_e2.common.state_machine;
4804		sb_data_p = (uint32_t *) & sb_data_e2;
4805		data_size = (sizeof(struct hc_status_block_data_e2) /
4806			     sizeof(uint32_t));
4807		bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4808	} else {
4809		memset(&sb_data_e1x, 0,
4810		       sizeof(struct hc_status_block_data_e1x));
4811		sb_data_e1x.common.state = SB_ENABLED;
4812		sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4813		sb_data_e1x.common.p_func.vf_id = 0xff;
4814		sb_data_e1x.common.p_func.vf_valid = FALSE;
4815		sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4816		sb_data_e1x.common.same_igu_sb_1b = TRUE;
4817		sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4818		sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4819		hc_sm_p = sb_data_e1x.common.state_machine;
4820		sb_data_p = (uint32_t *) & sb_data_e1x;
4821		data_size = (sizeof(struct hc_status_block_data_e1x) /
4822			     sizeof(uint32_t));
4823		bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4824	}
4825
4826	bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4827	bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4828
4829	/* write indices to HW - PCI guarantees endianity of regpairs */
4830	bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4831}
4832
4833static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4834{
4835	if (CHIP_IS_E1x(fp->sc)) {
4836		return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4837	} else {
4838		return fp->cl_id;
4839	}
4840}
4841
4842static uint32_t
4843bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4844{
4845	uint32_t offset = BAR_USTRORM_INTMEM;
4846
4847	if (IS_VF(sc)) {
4848		return PXP_VF_ADDR_USDM_QUEUES_START +
4849			(sc->acquire_resp.resc.hw_qid[fp->index] *
4850			 sizeof(struct ustorm_queue_zone_data));
4851	} else if (!CHIP_IS_E1x(sc)) {
4852		offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4853	} else {
4854		offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4855	}
4856
4857	return offset;
4858}
4859
4860static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4861{
4862	struct bnx2x_fastpath *fp = &sc->fp[idx];
4863	uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4864	unsigned long q_type = 0;
4865	int cos;
4866
4867	fp->sc = sc;
4868	fp->index = idx;
4869
4870	fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4871	fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4872
4873	if (CHIP_IS_E1x(sc))
4874		fp->cl_id = SC_L_ID(sc) + idx;
4875	else
4876/* want client ID same as IGU SB ID for non-E1 */
4877		fp->cl_id = fp->igu_sb_id;
4878	fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4879
4880	/* setup sb indices */
4881	if (!CHIP_IS_E1x(sc)) {
4882		fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4883		fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4884	} else {
4885		fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4886		fp->sb_running_index =
4887		    fp->status_block.e1x_sb->sb.running_index;
4888	}
4889
4890	/* init shortcut */
4891	fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4892
4893	fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4894
4895	for (cos = 0; cos < sc->max_cos; cos++) {
4896		cids[cos] = idx;
4897	}
4898	fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4899
4900	/* nothing more for a VF to do */
4901	if (IS_VF(sc)) {
4902		return;
4903	}
4904
4905	bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4906		    fp->fw_sb_id, fp->igu_sb_id);
4907
4908	bnx2x_update_fp_sb_idx(fp);
4909
4910	/* Configure Queue State object */
4911	bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4912	bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4913
4914	ecore_init_queue_obj(sc,
4915			     &sc->sp_objs[idx].q_obj,
4916			     fp->cl_id,
4917			     cids,
4918			     sc->max_cos,
4919			     SC_FUNC(sc),
4920			     BNX2X_SP(sc, q_rdata),
4921			     (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4922			     q_type);
4923
4924	/* configure classification DBs */
4925	ecore_init_mac_obj(sc,
4926			   &sc->sp_objs[idx].mac_obj,
4927			   fp->cl_id,
4928			   idx,
4929			   SC_FUNC(sc),
4930			   BNX2X_SP(sc, mac_rdata),
4931			   (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4932			   ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4933			   ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4934}
4935
4936static void
4937bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4938		   uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4939{
4940	union ustorm_eth_rx_producers rx_prods;
4941	uint32_t i;
4942
4943	/* update producers */
4944	rx_prods.prod.bd_prod = rx_bd_prod;
4945	rx_prods.prod.cqe_prod = rx_cq_prod;
4946	rx_prods.prod.reserved = 0;
4947
4948	/*
4949	 * Make sure that the BD and SGE data is updated before updating the
4950	 * producers since FW might read the BD/SGE right after the producer
4951	 * is updated.
4952	 * This is only applicable for weak-ordered memory model archs such
4953	 * as IA-64. The following barrier is also mandatory since FW will
4954	 * assumes BDs must have buffers.
4955	 */
4956	wmb();
4957
4958	for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4959		REG_WR(sc,
4960		       (fp->ustorm_rx_prods_offset + (i * 4)),
4961		       rx_prods.raw_data[i]);
4962	}
4963
4964	wmb();			/* keep prod updates ordered */
4965}
4966
4967static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4968{
4969	struct bnx2x_fastpath *fp;
4970	int i;
4971	struct bnx2x_rx_queue *rxq;
4972
4973	for (i = 0; i < sc->num_queues; i++) {
4974		fp = &sc->fp[i];
4975		rxq = sc->rx_queues[fp->index];
4976		if (!rxq) {
4977			PMD_RX_LOG(ERR, "RX queue is NULL");
4978			return;
4979		}
4980
4981		rxq->rx_bd_head = 0;
4982		rxq->rx_bd_tail = rxq->nb_rx_desc;
4983		rxq->rx_cq_head = 0;
4984		rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4985		*fp->rx_cq_cons_sb = 0;
4986
4987		/*
4988		 * Activate the BD ring...
4989		 * Warning, this will generate an interrupt (to the TSTORM)
4990		 * so this can only be done after the chip is initialized
4991		 */
4992		bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4993
4994		if (i != 0) {
4995			continue;
4996		}
4997	}
4998}
4999
5000static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5001{
5002	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5003
5004	fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5005	fp->tx_db.data.zero_fill1 = 0;
5006	fp->tx_db.data.prod = 0;
5007
5008	if (!txq) {
5009		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5010		return;
5011	}
5012
5013	txq->tx_pkt_tail = 0;
5014	txq->tx_pkt_head = 0;
5015	txq->tx_bd_tail = 0;
5016	txq->tx_bd_head = 0;
5017}
5018
5019static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5020{
5021	int i;
5022
5023	for (i = 0; i < sc->num_queues; i++) {
5024		bnx2x_init_tx_ring_one(&sc->fp[i]);
5025	}
5026}
5027
5028static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5029{
5030	struct host_sp_status_block *def_sb = sc->def_sb;
5031	phys_addr_t mapping = sc->def_sb_dma.paddr;
5032	int igu_sp_sb_index;
5033	int igu_seg_id;
5034	int port = SC_PORT(sc);
5035	int func = SC_FUNC(sc);
5036	int reg_offset, reg_offset_en5;
5037	uint64_t section;
5038	int index, sindex;
5039	struct hc_sp_status_block_data sp_sb_data;
5040
5041	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5042
5043	if (CHIP_INT_MODE_IS_BC(sc)) {
5044		igu_sp_sb_index = DEF_SB_IGU_ID;
5045		igu_seg_id = HC_SEG_ACCESS_DEF;
5046	} else {
5047		igu_sp_sb_index = sc->igu_dsb_id;
5048		igu_seg_id = IGU_SEG_ACCESS_DEF;
5049	}
5050
5051	/* attentions */
5052	section = ((uint64_t) mapping +
5053		   offsetof(struct host_sp_status_block, atten_status_block));
5054	def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5055	sc->attn_state = 0;
5056
5057	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5058	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5059
5060	reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5061	    MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5062
5063	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5064/* take care of sig[0]..sig[4] */
5065		for (sindex = 0; sindex < 4; sindex++) {
5066			sc->attn_group[index].sig[sindex] =
5067			    REG_RD(sc,
5068				   (reg_offset + (sindex * 0x4) +
5069				    (0x10 * index)));
5070		}
5071
5072		if (!CHIP_IS_E1x(sc)) {
5073			/*
5074			 * enable5 is separate from the rest of the registers,
5075			 * and the address skip is 4 and not 16 between the
5076			 * different groups
5077			 */
5078			sc->attn_group[index].sig[4] =
5079			    REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5080		} else {
5081			sc->attn_group[index].sig[4] = 0;
5082		}
5083	}
5084
5085	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5086		reg_offset =
5087		    port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5088		REG_WR(sc, reg_offset, U64_LO(section));
5089		REG_WR(sc, (reg_offset + 4), U64_HI(section));
5090	} else if (!CHIP_IS_E1x(sc)) {
5091		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5092		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5093	}
5094
5095	section = ((uint64_t) mapping +
5096		   offsetof(struct host_sp_status_block, sp_sb));
5097
5098	bnx2x_zero_sp_sb(sc);
5099
5100	/* PCI guarantees endianity of regpair */
5101	sp_sb_data.state = SB_ENABLED;
5102	sp_sb_data.host_sb_addr.lo = U64_LO(section);
5103	sp_sb_data.host_sb_addr.hi = U64_HI(section);
5104	sp_sb_data.igu_sb_id = igu_sp_sb_index;
5105	sp_sb_data.igu_seg_id = igu_seg_id;
5106	sp_sb_data.p_func.pf_id = func;
5107	sp_sb_data.p_func.vnic_id = SC_VN(sc);
5108	sp_sb_data.p_func.vf_id = 0xff;
5109
5110	bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5111
5112	bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5113}
5114
5115static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5116{
5117	atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5118	sc->spq_prod_idx = 0;
5119	sc->dsb_sp_prod =
5120	    &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5121	sc->spq_prod_bd = sc->spq;
5122	sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5123}
5124
5125static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5126{
5127	union event_ring_elem *elem;
5128	int i;
5129
5130	for (i = 1; i <= NUM_EQ_PAGES; i++) {
5131		elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5132
5133		elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5134							 BNX2X_PAGE_SIZE *
5135							 (i % NUM_EQ_PAGES)));
5136		elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5137							 BNX2X_PAGE_SIZE *
5138							 (i % NUM_EQ_PAGES)));
5139	}
5140
5141	sc->eq_cons = 0;
5142	sc->eq_prod = NUM_EQ_DESC;
5143	sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5144
5145	atomic_store_rel_long(&sc->eq_spq_left,
5146			      (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5147				   NUM_EQ_DESC) - 1));
5148}
5149
5150static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5151{
5152	int i;
5153
5154	if (IS_MF_SI(sc)) {
5155/*
5156 * In switch independent mode, the TSTORM needs to accept
5157 * packets that failed classification, since approximate match
5158 * mac addresses aren't written to NIG LLH.
5159 */
5160		REG_WR8(sc,
5161			(BAR_TSTRORM_INTMEM +
5162			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5163	} else
5164		REG_WR8(sc,
5165			(BAR_TSTRORM_INTMEM +
5166			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5167
5168	/*
5169	 * Zero this manually as its initialization is currently missing
5170	 * in the initTool.
5171	 */
5172	for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5173		REG_WR(sc,
5174		       (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5175		       0);
5176	}
5177
5178	if (!CHIP_IS_E1x(sc)) {
5179		REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5180			CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5181			HC_IGU_NBC_MODE);
5182	}
5183}
5184
5185static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5186{
5187	switch (load_code) {
5188	case FW_MSG_CODE_DRV_LOAD_COMMON:
5189	case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5190		bnx2x_init_internal_common(sc);
5191		/* no break */
5192
5193	case FW_MSG_CODE_DRV_LOAD_PORT:
5194		/* nothing to do */
5195		/* no break */
5196
5197	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5198		/* internal memory per function is initialized inside bnx2x_pf_init */
5199		break;
5200
5201	default:
5202		PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5203			    load_code);
5204		break;
5205	}
5206}
5207
5208static void
5209storm_memset_func_cfg(struct bnx2x_softc *sc,
5210		      struct tstorm_eth_function_common_config *tcfg,
5211		      uint16_t abs_fid)
5212{
5213	uint32_t addr;
5214	size_t size;
5215
5216	addr = (BAR_TSTRORM_INTMEM +
5217		TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5218	size = sizeof(struct tstorm_eth_function_common_config);
5219	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5220}
5221
5222static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5223{
5224	struct tstorm_eth_function_common_config tcfg = { 0 };
5225
5226	if (CHIP_IS_E1x(sc)) {
5227		storm_memset_func_cfg(sc, &tcfg, p->func_id);
5228	}
5229
5230	/* Enable the function in the FW */
5231	storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5232	storm_memset_func_en(sc, p->func_id, 1);
5233
5234	/* spq */
5235	if (p->func_flgs & FUNC_FLG_SPQ) {
5236		storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5237		REG_WR(sc,
5238		       (XSEM_REG_FAST_MEMORY +
5239			XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5240	}
5241}
5242
5243/*
5244 * Calculates the sum of vn_min_rates.
5245 * It's needed for further normalizing of the min_rates.
5246 * Returns:
5247 *   sum of vn_min_rates.
5248 *     or
5249 *   0 - if all the min_rates are 0.
5250 * In the later case fainess algorithm should be deactivated.
5251 * If all min rates are not zero then those that are zeroes will be set to 1.
5252 */
5253static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5254{
5255	uint32_t vn_cfg;
5256	uint32_t vn_min_rate;
5257	int all_zero = 1;
5258	int vn;
5259
5260	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5261		vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5262		vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5263				FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5264
5265		if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5266			/* skip hidden VNs */
5267			vn_min_rate = 0;
5268		} else if (!vn_min_rate) {
5269			/* If min rate is zero - set it to 100 */
5270			vn_min_rate = DEF_MIN_RATE;
5271		} else {
5272			all_zero = 0;
5273		}
5274
5275		input->vnic_min_rate[vn] = vn_min_rate;
5276	}
5277
5278	/* if ETS or all min rates are zeros - disable fairness */
5279	if (all_zero) {
5280		input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281	} else {
5282		input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5283	}
5284}
5285
5286static uint16_t
5287bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5288{
5289	uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5290			    FUNC_MF_CFG_MAX_BW_SHIFT);
5291
5292	if (!max_cfg) {
5293		PMD_DRV_LOG(DEBUG,
5294			    "Max BW configured to 0 - using 100 instead");
5295		max_cfg = 100;
5296	}
5297
5298	return max_cfg;
5299}
5300
5301static void
5302bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5303{
5304	uint16_t vn_max_rate;
5305	uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5306	uint32_t max_cfg;
5307
5308	if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5309		vn_max_rate = 0;
5310	} else {
5311		max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5312
5313		if (IS_MF_SI(sc)) {
5314			/* max_cfg in percents of linkspeed */
5315			vn_max_rate =
5316			    ((sc->link_vars.line_speed * max_cfg) / 100);
5317		} else {	/* SD modes */
5318			/* max_cfg is absolute in 100Mb units */
5319			vn_max_rate = (max_cfg * 100);
5320		}
5321	}
5322
5323	input->vnic_max_rate[vn] = vn_max_rate;
5324}
5325
5326static void
5327bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5328{
5329	struct cmng_init_input input;
5330	int vn;
5331
5332	memset(&input, 0, sizeof(struct cmng_init_input));
5333
5334	input.port_rate = sc->link_vars.line_speed;
5335
5336	if (cmng_type == CMNG_FNS_MINMAX) {
5337/* read mf conf from shmem */
5338		if (read_cfg) {
5339			bnx2x_read_mf_cfg(sc);
5340		}
5341
5342/* get VN min rate and enable fairness if not 0 */
5343		bnx2x_calc_vn_min(sc, &input);
5344
5345/* get VN max rate */
5346		if (sc->port.pmf) {
5347			for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5348				bnx2x_calc_vn_max(sc, vn, &input);
5349			}
5350		}
5351
5352/* always enable rate shaping and fairness */
5353		input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5354
5355		ecore_init_cmng(&input, &sc->cmng);
5356		return;
5357	}
5358}
5359
5360static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5361{
5362	if (CHIP_REV_IS_SLOW(sc)) {
5363		return CMNG_FNS_NONE;
5364	}
5365
5366	if (IS_MF(sc)) {
5367		return CMNG_FNS_MINMAX;
5368	}
5369
5370	return CMNG_FNS_NONE;
5371}
5372
5373static void
5374storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5375{
5376	int vn;
5377	int func;
5378	uint32_t addr;
5379	size_t size;
5380
5381	addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5382	size = sizeof(struct cmng_struct_per_port);
5383	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5384
5385	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5386		func = func_by_vn(sc, vn);
5387
5388		addr = (BAR_XSTRORM_INTMEM +
5389			XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5390		size = sizeof(struct rate_shaping_vars_per_vn);
5391		ecore_storm_memset_struct(sc, addr, size,
5392					  (uint32_t *) & cmng->
5393					  vnic.vnic_max_rate[vn]);
5394
5395		addr = (BAR_XSTRORM_INTMEM +
5396			XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5397		size = sizeof(struct fairness_vars_per_vn);
5398		ecore_storm_memset_struct(sc, addr, size,
5399					  (uint32_t *) & cmng->
5400					  vnic.vnic_min_rate[vn]);
5401	}
5402}
5403
5404static void bnx2x_pf_init(struct bnx2x_softc *sc)
5405{
5406	struct bnx2x_func_init_params func_init;
5407	struct event_ring_data eq_data;
5408	uint16_t flags;
5409
5410	memset(&eq_data, 0, sizeof(struct event_ring_data));
5411	memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5412
5413	if (!CHIP_IS_E1x(sc)) {
5414/* reset IGU PF statistics: MSIX + ATTN */
5415/* PF */
5416		REG_WR(sc,
5417		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5418			(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5419			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5420			 4)), 0);
5421/* ATTN */
5422		REG_WR(sc,
5423		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424			(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425			(BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5426			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5427			 4)), 0);
5428	}
5429
5430	/* function setup flags */
5431	flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5432
5433	func_init.func_flgs = flags;
5434	func_init.pf_id = SC_FUNC(sc);
5435	func_init.func_id = SC_FUNC(sc);
5436	func_init.spq_map = sc->spq_dma.paddr;
5437	func_init.spq_prod = sc->spq_prod_idx;
5438
5439	bnx2x_func_init(sc, &func_init);
5440
5441	memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5442
5443	/*
5444	 * Congestion management values depend on the link rate.
5445	 * There is no active link so initial link rate is set to 10Gbps.
5446	 * When the link comes up the congestion management values are
5447	 * re-calculated according to the actual link rate.
5448	 */
5449	sc->link_vars.line_speed = SPEED_10000;
5450	bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5451
5452	/* Only the PMF sets the HW */
5453	if (sc->port.pmf) {
5454		storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5455	}
5456
5457	/* init Event Queue - PCI bus guarantees correct endainity */
5458	eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5459	eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5460	eq_data.producer = sc->eq_prod;
5461	eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5462	eq_data.sb_id = DEF_SB_ID;
5463	storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5464}
5465
5466static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5467{
5468	int port = SC_PORT(sc);
5469	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5470	uint32_t val = REG_RD(sc, addr);
5471	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5472	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5474	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5475
5476	if (msix) {
5477		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5478			 HC_CONFIG_0_REG_INT_LINE_EN_0);
5479		val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5480			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5481		if (single_msix) {
5482			val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5483		}
5484	} else if (msi) {
5485		val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5486		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5487			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5488			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5489	} else {
5490		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5491			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492			HC_CONFIG_0_REG_INT_LINE_EN_0 |
5493			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494
5495		REG_WR(sc, addr, val);
5496
5497		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5498	}
5499
5500	REG_WR(sc, addr, val);
5501
5502	/* ensure that HC_CONFIG is written before leading/trailing edge config */
5503	mb();
5504
5505	/* init leading/trailing edge */
5506	if (IS_MF(sc)) {
5507		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5508		if (sc->port.pmf) {
5509			/* enable nig and gpio3 attention */
5510			val |= 0x1100;
5511		}
5512	} else {
5513		val = 0xffff;
5514	}
5515
5516	REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5517	REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5518
5519	/* make sure that interrupts are indeed enabled from here on */
5520	mb();
5521}
5522
5523static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5524{
5525	uint32_t val;
5526	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5527	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5529	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5530
5531	val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5532
5533	if (msix) {
5534		val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5535		val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5536		if (single_msix) {
5537			val |= IGU_PF_CONF_SINGLE_ISR_EN;
5538		}
5539	} else if (msi) {
5540		val &= ~IGU_PF_CONF_INT_LINE_EN;
5541		val |= (IGU_PF_CONF_MSI_MSIX_EN |
5542			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5543	} else {
5544		val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5545		val |= (IGU_PF_CONF_INT_LINE_EN |
5546			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5547	}
5548
5549	/* clean previous status - need to configure igu prior to ack */
5550	if ((!msix) || single_msix) {
5551		REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5552		bnx2x_ack_int(sc);
5553	}
5554
5555	val |= IGU_PF_CONF_FUNC_EN;
5556
5557	PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5558		    val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5559
5560	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5561
5562	mb();
5563
5564	/* init leading/trailing edge */
5565	if (IS_MF(sc)) {
5566		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5567		if (sc->port.pmf) {
5568			/* enable nig and gpio3 attention */
5569			val |= 0x1100;
5570		}
5571	} else {
5572		val = 0xffff;
5573	}
5574
5575	REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5576	REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5577
5578	/* make sure that interrupts are indeed enabled from here on */
5579	mb();
5580}
5581
5582static void bnx2x_int_enable(struct bnx2x_softc *sc)
5583{
5584	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5585		bnx2x_hc_int_enable(sc);
5586	} else {
5587		bnx2x_igu_int_enable(sc);
5588	}
5589}
5590
5591static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5592{
5593	int port = SC_PORT(sc);
5594	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5595	uint32_t val = REG_RD(sc, addr);
5596
5597	val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5598		 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5599		 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5600	/* flush all outstanding writes */
5601	mb();
5602
5603	REG_WR(sc, addr, val);
5604	if (REG_RD(sc, addr) != val) {
5605		PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5606	}
5607}
5608
5609static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5610{
5611	uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5612
5613	val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5614		 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5615
5616	PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5617
5618	/* flush all outstanding writes */
5619	mb();
5620
5621	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5622	if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5623		PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5624	}
5625}
5626
5627static void bnx2x_int_disable(struct bnx2x_softc *sc)
5628{
5629	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5630		bnx2x_hc_int_disable(sc);
5631	} else {
5632		bnx2x_igu_int_disable(sc);
5633	}
5634}
5635
5636static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5637{
5638	int i;
5639
5640	PMD_INIT_FUNC_TRACE();
5641
5642	for (i = 0; i < sc->num_queues; i++) {
5643		bnx2x_init_eth_fp(sc, i);
5644	}
5645
5646	rmb();			/* ensure status block indices were read */
5647
5648	bnx2x_init_rx_rings(sc);
5649	bnx2x_init_tx_rings(sc);
5650
5651	if (IS_VF(sc)) {
5652		bnx2x_memset_stats(sc);
5653		return;
5654	}
5655
5656	/* initialize MOD_ABS interrupts */
5657	elink_init_mod_abs_int(sc, &sc->link_vars,
5658			       sc->devinfo.chip_id,
5659			       sc->devinfo.shmem_base,
5660			       sc->devinfo.shmem2_base, SC_PORT(sc));
5661
5662	bnx2x_init_def_sb(sc);
5663	bnx2x_update_dsb_idx(sc);
5664	bnx2x_init_sp_ring(sc);
5665	bnx2x_init_eq_ring(sc);
5666	bnx2x_init_internal(sc, load_code);
5667	bnx2x_pf_init(sc);
5668	bnx2x_stats_init(sc);
5669
5670	/* flush all before enabling interrupts */
5671	mb();
5672
5673	bnx2x_int_enable(sc);
5674
5675	/* check for SPIO5 */
5676	bnx2x_attn_int_deasserted0(sc,
5677				 REG_RD(sc,
5678					(MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5679					 SC_PORT(sc) * 4)) &
5680				 AEU_INPUTS_ATTN_BITS_SPIO5);
5681}
5682
5683static void bnx2x_init_objs(struct bnx2x_softc *sc)
5684{
5685	/* mcast rules must be added to tx if tx switching is enabled */
5686	ecore_obj_type o_type;
5687	if (sc->flags & BNX2X_TX_SWITCHING)
5688		o_type = ECORE_OBJ_TYPE_RX_TX;
5689	else
5690		o_type = ECORE_OBJ_TYPE_RX;
5691
5692	/* RX_MODE controlling object */
5693	ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5694
5695	/* multicast configuration controlling object */
5696	ecore_init_mcast_obj(sc,
5697			     &sc->mcast_obj,
5698			     sc->fp[0].cl_id,
5699			     sc->fp[0].index,
5700			     SC_FUNC(sc),
5701			     SC_FUNC(sc),
5702			     BNX2X_SP(sc, mcast_rdata),
5703			     (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5704			     ECORE_FILTER_MCAST_PENDING,
5705			     &sc->sp_state, o_type);
5706
5707	/* Setup CAM credit pools */
5708	ecore_init_mac_credit_pool(sc,
5709				   &sc->macs_pool,
5710				   SC_FUNC(sc),
5711				   CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5712				   VNICS_PER_PATH(sc));
5713
5714	ecore_init_vlan_credit_pool(sc,
5715				    &sc->vlans_pool,
5716				    SC_ABS_FUNC(sc) >> 1,
5717				    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718				    VNICS_PER_PATH(sc));
5719
5720	/* RSS configuration object */
5721	ecore_init_rss_config_obj(&sc->rss_conf_obj,
5722				  sc->fp[0].cl_id,
5723				  sc->fp[0].index,
5724				  SC_FUNC(sc),
5725				  SC_FUNC(sc),
5726				  BNX2X_SP(sc, rss_rdata),
5727				  (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5728				  ECORE_FILTER_RSS_CONF_PENDING,
5729				  &sc->sp_state, ECORE_OBJ_TYPE_RX);
5730}
5731
5732/*
5733 * Initialize the function. This must be called before sending CLIENT_SETUP
5734 * for the first client.
5735 */
5736static int bnx2x_func_start(struct bnx2x_softc *sc)
5737{
5738	struct ecore_func_state_params func_params = { NULL };
5739	struct ecore_func_start_params *start_params =
5740	    &func_params.params.start;
5741
5742	/* Prepare parameters for function state transitions */
5743	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5744
5745	func_params.f_obj = &sc->func_obj;
5746	func_params.cmd = ECORE_F_CMD_START;
5747
5748	/* Function parameters */
5749	start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5750	start_params->sd_vlan_tag = OVLAN(sc);
5751
5752	if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5753		start_params->network_cos_mode = STATIC_COS;
5754	} else {		/* CHIP_IS_E1X */
5755		start_params->network_cos_mode = FW_WRR;
5756	}
5757
5758	start_params->gre_tunnel_mode = 0;
5759	start_params->gre_tunnel_rss = 0;
5760
5761	return ecore_func_state_change(sc, &func_params);
5762}
5763
5764static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5765{
5766	uint16_t pmcsr;
5767
5768	/* If there is no power capability, silently succeed */
5769	if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5770		PMD_DRV_LOG(WARNING, "No power capability");
5771		return 0;
5772	}
5773
5774	pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5775		 2);
5776
5777	switch (state) {
5778	case PCI_PM_D0:
5779		pci_write_word(sc,
5780			       (sc->devinfo.pcie_pm_cap_reg +
5781				PCIR_POWER_STATUS),
5782			       ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5783
5784		if (pmcsr & PCIM_PSTAT_DMASK) {
5785			/* delay required during transition out of D3hot */
5786			DELAY(20000);
5787		}
5788
5789		break;
5790
5791	case PCI_PM_D3hot:
5792		/* don't shut down the power for emulation and FPGA */
5793		if (CHIP_REV_IS_SLOW(sc)) {
5794			return 0;
5795		}
5796
5797		pmcsr &= ~PCIM_PSTAT_DMASK;
5798		pmcsr |= PCIM_PSTAT_D3;
5799
5800		if (sc->wol) {
5801			pmcsr |= PCIM_PSTAT_PMEENABLE;
5802		}
5803
5804		pci_write_long(sc,
5805			       (sc->devinfo.pcie_pm_cap_reg +
5806				PCIR_POWER_STATUS), pmcsr);
5807
5808		/*
5809		 * No more memory access after this point until device is brought back
5810		 * to D0 state.
5811		 */
5812		break;
5813
5814	default:
5815		PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5816			    state);
5817		return -1;
5818	}
5819
5820	return 0;
5821}
5822
5823/* return true if succeeded to acquire the lock */
5824static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5825{
5826	uint32_t lock_status;
5827	uint32_t resource_bit = (1 << resource);
5828	int func = SC_FUNC(sc);
5829	uint32_t hw_lock_control_reg;
5830
5831	/* Validating that the resource is within range */
5832	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5833		PMD_DRV_LOG(INFO,
5834			    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5835			    resource, HW_LOCK_MAX_RESOURCE_VALUE);
5836		return FALSE;
5837	}
5838
5839	if (func <= 5) {
5840		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5841	} else {
5842		hw_lock_control_reg =
5843		    (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5844	}
5845
5846	/* try to acquire the lock */
5847	REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5848	lock_status = REG_RD(sc, hw_lock_control_reg);
5849	if (lock_status & resource_bit) {
5850		return TRUE;
5851	}
5852
5853	PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5854
5855	return FALSE;
5856}
5857
5858/*
5859 * Get the recovery leader resource id according to the engine this function
5860 * belongs to. Currently only only 2 engines is supported.
5861 */
5862static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5863{
5864	if (SC_PATH(sc)) {
5865		return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5866	} else {
5867		return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5868	}
5869}
5870
5871/* try to acquire a leader lock for current engine */
5872static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5873{
5874	return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5875}
5876
5877static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5878{
5879	return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5880}
5881
5882/* close gates #2, #3 and #4 */
5883static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5884{
5885	uint32_t val;
5886
5887	/* gates #2 and #4a are closed/opened */
5888	/* #4 */
5889	REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5890	/* #2 */
5891	REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5892
5893	/* #3 */
5894	if (CHIP_IS_E1x(sc)) {
5895/* prevent interrupts from HC on both ports */
5896		val = REG_RD(sc, HC_REG_CONFIG_1);
5897		if (close)
5898			REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5899						     HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5900		else
5901			REG_WR(sc, HC_REG_CONFIG_1,
5902			       (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5903
5904		val = REG_RD(sc, HC_REG_CONFIG_0);
5905		if (close)
5906			REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5907						     HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5908		else
5909			REG_WR(sc, HC_REG_CONFIG_0,
5910			       (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5911
5912	} else {
5913/* Prevent incomming interrupts in IGU */
5914		val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5915
5916		if (close)
5917			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5918			       (val & ~(uint32_t)
5919				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5920		else
5921			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5922			       (val |
5923				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5924	}
5925
5926	wmb();
5927}
5928
5929/* poll for pending writes bit, it should get cleared in no more than 1s */
5930static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5931{
5932	uint32_t cnt = 1000;
5933	uint32_t pend_bits = 0;
5934
5935	do {
5936		pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5937
5938		if (pend_bits == 0) {
5939			break;
5940		}
5941
5942		DELAY(1000);
5943	} while (cnt-- > 0);
5944
5945	if (cnt <= 0) {
5946		PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5947			    pend_bits);
5948		return -1;
5949	}
5950
5951	return 0;
5952}
5953
5954#define SHARED_MF_CLP_MAGIC  0x80000000	/* 'magic' bit */
5955
5956static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5957{
5958	/* Do some magic... */
5959	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5960	*magic_val = val & SHARED_MF_CLP_MAGIC;
5961	MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5962}
5963
5964/* restore the value of the 'magic' bit */
5965static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5966{
5967	/* Restore the 'magic' bit value... */
5968	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5969	MFCFG_WR(sc, shared_mf_config.clp_mb,
5970		 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5971}
5972
5973/* prepare for MCP reset, takes care of CLP configurations */
5974static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5975{
5976	uint32_t shmem;
5977	uint32_t validity_offset;
5978
5979	/* set `magic' bit in order to save MF config */
5980	bnx2x_clp_reset_prep(sc, magic_val);
5981
5982	/* get shmem offset */
5983	shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5984	validity_offset =
5985	    offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5986
5987	/* Clear validity map flags */
5988	if (shmem > 0) {
5989		REG_WR(sc, shmem + validity_offset, 0);
5990	}
5991}
5992
5993#define MCP_TIMEOUT      5000	/* 5 seconds (in ms) */
5994#define MCP_ONE_TIMEOUT  100	/* 100 ms */
5995
5996static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5997{
5998	/* special handling for emulation and FPGA (10 times longer) */
5999	if (CHIP_REV_IS_SLOW(sc)) {
6000		DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6001	} else {
6002		DELAY((MCP_ONE_TIMEOUT) * 1000);
6003	}
6004}
6005
6006/* initialize shmem_base and waits for validity signature to appear */
6007static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6008{
6009	int cnt = 0;
6010	uint32_t val = 0;
6011
6012	do {
6013		sc->devinfo.shmem_base =
6014		    sc->link_params.shmem_base =
6015		    REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6016
6017		if (sc->devinfo.shmem_base) {
6018			val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6019			if (val & SHR_MEM_VALIDITY_MB)
6020				return 0;
6021		}
6022
6023		bnx2x_mcp_wait_one(sc);
6024
6025	} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6026
6027	PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6028
6029	return -1;
6030}
6031
6032static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6033{
6034	int rc = bnx2x_init_shmem(sc);
6035
6036	/* Restore the `magic' bit value */
6037	bnx2x_clp_reset_done(sc, magic_val);
6038
6039	return rc;
6040}
6041
6042static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6043{
6044	REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6045	REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6046	wmb();
6047}
6048
6049/*
6050 * Reset the whole chip except for:
6051 *      - PCIE core
6052 *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6053 *      - IGU
6054 *      - MISC (including AEU)
6055 *      - GRC
6056 *      - RBCN, RBCP
6057 */
6058static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6059{
6060	uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6061	uint32_t global_bits2, stay_reset2;
6062
6063	/*
6064	 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6065	 * (per chip) blocks.
6066	 */
6067	global_bits2 =
6068	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6069	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6070
6071	/*
6072	 * Don't reset the following blocks.
6073	 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6074	 *            reset, as in 4 port device they might still be owned
6075	 *            by the MCP (there is only one leader per path).
6076	 */
6077	not_reset_mask1 =
6078	    MISC_REGISTERS_RESET_REG_1_RST_HC |
6079	    MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6080	    MISC_REGISTERS_RESET_REG_1_RST_PXP;
6081
6082	not_reset_mask2 =
6083	    MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6084	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6085	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6086	    MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6087	    MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6088	    MISC_REGISTERS_RESET_REG_2_RST_GRC |
6089	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6090	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6091	    MISC_REGISTERS_RESET_REG_2_RST_ATC |
6092	    MISC_REGISTERS_RESET_REG_2_PGLC |
6093	    MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6094	    MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6095	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6096	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6097	    MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6098
6099	/*
6100	 * Keep the following blocks in reset:
6101	 *  - all xxMACs are handled by the elink code.
6102	 */
6103	stay_reset2 =
6104	    MISC_REGISTERS_RESET_REG_2_XMAC |
6105	    MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6106
6107	/* Full reset masks according to the chip */
6108	reset_mask1 = 0xffffffff;
6109
6110	if (CHIP_IS_E1H(sc))
6111		reset_mask2 = 0x1ffff;
6112	else if (CHIP_IS_E2(sc))
6113		reset_mask2 = 0xfffff;
6114	else			/* CHIP_IS_E3 */
6115		reset_mask2 = 0x3ffffff;
6116
6117	/* Don't reset global blocks unless we need to */
6118	if (!global)
6119		reset_mask2 &= ~global_bits2;
6120
6121	/*
6122	 * In case of attention in the QM, we need to reset PXP
6123	 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6124	 * because otherwise QM reset would release 'close the gates' shortly
6125	 * before resetting the PXP, then the PSWRQ would send a write
6126	 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6127	 * read the payload data from PSWWR, but PSWWR would not
6128	 * respond. The write queue in PGLUE would stuck, dmae commands
6129	 * would not return. Therefore it's important to reset the second
6130	 * reset register (containing the
6131	 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6132	 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6133	 * bit).
6134	 */
6135	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136	       reset_mask2 & (~not_reset_mask2));
6137
6138	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6139	       reset_mask1 & (~not_reset_mask1));
6140
6141	mb();
6142	wmb();
6143
6144	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6145	       reset_mask2 & (~stay_reset2));
6146
6147	mb();
6148	wmb();
6149
6150	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6151	wmb();
6152}
6153
6154static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6155{
6156	int cnt = 1000;
6157	uint32_t val = 0;
6158	uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6159	uint32_t tags_63_32 = 0;
6160
6161	/* Empty the Tetris buffer, wait for 1s */
6162	do {
6163		sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6164		blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6165		port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6166		port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6167		pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6168		if (CHIP_IS_E3(sc)) {
6169			tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6170		}
6171
6172		if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6173		    ((port_is_idle_0 & 0x1) == 0x1) &&
6174		    ((port_is_idle_1 & 0x1) == 0x1) &&
6175		    (pgl_exp_rom2 == 0xffffffff) &&
6176		    (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6177			break;
6178		DELAY(1000);
6179	} while (cnt-- > 0);
6180
6181	if (cnt <= 0) {
6182		PMD_DRV_LOG(NOTICE,
6183			    "ERROR: Tetris buffer didn't get empty or there "
6184			    "are still outstanding read requests after 1s! "
6185			    "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6186			    "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6187			    sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6188			    pgl_exp_rom2);
6189		return -1;
6190	}
6191
6192	mb();
6193
6194	/* Close gates #2, #3 and #4 */
6195	bnx2x_set_234_gates(sc, TRUE);
6196
6197	/* Poll for IGU VQs for 57712 and newer chips */
6198	if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6199		return -1;
6200	}
6201
6202	/* clear "unprepared" bit */
6203	REG_WR(sc, MISC_REG_UNPREPARED, 0);
6204	mb();
6205
6206	/* Make sure all is written to the chip before the reset */
6207	wmb();
6208
6209	/*
6210	 * Wait for 1ms to empty GLUE and PCI-E core queues,
6211	 * PSWHST, GRC and PSWRD Tetris buffer.
6212	 */
6213	DELAY(1000);
6214
6215	/* Prepare to chip reset: */
6216	/* MCP */
6217	if (global) {
6218		bnx2x_reset_mcp_prep(sc, &val);
6219	}
6220
6221	/* PXP */
6222	bnx2x_pxp_prep(sc);
6223	mb();
6224
6225	/* reset the chip */
6226	bnx2x_process_kill_chip_reset(sc, global);
6227	mb();
6228
6229	/* Recover after reset: */
6230	/* MCP */
6231	if (global && bnx2x_reset_mcp_comp(sc, val)) {
6232		return -1;
6233	}
6234
6235	/* Open the gates #2, #3 and #4 */
6236	bnx2x_set_234_gates(sc, FALSE);
6237
6238	return 0;
6239}
6240
6241static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6242{
6243	int rc = 0;
6244	uint8_t global = bnx2x_reset_is_global(sc);
6245	uint32_t load_code;
6246
6247	/*
6248	 * If not going to reset MCP, load "fake" driver to reset HW while
6249	 * driver is owner of the HW.
6250	 */
6251	if (!global && !BNX2X_NOMCP(sc)) {
6252		load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6253					   DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6254		if (!load_code) {
6255			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6256			rc = -1;
6257			goto exit_leader_reset;
6258		}
6259
6260		if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6261		    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6262			PMD_DRV_LOG(NOTICE,
6263				    "MCP unexpected response, aborting");
6264			rc = -1;
6265			goto exit_leader_reset2;
6266		}
6267
6268		load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6269		if (!load_code) {
6270			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6271			rc = -1;
6272			goto exit_leader_reset2;
6273		}
6274	}
6275
6276	/* try to recover after the failure */
6277	if (bnx2x_process_kill(sc, global)) {
6278		PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6279			    SC_PATH(sc));
6280		rc = -1;
6281		goto exit_leader_reset2;
6282	}
6283
6284	/*
6285	 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6286	 * state.
6287	 */
6288	bnx2x_set_reset_done(sc);
6289	if (global) {
6290		bnx2x_clear_reset_global(sc);
6291	}
6292
6293exit_leader_reset2:
6294
6295	/* unload "fake driver" if it was loaded */
6296	if (!global &&!BNX2X_NOMCP(sc)) {
6297		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6298		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6299	}
6300
6301exit_leader_reset:
6302
6303	sc->is_leader = 0;
6304	bnx2x_release_leader_lock(sc);
6305
6306	mb();
6307	return rc;
6308}
6309
6310/*
6311 * prepare INIT transition, parameters configured:
6312 *   - HC configuration
6313 *   - Queue's CDU context
6314 */
6315static void
6316bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6317		   struct ecore_queue_init_params *init_params)
6318{
6319	uint8_t cos;
6320	int cxt_index, cxt_offset;
6321
6322	bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6323	bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6324
6325	bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6326	bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6327
6328	/* HC rate */
6329	init_params->rx.hc_rate =
6330	    sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6331	init_params->tx.hc_rate =
6332	    sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6333
6334	/* FW SB ID */
6335	init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6336
6337	/* CQ index among the SB indices */
6338	init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6339	init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6340
6341	/* set maximum number of COSs supported by this queue */
6342	init_params->max_cos = sc->max_cos;
6343
6344	/* set the context pointers queue object */
6345	for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6346		cxt_index = fp->index / ILT_PAGE_CIDS;
6347		cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6348		init_params->cxts[cos] =
6349		    &sc->context[cxt_index].vcxt[cxt_offset].eth;
6350	}
6351}
6352
6353/* set flags that are common for the Tx-only and not normal connections */
6354static unsigned long
6355bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6356{
6357	unsigned long flags = 0;
6358
6359	/* PF driver will always initialize the Queue to an ACTIVE state */
6360	bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6361
6362	/*
6363	 * tx only connections collect statistics (on the same index as the
6364	 * parent connection). The statistics are zeroed when the parent
6365	 * connection is initialized.
6366	 */
6367
6368	bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6369	if (zero_stats) {
6370		bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6371	}
6372
6373	/*
6374	 * tx only connections can support tx-switching, though their
6375	 * CoS-ness doesn't survive the loopback
6376	 */
6377	if (sc->flags & BNX2X_TX_SWITCHING) {
6378		bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6379	}
6380
6381	bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6382
6383	return flags;
6384}
6385
6386static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6387{
6388	unsigned long flags = 0;
6389
6390	if (IS_MF_SD(sc)) {
6391		bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6392	}
6393
6394	if (leading) {
6395		bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6396		bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6397	}
6398
6399	bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6400
6401	/* merge with common flags */
6402	return flags | bnx2x_get_common_flags(sc, TRUE);
6403}
6404
6405static void
6406bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6407		      struct ecore_general_setup_params *gen_init, uint8_t cos)
6408{
6409	gen_init->stat_id = bnx2x_stats_id(fp);
6410	gen_init->spcl_id = fp->cl_id;
6411	gen_init->mtu = sc->mtu;
6412	gen_init->cos = cos;
6413}
6414
6415static void
6416bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6417		 struct rxq_pause_params *pause,
6418		 struct