bnx2x.c revision dceb010b
1/*-
2 * Copyright (c) 2007-2013 Broadcom Corporation.
3 *
4 * Eric Davis        <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano     <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
11 * www.qlogic.com
12 *
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
14 */
15
16#define BNX2X_DRIVER_VERSION "1.78.18"
17
18#include "bnx2x.h"
19#include "bnx2x_vfpf.h"
20#include "ecore_sp.h"
21#include "ecore_init.h"
22#include "ecore_init_ops.h"
23
24#include "rte_version.h"
25
26#include <sys/types.h>
27#include <sys/stat.h>
28#include <fcntl.h>
29#include <zlib.h>
30
31#define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32#define BNX2X_PMD_VERSION_MAJOR 1
33#define BNX2X_PMD_VERSION_MINOR 0
34#define BNX2X_PMD_VERSION_REVISION 1
35#define BNX2X_PMD_VERSION_PATCH 1
36
37static inline const char *
38bnx2x_pmd_version(void)
39{
40	static char version[32];
41
42	snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
43			BNX2X_PMD_VER_PREFIX,
44			BNX2X_DRIVER_VERSION,
45			BNX2X_PMD_VERSION_MAJOR,
46			BNX2X_PMD_VERSION_MINOR,
47			BNX2X_PMD_VERSION_REVISION,
48			BNX2X_PMD_VERSION_PATCH);
49
50	return version;
51}
52
53static z_stream zlib_stream;
54
55#define EVL_VLID_MASK 0x0FFF
56
57#define BNX2X_DEF_SB_ATT_IDX 0x0001
58#define BNX2X_DEF_SB_IDX     0x0002
59
60/*
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
63 */
64#define FLR_WAIT_USEC     10000	/* 10 msecs */
65#define FLR_WAIT_INTERVAL 50	/* usecs */
66#define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)	/* 200 */
67
68struct pbf_pN_buf_regs {
69	int pN;
70	uint32_t init_crd;
71	uint32_t crd;
72	uint32_t crd_freed;
73};
74
75struct pbf_pN_cmd_regs {
76	int pN;
77	uint32_t lines_occup;
78	uint32_t lines_freed;
79};
80
81/* resources needed for unloading a previously loaded device */
82
83#define BNX2X_PREV_WAIT_NEEDED 1
84rte_spinlock_t bnx2x_prev_mtx;
85struct bnx2x_prev_list_node {
86	LIST_ENTRY(bnx2x_prev_list_node) node;
87	uint8_t bus;
88	uint8_t slot;
89	uint8_t path;
90	uint8_t aer;
91	uint8_t undi;
92};
93
94static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95	= LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96
97static int load_count[2][3] = { { 0 } };
98	/* per-path: 0-common, 1-port0, 2-port1 */
99
100static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101				uint8_t cmng_type);
102static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104			      uint8_t port);
105static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110				     uint8_t print);
111static void bnx2x_int_disable(struct bnx2x_softc *sc);
112static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115				 struct bnx2x_fastpath *fp,
116				 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117static void bnx2x_link_report(struct bnx2x_softc *sc);
118void bnx2x_link_status_update(struct bnx2x_softc *sc);
119static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120static void bnx2x_free_mem(struct bnx2x_softc *sc);
121static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123static __attribute__ ((noinline))
124int bnx2x_nic_load(struct bnx2x_softc *sc);
125
126static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
128static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
129static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
130			 uint8_t storm, uint16_t index, uint8_t op,
131			 uint8_t update);
132
133int bnx2x_test_bit(int nr, volatile unsigned long *addr)
134{
135	int res;
136
137	mb();
138	res = ((*addr) & (1UL << nr)) != 0;
139	mb();
140	return res;
141}
142
143void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144{
145	__sync_fetch_and_or(addr, (1UL << nr));
146}
147
148void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149{
150	__sync_fetch_and_and(addr, ~(1UL << nr));
151}
152
153int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154{
155	unsigned long mask = (1UL << nr);
156	return __sync_fetch_and_and(addr, ~mask) & mask;
157}
158
159int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160{
161	return __sync_val_compare_and_swap(addr, old, new);
162}
163
164int
165bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
166	      const char *msg, uint32_t align)
167{
168	char mz_name[RTE_MEMZONE_NAMESIZE];
169	const struct rte_memzone *z;
170
171	dma->sc = sc;
172	if (IS_PF(sc))
173		sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
174			rte_get_timer_cycles());
175	else
176		sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
177			rte_get_timer_cycles());
178
179	/* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
180	z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
181					rte_lcore_to_socket_id(rte_lcore_id()),
182					0, align);
183	if (z == NULL) {
184		PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
185		return -ENOMEM;
186	}
187	dma->paddr = (uint64_t) z->phys_addr;
188	dma->vaddr = z->addr;
189
190	PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
191
192	return 0;
193}
194
195static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196{
197	uint32_t lock_status;
198	uint32_t resource_bit = (1 << resource);
199	int func = SC_FUNC(sc);
200	uint32_t hw_lock_control_reg;
201	int cnt;
202
203	PMD_INIT_FUNC_TRACE();
204
205	/* validate the resource is within range */
206	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
207		PMD_DRV_LOG(NOTICE,
208			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
209			    resource);
210		return -1;
211	}
212
213	if (func <= 5) {
214		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
215	} else {
216		hw_lock_control_reg =
217		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
218	}
219
220	/* validate the resource is not already taken */
221	lock_status = REG_RD(sc, hw_lock_control_reg);
222	if (lock_status & resource_bit) {
223		PMD_DRV_LOG(NOTICE,
224			    "resource in use (status 0x%x bit 0x%x)",
225			    lock_status, resource_bit);
226		return -1;
227	}
228
229	/* try every 5ms for 5 seconds */
230	for (cnt = 0; cnt < 1000; cnt++) {
231		REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
232		lock_status = REG_RD(sc, hw_lock_control_reg);
233		if (lock_status & resource_bit) {
234			return 0;
235		}
236		DELAY(5000);
237	}
238
239	PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
240	return -1;
241}
242
243static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
244{
245	uint32_t lock_status;
246	uint32_t resource_bit = (1 << resource);
247	int func = SC_FUNC(sc);
248	uint32_t hw_lock_control_reg;
249
250	PMD_INIT_FUNC_TRACE();
251
252	/* validate the resource is within range */
253	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254		PMD_DRV_LOG(NOTICE,
255			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
256			    resource);
257		return -1;
258	}
259
260	if (func <= 5) {
261		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
262	} else {
263		hw_lock_control_reg =
264		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
265	}
266
267	/* validate the resource is currently taken */
268	lock_status = REG_RD(sc, hw_lock_control_reg);
269	if (!(lock_status & resource_bit)) {
270		PMD_DRV_LOG(NOTICE,
271			    "resource not in use (status 0x%x bit 0x%x)",
272			    lock_status, resource_bit);
273		return -1;
274	}
275
276	REG_WR(sc, hw_lock_control_reg, resource_bit);
277	return 0;
278}
279
280/* copy command into DMAE command memory and set DMAE command Go */
281void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
282{
283	uint32_t cmd_offset;
284	uint32_t i;
285
286	cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
287	for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
288		REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
289	}
290
291	REG_WR(sc, dmae_reg_go_c[idx], 1);
292}
293
294uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
295{
296	return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
297			  DMAE_COMMAND_C_TYPE_ENABLE);
298}
299
300uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
301{
302	return opcode & ~DMAE_COMMAND_SRC_RESET;
303}
304
305uint32_t
306bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
307		uint8_t with_comp, uint8_t comp_type)
308{
309	uint32_t opcode = 0;
310
311	opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
312		   (dst_type << DMAE_COMMAND_DST_SHIFT));
313
314	opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
315
316	opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
317
318	opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
319		   (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
320
321	opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
322
323#ifdef __BIG_ENDIAN
324	opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
325#else
326	opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
327#endif
328
329	if (with_comp) {
330		opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
331	}
332
333	return opcode;
334}
335
336static void
337bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
338			uint8_t src_type, uint8_t dst_type)
339{
340	memset(dmae, 0, sizeof(struct dmae_command));
341
342	/* set the opcode */
343	dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
344				       TRUE, DMAE_COMP_PCI);
345
346	/* fill in the completion parameters */
347	dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
348	dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
349	dmae->comp_val = DMAE_COMP_VAL;
350}
351
352/* issue a DMAE command over the init channel and wait for completion */
353static int
354bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
355{
356	uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
357	int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
358
359	/* reset completion */
360	*wb_comp = 0;
361
362	/* post the command on the channel used for initializations */
363	bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
364
365	/* wait for completion */
366	DELAY(500);
367
368	while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
369		if (!timeout ||
370		    (sc->recovery_state != BNX2X_RECOVERY_DONE &&
371		     sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
372			PMD_DRV_LOG(INFO, "DMAE timeout!");
373			return DMAE_TIMEOUT;
374		}
375
376		timeout--;
377		DELAY(50);
378	}
379
380	if (*wb_comp & DMAE_PCI_ERR_FLAG) {
381		PMD_DRV_LOG(INFO, "DMAE PCI error!");
382		return DMAE_PCI_ERROR;
383	}
384
385	return 0;
386}
387
388void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
389{
390	struct dmae_command dmae;
391	uint32_t *data;
392	uint32_t i;
393	int rc;
394
395	if (!sc->dmae_ready) {
396		data = BNX2X_SP(sc, wb_data[0]);
397
398		for (i = 0; i < len32; i++) {
399			data[i] = REG_RD(sc, (src_addr + (i * 4)));
400		}
401
402		return;
403	}
404
405	/* set opcode and fixed command fields */
406	bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
407
408	/* fill in addresses and len */
409	dmae.src_addr_lo = (src_addr >> 2);	/* GRC addr has dword resolution */
410	dmae.src_addr_hi = 0;
411	dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
412	dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
413	dmae.len = len32;
414
415	/* issue the command and wait for completion */
416	if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
417		rte_panic("DMAE failed (%d)", rc);
418	};
419}
420
421void
422bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
423	       uint32_t len32)
424{
425	struct dmae_command dmae;
426	int rc;
427
428	if (!sc->dmae_ready) {
429		ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
430		return;
431	}
432
433	/* set opcode and fixed command fields */
434	bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
435
436	/* fill in addresses and len */
437	dmae.src_addr_lo = U64_LO(dma_addr);
438	dmae.src_addr_hi = U64_HI(dma_addr);
439	dmae.dst_addr_lo = (dst_addr >> 2);	/* GRC addr has dword resolution */
440	dmae.dst_addr_hi = 0;
441	dmae.len = len32;
442
443	/* issue the command and wait for completion */
444	if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
445		rte_panic("DMAE failed (%d)", rc);
446	}
447}
448
449static void
450bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
451			uint32_t addr, uint32_t len)
452{
453	uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
454	uint32_t offset = 0;
455
456	while (len > dmae_wr_max) {
457		bnx2x_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
458			       (addr + offset),	/* dst GRC address */
459			       dmae_wr_max);
460		offset += (dmae_wr_max * 4);
461		len -= dmae_wr_max;
462	}
463
464	bnx2x_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
465		       (addr + offset),	/* dst GRC address */
466		       len);
467}
468
469void
470bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
471		       uint32_t cid)
472{
473	/* ustorm cxt validation */
474	cxt->ustorm_ag_context.cdu_usage =
475	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
476				   CDU_REGION_NUMBER_UCM_AG,
477				   ETH_CONNECTION_TYPE);
478	/* xcontext validation */
479	cxt->xstorm_ag_context.cdu_reserved =
480	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
481				   CDU_REGION_NUMBER_XCM_AG,
482				   ETH_CONNECTION_TYPE);
483}
484
485static void
486bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
487			    uint8_t sb_index, uint8_t ticks)
488{
489	uint32_t addr =
490	    (BAR_CSTRORM_INTMEM +
491	     CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
492
493	REG_WR8(sc, addr, ticks);
494}
495
496static void
497bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
498			    uint8_t sb_index, uint8_t disable)
499{
500	uint32_t enable_flag =
501	    (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
502	uint32_t addr =
503	    (BAR_CSTRORM_INTMEM +
504	     CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
505	uint8_t flags;
506
507	/* clear and set */
508	flags = REG_RD8(sc, addr);
509	flags &= ~HC_INDEX_DATA_HC_ENABLED;
510	flags |= enable_flag;
511	REG_WR8(sc, addr, flags);
512}
513
514void
515bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
516			     uint8_t sb_index, uint8_t disable, uint16_t usec)
517{
518	uint8_t ticks = (usec / 4);
519
520	bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
521
522	disable = (disable) ? 1 : ((usec) ? 0 : 1);
523	bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
524}
525
526uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
527{
528	return REG_RD(sc, reg_addr);
529}
530
531void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
532{
533	REG_WR(sc, reg_addr, val);
534}
535
536void
537elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
538		   __rte_unused const elink_log_id_t elink_log_id, ...)
539{
540	PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
541}
542
543static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
544{
545	uint32_t spio_reg;
546
547	/* Only 2 SPIOs are configurable */
548	if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
549		PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
550		return -1;
551	}
552
553	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
554
555	/* read SPIO and mask except the float bits */
556	spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
557
558	switch (mode) {
559	case MISC_SPIO_OUTPUT_LOW:
560		/* clear FLOAT and set CLR */
561		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
562		spio_reg |= (spio << MISC_SPIO_CLR_POS);
563		break;
564
565	case MISC_SPIO_OUTPUT_HIGH:
566		/* clear FLOAT and set SET */
567		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
568		spio_reg |= (spio << MISC_SPIO_SET_POS);
569		break;
570
571	case MISC_SPIO_INPUT_HI_Z:
572		/* set FLOAT */
573		spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
574		break;
575
576	default:
577		break;
578	}
579
580	REG_WR(sc, MISC_REG_SPIO, spio_reg);
581	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
582
583	return 0;
584}
585
586static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
587{
588	/* The GPIO should be swapped if swap register is set and active */
589	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
590			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
591	int gpio_shift = gpio_num;
592	if (gpio_port)
593		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
594
595	uint32_t gpio_mask = (1 << gpio_shift);
596	uint32_t gpio_reg;
597
598	if (gpio_num > MISC_REGISTERS_GPIO_3) {
599		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
600		return -1;
601	}
602
603	/* read GPIO value */
604	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
605
606	/* get the requested pin value */
607	return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
608}
609
610static int
611bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
612{
613	/* The GPIO should be swapped if swap register is set and active */
614	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
615			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
616	int gpio_shift = gpio_num;
617	if (gpio_port)
618		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
619
620	uint32_t gpio_mask = (1 << gpio_shift);
621	uint32_t gpio_reg;
622
623	if (gpio_num > MISC_REGISTERS_GPIO_3) {
624		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
625		return -1;
626	}
627
628	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
629
630	/* read GPIO and mask except the float bits */
631	gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
632
633	switch (mode) {
634	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
635		/* clear FLOAT and set CLR */
636		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
637		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
638		break;
639
640	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
641		/* clear FLOAT and set SET */
642		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
643		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
644		break;
645
646	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
647		/* set FLOAT */
648		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
649		break;
650
651	default:
652		break;
653	}
654
655	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
656	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
657
658	return 0;
659}
660
661static int
662bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
663{
664	uint32_t gpio_reg;
665
666	/* any port swapping should be handled by caller */
667
668	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
669
670	/* read GPIO and mask except the float bits */
671	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
672	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
673	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
674	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
675
676	switch (mode) {
677	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
678		/* set CLR */
679		gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
680		break;
681
682	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
683		/* set SET */
684		gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
685		break;
686
687	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
688		/* set FLOAT */
689		gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
690		break;
691
692	default:
693		PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
694		bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
695		return -1;
696	}
697
698	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
699	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
700
701	return 0;
702}
703
704static int
705bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
706		   uint8_t port)
707{
708	/* The GPIO should be swapped if swap register is set and active */
709	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
710			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
711	int gpio_shift = gpio_num;
712	if (gpio_port)
713		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714
715	uint32_t gpio_mask = (1 << gpio_shift);
716	uint32_t gpio_reg;
717
718	if (gpio_num > MISC_REGISTERS_GPIO_3) {
719		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
720		return -1;
721	}
722
723	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
724
725	/* read GPIO int */
726	gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
727
728	switch (mode) {
729	case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
730		/* clear SET and set CLR */
731		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
732		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
733		break;
734
735	case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
736		/* clear CLR and set SET */
737		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
738		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
739		break;
740
741	default:
742		break;
743	}
744
745	REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
746	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
747
748	return 0;
749}
750
751uint32_t
752elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753{
754	return bnx2x_gpio_read(sc, gpio_num, port);
755}
756
757uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
758			    uint8_t port)
759{
760	return bnx2x_gpio_write(sc, gpio_num, mode, port);
761}
762
763uint8_t
764elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
765			 uint8_t mode /* 0=low 1=high */ )
766{
767	return bnx2x_gpio_mult_write(sc, pins, mode);
768}
769
770uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
771				uint8_t port)
772{
773	return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
774}
775
776void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777{
778	REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
779		    (SC_FUNC(sc) * sizeof(uint32_t))), 1);
780}
781
782/* send the MCP a request, block until there is a reply */
783uint32_t
784elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785{
786	int mb_idx = SC_FW_MB_IDX(sc);
787	uint32_t seq;
788	uint32_t rc = 0;
789	uint32_t cnt = 1;
790	uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
791
792	seq = ++sc->fw_seq;
793	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
794	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
795
796	PMD_DRV_LOG(DEBUG,
797		    "wrote command 0x%08x to FW MB param 0x%08x",
798		    (command | seq), param);
799
800	/* Let the FW do it's magic. GIve it up to 5 seconds... */
801	do {
802		DELAY(delay * 1000);
803		rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
804	} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805
806	/* is this a reply to our command? */
807	if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
808		rc &= FW_MSG_CODE_MASK;
809	} else {
810		/* Ruh-roh! */
811		PMD_DRV_LOG(NOTICE, "FW failed to respond!");
812		rc = 0;
813	}
814
815	return rc;
816}
817
818static uint32_t
819bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820{
821	return elink_cb_fw_command(sc, command, param);
822}
823
824static void
825__storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
826			   phys_addr_t mapping)
827{
828	REG_WR(sc, addr, U64_LO(mapping));
829	REG_WR(sc, (addr + 4), U64_HI(mapping));
830}
831
832static void
833storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
834		      uint16_t abs_fid)
835{
836	uint32_t addr = (XSEM_REG_FAST_MEMORY +
837			 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
838	__storm_memset_dma_mapping(sc, addr, mapping);
839}
840
841static void
842storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843{
844	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845		pf_id);
846	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847		pf_id);
848	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849		pf_id);
850	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
851		pf_id);
852}
853
854static void
855storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856{
857	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858		enable);
859	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860		enable);
861	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862		enable);
863	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
864		enable);
865}
866
867static void
868storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
869		     uint16_t pfid)
870{
871	uint32_t addr;
872	size_t size;
873
874	addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
875	size = sizeof(struct event_ring_data);
876	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
877}
878
879static void
880storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881{
882	uint32_t addr = (BAR_CSTRORM_INTMEM +
883			 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
884	REG_WR16(sc, addr, eq_prod);
885}
886
887/*
888 * Post a slowpath command.
889 *
890 * A slowpath command is used to propogate a configuration change through
891 * the controller in a controlled manner, allowing each STORM processor and
892 * other H/W blocks to phase in the change.  The commands sent on the
893 * slowpath are referred to as ramrods.  Depending on the ramrod used the
894 * completion of the ramrod will occur in different ways.  Here's a
895 * breakdown of ramrods and how they complete:
896 *
897 * RAMROD_CMD_ID_ETH_PORT_SETUP
898 *   Used to setup the leading connection on a port.  Completes on the
899 *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 *
901 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
902 *   Used to setup an additional connection on a port.  Completes on the
903 *   RCQ of the multi-queue/RSS connection being initialized.
904 *
905 * RAMROD_CMD_ID_ETH_STAT_QUERY
906 *   Used to force the storm processors to update the statistics database
907 *   in host memory.  This ramrod is send on the leading connection CID and
908 *   completes as an index increment of the CSTORM on the default status
909 *   block.
910 *
911 * RAMROD_CMD_ID_ETH_UPDATE
912 *   Used to update the state of the leading connection, usually to udpate
913 *   the RSS indirection table.  Completes on the RCQ of the leading
914 *   connection. (Not currently used under FreeBSD until OS support becomes
915 *   available.)
916 *
917 * RAMROD_CMD_ID_ETH_HALT
918 *   Used when tearing down a connection prior to driver unload.  Completes
919 *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
920 *   use this on the leading connection.
921 *
922 * RAMROD_CMD_ID_ETH_SET_MAC
923 *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
924 *   the RCQ of the leading connection.
925 *
926 * RAMROD_CMD_ID_ETH_CFC_DEL
927 *   Used when tearing down a conneciton prior to driver unload.  Completes
928 *   on the RCQ of the leading connection (since the current connection
929 *   has been completely removed from controller memory).
930 *
931 * RAMROD_CMD_ID_ETH_PORT_DEL
932 *   Used to tear down the leading connection prior to driver unload,
933 *   typically fp[0].  Completes as an index increment of the CSTORM on the
934 *   default status block.
935 *
936 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
937 *   Used for connection offload.  Completes on the RCQ of the multi-queue
938 *   RSS connection that is being offloaded.  (Not currently used under
939 *   FreeBSD.)
940 *
941 * There can only be one command pending per function.
942 *
943 * Returns:
944 *   0 = Success, !0 = Failure.
945 */
946
947/* must be called under the spq lock */
948static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949{
950	struct eth_spe *next_spe = sc->spq_prod_bd;
951
952	if (sc->spq_prod_bd == sc->spq_last_bd) {
953		/* wrap back to the first eth_spq */
954		sc->spq_prod_bd = sc->spq;
955		sc->spq_prod_idx = 0;
956	} else {
957		sc->spq_prod_bd++;
958		sc->spq_prod_idx++;
959	}
960
961	return next_spe;
962}
963
964/* must be called under the spq lock */
965static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966{
967	int func = SC_FUNC(sc);
968
969	/*
970	 * Make sure that BD data is updated before writing the producer.
971	 * BD data is written to the memory, the producer is read from the
972	 * memory, thus we need a full memory barrier to ensure the ordering.
973	 */
974	mb();
975
976	REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
977		 sc->spq_prod_idx);
978
979	mb();
980}
981
982/**
983 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 *
985 * @cmd:      command to check
986 * @cmd_type: command type
987 */
988static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989{
990	if ((cmd_type == NONE_CONNECTION_TYPE) ||
991	    (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
992	    (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
993	    (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
994	    (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
995	    (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
996	    (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
997		return TRUE;
998	} else {
999		return FALSE;
1000	}
1001}
1002
1003/**
1004 * bnx2x_sp_post - place a single command on an SP ring
1005 *
1006 * @sc:         driver handle
1007 * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008 * @cid:        SW CID the command is related to
1009 * @data_hi:    command private data address (high 32 bits)
1010 * @data_lo:    command private data address (low 32 bits)
1011 * @cmd_type:   command type (e.g. NONE, ETH)
1012 *
1013 * SP data is handled as if it's always an address pair, thus data fields are
1014 * not swapped to little endian in upper functions. Instead this function swaps
1015 * data as if it's two uint32 fields.
1016 */
1017int
1018bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019	    uint32_t data_lo, int cmd_type)
1020{
1021	struct eth_spe *spe;
1022	uint16_t type;
1023	int common;
1024
1025	common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027	if (common) {
1028		if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029			PMD_DRV_LOG(INFO, "EQ ring is full!");
1030			return -1;
1031		}
1032	} else {
1033		if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034			PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035			return -1;
1036		}
1037	}
1038
1039	spe = bnx2x_sp_get_next(sc);
1040
1041	/* CID needs port number to be encoded int it */
1042	spe->hdr.conn_and_cmd_data =
1043	    htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045	type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047	/* TBD: Check if it works for VFs */
1048	type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049		 SPE_HDR_FUNCTION_ID);
1050
1051	spe->hdr.type = htole16(type);
1052
1053	spe->data.update_data_addr.hi = htole32(data_hi);
1054	spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056	/*
1057	 * It's ok if the actual decrement is issued towards the memory
1058	 * somewhere between the lock and unlock. Thus no more explict
1059	 * memory barrier is needed.
1060	 */
1061	if (common) {
1062		atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063	} else {
1064		atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065	}
1066
1067	PMD_DRV_LOG(DEBUG,
1068		    "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069		    "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070		    sc->spq_prod_idx,
1071		    (uint32_t) U64_HI(sc->spq_dma.paddr),
1072		    (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073				(uint8_t *) sc->spq_prod_bd -
1074				(uint8_t *) sc->spq), command, common,
1075		    HW_CID(sc, cid), data_hi, data_lo, type,
1076		    atomic_load_acq_long(&sc->cq_spq_left),
1077		    atomic_load_acq_long(&sc->eq_spq_left));
1078
1079	bnx2x_sp_prod_update(sc);
1080
1081	return 0;
1082}
1083
1084static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085{
1086	SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087		 sc->fw_drv_pulse_wr_seq);
1088}
1089
1090static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091{
1092	uint16_t hw_cons;
1093	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095	if (unlikely(!txq)) {
1096		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097		return 0;
1098	}
1099
1100	mb();			/* status block fields can change */
1101	hw_cons = le16toh(*fp->tx_cons_sb);
1102	return hw_cons != txq->tx_pkt_head;
1103}
1104
1105static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106{
1107	/* expand this for multi-cos if ever supported */
1108	return bnx2x_tx_queue_has_work(fp);
1109}
1110
1111static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112{
1113	uint16_t rx_cq_cons_sb;
1114	struct bnx2x_rx_queue *rxq;
1115	rxq = fp->sc->rx_queues[fp->index];
1116	if (unlikely(!rxq)) {
1117		PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118		return 0;
1119	}
1120
1121	mb();			/* status block fields can change */
1122	rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123	if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124		     MAX_RCQ_ENTRIES(rxq)))
1125		rx_cq_cons_sb++;
1126	return rxq->rx_cq_head != rx_cq_cons_sb;
1127}
1128
1129static void
1130bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131	     union eth_rx_cqe *rr_cqe)
1132{
1133#ifdef RTE_LIBRTE_BNX2X_DEBUG
1134	int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135#endif
1136	int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1137	enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1138	struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1139
1140	PMD_DRV_LOG(DEBUG,
1141		    "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1142		    fp->index, cid, command, sc->state,
1143		    rr_cqe->ramrod_cqe.ramrod_type);
1144
1145	switch (command) {
1146	case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1147		PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1148		drv_cmd = ECORE_Q_CMD_UPDATE;
1149		break;
1150
1151	case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1152		PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1153		drv_cmd = ECORE_Q_CMD_SETUP;
1154		break;
1155
1156	case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1157		PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1158		drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1159		break;
1160
1161	case (RAMROD_CMD_ID_ETH_HALT):
1162		PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1163		drv_cmd = ECORE_Q_CMD_HALT;
1164		break;
1165
1166	case (RAMROD_CMD_ID_ETH_TERMINATE):
1167		PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1168		drv_cmd = ECORE_Q_CMD_TERMINATE;
1169		break;
1170
1171	case (RAMROD_CMD_ID_ETH_EMPTY):
1172		PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1173		drv_cmd = ECORE_Q_CMD_EMPTY;
1174		break;
1175
1176	default:
1177		PMD_DRV_LOG(DEBUG,
1178			    "ERROR: unexpected MC reply (%d)"
1179			    "on fp[%d]", command, fp->index);
1180		return;
1181	}
1182
1183	if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1184	    q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185		/*
1186		 * q_obj->complete_cmd() failure means that this was
1187		 * an unexpected completion.
1188		 *
1189		 * In this case we don't want to increase the sc->spq_left
1190		 * because apparently we haven't sent this command the first
1191		 * place.
1192		 */
1193		// rte_panic("Unexpected SP completion");
1194		return;
1195	}
1196
1197	atomic_add_acq_long(&sc->cq_spq_left, 1);
1198
1199	PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1200		    atomic_load_acq_long(&sc->cq_spq_left));
1201}
1202
1203static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204{
1205	struct bnx2x_rx_queue *rxq;
1206	uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1207	uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208
1209	rxq = sc->rx_queues[fp->index];
1210	if (!rxq) {
1211		PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1212		return 0;
1213	}
1214
1215	/* CQ "next element" is of the size of the regular element */
1216	hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1217	if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1218		     USABLE_RCQ_ENTRIES_PER_PAGE)) {
1219		hw_cq_cons++;
1220	}
1221
1222	bd_cons = rxq->rx_bd_head;
1223	bd_prod = rxq->rx_bd_tail;
1224	bd_prod_fw = bd_prod;
1225	sw_cq_cons = rxq->rx_cq_head;
1226	sw_cq_prod = rxq->rx_cq_tail;
1227
1228	/*
1229	 * Memory barrier necessary as speculative reads of the rx
1230	 * buffer can be ahead of the index in the status block
1231	 */
1232	rmb();
1233
1234	while (sw_cq_cons != hw_cq_cons) {
1235		union eth_rx_cqe *cqe;
1236		struct eth_fast_path_rx_cqe *cqe_fp;
1237		uint8_t cqe_fp_flags;
1238		enum eth_rx_cqe_type cqe_fp_type;
1239
1240		comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1241		bd_prod = RX_BD(bd_prod, rxq);
1242		bd_cons = RX_BD(bd_cons, rxq);
1243
1244		cqe = &rxq->cq_ring[comp_ring_cons];
1245		cqe_fp = &cqe->fast_path_cqe;
1246		cqe_fp_flags = cqe_fp->type_error_flags;
1247		cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248
1249		/* is this a slowpath msg? */
1250		if (CQE_TYPE_SLOW(cqe_fp_type)) {
1251			bnx2x_sp_event(sc, fp, cqe);
1252			goto next_cqe;
1253		}
1254
1255		/* is this an error packet? */
1256		if (unlikely(cqe_fp_flags &
1257			     ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1258			PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1259				   cqe_fp_flags, sw_cq_cons);
1260			goto next_rx;
1261		}
1262
1263		PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1264
1265next_rx:
1266		bd_cons = NEXT_RX_BD(bd_cons);
1267		bd_prod = NEXT_RX_BD(bd_prod);
1268		bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1269
1270next_cqe:
1271		sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1272		sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273
1274	}			/* while work to do */
1275
1276	rxq->rx_bd_head = bd_cons;
1277	rxq->rx_bd_tail = bd_prod_fw;
1278	rxq->rx_cq_head = sw_cq_cons;
1279	rxq->rx_cq_tail = sw_cq_prod;
1280
1281	/* Update producers */
1282	bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283
1284	return sw_cq_cons != hw_cq_cons;
1285}
1286
1287static uint16_t
1288bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1289		uint16_t pkt_idx, uint16_t bd_idx)
1290{
1291	struct eth_tx_start_bd *tx_start_bd =
1292	    &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1293	uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1294	struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295
1296	if (likely(tx_mbuf != NULL)) {
1297		rte_pktmbuf_free_seg(tx_mbuf);
1298	} else {
1299		PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1300			   fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1301	}
1302
1303	txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1304	txq->nb_tx_avail += nbd;
1305
1306	while (nbd--)
1307		bd_idx = NEXT_TX_BD(bd_idx);
1308
1309	return bd_idx;
1310}
1311
1312/* processes transmit completions */
1313uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314{
1315	uint16_t bd_cons, hw_cons, sw_cons;
1316	__rte_unused uint16_t tx_bd_avail;
1317
1318	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319
1320	if (unlikely(!txq)) {
1321		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1322		return 0;
1323	}
1324
1325	bd_cons = txq->tx_bd_head;
1326	hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1327	sw_cons = txq->tx_pkt_head;
1328
1329	while (sw_cons != hw_cons) {
1330		bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1331		sw_cons++;
1332	}
1333
1334	txq->tx_pkt_head = sw_cons;
1335	txq->tx_bd_head = bd_cons;
1336
1337	tx_bd_avail = txq->nb_tx_avail;
1338
1339	PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1340		   "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1341		   fp->index, tx_bd_avail, hw_cons,
1342		   txq->tx_pkt_head, txq->tx_pkt_tail,
1343		   txq->tx_bd_head, txq->tx_bd_tail);
1344	return TRUE;
1345}
1346
1347static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348{
1349	struct bnx2x_fastpath *fp;
1350	int i, count;
1351
1352	/* wait until all TX fastpath tasks have completed */
1353	for (i = 0; i < sc->num_queues; i++) {
1354		fp = &sc->fp[i];
1355
1356		count = 1000;
1357
1358		while (bnx2x_has_tx_work(fp)) {
1359			bnx2x_txeof(sc, fp);
1360
1361			if (count == 0) {
1362				PMD_TX_LOG(ERR,
1363					   "Timeout waiting for fp[%d] "
1364					   "transmits to complete!", i);
1365				rte_panic("tx drain failure");
1366				return;
1367			}
1368
1369			count--;
1370			DELAY(1000);
1371			rmb();
1372		}
1373	}
1374
1375	return;
1376}
1377
1378static int
1379bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1380		 int mac_type, uint8_t wait_for_comp)
1381{
1382	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1383	int rc;
1384
1385	/* wait for completion of requested */
1386	if (wait_for_comp) {
1387		bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1388	}
1389
1390	/* Set the mac type of addresses we want to clear */
1391	bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392
1393	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394	if (rc < 0)
1395		PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1396
1397	return rc;
1398}
1399
1400int
1401bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1402		      unsigned long *rx_accept_flags,
1403		      unsigned long *tx_accept_flags)
1404{
1405	/* Clear the flags first */
1406	*rx_accept_flags = 0;
1407	*tx_accept_flags = 0;
1408
1409	switch (rx_mode) {
1410	case BNX2X_RX_MODE_NONE:
1411		/*
1412		 * 'drop all' supersedes any accept flags that may have been
1413		 * passed to the function.
1414		 */
1415		break;
1416
1417	case BNX2X_RX_MODE_NORMAL:
1418		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1419		bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1420		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421
1422		/* internal switching mode */
1423		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1424		bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1425		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1426
1427		break;
1428
1429	case BNX2X_RX_MODE_ALLMULTI:
1430		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1431		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1432		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433
1434		/* internal switching mode */
1435		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1436		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1437		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1438
1439		break;
1440
1441	case BNX2X_RX_MODE_PROMISC:
1442		/*
1443		 * According to deffinition of SI mode, iface in promisc mode
1444		 * should receive matched and unmatched (in resolution of port)
1445		 * unicast packets.
1446		 */
1447		bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1448		bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1449		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1450		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451
1452		/* internal switching mode */
1453		bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1454		bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1455
1456		if (IS_MF_SI(sc)) {
1457			bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458		} else {
1459			bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1460		}
1461
1462		break;
1463
1464	default:
1465		PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1466		return -1;
1467	}
1468
1469	/* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1470	if (rx_mode != BNX2X_RX_MODE_NONE) {
1471		bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1472		bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1473	}
1474
1475	return 0;
1476}
1477
1478static int
1479bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1480		  unsigned long rx_mode_flags,
1481		  unsigned long rx_accept_flags,
1482		  unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483{
1484	struct ecore_rx_mode_ramrod_params ramrod_param;
1485	int rc;
1486
1487	memset(&ramrod_param, 0, sizeof(ramrod_param));
1488
1489	/* Prepare ramrod parameters */
1490	ramrod_param.cid = 0;
1491	ramrod_param.cl_id = cl_id;
1492	ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1493	ramrod_param.func_id = SC_FUNC(sc);
1494
1495	ramrod_param.pstate = &sc->sp_state;
1496	ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497
1498	ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1499	ramrod_param.rdata_mapping =
1500	    (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1501	    bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502
1503	ramrod_param.ramrod_flags = ramrod_flags;
1504	ramrod_param.rx_mode_flags = rx_mode_flags;
1505
1506	ramrod_param.rx_accept_flags = rx_accept_flags;
1507	ramrod_param.tx_accept_flags = tx_accept_flags;
1508
1509	rc = ecore_config_rx_mode(sc, &ramrod_param);
1510	if (rc < 0) {
1511		PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1512		return rc;
1513	}
1514
1515	return 0;
1516}
1517
1518int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519{
1520	unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1521	unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1522	int rc;
1523
1524	rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1525				   &tx_accept_flags);
1526	if (rc) {
1527		return rc;
1528	}
1529
1530	bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1531	bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1532	bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533
1534	return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1535				 rx_accept_flags, tx_accept_flags,
1536				 ramrod_flags);
1537}
1538
1539/* returns the "mcp load_code" according to global load_count array */
1540static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541{
1542	int path = SC_PATH(sc);
1543	int port = SC_PORT(sc);
1544
1545	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1546		    path, load_count[path][0], load_count[path][1],
1547		    load_count[path][2]);
1548
1549	load_count[path][0]++;
1550	load_count[path][1 + port]++;
1551	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1552		    path, load_count[path][0], load_count[path][1],
1553		    load_count[path][2]);
1554	if (load_count[path][0] == 1)
1555		return FW_MSG_CODE_DRV_LOAD_COMMON;
1556	else if (load_count[path][1 + port] == 1)
1557		return FW_MSG_CODE_DRV_LOAD_PORT;
1558	else
1559		return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1560}
1561
1562/* returns the "mcp load_code" according to global load_count array */
1563static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564{
1565	int port = SC_PORT(sc);
1566	int path = SC_PATH(sc);
1567
1568	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1569		    path, load_count[path][0], load_count[path][1],
1570		    load_count[path][2]);
1571	load_count[path][0]--;
1572	load_count[path][1 + port]--;
1573	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1574		    path, load_count[path][0], load_count[path][1],
1575		    load_count[path][2]);
1576	if (load_count[path][0] == 0) {
1577		return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1578	} else if (load_count[path][1 + port] == 0) {
1579		return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580	} else {
1581		return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1582	}
1583}
1584
1585/* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1586static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587{
1588	uint32_t reset_code = 0;
1589
1590	/* Select the UNLOAD request mode */
1591	if (unload_mode == UNLOAD_NORMAL) {
1592		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593	} else {
1594		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1595	}
1596
1597	/* Send the request to the MCP */
1598	if (!BNX2X_NOMCP(sc)) {
1599		reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600	} else {
1601		reset_code = bnx2x_nic_unload_no_mcp(sc);
1602	}
1603
1604	return reset_code;
1605}
1606
1607/* send UNLOAD_DONE command to the MCP */
1608static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609{
1610	uint32_t reset_param =
1611	    keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612
1613	/* Report UNLOAD_DONE to MCP */
1614	if (!BNX2X_NOMCP(sc)) {
1615		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1616	}
1617}
1618
1619static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1620{
1621	int tout = 50;
1622
1623	if (!sc->port.pmf) {
1624		return 0;
1625	}
1626
1627	/*
1628	 * (assumption: No Attention from MCP at this stage)
1629	 * PMF probably in the middle of TX disable/enable transaction
1630	 * 1. Sync IRS for default SB
1631	 * 2. Sync SP queue - this guarantees us that attention handling started
1632	 * 3. Wait, that TX disable/enable transaction completes
1633	 *
1634	 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1635	 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1636	 * received completion for the transaction the state is TX_STOPPED.
1637	 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1638	 * transaction.
1639	 */
1640
1641	while (ecore_func_get_state(sc, &sc->func_obj) !=
1642	       ECORE_F_STATE_STARTED && tout--) {
1643		DELAY(20000);
1644	}
1645
1646	if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647		/*
1648		 * Failed to complete the transaction in a "good way"
1649		 * Force both transactions with CLR bit.
1650		 */
1651		struct ecore_func_state_params func_params = { NULL };
1652
1653		PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1654			    "Forcing STARTED-->TX_STOPPED-->STARTED");
1655
1656		func_params.f_obj = &sc->func_obj;
1657		bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658
1659		/* STARTED-->TX_STOPPED */
1660		func_params.cmd = ECORE_F_CMD_TX_STOP;
1661		ecore_func_state_change(sc, &func_params);
1662
1663		/* TX_STOPPED-->STARTED */
1664		func_params.cmd = ECORE_F_CMD_TX_START;
1665		return ecore_func_state_change(sc, &func_params);
1666	}
1667
1668	return 0;
1669}
1670
1671static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672{
1673	struct bnx2x_fastpath *fp = &sc->fp[index];
1674	struct ecore_queue_state_params q_params = { NULL };
1675	int rc;
1676
1677	PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1678
1679	q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1680	/* We want to wait for completion in this context */
1681	bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682
1683	/* Stop the primary connection: */
1684
1685	/* ...halt the connection */
1686	q_params.cmd = ECORE_Q_CMD_HALT;
1687	rc = ecore_queue_state_change(sc, &q_params);
1688	if (rc) {
1689		return rc;
1690	}
1691
1692	/* ...terminate the connection */
1693	q_params.cmd = ECORE_Q_CMD_TERMINATE;
1694	memset(&q_params.params.terminate, 0,
1695	       sizeof(q_params.params.terminate));
1696	q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1697	rc = ecore_queue_state_change(sc, &q_params);
1698	if (rc) {
1699		return rc;
1700	}
1701
1702	/* ...delete cfc entry */
1703	q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1704	memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1705	q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1706	return ecore_queue_state_change(sc, &q_params);
1707}
1708
1709/* wait for the outstanding SP commands */
1710static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1711{
1712	unsigned long tmp;
1713	int tout = 5000;	/* wait for 5 secs tops */
1714
1715	while (tout--) {
1716		mb();
1717		if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1718			return TRUE;
1719		}
1720
1721		DELAY(1000);
1722	}
1723
1724	mb();
1725
1726	tmp = atomic_load_acq_long(&sc->sp_state);
1727	if (tmp & mask) {
1728		PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1729			    "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1730		return FALSE;
1731	}
1732
1733	return FALSE;
1734}
1735
1736static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737{
1738	struct ecore_func_state_params func_params = { NULL };
1739	int rc;
1740
1741	/* prepare parameters for function state transitions */
1742	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1743	func_params.f_obj = &sc->func_obj;
1744	func_params.cmd = ECORE_F_CMD_STOP;
1745
1746	/*
1747	 * Try to stop the function the 'good way'. If it fails (in case
1748	 * of a parity error during bnx2x_chip_cleanup()) and we are
1749	 * not in a debug mode, perform a state transaction in order to
1750	 * enable further HW_RESET transaction.
1751	 */
1752	rc = ecore_func_state_change(sc, &func_params);
1753	if (rc) {
1754		PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1755			    "Running a dry transaction");
1756		bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1757		return ecore_func_state_change(sc, &func_params);
1758	}
1759
1760	return 0;
1761}
1762
1763static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764{
1765	struct ecore_func_state_params func_params = { NULL };
1766
1767	/* Prepare parameters for function state transitions */
1768	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769
1770	func_params.f_obj = &sc->func_obj;
1771	func_params.cmd = ECORE_F_CMD_HW_RESET;
1772
1773	func_params.params.hw_init.load_phase = load_code;
1774
1775	return ecore_func_state_change(sc, &func_params);
1776}
1777
1778static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1779{
1780	if (disable_hw) {
1781		/* prevent the HW from sending interrupts */
1782		bnx2x_int_disable(sc);
1783	}
1784}
1785
1786static void
1787bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788{
1789	int port = SC_PORT(sc);
1790	struct ecore_mcast_ramrod_params rparam = { NULL };
1791	uint32_t reset_code;
1792	int i, rc = 0;
1793
1794	bnx2x_drain_tx_queues(sc);
1795
1796	/* give HW time to discard old tx messages */
1797	DELAY(1000);
1798
1799	/* Clean all ETH MACs */
1800	rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1801			      FALSE);
1802	if (rc < 0) {
1803		PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1804	}
1805
1806	/* Clean up UC list  */
1807	rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1808			      TRUE);
1809	if (rc < 0) {
1810		PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1811	}
1812
1813	/* Disable LLH */
1814	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1815
1816	/* Set "drop all" to stop Rx */
1817
1818	/*
1819	 * We need to take the if_maddr_lock() here in order to prevent
1820	 * a race between the completion code and this code.
1821	 */
1822
1823	if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1824		bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1825	} else {
1826		bnx2x_set_storm_rx_mode(sc);
1827	}
1828
1829	/* Clean up multicast configuration */
1830	rparam.mcast_obj = &sc->mcast_obj;
1831	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1832	if (rc < 0) {
1833		PMD_DRV_LOG(NOTICE,
1834			    "Failed to send DEL MCAST command (%d)", rc);
1835	}
1836
1837	/*
1838	 * Send the UNLOAD_REQUEST to the MCP. This will return if
1839	 * this function should perform FUNCTION, PORT, or COMMON HW
1840	 * reset.
1841	 */
1842	reset_code = bnx2x_send_unload_req(sc, unload_mode);
1843
1844	/*
1845	 * (assumption: No Attention from MCP at this stage)
1846	 * PMF probably in the middle of TX disable/enable transaction
1847	 */
1848	rc = bnx2x_func_wait_started(sc);
1849	if (rc) {
1850		PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1851	}
1852
1853	/*
1854	 * Close multi and leading connections
1855	 * Completions for ramrods are collected in a synchronous way
1856	 */
1857	for (i = 0; i < sc->num_queues; i++) {
1858		if (bnx2x_stop_queue(sc, i)) {
1859			goto unload_error;
1860		}
1861	}
1862
1863	/*
1864	 * If SP settings didn't get completed so far - something
1865	 * very wrong has happen.
1866	 */
1867	if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1868		PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1869	}
1870
1871unload_error:
1872
1873	rc = bnx2x_func_stop(sc);
1874	if (rc) {
1875		PMD_DRV_LOG(NOTICE, "Function stop failed!");
1876	}
1877
1878	/* disable HW interrupts */
1879	bnx2x_int_disable_sync(sc, TRUE);
1880
1881	/* Reset the chip */
1882	rc = bnx2x_reset_hw(sc, reset_code);
1883	if (rc) {
1884		PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1885	}
1886
1887	/* Report UNLOAD_DONE to MCP */
1888	bnx2x_send_unload_done(sc, keep_link);
1889}
1890
1891static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1892{
1893	uint32_t val;
1894
1895	PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1896
1897	val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1898	val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1899		 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1900	REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1901}
1902
1903/*
1904 * Cleans the object that have internal lists without sending
1905 * ramrods. Should be run when interrutps are disabled.
1906 */
1907static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1908{
1909	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1910	struct ecore_mcast_ramrod_params rparam = { NULL };
1911	struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1912	int rc;
1913
1914	/* Cleanup MACs' object first... */
1915
1916	/* Wait for completion of requested */
1917	bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1918	/* Perform a dry cleanup */
1919	bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1920
1921	/* Clean ETH primary MAC */
1922	bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1923	rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1924				 &ramrod_flags);
1925	if (rc != 0) {
1926		PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1927	}
1928
1929	/* Cleanup UC list */
1930	vlan_mac_flags = 0;
1931	bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1932	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1933	if (rc != 0) {
1934		PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1935	}
1936
1937	/* Now clean mcast object... */
1938
1939	rparam.mcast_obj = &sc->mcast_obj;
1940	bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1941
1942	/* Add a DEL command... */
1943	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1944	if (rc < 0) {
1945		PMD_DRV_LOG(NOTICE,
1946			    "Failed to send DEL MCAST command (%d)", rc);
1947	}
1948
1949	/* now wait until all pending commands are cleared */
1950
1951	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1952	while (rc != 0) {
1953		if (rc < 0) {
1954			PMD_DRV_LOG(NOTICE,
1955				    "Failed to clean MCAST object (%d)", rc);
1956			return;
1957		}
1958
1959		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1960	}
1961}
1962
1963/* stop the controller */
1964__attribute__ ((noinline))
1965int
1966bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1967{
1968	uint8_t global = FALSE;
1969	uint32_t val;
1970
1971	PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1972
1973	/* stop the periodic callout */
1974	bnx2x_periodic_stop(sc);
1975
1976	/* mark driver as unloaded in shmem2 */
1977	if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1978		val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1979		SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1980			  val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1981	}
1982
1983	if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1984	    (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1985		/*
1986		 * We can get here if the driver has been unloaded
1987		 * during parity error recovery and is either waiting for a
1988		 * leader to complete or for other functions to unload and
1989		 * then ifconfig down has been issued. In this case we want to
1990		 * unload and let other functions to complete a recovery
1991		 * process.
1992		 */
1993		sc->recovery_state = BNX2X_RECOVERY_DONE;
1994		sc->is_leader = 0;
1995		bnx2x_release_leader_lock(sc);
1996		mb();
1997
1998		PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1999		return -1;
2000	}
2001
2002	/*
2003	 * Nothing to do during unload if previous bnx2x_nic_load()
2004	 * did not completed succesfully - all resourses are released.
2005	 */
2006	if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2007		return 0;
2008	}
2009
2010	sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2011	mb();
2012
2013	sc->rx_mode = BNX2X_RX_MODE_NONE;
2014	bnx2x_set_rx_mode(sc);
2015	mb();
2016
2017	if (IS_PF(sc)) {
2018		/* set ALWAYS_ALIVE bit in shmem */
2019		sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2020
2021		bnx2x_drv_pulse(sc);
2022
2023		bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2024		bnx2x_save_statistics(sc);
2025	}
2026
2027	/* wait till consumers catch up with producers in all queues */
2028	bnx2x_drain_tx_queues(sc);
2029
2030	/* if VF indicate to PF this function is going down (PF will delete sp
2031	 * elements and clear initializations
2032	 */
2033	if (IS_VF(sc)) {
2034		bnx2x_vf_unload(sc);
2035	} else if (unload_mode != UNLOAD_RECOVERY) {
2036		/* if this is a normal/close unload need to clean up chip */
2037		bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2038	} else {
2039		/* Send the UNLOAD_REQUEST to the MCP */
2040		bnx2x_send_unload_req(sc, unload_mode);
2041
2042		/*
2043		 * Prevent transactions to host from the functions on the
2044		 * engine that doesn't reset global blocks in case of global
2045		 * attention once gloabl blocks are reset and gates are opened
2046		 * (the engine which leader will perform the recovery
2047		 * last).
2048		 */
2049		if (!CHIP_IS_E1x(sc)) {
2050			bnx2x_pf_disable(sc);
2051		}
2052
2053		/* disable HW interrupts */
2054		bnx2x_int_disable_sync(sc, TRUE);
2055
2056		/* Report UNLOAD_DONE to MCP */
2057		bnx2x_send_unload_done(sc, FALSE);
2058	}
2059
2060	/*
2061	 * At this stage no more interrupts will arrive so we may safely clean
2062	 * the queue'able objects here in case they failed to get cleaned so far.
2063	 */
2064	if (IS_PF(sc)) {
2065		bnx2x_squeeze_objects(sc);
2066	}
2067
2068	/* There should be no more pending SP commands at this stage */
2069	sc->sp_state = 0;
2070
2071	sc->port.pmf = 0;
2072
2073	if (IS_PF(sc)) {
2074		bnx2x_free_mem(sc);
2075	}
2076
2077	bnx2x_free_fw_stats_mem(sc);
2078
2079	sc->state = BNX2X_STATE_CLOSED;
2080
2081	/*
2082	 * Check if there are pending parity attentions. If there are - set
2083	 * RECOVERY_IN_PROGRESS.
2084	 */
2085	if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2086		bnx2x_set_reset_in_progress(sc);
2087
2088		/* Set RESET_IS_GLOBAL if needed */
2089		if (global) {
2090			bnx2x_set_reset_global(sc);
2091		}
2092	}
2093
2094	/*
2095	 * The last driver must disable a "close the gate" if there is no
2096	 * parity attention or "process kill" pending.
2097	 */
2098	if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2099	    bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2100		bnx2x_disable_close_the_gate(sc);
2101	}
2102
2103	PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2104
2105	return 0;
2106}
2107
2108/*
2109 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2110 * visible to the controller.
2111 *
2112 * If an mbuf is submitted to this routine and cannot be given to the
2113 * controller (e.g. it has too many fragments) then the function may free
2114 * the mbuf and return to the caller.
2115 *
2116 * Returns:
2117 *     int: Number of TX BDs used for the mbuf
2118 *
2119 *   Note the side effect that an mbuf may be freed if it causes a problem.
2120 */
2121int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2122{
2123	struct eth_tx_start_bd *tx_start_bd;
2124	uint16_t bd_prod, pkt_prod;
2125	struct bnx2x_softc *sc;
2126	uint32_t nbds = 0;
2127
2128	sc = txq->sc;
2129	bd_prod = txq->tx_bd_tail;
2130	pkt_prod = txq->tx_pkt_tail;
2131
2132	txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2133
2134	tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2135
2136	tx_start_bd->addr =
2137	    rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2138	tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2139	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2140	tx_start_bd->general_data =
2141	    (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2142
2143	tx_start_bd->nbd = rte_cpu_to_le_16(2);
2144
2145	if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2146		tx_start_bd->vlan_or_ethertype =
2147		    rte_cpu_to_le_16(m0->vlan_tci);
2148		tx_start_bd->bd_flags.as_bitfield |=
2149		    (X_ETH_OUTBAND_VLAN <<
2150		     ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2151	} else {
2152		if (IS_PF(sc))
2153			tx_start_bd->vlan_or_ethertype =
2154			    rte_cpu_to_le_16(pkt_prod);
2155		else {
2156			struct ether_hdr *eh =
2157			    rte_pktmbuf_mtod(m0, struct ether_hdr *);
2158
2159			tx_start_bd->vlan_or_ethertype =
2160			    rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2161		}
2162	}
2163
2164	bd_prod = NEXT_TX_BD(bd_prod);
2165	if (IS_VF(sc)) {
2166		struct eth_tx_parse_bd_e2 *tx_parse_bd;
2167		const struct ether_hdr *eh =
2168		    rte_pktmbuf_mtod(m0, struct ether_hdr *);
2169		uint8_t mac_type = UNICAST_ADDRESS;
2170
2171		tx_parse_bd =
2172		    &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2173		if (is_multicast_ether_addr(&eh->d_addr)) {
2174			if (is_broadcast_ether_addr(&eh->d_addr))
2175				mac_type = BROADCAST_ADDRESS;
2176			else
2177				mac_type = MULTICAST_ADDRESS;
2178		}
2179		tx_parse_bd->parsing_data =
2180		    (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2181
2182		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2183			   &eh->d_addr.addr_bytes[0], 2);
2184		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2185			   &eh->d_addr.addr_bytes[2], 2);
2186		rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2187			   &eh->d_addr.addr_bytes[4], 2);
2188		rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2189			   &eh->s_addr.addr_bytes[0], 2);
2190		rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2191			   &eh->s_addr.addr_bytes[2], 2);
2192		rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2193			   &eh->s_addr.addr_bytes[4], 2);
2194
2195		tx_parse_bd->data.mac_addr.dst_hi =
2196		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2197		tx_parse_bd->data.mac_addr.dst_mid =
2198		    rte_cpu_to_be_16(tx_parse_bd->data.
2199				     mac_addr.dst_mid);
2200		tx_parse_bd->data.mac_addr.dst_lo =
2201		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2202		tx_parse_bd->data.mac_addr.src_hi =
2203		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2204		tx_parse_bd->data.mac_addr.src_mid =
2205		    rte_cpu_to_be_16(tx_parse_bd->data.
2206				     mac_addr.src_mid);
2207		tx_parse_bd->data.mac_addr.src_lo =
2208		    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2209
2210		PMD_TX_LOG(DEBUG,
2211			   "PBD dst %x %x %x src %x %x %x p_data %x",
2212			   tx_parse_bd->data.mac_addr.dst_hi,
2213			   tx_parse_bd->data.mac_addr.dst_mid,
2214			   tx_parse_bd->data.mac_addr.dst_lo,
2215			   tx_parse_bd->data.mac_addr.src_hi,
2216			   tx_parse_bd->data.mac_addr.src_mid,
2217			   tx_parse_bd->data.mac_addr.src_lo,
2218			   tx_parse_bd->parsing_data);
2219	}
2220
2221	PMD_TX_LOG(DEBUG,
2222		   "start bd: nbytes %d flags %x vlan %x\n",
2223		   tx_start_bd->nbytes,
2224		   tx_start_bd->bd_flags.as_bitfield,
2225		   tx_start_bd->vlan_or_ethertype);
2226
2227	bd_prod = NEXT_TX_BD(bd_prod);
2228	pkt_prod++;
2229
2230	if (TX_IDX(bd_prod) < 2)
2231		nbds++;
2232
2233	txq->nb_tx_avail -= 2;
2234	txq->tx_bd_tail = bd_prod;
2235	txq->tx_pkt_tail = pkt_prod;
2236
2237	return nbds + 2;
2238}
2239
2240static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2241{
2242	return L2_ILT_LINES(sc);
2243}
2244
2245static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2246{
2247	struct ilt_client_info *ilt_client;
2248	struct ecore_ilt *ilt = sc->ilt;
2249	uint16_t line = 0;
2250
2251	PMD_INIT_FUNC_TRACE();
2252
2253	ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2254
2255	/* CDU */
2256	ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2257	ilt_client->client_num = ILT_CLIENT_CDU;
2258	ilt_client->page_size = CDU_ILT_PAGE_SZ;
2259	ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2260	ilt_client->start = line;
2261	line += bnx2x_cid_ilt_lines(sc);
2262
2263	if (CNIC_SUPPORT(sc)) {
2264		line += CNIC_ILT_LINES;
2265	}
2266
2267	ilt_client->end = (line - 1);
2268
2269	/* QM */
2270	if (QM_INIT(sc->qm_cid_count)) {
2271		ilt_client = &ilt->clients[ILT_CLIENT_QM];
2272		ilt_client->client_num = ILT_CLIENT_QM;
2273		ilt_client->page_size = QM_ILT_PAGE_SZ;
2274		ilt_client->flags = 0;
2275		ilt_client->start = line;
2276
2277		/* 4 bytes for each cid */
2278		line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2279				     QM_ILT_PAGE_SZ);
2280
2281		ilt_client->end = (line - 1);
2282	}
2283
2284	if (CNIC_SUPPORT(sc)) {
2285		/* SRC */
2286		ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2287		ilt_client->client_num = ILT_CLIENT_SRC;
2288		ilt_client->page_size = SRC_ILT_PAGE_SZ;
2289		ilt_client->flags = 0;
2290		ilt_client->start = line;
2291		line += SRC_ILT_LINES;
2292		ilt_client->end = (line - 1);
2293
2294		/* TM */
2295		ilt_client = &ilt->clients[ILT_CLIENT_TM];
2296		ilt_client->client_num = ILT_CLIENT_TM;
2297		ilt_client->page_size = TM_ILT_PAGE_SZ;
2298		ilt_client->flags = 0;
2299		ilt_client->start = line;
2300		line += TM_ILT_LINES;
2301		ilt_client->end = (line - 1);
2302	}
2303
2304	assert((line <= ILT_MAX_LINES));
2305}
2306
2307static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2308{
2309	int i;
2310
2311	for (i = 0; i < sc->num_queues; i++) {
2312		/* get the Rx buffer size for RX frames */
2313		sc->fp[i].rx_buf_size =
2314		    (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2315	}
2316}
2317
2318int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2319{
2320
2321	sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2322
2323	return sc->ilt == NULL;
2324}
2325
2326static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2327{
2328	sc->ilt->lines = rte_calloc("",
2329				    sizeof(struct ilt_line), ILT_MAX_LINES,
2330				    RTE_CACHE_LINE_SIZE);
2331	return sc->ilt->lines == NULL;
2332}
2333
2334void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2335{
2336	rte_free(sc->ilt);
2337	sc->ilt = NULL;
2338}
2339
2340static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2341{
2342	if (sc->ilt->lines != NULL) {
2343		rte_free(sc->ilt->lines);
2344		sc->ilt->lines = NULL;
2345	}
2346}
2347
2348static void bnx2x_free_mem(struct bnx2x_softc *sc)
2349{
2350	uint32_t i;
2351
2352	for (i = 0; i < L2_ILT_LINES(sc); i++) {
2353		sc->context[i].vcxt = NULL;
2354		sc->context[i].size = 0;
2355	}
2356
2357	ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2358
2359	bnx2x_free_ilt_lines_mem(sc);
2360}
2361
2362static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2363{
2364	int context_size;
2365	int allocated;
2366	int i;
2367	char cdu_name[RTE_MEMZONE_NAMESIZE];
2368
2369	/*
2370	 * Allocate memory for CDU context:
2371	 * This memory is allocated separately and not in the generic ILT
2372	 * functions because CDU differs in few aspects:
2373	 * 1. There can be multiple entities allocating memory for context -
2374	 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2375	 * its own ILT lines.
2376	 * 2. Since CDU page-size is not a single 4KB page (which is the case
2377	 * for the other ILT clients), to be efficient we want to support
2378	 * allocation of sub-page-size in the last entry.
2379	 * 3. Context pointers are used by the driver to pass to FW / update
2380	 * the context (for the other ILT clients the pointers are used just to
2381	 * free the memory during unload).
2382	 */
2383	context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2384	for (i = 0, allocated = 0; allocated < context_size; i++) {
2385		sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2386					  (context_size - allocated));
2387
2388		snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2389		if (bnx2x_dma_alloc(sc, sc->context[i].size,
2390				  &sc->context[i].vcxt_dma,
2391				  cdu_name, BNX2X_PAGE_SIZE) != 0) {
2392			bnx2x_free_mem(sc);
2393			return -1;
2394		}
2395
2396		sc->context[i].vcxt =
2397		    (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2398
2399		allocated += sc->context[i].size;
2400	}
2401
2402	bnx2x_alloc_ilt_lines_mem(sc);
2403
2404	if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2405		PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2406		bnx2x_free_mem(sc);
2407		return -1;
2408	}
2409
2410	return 0;
2411}
2412
2413static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2414{
2415	sc->fw_stats_num = 0;
2416
2417	sc->fw_stats_req_size = 0;
2418	sc->fw_stats_req = NULL;
2419	sc->fw_stats_req_mapping = 0;
2420
2421	sc->fw_stats_data_size = 0;
2422	sc->fw_stats_data = NULL;
2423	sc->fw_stats_data_mapping = 0;
2424}
2425
2426static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2427{
2428	uint8_t num_queue_stats;
2429	int num_groups, vf_headroom = 0;
2430
2431	/* number of queues for statistics is number of eth queues */
2432	num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2433
2434	/*
2435	 * Total number of FW statistics requests =
2436	 *   1 for port stats + 1 for PF stats + num of queues
2437	 */
2438	sc->fw_stats_num = (2 + num_queue_stats);
2439
2440	/*
2441	 * Request is built from stats_query_header and an array of
2442	 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2443	 * rules. The real number or requests is configured in the
2444	 * stats_query_header.
2445	 */
2446	num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2447	if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2448		num_groups++;
2449
2450	sc->fw_stats_req_size =
2451	    (sizeof(struct stats_query_header) +
2452	     (num_groups * sizeof(struct stats_query_cmd_group)));
2453
2454	/*
2455	 * Data for statistics requests + stats_counter.
2456	 * stats_counter holds per-STORM counters that are incremented when
2457	 * STORM has finished with the current request. Memory for FCoE
2458	 * offloaded statistics are counted anyway, even if they will not be sent.
2459	 * VF stats are not accounted for here as the data of VF stats is stored
2460	 * in memory allocated by the VF, not here.
2461	 */
2462	sc->fw_stats_data_size =
2463	    (sizeof(struct stats_counter) +
2464	     sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2465	     /* sizeof(struct fcoe_statistics_params) + */
2466	     (sizeof(struct per_queue_stats) * num_queue_stats));
2467
2468	if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2469			  &sc->fw_stats_dma, "fw_stats",
2470			  RTE_CACHE_LINE_SIZE) != 0) {
2471		bnx2x_free_fw_stats_mem(sc);
2472		return -1;
2473	}
2474
2475	/* set up the shortcuts */
2476
2477	sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2478	sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2479
2480	sc->fw_stats_data =
2481	    (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2482					 sc->fw_stats_req_size);
2483	sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2484				     sc->fw_stats_req_size);
2485
2486	return 0;
2487}
2488
2489/*
2490 * Bits map:
2491 * 0-7  - Engine0 load counter.
2492 * 8-15 - Engine1 load counter.
2493 * 16   - Engine0 RESET_IN_PROGRESS bit.
2494 * 17   - Engine1 RESET_IN_PROGRESS bit.
2495 * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2496 *        function on the engine
2497 * 19   - Engine1 ONE_IS_LOADED.
2498 * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2499 *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2500 *        for just the one belonging to its engine).
2501 */
2502#define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2503#define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2504#define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2505#define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2506#define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2507#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2508#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2509#define BNX2X_GLOBAL_RESET_BIT      0x00040000
2510
2511/* set the GLOBAL_RESET bit, should be run under rtnl lock */
2512static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2513{
2514	uint32_t val;
2515	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2516	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2517	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2518	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2519}
2520
2521/* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2522static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2523{
2524	uint32_t val;
2525	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2526	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2527	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2528	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2529}
2530
2531/* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2532static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2533{
2534	return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2535}
2536
2537/* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2538static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2539{
2540	uint32_t val;
2541	uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2542	    BNX2X_PATH0_RST_IN_PROG_BIT;
2543
2544	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2545
2546	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2547	/* Clear the bit */
2548	val &= ~bit;
2549	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2550
2551	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2552}
2553
2554/* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2555static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2556{
2557	uint32_t val;
2558	uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2559	    BNX2X_PATH0_RST_IN_PROG_BIT;
2560
2561	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2562
2563	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2564	/* Set the bit */
2565	val |= bit;
2566	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2567
2568	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2569}
2570
2571/* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2572static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2573{
2574	uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2575	uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2576	    BNX2X_PATH0_RST_IN_PROG_BIT;
2577
2578	/* return false if bit is set */
2579	return (val & bit) ? FALSE : TRUE;
2580}
2581
2582/* get the load status for an engine, should be run under rtnl lock */
2583static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2584{
2585	uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2586	    BNX2X_PATH0_LOAD_CNT_MASK;
2587	uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2588	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2589	uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2590
2591	val = ((val & mask) >> shift);
2592
2593	return val != 0;
2594}
2595
2596/* set pf load mark */
2597static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2598{
2599	uint32_t val;
2600	uint32_t val1;
2601	uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2602	    BNX2X_PATH0_LOAD_CNT_MASK;
2603	uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2604	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2605
2606	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2607
2608	PMD_INIT_FUNC_TRACE();
2609
2610	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611
2612	/* get the current counter value */
2613	val1 = ((val & mask) >> shift);
2614
2615	/* set bit of this PF */
2616	val1 |= (1 << SC_ABS_FUNC(sc));
2617
2618	/* clear the old value */
2619	val &= ~mask;
2620
2621	/* set the new one */
2622	val |= ((val1 << shift) & mask);
2623
2624	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2625
2626	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2627}
2628
2629/* clear pf load mark */
2630static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2631{
2632	uint32_t val1, val;
2633	uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2634	    BNX2X_PATH0_LOAD_CNT_MASK;
2635	uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2636	    BNX2X_PATH0_LOAD_CNT_SHIFT;
2637
2638	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2639	val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2640
2641	/* get the current counter value */
2642	val1 = (val & mask) >> shift;
2643
2644	/* clear bit of that PF */
2645	val1 &= ~(1 << SC_ABS_FUNC(sc));
2646
2647	/* clear the old value */
2648	val &= ~mask;
2649
2650	/* set the new one */
2651	val |= ((val1 << shift) & mask);
2652
2653	REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2654	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2655	return val1 != 0;
2656}
2657
2658/* send load requrest to mcp and analyze response */
2659static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2660{
2661	PMD_INIT_FUNC_TRACE();
2662
2663	/* init fw_seq */
2664	sc->fw_seq =
2665	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2666	     DRV_MSG_SEQ_NUMBER_MASK);
2667
2668	PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2669
2670#ifdef BNX2X_PULSE
2671	/* get the current FW pulse sequence */
2672	sc->fw_drv_pulse_wr_seq =
2673	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2674	     DRV_PULSE_SEQ_MASK);
2675#else
2676	/* set ALWAYS_ALIVE bit in shmem */
2677	sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2678	bnx2x_drv_pulse(sc);
2679#endif
2680
2681	/* load request */
2682	(*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2683				      DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2684
2685	/* if the MCP fails to respond we must abort */
2686	if (!(*load_code)) {
2687		PMD_DRV_LOG(NOTICE, "MCP response failure!");
2688		return -1;
2689	}
2690
2691	/* if MCP refused then must abort */
2692	if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2693		PMD_DRV_LOG(NOTICE, "MCP refused load request");
2694		return -1;
2695	}
2696
2697	return 0;
2698}
2699
2700/*
2701 * Check whether another PF has already loaded FW to chip. In virtualized
2702 * environments a pf from anoth VM may have already initialized the device
2703 * including loading FW.
2704 */
2705static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2706{
2707	uint32_t my_fw, loaded_fw;
2708
2709	/* is another pf loaded on this engine? */
2710	if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2711	    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2712		/* build my FW version dword */
2713		my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2714			 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2715			 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2716			 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2717
2718		/* read loaded FW from chip */
2719		loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2720		PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2721			    loaded_fw, my_fw);
2722
2723		/* abort nic load if version mismatch */
2724		if (my_fw != loaded_fw) {
2725			PMD_DRV_LOG(NOTICE,
2726				    "FW 0x%08x already loaded (mine is 0x%08x)",
2727				    loaded_fw, my_fw);
2728			return -1;
2729		}
2730	}
2731
2732	return 0;
2733}
2734
2735/* mark PMF if applicable */
2736static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2737{
2738	uint32_t ncsi_oem_data_addr;
2739
2740	PMD_INIT_FUNC_TRACE();
2741
2742	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2743	    (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2744	    (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2745		/*
2746		 * Barrier here for ordering between the writing to sc->port.pmf here
2747		 * and reading it from the periodic task.
2748		 */
2749		sc->port.pmf = 1;
2750		mb();
2751	} else {
2752		sc->port.pmf = 0;
2753	}
2754
2755	PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2756
2757	if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2758		if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2759			ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2760			if (ncsi_oem_data_addr) {
2761				REG_WR(sc,
2762				       (ncsi_oem_data_addr +
2763					offsetof(struct glob_ncsi_oem_data,
2764						 driver_version)), 0);
2765			}
2766		}
2767	}
2768}
2769
2770static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2771{
2772	int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2773	int abs_func;
2774	int vn;
2775
2776	if (BNX2X_NOMCP(sc)) {
2777		return;		/* what should be the default bvalue in this case */
2778	}
2779
2780	/*
2781	 * The formula for computing the absolute function number is...
2782	 * For 2 port configuration (4 functions per port):
2783	 *   abs_func = 2 * vn + SC_PORT + SC_PATH
2784	 * For 4 port configuration (2 functions per port):
2785	 *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2786	 */
2787	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2788		abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2789		if (abs_func >= E1H_FUNC_MAX) {
2790			break;
2791		}
2792		sc->devinfo.mf_info.mf_config[vn] =
2793		    MFCFG_RD(sc, func_mf_config[abs_func].config);
2794	}
2795
2796	if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2797	    FUNC_MF_CFG_FUNC_DISABLED) {
2798		PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2799		sc->flags |= BNX2X_MF_FUNC_DIS;
2800	} else {
2801		PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2802		sc->flags &= ~BNX2X_MF_FUNC_DIS;
2803	}
2804}
2805
2806/* acquire split MCP access lock register */
2807static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2808{
2809	uint32_t j, val;
2810
2811	for (j = 0; j < 1000; j++) {
2812		val = (1UL << 31);
2813		REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2814		val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2815		if (val & (1L << 31))
2816			break;
2817
2818		DELAY(5000);
2819	}
2820
2821	if (!(val & (1L << 31))) {
2822		PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2823		return -1;
2824	}
2825
2826	return 0;
2827}
2828
2829/* release split MCP access lock register */
2830static void bnx2x_release_alr(struct bnx2x_softc *sc)
2831{
2832	REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2833}
2834
2835static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2836{
2837	int port = SC_PORT(sc);
2838	uint32_t ext_phy_config;
2839
2840	/* mark the failure */
2841	ext_phy_config =
2842	    SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2843
2844	ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2845	ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2846	SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2847		 ext_phy_config);
2848
2849	/* log the failure */
2850	PMD_DRV_LOG(INFO,
2851		    "Fan Failure has caused the driver to shutdown "
2852		    "the card to prevent permanent damage. "
2853		    "Please contact OEM Support for assistance");
2854
2855	rte_panic("Schedule task to handle fan failure");
2856}
2857
2858/* this function is called upon a link interrupt */
2859static void bnx2x_link_attn(struct bnx2x_softc *sc)
2860{
2861	uint32_t pause_enabled = 0;
2862	struct host_port_stats *pstats;
2863	int cmng_fns;
2864
2865	/* Make sure that we are synced with the current statistics */
2866	bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2867
2868	elink_link_update(&sc->link_params, &sc->link_vars);
2869
2870	if (sc->link_vars.link_up) {
2871
2872		/* dropless flow control */
2873		if (sc->dropless_fc) {
2874			pause_enabled = 0;
2875
2876			if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2877				pause_enabled = 1;
2878			}
2879
2880			REG_WR(sc,
2881			       (BAR_USTRORM_INTMEM +
2882				USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2883			       pause_enabled);
2884		}
2885
2886		if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2887			pstats = BNX2X_SP(sc, port_stats);
2888			/* reset old mac stats */
2889			memset(&(pstats->mac_stx[0]), 0,
2890			       sizeof(struct mac_stx));
2891		}
2892
2893		if (sc->state == BNX2X_STATE_OPEN) {
2894			bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2895		}
2896	}
2897
2898	if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2899		cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2900
2901		if (cmng_fns != CMNG_FNS_NONE) {
2902			bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2903			storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2904		}
2905	}
2906
2907	bnx2x_link_report(sc);
2908
2909	if (IS_MF(sc)) {
2910		bnx2x_link_sync_notify(sc);
2911	}
2912}
2913
2914static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2915{
2916	int port = SC_PORT(sc);
2917	uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2918	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
2919	uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2920	    NIG_REG_MASK_INTERRUPT_PORT0;
2921	uint32_t aeu_mask;
2922	uint32_t nig_mask = 0;
2923	uint32_t reg_addr;
2924	uint32_t igu_acked;
2925	uint32_t cnt;
2926
2927	if (sc->attn_state & asserted) {
2928		PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2929	}
2930
2931	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2932
2933	aeu_mask = REG_RD(sc, aeu_addr);
2934
2935	aeu_mask &= ~(asserted & 0x3ff);
2936
2937	REG_WR(sc, aeu_addr, aeu_mask);
2938
2939	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2940
2941	sc->attn_state |= asserted;
2942
2943	if (asserted & ATTN_HARD_WIRED_MASK) {
2944		if (asserted & ATTN_NIG_FOR_FUNC) {
2945
2946			/* save nig interrupt mask */
2947			nig_mask = REG_RD(sc, nig_int_mask_addr);
2948
2949			/* If nig_mask is not set, no need to call the update function */
2950			if (nig_mask) {
2951				REG_WR(sc, nig_int_mask_addr, 0);
2952
2953				bnx2x_link_attn(sc);
2954			}
2955
2956			/* handle unicore attn? */
2957		}
2958
2959		if (asserted & ATTN_SW_TIMER_4_FUNC) {
2960			PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2961		}
2962
2963		if (asserted & GPIO_2_FUNC) {
2964			PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2965		}
2966
2967		if (asserted & GPIO_3_FUNC) {
2968			PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2969		}
2970
2971		if (asserted & GPIO_4_FUNC) {
2972			PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2973		}
2974
2975		if (port == 0) {
2976			if (asserted & ATTN_GENERAL_ATTN_1) {
2977				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2978				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2979			}
2980			if (asserted & ATTN_GENERAL_ATTN_2) {
2981				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2982				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2983			}
2984			if (asserted & ATTN_GENERAL_ATTN_3) {
2985				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2986				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2987			}
2988		} else {
2989			if (asserted & ATTN_GENERAL_ATTN_4) {
2990				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2991				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2992			}
2993			if (asserted & ATTN_GENERAL_ATTN_5) {
2994				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2995				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2996			}
2997			if (asserted & ATTN_GENERAL_ATTN_6) {
2998				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2999				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3000			}
3001		}
3002	}
3003	/* hardwired */
3004	if (sc->devinfo.int_block == INT_BLOCK_HC) {
3005		reg_addr =
3006		    (HC_REG_COMMAND_REG + port * 32 +
3007		     COMMAND_REG_ATTN_BITS_SET);
3008	} else {
3009		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3010	}
3011
3012	PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3013		    asserted,
3014		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3015		    reg_addr);
3016	REG_WR(sc, reg_addr, asserted);
3017
3018	/* now set back the mask */
3019	if (asserted & ATTN_NIG_FOR_FUNC) {
3020		/*
3021		 * Verify that IGU ack through BAR was written before restoring
3022		 * NIG mask. This loop should exit after 2-3 iterations max.
3023		 */
3024		if (sc->devinfo.int_block != INT_BLOCK_HC) {
3025			cnt = 0;
3026
3027			do {
3028				igu_acked =
3029				    REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3030			} while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3031				 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3032
3033			if (!igu_acked) {
3034				PMD_DRV_LOG(ERR,
3035					    "Failed to verify IGU ack on time");
3036			}
3037
3038			mb();
3039		}
3040
3041		REG_WR(sc, nig_int_mask_addr, nig_mask);
3042
3043	}
3044}
3045
3046static void
3047bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3048		     __rte_unused const char *blk)
3049{
3050	PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3051}
3052
3053static int
3054bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3055			      uint8_t print)
3056{
3057	uint32_t cur_bit = 0;
3058	int i = 0;
3059
3060	for (i = 0; sig; i++) {
3061		cur_bit = ((uint32_t) 0x1 << i);
3062		if (sig & cur_bit) {
3063			switch (cur_bit) {
3064			case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3065				if (print)
3066					bnx2x_print_next_block(sc, par_num++,
3067							     "BRB");
3068				break;
3069			case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3070				if (print)
3071					bnx2x_print_next_block(sc, par_num++,
3072							     "PARSER");
3073				break;
3074			case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3075				if (print)
3076					bnx2x_print_next_block(sc, par_num++,
3077							     "TSDM");
3078				break;
3079			case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3080				if (print)
3081					bnx2x_print_next_block(sc, par_num++,
3082							     "SEARCHER");
3083				break;
3084			case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3085				if (print)
3086					bnx2x_print_next_block(sc, par_num++,
3087							     "TCM");
3088				break;
3089			case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3090				if (print)
3091					bnx2x_print_next_block(sc, par_num++,
3092							     "TSEMI");
3093				break;
3094			case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3095				if (print)
3096					bnx2x_print_next_block(sc, par_num++,
3097							     "XPB");
3098				break;
3099			}
3100
3101			/* Clear the bit */
3102			sig &= ~cur_bit;
3103		}
3104	}
3105
3106	return par_num;
3107}
3108
3109static int
3110bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3111			      uint8_t * global, uint8_t print)
3112{
3113	int i = 0;
3114	uint32_t cur_bit = 0;
3115	for (i = 0; sig; i++) {
3116		cur_bit = ((uint32_t) 0x1 << i);
3117		if (sig & cur_bit) {
3118			switch (cur_bit) {
3119			case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3120				if (print)
3121					bnx2x_print_next_block(sc, par_num++,
3122							     "PBF");
3123				break;
3124			case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3125				if (print)
3126					bnx2x_print_next_block(sc, par_num++,
3127							     "QM");
3128				break;
3129			case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3130				if (print)
3131					bnx2x_print_next_block(sc, par_num++,
3132							     "TM");
3133				break;
3134			case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3135				if (print)
3136					bnx2x_print_next_block(sc, par_num++,
3137							     "XSDM");
3138				break;
3139			case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3140				if (print)
3141					bnx2x_print_next_block(sc, par_num++,
3142							     "XCM");
3143				break;
3144			case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3145				if (print)
3146					bnx2x_print_next_block(sc, par_num++,
3147							     "XSEMI");
3148				break;
3149			case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3150				if (print)
3151					bnx2x_print_next_block(sc, par_num++,
3152							     "DOORBELLQ");
3153				break;
3154			case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3155				if (print)
3156					bnx2x_print_next_block(sc, par_num++,
3157							     "NIG");
3158				break;
3159			case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3160				if (print)
3161					bnx2x_print_next_block(sc, par_num++,
3162							     "VAUX PCI CORE");
3163				*global = TRUE;
3164				break;
3165			case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3166				if (print)
3167					bnx2x_print_next_block(sc, par_num++,
3168							     "DEBUG");
3169				break;
3170			case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3171				if (print)
3172					bnx2x_print_next_block(sc, par_num++,
3173							     "USDM");
3174				break;
3175			case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3176				if (print)
3177					bnx2x_print_next_block(sc, par_num++,
3178							     "UCM");
3179				break;
3180			case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3181				if (print)
3182					bnx2x_print_next_block(sc, par_num++,
3183							     "USEMI");
3184				break;
3185			case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3186				if (print)
3187					bnx2x_print_next_block(sc, par_num++,
3188							     "UPB");
3189				break;
3190			case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3191				if (print)
3192					bnx2x_print_next_block(sc, par_num++,
3193							     "CSDM");
3194				break;
3195			case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3196				if (print)
3197					bnx2x_print_next_block(sc, par_num++,
3198							     "CCM");
3199				break;
3200			}
3201
3202			/* Clear the bit */
3203			sig &= ~cur_bit;
3204		}
3205	}
3206
3207	return par_num;
3208}
3209
3210static int
3211bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3212			      uint8_t print)
3213{
3214	uint32_t cur_bit = 0;
3215	int i = 0;
3216
3217	for (i = 0; sig; i++) {
3218		cur_bit = ((uint32_t) 0x1 << i);
3219		if (sig & cur_bit) {
3220			switch (cur_bit) {
3221			case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3222				if (print)
3223					bnx2x_print_next_block(sc, par_num++,
3224							     "CSEMI");
3225				break;
3226			case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3227				if (print)
3228					bnx2x_print_next_block(sc, par_num++,
3229							     "PXP");
3230				break;
3231			case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3232				if (print)
3233					bnx2x_print_next_block(sc, par_num++,
3234							     "PXPPCICLOCKCLIENT");
3235				break;
3236			case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3237				if (print)
3238					bnx2x_print_next_block(sc, par_num++,
3239							     "CFC");
3240				break;
3241			case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3242				if (print)
3243					bnx2x_print_next_block(sc, par_num++,
3244							     "CDU");
3245				break;
3246			case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3247				if (print)
3248					bnx2x_print_next_block(sc, par_num++,
3249							     "DMAE");
3250				break;
3251			case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3252				if (print)
3253					bnx2x_print_next_block(sc, par_num++,
3254							     "IGU");
3255				break;
3256			case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3257				if (print)
3258					bnx2x_print_next_block(sc, par_num++,
3259							     "MISC");
3260				break;
3261			}
3262
3263			/* Clear the bit */
3264			sig &= ~cur_bit;
3265		}
3266	}
3267
3268	return par_num;
3269}
3270
3271static int
3272bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3273			      uint8_t * global, uint8_t print)
3274{
3275	uint32_t cur_bit = 0;
3276	int i = 0;
3277
3278	for (i = 0; sig; i++) {
3279		cur_bit = ((uint32_t) 0x1 << i);
3280		if (sig & cur_bit) {
3281			switch (cur_bit) {
3282			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3283				if (print)
3284					bnx2x_print_next_block(sc, par_num++,
3285							     "MCP ROM");
3286				*global = TRUE;
3287				break;
3288			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3289				if (print)
3290					bnx2x_print_next_block(sc, par_num++,
3291							     "MCP UMP RX");
3292				*global = TRUE;
3293				break;
3294			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3295				if (print)
3296					bnx2x_print_next_block(sc, par_num++,
3297							     "MCP UMP TX");
3298				*global = TRUE;
3299				break;
3300			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3301				if (print)
3302					bnx2x_print_next_block(sc, par_num++,
3303							     "MCP SCPAD");
3304				*global = TRUE;
3305				break;
3306			}
3307
3308			/* Clear the bit */
3309			sig &= ~cur_bit;
3310		}
3311	}
3312
3313	return par_num;
3314}
3315
3316static int
3317bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3318			      uint8_t print)
3319{
3320	uint32_t cur_bit = 0;
3321	int i = 0;
3322
3323	for (i = 0; sig; i++) {
3324		cur_bit = ((uint32_t) 0x1 << i);
3325		if (sig & cur_bit) {
3326			switch (cur_bit) {
3327			case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3328				if (print)
3329					bnx2x_print_next_block(sc, par_num++,
3330							     "PGLUE_B");
3331				break;
3332			case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3333				if (print)
3334					bnx2x_print_next_block(sc, par_num++,
3335							     "ATC");
3336				break;
3337			}
3338
3339			/* Clear the bit */
3340			sig &= ~cur_bit;
3341		}
3342	}
3343
3344	return par_num;
3345}
3346
3347static uint8_t
3348bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3349		uint32_t * sig)
3350{
3351	int par_num = 0;
3352
3353	if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3354	    (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3355	    (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3356	    (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3357	    (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3358		PMD_DRV_LOG(ERR,
3359			    "Parity error: HW block parity attention:"
3360			    "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3361			    (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3362			    (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3363			    (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3364			    (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3365			    (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3366
3367		if (print)
3368			PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3369
3370		par_num =
3371		    bnx2x_check_blocks_with_parity0(sc, sig[0] &
3372						  HW_PRTY_ASSERT_SET_0,
3373						  par_num, print);
3374		par_num =
3375		    bnx2x_check_blocks_with_parity1(sc, sig[1] &
3376						  HW_PRTY_ASSERT_SET_1,
3377						  par_num, global, print);
3378		par_num =
3379		    bnx2x_check_blocks_with_parity2(sc, sig[2] &
3380						  HW_PRTY_ASSERT_SET_2,
3381						  par_num, print);
3382		par_num =
3383		    bnx2x_check_blocks_with_parity3(sc, sig[3] &
3384						  HW_PRTY_ASSERT_SET_3,
3385						  par_num, global, print);
3386		par_num =
3387		    bnx2x_check_blocks_with_parity4(sc, sig[4] &
3388						  HW_PRTY_ASSERT_SET_4,
3389						  par_num, print);
3390
3391		if (print)
3392			PMD_DRV_LOG(INFO, "");
3393
3394		return TRUE;
3395	}
3396
3397	return FALSE;
3398}
3399
3400static uint8_t
3401bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3402{
3403	struct attn_route attn = { {0} };
3404	int port = SC_PORT(sc);
3405
3406	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3407	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3408	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3409	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3410
3411	if (!CHIP_IS_E1x(sc))
3412		attn.sig[4] =
3413		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3414
3415	return bnx2x_parity_attn(sc, global, print, attn.sig);
3416}
3417
3418static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3419{
3420	uint32_t val;
3421
3422	if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3423		val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3424		PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3425		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3426			PMD_DRV_LOG(INFO,
3427				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3428		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3429			PMD_DRV_LOG(INFO,
3430				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3431		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3432			PMD_DRV_LOG(INFO,
3433				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3434		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3435			PMD_DRV_LOG(INFO,
3436				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3437		if (val &
3438		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3439			PMD_DRV_LOG(INFO,
3440				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3441		if (val &
3442		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3443			PMD_DRV_LOG(INFO,
3444				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3445		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3446			PMD_DRV_LOG(INFO,
3447				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3448		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3449			PMD_DRV_LOG(INFO,
3450				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3451		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3452			PMD_DRV_LOG(INFO,
3453				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3454	}
3455
3456	if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3457		val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3458		PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3459		if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3460			PMD_DRV_LOG(INFO,
3461				    "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3462		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3463			PMD_DRV_LOG(INFO,
3464				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3465		if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3466			PMD_DRV_LOG(INFO,
3467				    "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3468		if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3469			PMD_DRV_LOG(INFO,
3470				    "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3471		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3472			PMD_DRV_LOG(INFO,
3473				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3474		if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3475			PMD_DRV_LOG(INFO,
3476				    "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3477	}
3478
3479	if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3480		    AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3481		PMD_DRV_LOG(INFO,
3482			    "ERROR: FATAL parity attention set4 0x%08x",
3483			    (uint32_t) (attn &
3484					(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3485					 |
3486					 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3487	}
3488}
3489
3490static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3491{
3492	int port = SC_PORT(sc);
3493
3494	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3495}
3496
3497static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3498{
3499	int port = SC_PORT(sc);
3500
3501	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3502}
3503
3504/*
3505 * called due to MCP event (on pmf):
3506 *   reread new bandwidth configuration
3507 *   configure FW
3508 *   notify others function about the change
3509 */
3510static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3511{
3512	if (sc->link_vars.link_up) {
3513		bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3514		bnx2x_link_sync_notify(sc);
3515	}
3516
3517	storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3518}
3519
3520static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3521{
3522	bnx2x_config_mf_bw(sc);
3523	bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3524}
3525
3526static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3527{
3528	bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3529}
3530
3531#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3532
3533static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3534{
3535	struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3536
3537	strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3538		ETH_STAT_INFO_VERSION_LEN);
3539
3540	sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3541					      DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3542					      ether_stat->mac_local + MAC_PAD,
3543					      MAC_PAD, ETH_ALEN);
3544
3545	ether_stat->mtu_size = sc->mtu;
3546
3547	ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3548	ether_stat->promiscuous_mode = 0;	// (flags & PROMISC) ? 1 : 0;
3549
3550	ether_stat->txq_size = sc->tx_ring_size;
3551	ether_stat->rxq_size = sc->rx_ring_size;
3552}
3553
3554static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3555{
3556	enum drv_info_opcode op_code;
3557	uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3558
3559	/* if drv_info version supported by MFW doesn't match - send NACK */
3560	if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3561		bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3562		return;
3563	}
3564
3565	op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3566		   DRV_INFO_CONTROL_OP_CODE_SHIFT);
3567
3568	memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3569
3570	switch (op_code) {
3571	case ETH_STATS_OPCODE:
3572		bnx2x_drv_info_ether_stat(sc);
3573		break;
3574	case FCOE_STATS_OPCODE:
3575	case ISCSI_STATS_OPCODE:
3576	default:
3577		/* if op code isn't supported - send NACK */
3578		bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3579		return;
3580	}
3581
3582	/*
3583	 * If we got drv_info attn from MFW then these fields are defined in
3584	 * shmem2 for sure
3585	 */
3586	SHMEM2_WR(sc, drv_info_host_addr_lo,
3587		  U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3588	SHMEM2_WR(sc, drv_info_host_addr_hi,
3589		  U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3590
3591	bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3592}
3593
3594static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3595{
3596	if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3597/*
3598 * This is the only place besides the function initialization
3599 * where the sc->flags can change so it is done without any
3600 * locks
3601 */
3602		if (sc->devinfo.
3603		    mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3604			PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3605			sc->flags |= BNX2X_MF_FUNC_DIS;
3606			bnx2x_e1h_disable(sc);
3607		} else {
3608			PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3609			sc->flags &= ~BNX2X_MF_FUNC_DIS;
3610			bnx2x_e1h_enable(sc);
3611		}
3612		dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3613	}
3614
3615	if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3616		bnx2x_config_mf_bw(sc);
3617		dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3618	}
3619
3620	/* Report results to MCP */
3621	if (dcc_event)
3622		bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3623	else
3624		bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3625}
3626
3627static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3628{
3629	int port = SC_PORT(sc);
3630	uint32_t val;
3631
3632	sc->port.pmf = 1;
3633
3634	/*
3635	 * We need the mb() to ensure the ordering between the writing to
3636	 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3637	 */
3638	mb();
3639
3640	/* enable nig attention */
3641	val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3642	if (sc->devinfo.int_block == INT_BLOCK_HC) {
3643		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3644		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3645	} else if (!CHIP_IS_E1x(sc)) {
3646		REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3647		REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3648	}
3649
3650	bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3651}
3652
3653static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3654{
3655	char last_idx;
3656	int i, rc = 0;
3657	__rte_unused uint32_t row0, row1, row2, row3;
3658
3659	/* XSTORM */
3660	last_idx =
3661	    REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3662	if (last_idx)
3663		PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3664
3665	/* print the asserts */
3666	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3667
3668		row0 =
3669		    REG_RD(sc,
3670			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3671		row1 =
3672		    REG_RD(sc,
3673			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3674			   4);
3675		row2 =
3676		    REG_RD(sc,
3677			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3678			   8);
3679		row3 =
3680		    REG_RD(sc,
3681			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3682			   12);
3683
3684		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3685			PMD_DRV_LOG(ERR,
3686				    "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3687				    i, row3, row2, row1, row0);
3688			rc++;
3689		} else {
3690			break;
3691		}
3692	}
3693
3694	/* TSTORM */
3695	last_idx =
3696	    REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3697	if (last_idx) {
3698		PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3699	}
3700
3701	/* print the asserts */
3702	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3703
3704		row0 =
3705		    REG_RD(sc,
3706			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3707		row1 =
3708		    REG_RD(sc,
3709			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3710			   4);
3711		row2 =
3712		    REG_RD(sc,
3713			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3714			   8);
3715		row3 =
3716		    REG_RD(sc,
3717			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3718			   12);
3719
3720		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3721			PMD_DRV_LOG(ERR,
3722				    "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3723				    i, row3, row2, row1, row0);
3724			rc++;
3725		} else {
3726			break;
3727		}
3728	}
3729
3730	/* CSTORM */
3731	last_idx =
3732	    REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3733	if (last_idx) {
3734		PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3735	}
3736
3737	/* print the asserts */
3738	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3739
3740		row0 =
3741		    REG_RD(sc,
3742			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3743		row1 =
3744		    REG_RD(sc,
3745			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3746			   4);
3747		row2 =
3748		    REG_RD(sc,
3749			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3750			   8);
3751		row3 =
3752		    REG_RD(sc,
3753			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3754			   12);
3755
3756		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3757			PMD_DRV_LOG(ERR,
3758				    "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3759				    i, row3, row2, row1, row0);
3760			rc++;
3761		} else {
3762			break;
3763		}
3764	}
3765
3766	/* USTORM */
3767	last_idx =
3768	    REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3769	if (last_idx) {
3770		PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3771	}
3772
3773	/* print the asserts */
3774	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3775
3776		row0 =
3777		    REG_RD(sc,
3778			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3779		row1 =
3780		    REG_RD(sc,
3781			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3782			   4);
3783		row2 =
3784		    REG_RD(sc,
3785			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3786			   8);
3787		row3 =
3788		    REG_RD(sc,
3789			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3790			   12);
3791
3792		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3793			PMD_DRV_LOG(ERR,
3794				    "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3795				    i, row3, row2, row1, row0);
3796			rc++;
3797		} else {
3798			break;
3799		}
3800	}
3801
3802	return rc;
3803}
3804
3805static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3806{
3807	int func = SC_FUNC(sc);
3808	uint32_t val;
3809
3810	if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3811
3812		if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3813
3814			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3815			bnx2x_read_mf_cfg(sc);
3816			sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3817			    MFCFG_RD(sc,
3818				     func_mf_config[SC_ABS_FUNC(sc)].config);
3819			val =
3820			    SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3821
3822			if (val & DRV_STATUS_DCC_EVENT_MASK)
3823				bnx2x_dcc_event(sc,
3824					      (val &
3825					       DRV_STATUS_DCC_EVENT_MASK));
3826
3827			if (val & DRV_STATUS_SET_MF_BW)
3828				bnx2x_set_mf_bw(sc);
3829
3830			if (val & DRV_STATUS_DRV_INFO_REQ)
3831				bnx2x_handle_drv_info_req(sc);
3832
3833			if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3834				bnx2x_pmf_update(sc);
3835
3836			if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3837				bnx2x_handle_eee_event(sc);
3838
3839			if (sc->link_vars.periodic_flags &
3840			    ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3841				/* sync with link */
3842				sc->link_vars.periodic_flags &=
3843				    ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3844				if (IS_MF(sc)) {
3845					bnx2x_link_sync_notify(sc);
3846				}
3847				bnx2x_link_report(sc);
3848			}
3849
3850			/*
3851			 * Always call it here: bnx2x_link_report() will
3852			 * prevent the link indication duplication.
3853			 */
3854			bnx2x_link_status_update(sc);
3855
3856		} else if (attn & BNX2X_MC_ASSERT_BITS) {
3857
3858			PMD_DRV_LOG(ERR, "MC assert!");
3859			bnx2x_mc_assert(sc);
3860			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3861			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3862			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3863			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3864			rte_panic("MC assert!");
3865
3866		} else if (attn & BNX2X_MCP_ASSERT) {
3867
3868			PMD_DRV_LOG(ERR, "MCP assert!");
3869			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3870
3871		} else {
3872			PMD_DRV_LOG(ERR,
3873				    "Unknown HW assert! (attn 0x%08x)", attn);
3874		}
3875	}
3876
3877	if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3878		PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3879		if (attn & BNX2X_GRC_TIMEOUT) {
3880			val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3881			PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3882		}
3883		if (attn & BNX2X_GRC_RSV) {
3884			val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3885			PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3886		}
3887		REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3888	}
3889}
3890
3891static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3892{
3893	int port = SC_PORT(sc);
3894	int reg_offset;
3895	uint32_t val0, mask0, val1, mask1;
3896	uint32_t val;
3897
3898	if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3899		val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3900		PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3901/* CFC error attention */
3902		if (val & 0x2) {
3903			PMD_DRV_LOG(ERR, "FATAL error from CFC");
3904		}
3905	}
3906
3907	if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3908		val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3909		PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3910/* RQ_USDMDP_FIFO_OVERFLOW */
3911		if (val & 0x18000) {
3912			PMD_DRV_LOG(ERR, "FATAL error from PXP");
3913		}
3914
3915		if (!CHIP_IS_E1x(sc)) {
3916			val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3917			PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3918		}
3919	}
3920#define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3921#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3922
3923	if (attn & AEU_PXP2_HW_INT_BIT) {
3924/*  CQ47854 workaround do not panic on
3925 *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3926 */
3927		if (!CHIP_IS_E1x(sc)) {
3928			mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3929			val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3930			mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3931			val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3932			/*
3933			 * If the olny PXP2_EOP_ERROR_BIT is set in
3934			 * STS0 and STS1 - clear it
3935			 *
3936			 * probably we lose additional attentions between
3937			 * STS0 and STS_CLR0, in this case user will not
3938			 * be notified about them
3939			 */
3940			if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3941			    !(val1 & mask1))
3942				val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3943
3944			/* print the register, since no one can restore it */
3945			PMD_DRV_LOG(ERR,
3946				    "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3947
3948			/*
3949			 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3950			 * then notify
3951			 */
3952			if (val0 & PXP2_EOP_ERROR_BIT) {
3953				PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3954
3955				/*
3956				 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3957				 * set then clear attention from PXP2 block without panic
3958				 */
3959				if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3960				    ((val1 & mask1) == 0))
3961					attn &= ~AEU_PXP2_HW_INT_BIT;
3962			}
3963		}
3964	}
3965
3966	if (attn & HW_INTERRUT_ASSERT_SET_2) {
3967		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3968			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3969
3970		val = REG_RD(sc, reg_offset);
3971		val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3972		REG_WR(sc, reg_offset, val);
3973
3974		PMD_DRV_LOG(ERR,
3975			    "FATAL HW block attention set2 0x%x",
3976			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3977		rte_panic("HW block attention set2");
3978	}
3979}
3980
3981static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3982{
3983	int port = SC_PORT(sc);
3984	int reg_offset;
3985	uint32_t val;
3986
3987	if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3988		val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3989		PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3990/* DORQ discard attention */
3991		if (val & 0x2) {
3992			PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3993		}
3994	}
3995
3996	if (attn & HW_INTERRUT_ASSERT_SET_1) {
3997		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3998			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3999
4000		val = REG_RD(sc, reg_offset);
4001		val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4002		REG_WR(sc, reg_offset, val);
4003
4004		PMD_DRV_LOG(ERR,
4005			    "FATAL HW block attention set1 0x%08x",
4006			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4007		rte_panic("HW block attention set1");
4008	}
4009}
4010
4011static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4012{
4013	int port = SC_PORT(sc);
4014	int reg_offset;
4015	uint32_t val;
4016
4017	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4018	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4019
4020	if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4021		val = REG_RD(sc, reg_offset);
4022		val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4023		REG_WR(sc, reg_offset, val);
4024
4025		PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4026
4027/* Fan failure attention */
4028		elink_hw_reset_phy(&sc->link_params);
4029		bnx2x_fan_failure(sc);
4030	}
4031
4032	if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4033		elink_handle_module_detect_int(&sc->link_params);
4034	}
4035
4036	if (attn & HW_INTERRUT_ASSERT_SET_0) {
4037		val = REG_RD(sc, reg_offset);
4038		val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4039		REG_WR(sc, reg_offset, val);
4040
4041		rte_panic("FATAL HW block attention set0 0x%lx",
4042			  (attn & HW_INTERRUT_ASSERT_SET_0));
4043	}
4044}
4045
4046static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4047{
4048	struct attn_route attn;
4049	struct attn_route *group_mask;
4050	int port = SC_PORT(sc);
4051	int index;
4052	uint32_t reg_addr;
4053	uint32_t val;
4054	uint32_t aeu_mask;
4055	uint8_t global = FALSE;
4056
4057	/*
4058	 * Need to take HW lock because MCP or other port might also
4059	 * try to handle this event.
4060	 */
4061	bnx2x_acquire_alr(sc);
4062
4063	if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4064		sc->recovery_state = BNX2X_RECOVERY_INIT;
4065
4066/* disable HW interrupts */
4067		bnx2x_int_disable(sc);
4068		bnx2x_release_alr(sc);
4069		return;
4070	}
4071
4072	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4073	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4074	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4075	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4076	if (!CHIP_IS_E1x(sc)) {
4077		attn.sig[4] =
4078		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4079	} else {
4080		attn.sig[4] = 0;
4081	}
4082
4083	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4084		if (deasserted & (1 << index)) {
4085			group_mask = &sc->attn_group[index];
4086
4087			bnx2x_attn_int_deasserted4(sc,
4088						 attn.
4089						 sig[4] & group_mask->sig[4]);
4090			bnx2x_attn_int_deasserted3(sc,
4091						 attn.
4092						 sig[3] & group_mask->sig[3]);
4093			bnx2x_attn_int_deasserted1(sc,
4094						 attn.
4095						 sig[1] & group_mask->sig[1]);
4096			bnx2x_attn_int_deasserted2(sc,
4097						 attn.
4098						 sig[2] & group_mask->sig[2]);
4099			bnx2x_attn_int_deasserted0(sc,
4100						 attn.
4101						 sig[0] & group_mask->sig[0]);
4102		}
4103	}
4104
4105	bnx2x_release_alr(sc);
4106
4107	if (sc->devinfo.int_block == INT_BLOCK_HC) {
4108		reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4109			    COMMAND_REG_ATTN_BITS_CLR);
4110	} else {
4111		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4112	}
4113
4114	val = ~deasserted;
4115	PMD_DRV_LOG(DEBUG,
4116		    "about to mask 0x%08x at %s addr 0x%08x", val,
4117		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4118		    reg_addr);
4119	REG_WR(sc, reg_addr, val);
4120
4121	if (~sc->attn_state & deasserted) {
4122		PMD_DRV_LOG(ERR, "IGU error");
4123	}
4124
4125	reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4126	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
4127
4128	bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4129
4130	aeu_mask = REG_RD(sc, reg_addr);
4131
4132	aeu_mask |= (deasserted & 0x3ff);
4133
4134	REG_WR(sc, reg_addr, aeu_mask);
4135	bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4136
4137	sc->attn_state &= ~deasserted;
4138}
4139
4140static void bnx2x_attn_int(struct bnx2x_softc *sc)
4141{
4142	/* read local copy of bits */
4143	uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4144	uint32_t attn_ack =
4145	    le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4146	uint32_t attn_state = sc->attn_state;
4147
4148	/* look for changed bits */
4149	uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4150	uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4151
4152	PMD_DRV_LOG(DEBUG,
4153		    "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4154		    attn_bits, attn_ack, asserted, deasserted);
4155
4156	if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4157		PMD_DRV_LOG(ERR, "BAD attention state");
4158	}
4159
4160	/* handle bits that were raised */
4161	if (asserted) {
4162		bnx2x_attn_int_asserted(sc, asserted);
4163	}
4164
4165	if (deasserted) {
4166		bnx2x_attn_int_deasserted(sc, deasserted);
4167	}
4168}
4169
4170static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4171{
4172	struct host_sp_status_block *def_sb = sc->def_sb;
4173	uint16_t rc = 0;
4174
4175	mb();			/* status block is written to by the chip */
4176
4177	if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4178		sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4179		rc |= BNX2X_DEF_SB_ATT_IDX;
4180	}
4181
4182	if (sc->def_idx != def_sb->sp_sb.running_index) {
4183		sc->def_idx = def_sb->sp_sb.running_index;
4184		rc |= BNX2X_DEF_SB_IDX;
4185	}
4186
4187	mb();
4188
4189	return rc;
4190}
4191
4192static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4193							  uint32_t cid)
4194{
4195	return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4196}
4197
4198static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4199{
4200	struct ecore_mcast_ramrod_params rparam;
4201	int rc;
4202
4203	memset(&rparam, 0, sizeof(rparam));
4204
4205	rparam.mcast_obj = &sc->mcast_obj;
4206
4207	/* clear pending state for the last command */
4208	sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4209
4210	/* if there are pending mcast commands - send them */
4211	if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4212		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4213		if (rc < 0) {
4214			PMD_DRV_LOG(INFO,
4215				    "Failed to send pending mcast commands (%d)",
4216				    rc);
4217		}
4218	}
4219}
4220
4221static void
4222bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4223{
4224	unsigned long ramrod_flags = 0;
4225	int rc = 0;
4226	uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4227	struct ecore_vlan_mac_obj *vlan_mac_obj;
4228
4229	/* always push next commands out, don't wait here */
4230	bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4231
4232	switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4233	case ECORE_FILTER_MAC_PENDING:
4234		PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4235		vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4236		break;
4237
4238	case ECORE_FILTER_MCAST_PENDING:
4239		PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4240		bnx2x_handle_mcast_eqe(sc);
4241		return;
4242
4243	default:
4244		PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4245			    elem->message.data.eth_event.echo);
4246		return;
4247	}
4248
4249	rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4250
4251	if (rc < 0) {
4252		PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4253	} else if (rc > 0) {
4254		PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4255	}
4256}
4257
4258static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4259{
4260	bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4261
4262	/* send rx_mode command again if was requested */
4263	if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4264		bnx2x_set_storm_rx_mode(sc);
4265	}
4266}
4267
4268static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4269{
4270	storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4271	wmb();			/* keep prod updates ordered */
4272}
4273
4274static void bnx2x_eq_int(struct bnx2x_softc *sc)
4275{
4276	uint16_t hw_cons, sw_cons, sw_prod;
4277	union event_ring_elem *elem;
4278	uint8_t echo;
4279	uint32_t cid;
4280	uint8_t opcode;
4281	int spqe_cnt = 0;
4282	struct ecore_queue_sp_obj *q_obj;
4283	struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4284	struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4285
4286	hw_cons = le16toh(*sc->eq_cons_sb);
4287
4288	/*
4289	 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4290	 * when we get to the next-page we need to adjust so the loop
4291	 * condition below will be met. The next element is the size of a
4292	 * regular element and hence incrementing by 1
4293	 */
4294	if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4295		hw_cons++;
4296	}
4297
4298	/*
4299	 * This function may never run in parallel with itself for a
4300	 * specific sc and no need for a read memory barrier here.
4301	 */
4302	sw_cons = sc->eq_cons;
4303	sw_prod = sc->eq_prod;
4304
4305	for (;
4306	     sw_cons != hw_cons;
4307	     sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4308
4309		elem = &sc->eq[EQ_DESC(sw_cons)];
4310
4311/* elem CID originates from FW, actually LE */
4312		cid = SW_CID(elem->message.data.cfc_del_event.cid);
4313		opcode = elem->message.opcode;
4314
4315/* handle eq element */
4316		switch (opcode) {
4317		case EVENT_RING_OPCODE_STAT_QUERY:
4318			PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4319				    sc->stats_comp++);
4320			/* nothing to do with stats comp */
4321			goto next_spqe;
4322
4323		case EVENT_RING_OPCODE_CFC_DEL:
4324			/* handle according to cid range */
4325			/* we may want to verify here that the sc state is HALTING */
4326			PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4327				    cid);
4328			q_obj = bnx2x_cid_to_q_obj(sc, cid);
4329			if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4330				break;
4331			}
4332			goto next_spqe;
4333
4334		case EVENT_RING_OPCODE_STOP_TRAFFIC:
4335			PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4336			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4337				break;
4338			}
4339			goto next_spqe;
4340
4341		case EVENT_RING_OPCODE_START_TRAFFIC:
4342			PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4343			if (f_obj->complete_cmd
4344			    (sc, f_obj, ECORE_F_CMD_TX_START)) {
4345				break;
4346			}
4347			goto next_spqe;
4348
4349		case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4350			echo = elem->message.data.function_update_event.echo;
4351			if (echo == SWITCH_UPDATE) {
4352				PMD_DRV_LOG(DEBUG,
4353					    "got FUNC_SWITCH_UPDATE ramrod");
4354				if (f_obj->complete_cmd(sc, f_obj,
4355							ECORE_F_CMD_SWITCH_UPDATE))
4356				{
4357					break;
4358				}
4359			} else {
4360				PMD_DRV_LOG(DEBUG,
4361					    "AFEX: ramrod completed FUNCTION_UPDATE");
4362				f_obj->complete_cmd(sc, f_obj,
4363						    ECORE_F_CMD_AFEX_UPDATE);
4364			}
4365			goto next_spqe;
4366
4367		case EVENT_RING_OPCODE_FORWARD_SETUP:
4368			q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4369			if (q_obj->complete_cmd(sc, q_obj,
4370						ECORE_Q_CMD_SETUP_TX_ONLY)) {
4371				break;
4372			}
4373			goto next_spqe;
4374
4375		case EVENT_RING_OPCODE_FUNCTION_START:
4376			PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4377			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4378				break;
4379			}
4380			goto next_spqe;
4381
4382		case EVENT_RING_OPCODE_FUNCTION_STOP:
4383			PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4384			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4385				break;
4386			}
4387			goto next_spqe;
4388		}
4389
4390		switch (opcode | sc->state) {
4391		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4392		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4393			cid =
4394			    elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4395			PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4396				    cid);
4397			rss_raw->clear_pending(rss_raw);
4398			break;
4399
4400		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4401		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4402		case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4403		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4404		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4405		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4406			PMD_DRV_LOG(DEBUG,
4407				    "got (un)set mac ramrod");
4408			bnx2x_handle_classification_eqe(sc, elem);
4409			break;
4410
4411		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4412		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4413		case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4414			PMD_DRV_LOG(DEBUG,
4415				    "got mcast ramrod");
4416			bnx2x_handle_mcast_eqe(sc);
4417			break;
4418
4419		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4420		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4421		case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4422			PMD_DRV_LOG(DEBUG,
4423				    "got rx_mode ramrod");
4424			bnx2x_handle_rx_mode_eqe(sc);
4425			break;
4426
4427		default:
4428			/* unknown event log error and continue */
4429			PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4430				    elem->message.opcode, sc->state);
4431		}
4432
4433next_spqe:
4434		spqe_cnt++;
4435	}			/* for */
4436
4437	mb();
4438	atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4439
4440	sc->eq_cons = sw_cons;
4441	sc->eq_prod = sw_prod;
4442
4443	/* make sure that above mem writes were issued towards the memory */
4444	wmb();
4445
4446	/* update producer */
4447	bnx2x_update_eq_prod(sc, sc->eq_prod);
4448}
4449
4450static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4451{
4452	uint16_t status;
4453	int rc = 0;
4454
4455	/* what work needs to be performed? */
4456	status = bnx2x_update_dsb_idx(sc);
4457
4458	/* HW attentions */
4459	if (status & BNX2X_DEF_SB_ATT_IDX) {
4460		PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4461		bnx2x_attn_int(sc);
4462		status &= ~BNX2X_DEF_SB_ATT_IDX;
4463		rc = 1;
4464	}
4465
4466	/* SP events: STAT_QUERY and others */
4467	if (status & BNX2X_DEF_SB_IDX) {
4468/* handle EQ completions */
4469		PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4470		bnx2x_eq_int(sc);
4471		bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4472			   le16toh(sc->def_idx), IGU_INT_NOP, 1);
4473		status &= ~BNX2X_DEF_SB_IDX;
4474	}
4475
4476	/* if status is non zero then something went wrong */
4477	if (unlikely(status)) {
4478		PMD_DRV_LOG(INFO,
4479			    "Got an unknown SP interrupt! (0x%04x)", status);
4480	}
4481
4482	/* ack status block only if something was actually handled */
4483	bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4484		   le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4485
4486	return rc;
4487}
4488
4489static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4490{
4491	struct bnx2x_softc *sc = fp->sc;
4492	uint8_t more_rx = FALSE;
4493
4494	/* update the fastpath index */
4495	bnx2x_update_fp_sb_idx(fp);
4496
4497	if (scan_fp) {
4498		if (bnx2x_has_rx_work(fp)) {
4499			more_rx = bnx2x_rxeof(sc, fp);
4500		}
4501
4502		if (more_rx) {
4503			/* still more work to do */
4504			bnx2x_handle_fp_tq(fp, scan_fp);
4505			return;
4506		}
4507	}
4508
4509	bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4510		   le16toh(fp->fp_hc_idx), IGU_INT_DISABLE, 1);
4511}
4512
4513/*
4514 * Legacy interrupt entry point.
4515 *
4516 * Verifies that the controller generated the interrupt and
4517 * then calls a separate routine to handle the various
4518 * interrupt causes: link, RX, and TX.
4519 */
4520int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4521{
4522	struct bnx2x_fastpath *fp;
4523	uint32_t status, mask;
4524	int i, rc = 0;
4525
4526	/*
4527	 * 0 for ustorm, 1 for cstorm
4528	 * the bits returned from ack_int() are 0-15
4529	 * bit 0 = attention status block
4530	 * bit 1 = fast path status block
4531	 * a mask of 0x2 or more = tx/rx event
4532	 * a mask of 1 = slow path event
4533	 */
4534
4535	status = bnx2x_ack_int(sc);
4536
4537	/* the interrupt is not for us */
4538	if (unlikely(status == 0)) {
4539		return 0;
4540	}
4541
4542	PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4543	//bnx2x_dump_status_block(sc);
4544
4545	FOR_EACH_ETH_QUEUE(sc, i) {
4546		fp = &sc->fp[i];
4547		mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4548		if (status & mask) {
4549			bnx2x_handle_fp_tq(fp, scan_fp);
4550			status &= ~mask;
4551		}
4552	}
4553
4554	if (unlikely(status & 0x1)) {
4555		rc = bnx2x_handle_sp_tq(sc);
4556		status &= ~0x1;
4557	}
4558
4559	if (unlikely(status)) {
4560		PMD_DRV_LOG(WARNING,
4561			    "Unexpected fastpath status (0x%08x)!", status);
4562	}
4563
4564	return rc;
4565}
4566
4567static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4568static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4569static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4570static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4571static void bnx2x_reset_common(struct bnx2x_softc *sc);
4572static void bnx2x_reset_port(struct bnx2x_softc *sc);
4573static void bnx2x_reset_func(struct bnx2x_softc *sc);
4574static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4575static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4576
4577static struct
4578ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4579	.init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4580	.init_hw_cmn = bnx2x_init_hw_common,
4581	.init_hw_port = bnx2x_init_hw_port,
4582	.init_hw_func = bnx2x_init_hw_func,
4583
4584	.reset_hw_cmn = bnx2x_reset_common,
4585	.reset_hw_port = bnx2x_reset_port,
4586	.reset_hw_func = bnx2x_reset_func,
4587
4588	.init_fw = bnx2x_init_firmware,
4589	.release_fw = bnx2x_release_firmware,
4590};
4591
4592static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4593{
4594	sc->dmae_ready = 0;
4595
4596	PMD_INIT_FUNC_TRACE();
4597
4598	ecore_init_func_obj(sc,
4599			    &sc->func_obj,
4600			    BNX2X_SP(sc, func_rdata),
4601			    (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4602			    BNX2X_SP(sc, func_afex_rdata),
4603			    (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4604			    &bnx2x_func_sp_drv);
4605}
4606
4607static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4608{
4609	struct ecore_func_state_params func_params = { NULL };
4610	int rc;
4611
4612	PMD_INIT_FUNC_TRACE();
4613
4614	/* prepare the parameters for function state transitions */
4615	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4616
4617	func_params.f_obj = &sc->func_obj;
4618	func_params.cmd = ECORE_F_CMD_HW_INIT;
4619
4620	func_params.params.hw_init.load_phase = load_code;
4621
4622	/*
4623	 * Via a plethora of function pointers, we will eventually reach
4624	 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4625	 */
4626	rc = ecore_func_state_change(sc, &func_params);
4627
4628	return rc;
4629}
4630
4631static void
4632bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4633{
4634	uint32_t i;
4635
4636	if (!(len % 4) && !(addr % 4)) {
4637		for (i = 0; i < len; i += 4) {
4638			REG_WR(sc, (addr + i), fill);
4639		}
4640	} else {
4641		for (i = 0; i < len; i++) {
4642			REG_WR8(sc, (addr + i), fill);
4643		}
4644	}
4645}
4646
4647/* writes FP SP data to FW - data_size in dwords */
4648static void
4649bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4650		  uint32_t data_size)
4651{
4652	uint32_t index;
4653
4654	for (index = 0; index < data_size; index++) {
4655		REG_WR(sc,
4656		       (BAR_CSTRORM_INTMEM +
4657			CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4658			(sizeof(uint32_t) * index)), *(sb_data_p + index));
4659	}
4660}
4661
4662static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4663{
4664	struct hc_status_block_data_e2 sb_data_e2;
4665	struct hc_status_block_data_e1x sb_data_e1x;
4666	uint32_t *sb_data_p;
4667	uint32_t data_size = 0;
4668
4669	if (!CHIP_IS_E1x(sc)) {
4670		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4671		sb_data_e2.common.state = SB_DISABLED;
4672		sb_data_e2.common.p_func.vf_valid = FALSE;
4673		sb_data_p = (uint32_t *) & sb_data_e2;
4674		data_size = (sizeof(struct hc_status_block_data_e2) /
4675			     sizeof(uint32_t));
4676	} else {
4677		memset(&sb_data_e1x, 0,
4678		       sizeof(struct hc_status_block_data_e1x));
4679		sb_data_e1x.common.state = SB_DISABLED;
4680		sb_data_e1x.common.p_func.vf_valid = FALSE;
4681		sb_data_p = (uint32_t *) & sb_data_e1x;
4682		data_size = (sizeof(struct hc_status_block_data_e1x) /
4683			     sizeof(uint32_t));
4684	}
4685
4686	bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4687
4688	bnx2x_fill(sc,
4689		 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4690		 CSTORM_STATUS_BLOCK_SIZE);
4691	bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4692		 0, CSTORM_SYNC_BLOCK_SIZE);
4693}
4694
4695static void
4696bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4697		  struct hc_sp_status_block_data *sp_sb_data)
4698{
4699	uint32_t i;
4700
4701	for (i = 0;
4702	     i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4703	     i++) {
4704		REG_WR(sc,
4705		       (BAR_CSTRORM_INTMEM +
4706			CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4707			(i * sizeof(uint32_t))),
4708		       *((uint32_t *) sp_sb_data + i));
4709	}
4710}
4711
4712static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4713{
4714	struct hc_sp_status_block_data sp_sb_data;
4715
4716	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4717
4718	sp_sb_data.state = SB_DISABLED;
4719	sp_sb_data.p_func.vf_valid = FALSE;
4720
4721	bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4722
4723	bnx2x_fill(sc,
4724		 (BAR_CSTRORM_INTMEM +
4725		  CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4726		 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4727	bnx2x_fill(sc,
4728		 (BAR_CSTRORM_INTMEM +
4729		  CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4730		 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4731}
4732
4733static void
4734bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4735			     int igu_seg_id)
4736{
4737	hc_sm->igu_sb_id = igu_sb_id;
4738	hc_sm->igu_seg_id = igu_seg_id;
4739	hc_sm->timer_value = 0xFF;
4740	hc_sm->time_to_expire = 0xFFFFFFFF;
4741}
4742
4743static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4744{
4745	/* zero out state machine indices */
4746
4747	/* rx indices */
4748	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4749
4750	/* tx indices */
4751	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4752	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4753	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4754	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4755
4756	/* map indices */
4757
4758	/* rx indices */
4759	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4760	    (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4761
4762	/* tx indices */
4763	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4764	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4765	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4766	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4767	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4768	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4769	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4770	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4771}
4772
4773static void
4774bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4775	    uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4776{
4777	struct hc_status_block_data_e2 sb_data_e2;
4778	struct hc_status_block_data_e1x sb_data_e1x;
4779	struct hc_status_block_sm *hc_sm_p;
4780	uint32_t *sb_data_p;
4781	int igu_seg_id;
4782	int data_size;
4783
4784	if (CHIP_INT_MODE_IS_BC(sc)) {
4785		igu_seg_id = HC_SEG_ACCESS_NORM;
4786	} else {
4787		igu_seg_id = IGU_SEG_ACCESS_NORM;
4788	}
4789
4790	bnx2x_zero_fp_sb(sc, fw_sb_id);
4791
4792	if (!CHIP_IS_E1x(sc)) {
4793		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4794		sb_data_e2.common.state = SB_ENABLED;
4795		sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4796		sb_data_e2.common.p_func.vf_id = vfid;
4797		sb_data_e2.common.p_func.vf_valid = vf_valid;
4798		sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4799		sb_data_e2.common.same_igu_sb_1b = TRUE;
4800		sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4801		sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4802		hc_sm_p = sb_data_e2.common.state_machine;
4803		sb_data_p = (uint32_t *) & sb_data_e2;
4804		data_size = (sizeof(struct hc_status_block_data_e2) /
4805			     sizeof(uint32_t));
4806		bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4807	} else {
4808		memset(&sb_data_e1x, 0,
4809		       sizeof(struct hc_status_block_data_e1x));
4810		sb_data_e1x.common.state = SB_ENABLED;
4811		sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4812		sb_data_e1x.common.p_func.vf_id = 0xff;
4813		sb_data_e1x.common.p_func.vf_valid = FALSE;
4814		sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4815		sb_data_e1x.common.same_igu_sb_1b = TRUE;
4816		sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4817		sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4818		hc_sm_p = sb_data_e1x.common.state_machine;
4819		sb_data_p = (uint32_t *) & sb_data_e1x;
4820		data_size = (sizeof(struct hc_status_block_data_e1x) /
4821			     sizeof(uint32_t));
4822		bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4823	}
4824
4825	bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4826	bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4827
4828	/* write indices to HW - PCI guarantees endianity of regpairs */
4829	bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4830}
4831
4832static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4833{
4834	if (CHIP_IS_E1x(fp->sc)) {
4835		return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4836	} else {
4837		return fp->cl_id;
4838	}
4839}
4840
4841static uint32_t
4842bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4843{
4844	uint32_t offset = BAR_USTRORM_INTMEM;
4845
4846	if (IS_VF(sc)) {
4847		return PXP_VF_ADDR_USDM_QUEUES_START +
4848			(sc->acquire_resp.resc.hw_qid[fp->index] *
4849			 sizeof(struct ustorm_queue_zone_data));
4850	} else if (!CHIP_IS_E1x(sc)) {
4851		offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4852	} else {
4853		offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4854	}
4855
4856	return offset;
4857}
4858
4859static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4860{
4861	struct bnx2x_fastpath *fp = &sc->fp[idx];
4862	uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4863	unsigned long q_type = 0;
4864	int cos;
4865
4866	fp->sc = sc;
4867	fp->index = idx;
4868
4869	fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4870	fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4871
4872	if (CHIP_IS_E1x(sc))
4873		fp->cl_id = SC_L_ID(sc) + idx;
4874	else
4875/* want client ID same as IGU SB ID for non-E1 */
4876		fp->cl_id = fp->igu_sb_id;
4877	fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4878
4879	/* setup sb indices */
4880	if (!CHIP_IS_E1x(sc)) {
4881		fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4882		fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4883	} else {
4884		fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4885		fp->sb_running_index =
4886		    fp->status_block.e1x_sb->sb.running_index;
4887	}
4888
4889	/* init shortcut */
4890	fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4891
4892	fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4893
4894	for (cos = 0; cos < sc->max_cos; cos++) {
4895		cids[cos] = idx;
4896	}
4897	fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4898
4899	/* nothing more for a VF to do */
4900	if (IS_VF(sc)) {
4901		return;
4902	}
4903
4904	bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4905		    fp->fw_sb_id, fp->igu_sb_id);
4906
4907	bnx2x_update_fp_sb_idx(fp);
4908
4909	/* Configure Queue State object */
4910	bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4911	bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4912
4913	ecore_init_queue_obj(sc,
4914			     &sc->sp_objs[idx].q_obj,
4915			     fp->cl_id,
4916			     cids,
4917			     sc->max_cos,
4918			     SC_FUNC(sc),
4919			     BNX2X_SP(sc, q_rdata),
4920			     (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4921			     q_type);
4922
4923	/* configure classification DBs */
4924	ecore_init_mac_obj(sc,
4925			   &sc->sp_objs[idx].mac_obj,
4926			   fp->cl_id,
4927			   idx,
4928			   SC_FUNC(sc),
4929			   BNX2X_SP(sc, mac_rdata),
4930			   (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4931			   ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4932			   ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4933}
4934
4935static void
4936bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4937		   uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4938{
4939	union ustorm_eth_rx_producers rx_prods;
4940	uint32_t i;
4941
4942	/* update producers */
4943	rx_prods.prod.bd_prod = rx_bd_prod;
4944	rx_prods.prod.cqe_prod = rx_cq_prod;
4945	rx_prods.prod.reserved = 0;
4946
4947	/*
4948	 * Make sure that the BD and SGE data is updated before updating the
4949	 * producers since FW might read the BD/SGE right after the producer
4950	 * is updated.
4951	 * This is only applicable for weak-ordered memory model archs such
4952	 * as IA-64. The following barrier is also mandatory since FW will
4953	 * assumes BDs must have buffers.
4954	 */
4955	wmb();
4956
4957	for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4958		REG_WR(sc,
4959		       (fp->ustorm_rx_prods_offset + (i * 4)),
4960		       rx_prods.raw_data[i]);
4961	}
4962
4963	wmb();			/* keep prod updates ordered */
4964}
4965
4966static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4967{
4968	struct bnx2x_fastpath *fp;
4969	int i;
4970	struct bnx2x_rx_queue *rxq;
4971
4972	for (i = 0; i < sc->num_queues; i++) {
4973		fp = &sc->fp[i];
4974		rxq = sc->rx_queues[fp->index];
4975		if (!rxq) {
4976			PMD_RX_LOG(ERR, "RX queue is NULL");
4977			return;
4978		}
4979
4980		rxq->rx_bd_head = 0;
4981		rxq->rx_bd_tail = rxq->nb_rx_desc;
4982		rxq->rx_cq_head = 0;
4983		rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4984		*fp->rx_cq_cons_sb = 0;
4985
4986		/*
4987		 * Activate the BD ring...
4988		 * Warning, this will generate an interrupt (to the TSTORM)
4989		 * so this can only be done after the chip is initialized
4990		 */
4991		bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4992
4993		if (i != 0) {
4994			continue;
4995		}
4996	}
4997}
4998
4999static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5000{
5001	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5002
5003	fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5004	fp->tx_db.data.zero_fill1 = 0;
5005	fp->tx_db.data.prod = 0;
5006
5007	if (!txq) {
5008		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5009		return;
5010	}
5011
5012	txq->tx_pkt_tail = 0;
5013	txq->tx_pkt_head = 0;
5014	txq->tx_bd_tail = 0;
5015	txq->tx_bd_head = 0;
5016}
5017
5018static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5019{
5020	int i;
5021
5022	for (i = 0; i < sc->num_queues; i++) {
5023		bnx2x_init_tx_ring_one(&sc->fp[i]);
5024	}
5025}
5026
5027static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5028{
5029	struct host_sp_status_block *def_sb = sc->def_sb;
5030	phys_addr_t mapping = sc->def_sb_dma.paddr;
5031	int igu_sp_sb_index;
5032	int igu_seg_id;
5033	int port = SC_PORT(sc);
5034	int func = SC_FUNC(sc);
5035	int reg_offset, reg_offset_en5;
5036	uint64_t section;
5037	int index, sindex;
5038	struct hc_sp_status_block_data sp_sb_data;
5039
5040	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5041
5042	if (CHIP_INT_MODE_IS_BC(sc)) {
5043		igu_sp_sb_index = DEF_SB_IGU_ID;
5044		igu_seg_id = HC_SEG_ACCESS_DEF;
5045	} else {
5046		igu_sp_sb_index = sc->igu_dsb_id;
5047		igu_seg_id = IGU_SEG_ACCESS_DEF;
5048	}
5049
5050	/* attentions */
5051	section = ((uint64_t) mapping +
5052		   offsetof(struct host_sp_status_block, atten_status_block));
5053	def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5054	sc->attn_state = 0;
5055
5056	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5057	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5058
5059	reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5060	    MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5061
5062	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5063/* take care of sig[0]..sig[4] */
5064		for (sindex = 0; sindex < 4; sindex++) {
5065			sc->attn_group[index].sig[sindex] =
5066			    REG_RD(sc,
5067				   (reg_offset + (sindex * 0x4) +
5068				    (0x10 * index)));
5069		}
5070
5071		if (!CHIP_IS_E1x(sc)) {
5072			/*
5073			 * enable5 is separate from the rest of the registers,
5074			 * and the address skip is 4 and not 16 between the
5075			 * different groups
5076			 */
5077			sc->attn_group[index].sig[4] =
5078			    REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5079		} else {
5080			sc->attn_group[index].sig[4] = 0;
5081		}
5082	}
5083
5084	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5085		reg_offset =
5086		    port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5087		REG_WR(sc, reg_offset, U64_LO(section));
5088		REG_WR(sc, (reg_offset + 4), U64_HI(section));
5089	} else if (!CHIP_IS_E1x(sc)) {
5090		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5091		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5092	}
5093
5094	section = ((uint64_t) mapping +
5095		   offsetof(struct host_sp_status_block, sp_sb));
5096
5097	bnx2x_zero_sp_sb(sc);
5098
5099	/* PCI guarantees endianity of regpair */
5100	sp_sb_data.state = SB_ENABLED;
5101	sp_sb_data.host_sb_addr.lo = U64_LO(section);
5102	sp_sb_data.host_sb_addr.hi = U64_HI(section);
5103	sp_sb_data.igu_sb_id = igu_sp_sb_index;
5104	sp_sb_data.igu_seg_id = igu_seg_id;
5105	sp_sb_data.p_func.pf_id = func;
5106	sp_sb_data.p_func.vnic_id = SC_VN(sc);
5107	sp_sb_data.p_func.vf_id = 0xff;
5108
5109	bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5110
5111	bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5112}
5113
5114static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5115{
5116	atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5117	sc->spq_prod_idx = 0;
5118	sc->dsb_sp_prod =
5119	    &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5120	sc->spq_prod_bd = sc->spq;
5121	sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5122}
5123
5124static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5125{
5126	union event_ring_elem *elem;
5127	int i;
5128
5129	for (i = 1; i <= NUM_EQ_PAGES; i++) {
5130		elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5131
5132		elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5133							 BNX2X_PAGE_SIZE *
5134							 (i % NUM_EQ_PAGES)));
5135		elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5136							 BNX2X_PAGE_SIZE *
5137							 (i % NUM_EQ_PAGES)));
5138	}
5139
5140	sc->eq_cons = 0;
5141	sc->eq_prod = NUM_EQ_DESC;
5142	sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5143
5144	atomic_store_rel_long(&sc->eq_spq_left,
5145			      (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5146				   NUM_EQ_DESC) - 1));
5147}
5148
5149static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5150{
5151	int i;
5152
5153	if (IS_MF_SI(sc)) {
5154/*
5155 * In switch independent mode, the TSTORM needs to accept
5156 * packets that failed classification, since approximate match
5157 * mac addresses aren't written to NIG LLH.
5158 */
5159		REG_WR8(sc,
5160			(BAR_TSTRORM_INTMEM +
5161			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5162	} else
5163		REG_WR8(sc,
5164			(BAR_TSTRORM_INTMEM +
5165			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5166
5167	/*
5168	 * Zero this manually as its initialization is currently missing
5169	 * in the initTool.
5170	 */
5171	for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5172		REG_WR(sc,
5173		       (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5174		       0);
5175	}
5176
5177	if (!CHIP_IS_E1x(sc)) {
5178		REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5179			CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5180			HC_IGU_NBC_MODE);
5181	}
5182}
5183
5184static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5185{
5186	switch (load_code) {
5187	case FW_MSG_CODE_DRV_LOAD_COMMON:
5188	case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5189		bnx2x_init_internal_common(sc);
5190		/* no break */
5191
5192	case FW_MSG_CODE_DRV_LOAD_PORT:
5193		/* nothing to do */
5194		/* no break */
5195
5196	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5197		/* internal memory per function is initialized inside bnx2x_pf_init */
5198		break;
5199
5200	default:
5201		PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5202			    load_code);
5203		break;
5204	}
5205}
5206
5207static void
5208storm_memset_func_cfg(struct bnx2x_softc *sc,
5209		      struct tstorm_eth_function_common_config *tcfg,
5210		      uint16_t abs_fid)
5211{
5212	uint32_t addr;
5213	size_t size;
5214
5215	addr = (BAR_TSTRORM_INTMEM +
5216		TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5217	size = sizeof(struct tstorm_eth_function_common_config);
5218	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5219}
5220
5221static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5222{
5223	struct tstorm_eth_function_common_config tcfg = { 0 };
5224
5225	if (CHIP_IS_E1x(sc)) {
5226		storm_memset_func_cfg(sc, &tcfg, p->func_id);
5227	}
5228
5229	/* Enable the function in the FW */
5230	storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5231	storm_memset_func_en(sc, p->func_id, 1);
5232
5233	/* spq */
5234	if (p->func_flgs & FUNC_FLG_SPQ) {
5235		storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5236		REG_WR(sc,
5237		       (XSEM_REG_FAST_MEMORY +
5238			XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5239	}
5240}
5241
5242/*
5243 * Calculates the sum of vn_min_rates.
5244 * It's needed for further normalizing of the min_rates.
5245 * Returns:
5246 *   sum of vn_min_rates.
5247 *     or
5248 *   0 - if all the min_rates are 0.
5249 * In the later case fainess algorithm should be deactivated.
5250 * If all min rates are not zero then those that are zeroes will be set to 1.
5251 */
5252static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5253{
5254	uint32_t vn_cfg;
5255	uint32_t vn_min_rate;
5256	int all_zero = 1;
5257	int vn;
5258
5259	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5260		vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5261		vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5262				FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5263
5264		if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5265			/* skip hidden VNs */
5266			vn_min_rate = 0;
5267		} else if (!vn_min_rate) {
5268			/* If min rate is zero - set it to 100 */
5269			vn_min_rate = DEF_MIN_RATE;
5270		} else {
5271			all_zero = 0;
5272		}
5273
5274		input->vnic_min_rate[vn] = vn_min_rate;
5275	}
5276
5277	/* if ETS or all min rates are zeros - disable fairness */
5278	if (all_zero) {
5279		input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5280	} else {
5281		input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5282	}
5283}
5284
5285static uint16_t
5286bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5287{
5288	uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5289			    FUNC_MF_CFG_MAX_BW_SHIFT);
5290
5291	if (!max_cfg) {
5292		PMD_DRV_LOG(DEBUG,
5293			    "Max BW configured to 0 - using 100 instead");
5294		max_cfg = 100;
5295	}
5296
5297	return max_cfg;
5298}
5299
5300static void
5301bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5302{
5303	uint16_t vn_max_rate;
5304	uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5305	uint32_t max_cfg;
5306
5307	if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5308		vn_max_rate = 0;
5309	} else {
5310		max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5311
5312		if (IS_MF_SI(sc)) {
5313			/* max_cfg in percents of linkspeed */
5314			vn_max_rate =
5315			    ((sc->link_vars.line_speed * max_cfg) / 100);
5316		} else {	/* SD modes */
5317			/* max_cfg is absolute in 100Mb units */
5318			vn_max_rate = (max_cfg * 100);
5319		}
5320	}
5321
5322	input->vnic_max_rate[vn] = vn_max_rate;
5323}
5324
5325static void
5326bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5327{
5328	struct cmng_init_input input;
5329	int vn;
5330
5331	memset(&input, 0, sizeof(struct cmng_init_input));
5332
5333	input.port_rate = sc->link_vars.line_speed;
5334
5335	if (cmng_type == CMNG_FNS_MINMAX) {
5336/* read mf conf from shmem */
5337		if (read_cfg) {
5338			bnx2x_read_mf_cfg(sc);
5339		}
5340
5341/* get VN min rate and enable fairness if not 0 */
5342		bnx2x_calc_vn_min(sc, &input);
5343
5344/* get VN max rate */
5345		if (sc->port.pmf) {
5346			for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5347				bnx2x_calc_vn_max(sc, vn, &input);
5348			}
5349		}
5350
5351/* always enable rate shaping and fairness */
5352		input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5353
5354		ecore_init_cmng(&input, &sc->cmng);
5355		return;
5356	}
5357}
5358
5359static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5360{
5361	if (CHIP_REV_IS_SLOW(sc)) {
5362		return CMNG_FNS_NONE;
5363	}
5364
5365	if (IS_MF(sc)) {
5366		return CMNG_FNS_MINMAX;
5367	}
5368
5369	return CMNG_FNS_NONE;
5370}
5371
5372static void
5373storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5374{
5375	int vn;
5376	int func;
5377	uint32_t addr;
5378	size_t size;
5379
5380	addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5381	size = sizeof(struct cmng_struct_per_port);
5382	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5383
5384	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5385		func = func_by_vn(sc, vn);
5386
5387		addr = (BAR_XSTRORM_INTMEM +
5388			XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5389		size = sizeof(struct rate_shaping_vars_per_vn);
5390		ecore_storm_memset_struct(sc, addr, size,
5391					  (uint32_t *) & cmng->
5392					  vnic.vnic_max_rate[vn]);
5393
5394		addr = (BAR_XSTRORM_INTMEM +
5395			XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5396		size = sizeof(struct fairness_vars_per_vn);
5397		ecore_storm_memset_struct(sc, addr, size,
5398					  (uint32_t *) & cmng->
5399					  vnic.vnic_min_rate[vn]);
5400	}
5401}
5402
5403static void bnx2x_pf_init(struct bnx2x_softc *sc)
5404{
5405	struct bnx2x_func_init_params func_init;
5406	struct event_ring_data eq_data;
5407	uint16_t flags;
5408
5409	memset(&eq_data, 0, sizeof(struct event_ring_data));
5410	memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5411
5412	if (!CHIP_IS_E1x(sc)) {
5413/* reset IGU PF statistics: MSIX + ATTN */
5414/* PF */
5415		REG_WR(sc,
5416		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5417			(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5418			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5419			 4)), 0);
5420/* ATTN */
5421		REG_WR(sc,
5422		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5423			(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5424			(BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5425			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5426			 4)), 0);
5427	}
5428
5429	/* function setup flags */
5430	flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5431
5432	func_init.func_flgs = flags;
5433	func_init.pf_id = SC_FUNC(sc);
5434	func_init.func_id = SC_FUNC(sc);
5435	func_init.spq_map = sc->spq_dma.paddr;
5436	func_init.spq_prod = sc->spq_prod_idx;
5437
5438	bnx2x_func_init(sc, &func_init);
5439
5440	memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5441
5442	/*
5443	 * Congestion management values depend on the link rate.
5444	 * There is no active link so initial link rate is set to 10Gbps.
5445	 * When the link comes up the congestion management values are
5446	 * re-calculated according to the actual link rate.
5447	 */
5448	sc->link_vars.line_speed = SPEED_10000;
5449	bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5450
5451	/* Only the PMF sets the HW */
5452	if (sc->port.pmf) {
5453		storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5454	}
5455
5456	/* init Event Queue - PCI bus guarantees correct endainity */
5457	eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5458	eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5459	eq_data.producer = sc->eq_prod;
5460	eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5461	eq_data.sb_id = DEF_SB_ID;
5462	storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5463}
5464
5465static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5466{
5467	int port = SC_PORT(sc);
5468	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5469	uint32_t val = REG_RD(sc, addr);
5470	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5471	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5472	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5474
5475	if (msix) {
5476		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5477			 HC_CONFIG_0_REG_INT_LINE_EN_0);
5478		val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5479			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5480		if (single_msix) {
5481			val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5482		}
5483	} else if (msi) {
5484		val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5485		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5486			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5487			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5488	} else {
5489		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5490			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5491			HC_CONFIG_0_REG_INT_LINE_EN_0 |
5492			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5493
5494		REG_WR(sc, addr, val);
5495
5496		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5497	}
5498
5499	REG_WR(sc, addr, val);
5500
5501	/* ensure that HC_CONFIG is written before leading/trailing edge config */
5502	mb();
5503
5504	/* init leading/trailing edge */
5505	if (IS_MF(sc)) {
5506		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5507		if (sc->port.pmf) {
5508			/* enable nig and gpio3 attention */
5509			val |= 0x1100;
5510		}
5511	} else {
5512		val = 0xffff;
5513	}
5514
5515	REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5516	REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5517
5518	/* make sure that interrupts are indeed enabled from here on */
5519	mb();
5520}
5521
5522static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5523{
5524	uint32_t val;
5525	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5526	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5527	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5529
5530	val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5531
5532	if (msix) {
5533		val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5534		val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5535		if (single_msix) {
5536			val |= IGU_PF_CONF_SINGLE_ISR_EN;
5537		}
5538	} else if (msi) {
5539		val &= ~IGU_PF_CONF_INT_LINE_EN;
5540		val |= (IGU_PF_CONF_MSI_MSIX_EN |
5541			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5542	} else {
5543		val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5544		val |= (IGU_PF_CONF_INT_LINE_EN |
5545			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5546	}
5547
5548	/* clean previous status - need to configure igu prior to ack */
5549	if ((!msix) || single_msix) {
5550		REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5551		bnx2x_ack_int(sc);
5552	}
5553
5554	val |= IGU_PF_CONF_FUNC_EN;
5555
5556	PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5557		    val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5558
5559	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5560
5561	mb();
5562
5563	/* init leading/trailing edge */
5564	if (IS_MF(sc)) {
5565		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5566		if (sc->port.pmf) {
5567			/* enable nig and gpio3 attention */
5568			val |= 0x1100;
5569		}
5570	} else {
5571		val = 0xffff;
5572	}
5573
5574	REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5575	REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5576
5577	/* make sure that interrupts are indeed enabled from here on */
5578	mb();
5579}
5580
5581static void bnx2x_int_enable(struct bnx2x_softc *sc)
5582{
5583	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5584		bnx2x_hc_int_enable(sc);
5585	} else {
5586		bnx2x_igu_int_enable(sc);
5587	}
5588}
5589
5590static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5591{
5592	int port = SC_PORT(sc);
5593	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5594	uint32_t val = REG_RD(sc, addr);
5595
5596	val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5597		 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5598		 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5599	/* flush all outstanding writes */
5600	mb();
5601
5602	REG_WR(sc, addr, val);
5603	if (REG_RD(sc, addr) != val) {
5604		PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5605	}
5606}
5607
5608static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5609{
5610	uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5611
5612	val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5613		 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5614
5615	PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5616
5617	/* flush all outstanding writes */
5618	mb();
5619
5620	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5621	if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5622		PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5623	}
5624}
5625
5626static void bnx2x_int_disable(struct bnx2x_softc *sc)
5627{
5628	if (sc->devinfo.int_block == INT_BLOCK_HC) {
5629		bnx2x_hc_int_disable(sc);
5630	} else {
5631		bnx2x_igu_int_disable(sc);
5632	}
5633}
5634
5635static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5636{
5637	int i;
5638
5639	PMD_INIT_FUNC_TRACE();
5640
5641	for (i = 0; i < sc->num_queues; i++) {
5642		bnx2x_init_eth_fp(sc, i);
5643	}
5644
5645	rmb();			/* ensure status block indices were read */
5646
5647	bnx2x_init_rx_rings(sc);
5648	bnx2x_init_tx_rings(sc);
5649
5650	if (IS_VF(sc)) {
5651		bnx2x_memset_stats(sc);
5652		return;
5653	}
5654
5655	/* initialize MOD_ABS interrupts */
5656	elink_init_mod_abs_int(sc, &sc->link_vars,
5657			       sc->devinfo.chip_id,
5658			       sc->devinfo.shmem_base,
5659			       sc->devinfo.shmem2_base, SC_PORT(sc));
5660
5661	bnx2x_init_def_sb(sc);
5662	bnx2x_update_dsb_idx(sc);
5663	bnx2x_init_sp_ring(sc);
5664	bnx2x_init_eq_ring(sc);
5665	bnx2x_init_internal(sc, load_code);
5666	bnx2x_pf_init(sc);
5667	bnx2x_stats_init(sc);
5668
5669	/* flush all before enabling interrupts */
5670	mb();
5671
5672	bnx2x_int_enable(sc);
5673
5674	/* check for SPIO5 */
5675	bnx2x_attn_int_deasserted0(sc,
5676				 REG_RD(sc,
5677					(MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5678					 SC_PORT(sc) * 4)) &
5679				 AEU_INPUTS_ATTN_BITS_SPIO5);
5680}
5681
5682static void bnx2x_init_objs(struct bnx2x_softc *sc)
5683{
5684	/* mcast rules must be added to tx if tx switching is enabled */
5685	ecore_obj_type o_type;
5686	if (sc->flags & BNX2X_TX_SWITCHING)
5687		o_type = ECORE_OBJ_TYPE_RX_TX;
5688	else
5689		o_type = ECORE_OBJ_TYPE_RX;
5690
5691	/* RX_MODE controlling object */
5692	ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5693
5694	/* multicast configuration controlling object */
5695	ecore_init_mcast_obj(sc,
5696			     &sc->mcast_obj,
5697			     sc->fp[0].cl_id,
5698			     sc->fp[0].index,
5699			     SC_FUNC(sc),
5700			     SC_FUNC(sc),
5701			     BNX2X_SP(sc, mcast_rdata),
5702			     (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5703			     ECORE_FILTER_MCAST_PENDING,
5704			     &sc->sp_state, o_type);
5705
5706	/* Setup CAM credit pools */
5707	ecore_init_mac_credit_pool(sc,
5708				   &sc->macs_pool,
5709				   SC_FUNC(sc),
5710				   CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5711				   VNICS_PER_PATH(sc));
5712
5713	ecore_init_vlan_credit_pool(sc,
5714				    &sc->vlans_pool,
5715				    SC_ABS_FUNC(sc) >> 1,
5716				    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5717				    VNICS_PER_PATH(sc));
5718
5719	/* RSS configuration object */
5720	ecore_init_rss_config_obj(&sc->rss_conf_obj,
5721				  sc->fp[0].cl_id,
5722				  sc->fp[0].index,
5723				  SC_FUNC(sc),
5724				  SC_FUNC(sc),
5725				  BNX2X_SP(sc, rss_rdata),
5726				  (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5727				  ECORE_FILTER_RSS_CONF_PENDING,
5728				  &sc->sp_state, ECORE_OBJ_TYPE_RX);
5729}
5730
5731/*
5732 * Initialize the function. This must be called before sending CLIENT_SETUP
5733 * for the first client.
5734 */
5735static int bnx2x_func_start(struct bnx2x_softc *sc)
5736{
5737	struct ecore_func_state_params func_params = { NULL };
5738	struct ecore_func_start_params *start_params =
5739	    &func_params.params.start;
5740
5741	/* Prepare parameters for function state transitions */
5742	bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5743
5744	func_params.f_obj = &sc->func_obj;
5745	func_params.cmd = ECORE_F_CMD_START;
5746
5747	/* Function parameters */
5748	start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5749	start_params->sd_vlan_tag = OVLAN(sc);
5750
5751	if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5752		start_params->network_cos_mode = STATIC_COS;
5753	} else {		/* CHIP_IS_E1X */
5754		start_params->network_cos_mode = FW_WRR;
5755	}
5756
5757	start_params->gre_tunnel_mode = 0;
5758	start_params->gre_tunnel_rss = 0;
5759
5760	return ecore_func_state_change(sc, &func_params);
5761}
5762
5763static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5764{
5765	uint16_t pmcsr;
5766
5767	/* If there is no power capability, silently succeed */
5768	if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5769		PMD_DRV_LOG(WARNING, "No power capability");
5770		return 0;
5771	}
5772
5773	pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5774		 2);
5775
5776	switch (state) {
5777	case PCI_PM_D0:
5778		pci_write_word(sc,
5779			       (sc->devinfo.pcie_pm_cap_reg +
5780				PCIR_POWER_STATUS),
5781			       ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5782
5783		if (pmcsr & PCIM_PSTAT_DMASK) {
5784			/* delay required during transition out of D3hot */
5785			DELAY(20000);
5786		}
5787
5788		break;
5789
5790	case PCI_PM_D3hot:
5791		/* don't shut down the power for emulation and FPGA */
5792		if (CHIP_REV_IS_SLOW(sc)) {
5793			return 0;
5794		}
5795
5796		pmcsr &= ~PCIM_PSTAT_DMASK;
5797		pmcsr |= PCIM_PSTAT_D3;
5798
5799		if (sc->wol) {
5800			pmcsr |= PCIM_PSTAT_PMEENABLE;
5801		}
5802
5803		pci_write_long(sc,
5804			       (sc->devinfo.pcie_pm_cap_reg +
5805				PCIR_POWER_STATUS), pmcsr);
5806
5807		/*
5808		 * No more memory access after this point until device is brought back
5809		 * to D0 state.
5810		 */
5811		break;
5812
5813	default:
5814		PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5815			    state);
5816		return -1;
5817	}
5818
5819	return 0;
5820}
5821
5822/* return true if succeeded to acquire the lock */
5823static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5824{
5825	uint32_t lock_status;
5826	uint32_t resource_bit = (1 << resource);
5827	int func = SC_FUNC(sc);
5828	uint32_t hw_lock_control_reg;
5829
5830	/* Validating that the resource is within range */
5831	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5832		PMD_DRV_LOG(INFO,
5833			    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5834			    resource, HW_LOCK_MAX_RESOURCE_VALUE);
5835		return FALSE;
5836	}
5837
5838	if (func <= 5) {
5839		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5840	} else {
5841		hw_lock_control_reg =
5842		    (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5843	}
5844
5845	/* try to acquire the lock */
5846	REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5847	lock_status = REG_RD(sc, hw_lock_control_reg);
5848	if (lock_status & resource_bit) {
5849		return TRUE;
5850	}
5851
5852	PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5853
5854	return FALSE;
5855}
5856
5857/*
5858 * Get the recovery leader resource id according to the engine this function
5859 * belongs to. Currently only only 2 engines is supported.
5860 */
5861static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5862{
5863	if (SC_PATH(sc)) {
5864		return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5865	} else {
5866		return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5867	}
5868}
5869
5870/* try to acquire a leader lock for current engine */
5871static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5872{
5873	return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5874}
5875
5876static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5877{
5878	return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5879}
5880
5881/* close gates #2, #3 and #4 */
5882static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5883{
5884	uint32_t val;
5885
5886	/* gates #2 and #4a are closed/opened */
5887	/* #4 */
5888	REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5889	/* #2 */
5890	REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5891
5892	/* #3 */
5893	if (CHIP_IS_E1x(sc)) {
5894/* prevent interrupts from HC on both ports */
5895		val = REG_RD(sc, HC_REG_CONFIG_1);
5896		if (close)
5897			REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5898						     HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5899		else
5900			REG_WR(sc, HC_REG_CONFIG_1,
5901			       (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5902
5903		val = REG_RD(sc, HC_REG_CONFIG_0);
5904		if (close)
5905			REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5906						     HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5907		else
5908			REG_WR(sc, HC_REG_CONFIG_0,
5909			       (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5910
5911	} else {
5912/* Prevent incomming interrupts in IGU */
5913		val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5914
5915		if (close)
5916			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5917			       (val & ~(uint32_t)
5918				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5919		else
5920			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5921			       (val |
5922				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5923	}
5924
5925	wmb();
5926}
5927
5928/* poll for pending writes bit, it should get cleared in no more than 1s */
5929static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5930{
5931	uint32_t cnt = 1000;
5932	uint32_t pend_bits = 0;
5933
5934	do {
5935		pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5936
5937		if (pend_bits == 0) {
5938			break;
5939		}
5940
5941		DELAY(1000);
5942	} while (cnt-- > 0);
5943
5944	if (cnt <= 0) {
5945		PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5946			    pend_bits);
5947		return -1;
5948	}
5949
5950	return 0;
5951}
5952
5953#define SHARED_MF_CLP_MAGIC  0x80000000	/* 'magic' bit */
5954
5955static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5956{
5957	/* Do some magic... */
5958	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5959	*magic_val = val & SHARED_MF_CLP_MAGIC;
5960	MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5961}
5962
5963/* restore the value of the 'magic' bit */
5964static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5965{
5966	/* Restore the 'magic' bit value... */
5967	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5968	MFCFG_WR(sc, shared_mf_config.clp_mb,
5969		 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5970}
5971
5972/* prepare for MCP reset, takes care of CLP configurations */
5973static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5974{
5975	uint32_t shmem;
5976	uint32_t validity_offset;
5977
5978	/* set `magic' bit in order to save MF config */
5979	bnx2x_clp_reset_prep(sc, magic_val);
5980
5981	/* get shmem offset */
5982	shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5983	validity_offset =
5984	    offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5985
5986	/* Clear validity map flags */
5987	if (shmem > 0) {
5988		REG_WR(sc, shmem + validity_offset, 0);
5989	}
5990}
5991
5992#define MCP_TIMEOUT      5000	/* 5 seconds (in ms) */
5993#define MCP_ONE_TIMEOUT  100	/* 100 ms */
5994
5995static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5996{
5997	/* special handling for emulation and FPGA (10 times longer) */
5998	if (CHIP_REV_IS_SLOW(sc)) {
5999		DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6000	} else {
6001		DELAY((MCP_ONE_TIMEOUT) * 1000);
6002	}
6003}
6004
6005/* initialize shmem_base and waits for validity signature to appear */
6006static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6007{
6008	int cnt = 0;
6009	uint32_t val = 0;
6010
6011	do {
6012		sc->devinfo.shmem_base =
6013		    sc->link_params.shmem_base =
6014		    REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6015
6016		if (sc->devinfo.shmem_base) {
6017			val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6018			if (val & SHR_MEM_VALIDITY_MB)
6019				return 0;
6020		}
6021
6022		bnx2x_mcp_wait_one(sc);
6023
6024	} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6025
6026	PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6027
6028	return -1;
6029}
6030
6031static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6032{
6033	int rc = bnx2x_init_shmem(sc);
6034
6035	/* Restore the `magic' bit value */
6036	bnx2x_clp_reset_done(sc, magic_val);
6037
6038	return rc;
6039}
6040
6041static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6042{
6043	REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6044	REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6045	wmb();
6046}
6047
6048/*
6049 * Reset the whole chip except for:
6050 *      - PCIE core
6051 *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6052 *      - IGU
6053 *      - MISC (including AEU)
6054 *      - GRC
6055 *      - RBCN, RBCP
6056 */
6057static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6058{
6059	uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6060	uint32_t global_bits2, stay_reset2;
6061
6062	/*
6063	 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6064	 * (per chip) blocks.
6065	 */
6066	global_bits2 =
6067	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6068	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6069
6070	/*
6071	 * Don't reset the following blocks.
6072	 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6073	 *            reset, as in 4 port device they might still be owned
6074	 *            by the MCP (there is only one leader per path).
6075	 */
6076	not_reset_mask1 =
6077	    MISC_REGISTERS_RESET_REG_1_RST_HC |
6078	    MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6079	    MISC_REGISTERS_RESET_REG_1_RST_PXP;
6080
6081	not_reset_mask2 =
6082	    MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6083	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6084	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6085	    MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6086	    MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6087	    MISC_REGISTERS_RESET_REG_2_RST_GRC |
6088	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6089	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6090	    MISC_REGISTERS_RESET_REG_2_RST_ATC |
6091	    MISC_REGISTERS_RESET_REG_2_PGLC |
6092	    MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6093	    MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6094	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6095	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6096	    MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6097
6098	/*
6099	 * Keep the following blocks in reset:
6100	 *  - all xxMACs are handled by the elink code.
6101	 */
6102	stay_reset2 =
6103	    MISC_REGISTERS_RESET_REG_2_XMAC |
6104	    MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6105
6106	/* Full reset masks according to the chip */
6107	reset_mask1 = 0xffffffff;
6108
6109	if (CHIP_IS_E1H(sc))
6110		reset_mask2 = 0x1ffff;
6111	else if (CHIP_IS_E2(sc))
6112		reset_mask2 = 0xfffff;
6113	else			/* CHIP_IS_E3 */
6114		reset_mask2 = 0x3ffffff;
6115
6116	/* Don't reset global blocks unless we need to */
6117	if (!global)
6118		reset_mask2 &= ~global_bits2;
6119
6120	/*
6121	 * In case of attention in the QM, we need to reset PXP
6122	 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6123	 * because otherwise QM reset would release 'close the gates' shortly
6124	 * before resetting the PXP, then the PSWRQ would send a write
6125	 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6126	 * read the payload data from PSWWR, but PSWWR would not
6127	 * respond. The write queue in PGLUE would stuck, dmae commands
6128	 * would not return. Therefore it's important to reset the second
6129	 * reset register (containing the
6130	 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6131	 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6132	 * bit).
6133	 */
6134	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6135	       reset_mask2 & (~not_reset_mask2));
6136
6137	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6138	       reset_mask1 & (~not_reset_mask1));
6139
6140	mb();
6141	wmb();
6142
6143	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6144	       reset_mask2 & (~stay_reset2));
6145
6146	mb();
6147	wmb();
6148
6149	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6150	wmb();
6151}
6152
6153static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6154{
6155	int cnt = 1000;
6156	uint32_t val = 0;
6157	uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6158	uint32_t tags_63_32 = 0;
6159
6160	/* Empty the Tetris buffer, wait for 1s */
6161	do {
6162		sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6163		blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6164		port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6165		port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6166		pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6167		if (CHIP_IS_E3(sc)) {
6168			tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6169		}
6170
6171		if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6172		    ((port_is_idle_0 & 0x1) == 0x1) &&
6173		    ((port_is_idle_1 & 0x1) == 0x1) &&
6174		    (pgl_exp_rom2 == 0xffffffff) &&
6175		    (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6176			break;
6177		DELAY(1000);
6178	} while (cnt-- > 0);
6179
6180	if (cnt <= 0) {
6181		PMD_DRV_LOG(NOTICE,
6182			    "ERROR: Tetris buffer didn't get empty or there "
6183			    "are still outstanding read requests after 1s! "
6184			    "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6185			    "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6186			    sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6187			    pgl_exp_rom2);
6188		return -1;
6189	}
6190
6191	mb();
6192
6193	/* Close gates #2, #3 and #4 */
6194	bnx2x_set_234_gates(sc, TRUE);
6195
6196	/* Poll for IGU VQs for 57712 and newer chips */
6197	if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6198		return -1;
6199	}
6200
6201	/* clear "unprepared" bit */
6202	REG_WR(sc, MISC_REG_UNPREPARED, 0);
6203	mb();
6204
6205	/* Make sure all is written to the chip before the reset */
6206	wmb();
6207
6208	/*
6209	 * Wait for 1ms to empty GLUE and PCI-E core queues,
6210	 * PSWHST, GRC and PSWRD Tetris buffer.
6211	 */
6212	DELAY(1000);
6213
6214	/* Prepare to chip reset: */
6215	/* MCP */
6216	if (global) {
6217		bnx2x_reset_mcp_prep(sc, &val);
6218	}
6219
6220	/* PXP */
6221	bnx2x_pxp_prep(sc);
6222	mb();
6223
6224	/* reset the chip */
6225	bnx2x_process_kill_chip_reset(sc, global);
6226	mb();
6227
6228	/* Recover after reset: */
6229	/* MCP */
6230	if (global && bnx2x_reset_mcp_comp(sc, val)) {
6231		return -1;
6232	}
6233
6234	/* Open the gates #2, #3 and #4 */
6235	bnx2x_set_234_gates(sc, FALSE);
6236
6237	return 0;
6238}
6239
6240static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6241{
6242	int rc = 0;
6243	uint8_t global = bnx2x_reset_is_global(sc);
6244	uint32_t load_code;
6245
6246	/*
6247	 * If not going to reset MCP, load "fake" driver to reset HW while
6248	 * driver is owner of the HW.
6249	 */
6250	if (!global && !BNX2X_NOMCP(sc)) {
6251		load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6252					   DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6253		if (!load_code) {
6254			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6255			rc = -1;
6256			goto exit_leader_reset;
6257		}
6258
6259		if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6260		    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6261			PMD_DRV_LOG(NOTICE,
6262				    "MCP unexpected response, aborting");
6263			rc = -1;
6264			goto exit_leader_reset2;
6265		}
6266
6267		load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6268		if (!load_code) {
6269			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6270			rc = -1;
6271			goto exit_leader_reset2;
6272		}
6273	}
6274
6275	/* try to recover after the failure */
6276	if (bnx2x_process_kill(sc, global)) {
6277		PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6278			    SC_PATH(sc));
6279		rc = -1;
6280		goto exit_leader_reset2;
6281	}
6282
6283	/*
6284	 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6285	 * state.
6286	 */
6287	bnx2x_set_reset_done(sc);
6288	if (global) {
6289		bnx2x_clear_reset_global(sc);
6290	}
6291
6292exit_leader_reset2:
6293
6294	/* unload "fake driver" if it was loaded */
6295	if (!global &&!BNX2X_NOMCP(sc)) {
6296		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6297		bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6298	}
6299
6300exit_leader_reset:
6301
6302	sc->is_leader = 0;
6303	bnx2x_release_leader_lock(sc);
6304
6305	mb();
6306	return rc;
6307}
6308
6309/*
6310 * prepare INIT transition, parameters configured:
6311 *   - HC configuration
6312 *   - Queue's CDU context
6313 */
6314static void
6315bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6316		   struct ecore_queue_init_params *init_params)
6317{
6318	uint8_t cos;
6319	int cxt_index, cxt_offset;
6320
6321	bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6322	bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6323
6324	bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6325	bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6326
6327	/* HC rate */
6328	init_params->rx.hc_rate =
6329	    sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6330	init_params->tx.hc_rate =
6331	    sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6332
6333	/* FW SB ID */
6334	init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6335
6336	/* CQ index among the SB indices */
6337	init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6338	init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6339
6340	/* set maximum number of COSs supported by this queue */
6341	init_params->max_cos = sc->max_cos;
6342
6343	/* set the context pointers queue object */
6344	for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6345		cxt_index = fp->index / ILT_PAGE_CIDS;
6346		cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6347		init_params->cxts[cos] =
6348		    &sc->context[cxt_index].vcxt[cxt_offset].eth;
6349	}
6350}
6351
6352/* set flags that are common for the Tx-only and not normal connections */
6353static unsigned long
6354bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6355{
6356	unsigned long flags = 0;
6357
6358	/* PF driver will always initialize the Queue to an ACTIVE state */
6359	bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6360
6361	/*
6362	 * tx only connections collect statistics (on the same index as the
6363	 * parent connection). The statistics are zeroed when the parent
6364	 * connection is initialized.
6365	 */
6366
6367	bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6368	if (zero_stats) {
6369		bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6370	}
6371
6372	/*
6373	 * tx only connections can support tx-switching, though their
6374	 * CoS-ness doesn't survive the loopback
6375	 */
6376	if (sc->flags & BNX2X_TX_SWITCHING) {
6377		bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6378	}
6379
6380	bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6381
6382	return flags;
6383}
6384
6385static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6386{
6387	unsigned long flags = 0;
6388
6389	if (IS_MF_SD(sc)) {
6390		bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6391	}
6392
6393	if (leading) {
6394		bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6395		bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6396	}
6397
6398	bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6399
6400	/* merge with common flags */
6401	return flags | bnx2x_get_common_flags(sc, TRUE);
6402}
6403
6404static void
6405bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6406		      struct ecore_general_setup_params *gen_init, uint8_t cos)
6407{
6408	gen_init->stat_id = bnx2x_stats_id(fp);
6409	gen_init->spcl_id = fp->cl_id;
6410	gen_init->mtu = sc->mtu;
6411	gen_init->cos = cos;
6412}
6413
6414static void
6415bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6416		 struct rxq_pause_params *pause,
6417		 struct ecore_rxq_setup_params *rxq_init)
6418{
6419	struct bnx2x_rx_queue *rxq;
6420
6421	rxq = sc->rx_queues[fp->index];
6422	if (!rxq) {
6423		PMD_RX_LOG(ERR, "RX queue is NULL");
6424		return;
6425	}
6426	/* pause */
6427	pause->bd_th_lo = BD_TH_LO(sc);
6428	pause->bd_th_hi = BD_TH_HI(sc);
6429
6430	pause->rcq_th_lo = RCQ_TH_LO(sc);
6431	pause->rcq_th_hi = RCQ_TH_HI(sc);
6432
6433	/* validate rings have enough entries to cross high thresholds */
6434	if (sc->dropless_fc &&
6435	    pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6436		PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6437	}
6438
6439	if (sc->dropless_fc &&
6440	    pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6441		PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6442	}
6443
6444	pause->pri_map = 1;
6445
6446	/* rxq setup */
6447	rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6448	rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6449	rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6450					      BNX2X_PAGE_SIZE);
6451
6452	/*
6453	 * This should be a maximum number of data bytes that may be
6454	 * placed on the BD (not including paddings).
6455	 */
6456	rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6457
6458	rxq_init->cl_qzone_id = fp->cl_qzone_id;
6459	rxq_init->rss_engine_id = SC_FUNC(sc);
6460	rxq_init->mcast_engine_id = SC_FUNC(sc);
6461
6462	rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6463	rxq_init->fw_sb_id = fp->fw_sb_id;
6464
6465	rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6466
6467	/*
6468	 * configure silent vlan removal
6469	 * if multi function mode is afex, then mask default vlan
6470	 */
6471	if (IS_MF_AFEX(sc)) {
6472		rxq_init->silent_removal_value =
6473		    sc->devinfo.mf_info.afex_def_vlan_tag;
6474		rxq_init->silent_removal_mask = EVL_VLID_MASK;
6475	}
6476}
6477
6478static void
6479bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6480		 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6481{
6482	struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6483
6484	if (!txq) {
6485		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6486		return;
6487	}
6488	txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6489	txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6490	txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6491	txq_init->fw_sb_id = fp->fw_sb_id;
6492
6493	/*
6494	 * set the TSS leading client id for TX classfication to the
6495	 * leading RSS client id
6496	 */
6497	txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6498}
6499
6500/*
6501 * This function performs 2 steps in a queue state machine:
6502 *   1) RESET->INIT
6503 *   2) INIT->SETUP
6504 */
6505static int
6506bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6507{
6508	struct ecore_queue_state_params q_params = { NULL };
6509	struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6510	int rc;
6511
6512	PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6513
6514	bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6515
6516	q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6517
6518	/* we want to wait for completion in this context */
6519	bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6520
6521	/* prepare the INIT parameters */
6522	bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6523
6524	/* Set the command */
6525	q_params.cmd = ECORE_Q_CMD_INIT;
6526
6527	/* Change the state to INIT */
6528	rc = ecore_queue_state_change(sc, &q_params);
6529	if (rc) {
6530		PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6531		return rc;
6532	}
6533
6534	PMD_DRV_LOG(DEBUG, "init complete");
6535
6536	/* now move the Queue to the SETUP state */
6537	memset(setup_params, 0, sizeof(*setup_params));
6538
6539	/* set Queue flags */
6540	setup_params->flags = bnx2x_get_q_flags(sc, leading);
6541
6542	/* set general SETUP parameters */
6543	bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6544			      FIRST_TX_COS_INDEX);
6545
6546	bnx2x_pf_rx_q_prep(sc, fp,
6547			 &setup_params->pause_params,
6548			 &setup_params->rxq_params);
6549
6550	bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6551
6552	/* Set the command */
6553	q_params.cmd = ECORE_Q_CMD_SETUP;
6554
6555	/* change the state to SETUP */
6556	rc = ecore_queue_state_change(sc, &q_params);
6557	if (rc) {
6558		PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6559		return rc;
6560	}
6561
6562	return rc;
6563}
6564
6565static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6566{
6567	if (IS_PF(sc))
6568		return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6569	else			/* VF */
6570		return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6571}
6572
6573static int
6574bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6575		  uint8_t config_hash)
6576{
6577	struct ecore_config_rss_params params = { NULL };
6578	uint32_t i;
6579
6580	/*
6581	 * Although RSS is meaningless when there is a single HW queue we
6582	 * still need it enabled in order to hav