1/*-
2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
3 *
4 * Eric Davis        <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano     <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
11 * www.qlogic.com
12 *
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
14 */
15
16#ifndef ECORE_INIT_H
17#define ECORE_INIT_H
18
19/* Init operation types and structures */
20enum {
21	OP_RD = 0x1,	/* read a single register */
22	OP_WR,		/* write a single register */
23	OP_SW,		/* copy a string to the device */
24	OP_ZR,		/* clear memory */
25	OP_ZP,		/* unzip then copy with DMAE */
26	OP_WR_64,	/* write 64 bit pattern */
27	OP_WB,		/* copy a string using DMAE */
28	OP_WB_ZR,	/* Clear a string using DMAE or indirect-wr */
29	OP_IF_MODE_OR,  /* Skip the following ops if all init modes don't match */
30	OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
31	OP_IF_PHASE,
32	OP_RT,
33	OP_DELAY,
34	OP_VERIFY,
35	OP_MAX
36};
37
38enum {
39	STAGE_START,
40	STAGE_END,
41};
42
43/* Returns the index of start or end of a specific block stage in ops array*/
44#define BLOCK_OPS_IDX(block, stage, end) \
45	(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
46
47
48/* structs for the various opcodes */
49struct raw_op {
50	uint32_t op:8;
51	uint32_t offset:24;
52	uint32_t raw_data;
53};
54
55struct op_read {
56	uint32_t op:8;
57	uint32_t offset:24;
58	uint32_t val;
59};
60
61struct op_write {
62	uint32_t op:8;
63	uint32_t offset:24;
64	uint32_t val;
65};
66
67struct op_arr_write {
68	uint32_t op:8;
69	uint32_t offset:24;
70#ifdef __BIG_ENDIAN
71	uint16_t data_len;
72	uint16_t data_off;
73#else /* __LITTLE_ENDIAN */
74	uint16_t data_off;
75	uint16_t data_len;
76#endif
77};
78
79struct op_zero {
80	uint32_t op:8;
81	uint32_t offset:24;
82	uint32_t len;
83};
84
85struct op_if_mode {
86	uint32_t op:8;
87	uint32_t cmd_offset:24;
88	uint32_t mode_bit_map;
89};
90
91struct op_if_phase {
92	uint32_t op:8;
93	uint32_t cmd_offset:24;
94	uint32_t phase_bit_map;
95};
96
97struct op_delay {
98	uint32_t op:8;
99	uint32_t reserved:24;
100	uint32_t delay;
101};
102
103union init_op {
104	struct op_read		read;
105	struct op_write		write;
106	struct op_arr_write	arr_wr;
107	struct op_zero		zero;
108	struct raw_op		raw;
109	struct op_if_mode	if_mode;
110	struct op_if_phase	if_phase;
111	struct op_delay		delay;
112};
113
114
115/* Init Phases */
116enum {
117	PHASE_COMMON,
118	PHASE_PORT0,
119	PHASE_PORT1,
120	PHASE_PF0,
121	PHASE_PF1,
122	PHASE_PF2,
123	PHASE_PF3,
124	PHASE_PF4,
125	PHASE_PF5,
126	PHASE_PF6,
127	PHASE_PF7,
128	NUM_OF_INIT_PHASES
129};
130
131/* Init Modes */
132enum {
133	MODE_ASIC                      = 0x00000001,
134	MODE_FPGA                      = 0x00000002,
135	MODE_EMUL                      = 0x00000004,
136	MODE_E2                        = 0x00000008,
137	MODE_E3                        = 0x00000010,
138	MODE_PORT2                     = 0x00000020,
139	MODE_PORT4                     = 0x00000040,
140	MODE_SF                        = 0x00000080,
141	MODE_MF                        = 0x00000100,
142	MODE_MF_SD                     = 0x00000200,
143	MODE_MF_SI                     = 0x00000400,
144	MODE_MF_AFEX                   = 0x00000800,
145	MODE_E3_A0                     = 0x00001000,
146	MODE_E3_B0                     = 0x00002000,
147	MODE_COS3                      = 0x00004000,
148	MODE_COS6                      = 0x00008000,
149	MODE_LITTLE_ENDIAN             = 0x00010000,
150	MODE_BIG_ENDIAN                = 0x00020000,
151};
152
153/* Init Blocks */
154enum {
155	BLOCK_ATC,
156	BLOCK_BRB1,
157	BLOCK_CCM,
158	BLOCK_CDU,
159	BLOCK_CFC,
160	BLOCK_CSDM,
161	BLOCK_CSEM,
162	BLOCK_DBG,
163	BLOCK_DMAE,
164	BLOCK_DORQ,
165	BLOCK_HC,
166	BLOCK_IGU,
167	BLOCK_MISC,
168	BLOCK_NIG,
169	BLOCK_PBF,
170	BLOCK_PGLUE_B,
171	BLOCK_PRS,
172	BLOCK_PXP2,
173	BLOCK_PXP,
174	BLOCK_QM,
175	BLOCK_SRC,
176	BLOCK_TCM,
177	BLOCK_TM,
178	BLOCK_TSDM,
179	BLOCK_TSEM,
180	BLOCK_UCM,
181	BLOCK_UPB,
182	BLOCK_USDM,
183	BLOCK_USEM,
184	BLOCK_XCM,
185	BLOCK_XPB,
186	BLOCK_XSDM,
187	BLOCK_XSEM,
188	BLOCK_MISC_AEU,
189	NUM_OF_INIT_BLOCKS
190};
191
192
193
194
195
196
197
198
199/* Vnics per mode */
200#define ECORE_PORT2_MODE_NUM_VNICS 4
201
202
203/* QM queue numbers */
204#define ECORE_ETH_Q		0
205#define ECORE_TOE_Q		3
206#define ECORE_TOE_ACK_Q		6
207#define ECORE_ISCSI_Q		9
208#define ECORE_ISCSI_ACK_Q	11
209#define ECORE_FCOE_Q		10
210
211/* Vnics per mode */
212#define ECORE_PORT4_MODE_NUM_VNICS 2
213
214/* COS offset for port1 in E3 B0 4port mode */
215#define ECORE_E3B0_PORT1_COS_OFFSET 3
216
217/* QM Register addresses */
218#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
219	(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
220#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
221	(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
222#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
223	(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
224
225/* extracts the QM queue number for the specified port and vnic */
226#define ECORE_PF_Q_NUM(q_num, port, vnic)\
227	((((port) << 1) | (vnic)) * 16 + (q_num))
228
229
230/* Maps the specified queue to the specified COS */
231static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos)
232{
233	/* find current COS mapping */
234	uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
235
236	/* check if queue->COS mapping has changed */
237	if (curr_cos != new_cos) {
238		uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
239		uint32_t reg_addr, reg_bit_map, vnic;
240
241		/* update parameters for 4port mode */
242		if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
243			num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
244			if (PORT_ID(sc)) {
245				curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
246				new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
247			}
248		}
249
250		/* change queue mapping for each VNIC */
251		for (vnic = 0; vnic < num_vnics; vnic++) {
252			uint32_t pf_q_num =
253				ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
254			uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
255
256			/* overwrite queue->VOQ mapping */
257			REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
258
259			/* clear queue bit from current COS bit map */
260			reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
261			reg_bit_map = REG_RD(sc, reg_addr);
262			REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
263
264			/* set queue bit in new COS bit map */
265			reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
266			reg_bit_map = REG_RD(sc, reg_addr);
267			REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
268
269			/* set/clear queue bit in command-queue bit map
270			(E2/E3A0 only, valid COS values are 0/1) */
271			if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
272				reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
273				reg_bit_map = REG_RD(sc, reg_addr);
274				q_bit_map = 1 << (2 * (pf_q_num & 0xf));
275				reg_bit_map = new_cos ?
276					      (reg_bit_map | q_bit_map) :
277					      (reg_bit_map & (~q_bit_map));
278				REG_WR(sc, reg_addr, reg_bit_map);
279			}
280		}
281	}
282}
283
284/* Configures the QM according to the specified per-traffic-type COSes */
285static inline void ecore_dcb_config_qm(struct bnx2x_softc *sc, enum cos_mode mode,
286				       struct priority_cos *traffic_cos)
287{
288	ecore_map_q_cos(sc, ECORE_FCOE_Q,
289			traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
290	ecore_map_q_cos(sc, ECORE_ISCSI_Q,
291			traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
292	ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
293		traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
294	if (mode != STATIC_COS) {
295		/* required only in OVERRIDE_COS mode */
296		ecore_map_q_cos(sc, ECORE_ETH_Q,
297				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
298		ecore_map_q_cos(sc, ECORE_TOE_Q,
299				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
300		ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
301				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
302	}
303}
304
305
306/*
307 * congestion managment port init api description
308 * the api works as follows:
309 * the driver should pass the cmng_init_input struct, the port_init function
310 * will prepare the required internal ram structure which will be passed back
311 * to the driver (cmng_init) that will write it into the internal ram.
312 *
313 * IMPORTANT REMARKS:
314 * 1. the cmng_init struct does not represent the contiguous internal ram
315 *    structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
316 *    offset in order to write the port sub struct and the
317 *    PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
318 *    words - don't use memcpy!).
319 * 2. although the cmng_init struct is filled for the maximal vnic number
320 *    possible, the driver should only write the valid vnics into the internal
321 *    ram according to the appropriate port mode.
322 */
323#define BITS_TO_BYTES(x) ((x)/8)
324
325/* CMNG constants, as derived from system spec calculations */
326
327/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
328#define DEF_MIN_RATE 100
329
330/* resolution of the rate shaping timer - 400 usec */
331#define RS_PERIODIC_TIMEOUT_USEC 400
332
333/*
334 *  number of bytes in single QM arbitration cycle -
335 *  coefficient for calculating the fairness timer
336 */
337#define QM_ARB_BYTES 160000
338
339/* resolution of Min algorithm 1:100 */
340#define MIN_RES 100
341
342/*
343 *  how many bytes above threshold for
344 *  the minimal credit of Min algorithm
345 */
346#define MIN_ABOVE_THRESH 32768
347
348/*
349 *  Fairness algorithm integration time coefficient -
350 *  for calculating the actual Tfair
351 */
352#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
353
354/* Memory of fairness algorithm - 2 cycles */
355#define FAIR_MEM 2
356#define SAFC_TIMEOUT_USEC 52
357
358#define SDM_TICKS 4
359
360
361static inline void ecore_init_max(const struct cmng_init_input *input_data,
362				  uint32_t r_param, struct cmng_init *ram_data)
363{
364	uint32_t vnic;
365	struct cmng_vnic *vdata = &ram_data->vnic;
366	struct cmng_struct_per_port *pdata = &ram_data->port;
367	/*
368	 * rate shaping per-port variables
369	 *  100 micro seconds in SDM ticks = 25
370	 *  since each tick is 4 microSeconds
371	 */
372
373	pdata->rs_vars.rs_periodic_timeout =
374	RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
375
376	/* this is the threshold below which no timer arming will occur.
377	 *  1.25 coefficient is for the threshold to be a little bigger
378	 *  then the real time to compensate for timer in-accuracy
379	 */
380	pdata->rs_vars.rs_threshold =
381	(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
382
383	/* rate shaping per-vnic variables */
384	for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
385		/* global vnic counter */
386		vdata->vnic_max_rate[vnic].vn_counter.rate =
387		input_data->vnic_max_rate[vnic];
388		/*
389		 * maximal Mbps for this vnic
390		 * the quota in each timer period - number of bytes
391		 * transmitted in this period
392		 */
393		vdata->vnic_max_rate[vnic].vn_counter.quota =
394			RS_PERIODIC_TIMEOUT_USEC *
395			(uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
396	}
397
398}
399
400static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
401				  struct rate_shaping_vars_per_vn *ram_data)
402{
403	/* global vnic counter */
404	ram_data->vn_counter.rate = vnic_max_rate;
405
406	/*
407	* maximal Mbps for this vnic
408	* the quota in each timer period - number of bytes
409	* transmitted in this period
410	*/
411	ram_data->vn_counter.quota =
412		RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
413}
414
415static inline void ecore_init_min(const struct cmng_init_input *input_data,
416				  uint32_t r_param, struct cmng_init *ram_data)
417{
418	uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
419	struct cmng_vnic *vdata = &ram_data->vnic;
420	struct cmng_struct_per_port *pdata = &ram_data->port;
421
422	/* this is the resolution of the fairness timer */
423	fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
424
425	/*
426	 * fairness per-port variables
427	 * for 10G it is 1000usec. for 1G it is 10000usec.
428	 */
429	tFair = T_FAIR_COEF / input_data->port_rate;
430
431	/* this is the threshold below which we won't arm the timer anymore */
432	pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
433
434	/*
435	 *  we multiply by 1e3/8 to get bytes/msec. We don't want the credits
436	 *  to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
437	 */
438	pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
439
440	/* since each tick is 4 microSeconds */
441	pdata->fair_vars.fairness_timeout =
442				fair_periodic_timeout_usec / SDM_TICKS;
443
444	/* calculate sum of weights */
445	vnicWeightSum = 0;
446
447	for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
448		vnicWeightSum += input_data->vnic_min_rate[vnic];
449
450	/* global vnic counter */
451	if (vnicWeightSum > 0) {
452		/* fairness per-vnic variables */
453		for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
454			/*
455			 *  this is the credit for each period of the fairness
456			 *  algorithm - number of bytes in T_FAIR (this vnic
457			 *  share of the port rate)
458			 */
459			vdata->vnic_min_rate[vnic].vn_credit_delta =
460				((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
461				(T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
462			if (vdata->vnic_min_rate[vnic].vn_credit_delta <
463			    pdata->fair_vars.fair_threshold +
464			    MIN_ABOVE_THRESH) {
465				vdata->vnic_min_rate[vnic].vn_credit_delta =
466					pdata->fair_vars.fair_threshold +
467					MIN_ABOVE_THRESH;
468			}
469		}
470	}
471}
472
473static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
474				     struct cmng_init *ram_data)
475{
476	uint32_t vnic, cos;
477	uint32_t cosWeightSum = 0;
478	struct cmng_vnic *vdata = &ram_data->vnic;
479	struct cmng_struct_per_port *pdata = &ram_data->port;
480
481	for (cos = 0; cos < MAX_COS_NUMBER; cos++)
482		cosWeightSum += input_data->cos_min_rate[cos];
483
484	if (cosWeightSum > 0) {
485
486		for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
487			/*
488			 *  Since cos and vnic shouldn't work together the rate
489			 *  to divide between the coses is the port rate.
490			 */
491			uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
492			for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
493				/*
494				 * this is the credit for each period of
495				 * the fairness algorithm - number of bytes
496				 * in T_FAIR (this cos share of the vnic rate)
497				 */
498				ccd[cos] =
499				    ((uint32_t)input_data->cos_min_rate[cos] * 100 *
500				    (T_FAIR_COEF / (8 * 100 * cosWeightSum)));
501				 if (ccd[cos] < pdata->fair_vars.fair_threshold
502						+ MIN_ABOVE_THRESH) {
503					ccd[cos] =
504					    pdata->fair_vars.fair_threshold +
505					    MIN_ABOVE_THRESH;
506				}
507			}
508		}
509	}
510}
511
512static inline void ecore_init_safc(struct cmng_init *ram_data)
513{
514	/* in microSeconds */
515	ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
516}
517
518/* Congestion management port init */
519static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
520				   struct cmng_init *ram_data)
521{
522	uint32_t r_param;
523	ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
524
525	ram_data->port.flags = input_data->flags;
526
527	/*
528	 *  number of bytes transmitted in a rate of 10Gbps
529	 *  in one usec = 1.25KB.
530	 */
531	r_param = BITS_TO_BYTES(input_data->port_rate);
532	ecore_init_max(input_data, r_param, ram_data);
533	ecore_init_min(input_data, r_param, ram_data);
534	ecore_init_fw_wrr(input_data, ram_data);
535	ecore_init_safc(ram_data);
536}
537
538
539
540
541/* Returns the index of start or end of a specific block stage in ops array*/
542#define BLOCK_OPS_IDX(block, stage, end) \
543			(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
544
545
546#define INITOP_SET		0	/* set the HW directly */
547#define INITOP_CLEAR		1	/* clear the HW directly */
548#define INITOP_INIT		2	/* set the init-value array */
549
550/****************************************************************************
551* ILT management
552****************************************************************************/
553struct ilt_line {
554	ecore_dma_addr_t page_mapping;
555	void *page;
556	uint32_t size;
557};
558
559struct ilt_client_info {
560	uint32_t page_size;
561	uint16_t start;
562	uint16_t end;
563	uint16_t client_num;
564	uint16_t flags;
565#define ILT_CLIENT_SKIP_INIT	0x1
566#define ILT_CLIENT_SKIP_MEM	0x2
567};
568
569struct ecore_ilt {
570	uint32_t start_line;
571	struct ilt_line		*lines;
572	struct ilt_client_info	clients[4];
573#define ILT_CLIENT_CDU	0
574#define ILT_CLIENT_QM	1
575#define ILT_CLIENT_SRC	2
576#define ILT_CLIENT_TM	3
577};
578
579/****************************************************************************
580* SRC configuration
581****************************************************************************/
582struct src_ent {
583	uint8_t opaque[56];
584	uint64_t next;
585};
586
587/****************************************************************************
588* Parity configuration
589****************************************************************************/
590#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
591{ \
592	block##_REG_##block##_PRTY_MASK, \
593	block##_REG_##block##_PRTY_STS_CLR, \
594	en_mask, {m1h, m2, m3}, #block \
595}
596
597#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
598{ \
599	block##_REG_##block##_PRTY_MASK_0, \
600	block##_REG_##block##_PRTY_STS_CLR_0, \
601	en_mask, {m1h, m2, m3}, #block"_0" \
602}
603
604#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
605{ \
606	block##_REG_##block##_PRTY_MASK_1, \
607	block##_REG_##block##_PRTY_STS_CLR_1, \
608	en_mask, {m1h, m2, m3}, #block"_1" \
609}
610
611static const struct {
612	uint32_t mask_addr;
613	uint32_t sts_clr_addr;
614	uint32_t en_mask;		/* Mask to enable parity attentions */
615	struct {
616		uint32_t e1h;	/* 57711 */
617		uint32_t e2;		/* 57712 */
618		uint32_t e3;		/* 578xx */
619	} reg_mask;		/* Register mask (all valid bits) */
620	char name[8];		/* Block's longest name is 7 characters long
621				 * (name + suffix)
622				 */
623} ecore_blocks_parity_data[] = {
624	/* bit 19 masked */
625	/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
626	/* bit 5,18,20-31 */
627	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
628	/* bit 5 */
629	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);	*/
630	/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
631	/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
632
633	/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
634	 * want to handle "system kill" flow at the moment.
635	 */
636	BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
637			0x7ffffff),
638	BLOCK_PRTY_INFO_0(PXP2,	0xffffffff, 0xffffffff, 0xffffffff,
639			  0xffffffff),
640	BLOCK_PRTY_INFO_1(PXP2,	0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
641	BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
642	BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
643	BLOCK_PRTY_INFO_0(NIG,	0xffffffff, 0, 0xffffffff, 0xffffffff),
644	BLOCK_PRTY_INFO_1(NIG,	0xffff, 0, 0xff, 0xffff),
645	BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
646	BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
647	BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
648	BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
649	BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
650	BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
651	{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
652		GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
653		{0xf, 0xf, 0xf}, "UPB"},
654	{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
655		GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
656		{0xf, 0xf, 0xf}, "XPB"},
657	BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
658	BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
659	BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
660	BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
661	BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
662	BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
663	BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
664	BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
665	BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
666	BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
667	BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
668	BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
669	BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
670	BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
671	BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
672	BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
673	BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
674	BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
675	BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
676	BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
677	BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
678	BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
679	BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
680	BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
681	BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
682};
683
684
685/* [28] MCP Latched rom_parity
686 * [29] MCP Latched ump_rx_parity
687 * [30] MCP Latched ump_tx_parity
688 * [31] MCP Latched scpad_parity
689 */
690#define MISC_AEU_ENABLE_MCP_PRTY_BITS	\
691	(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
692	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
693	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
694	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
695
696/* Below registers control the MCP parity attention output. When
697 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
698 * enabled, when cleared - disabled.
699 */
700static const uint32_t mcp_attn_ctl_regs[] = {
701	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
702	MISC_REG_AEU_ENABLE4_NIG_0,
703	MISC_REG_AEU_ENABLE4_PXP_0,
704	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
705	MISC_REG_AEU_ENABLE4_NIG_1,
706	MISC_REG_AEU_ENABLE4_PXP_1
707};
708
709static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
710{
711	uint32_t i;
712	uint32_t reg_val;
713
714	for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
715		reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
716
717		if (enable)
718			reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
719		else
720			reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
721
722		REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
723	}
724}
725
726static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
727{
728	if (CHIP_IS_E1H(sc))
729		return ecore_blocks_parity_data[idx].reg_mask.e1h;
730	else if (CHIP_IS_E2(sc))
731		return ecore_blocks_parity_data[idx].reg_mask.e2;
732	else /* CHIP_IS_E3 */
733		return ecore_blocks_parity_data[idx].reg_mask.e3;
734}
735
736static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
737{
738	uint32_t i;
739
740	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
741		uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
742
743		if (dis_mask) {
744			REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
745			       dis_mask);
746			ECORE_MSG("Setting parity mask "
747						 "for %s to\t\t0x%x",
748				    ecore_blocks_parity_data[i].name, dis_mask);
749		}
750	}
751
752	/* Disable MCP parity attentions */
753	ecore_set_mcp_parity(sc, FALSE);
754}
755
756/**
757 * Clear the parity error status registers.
758 */
759static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
760{
761	uint32_t i;
762	uint32_t reg_val, mcp_aeu_bits =
763		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
764		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
765		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
766		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
767
768	/* Clear SEM_FAST parities */
769	REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
770	REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
771	REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
772	REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
773
774	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
775		uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
776
777		if (reg_mask) {
778			reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
779					 sts_clr_addr);
780			if (reg_val & reg_mask)
781				ECORE_MSG("Parity errors in %s: 0x%x",
782					   ecore_blocks_parity_data[i].name,
783					   reg_val & reg_mask);
784		}
785	}
786
787	/* Check if there were parity attentions in MCP */
788	reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
789	if (reg_val & mcp_aeu_bits)
790		ECORE_MSG("Parity error in MCP: 0x%x",
791			   reg_val & mcp_aeu_bits);
792
793	/* Clear parity attentions in MCP:
794	 * [7]  clears Latched rom_parity
795	 * [8]  clears Latched ump_rx_parity
796	 * [9]  clears Latched ump_tx_parity
797	 * [10] clears Latched scpad_parity (both ports)
798	 */
799	REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
800}
801
802static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
803{
804	uint32_t i;
805
806	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
807		uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
808
809		if (reg_mask)
810			REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
811				ecore_blocks_parity_data[i].en_mask & reg_mask);
812	}
813
814	/* Enable MCP parity attentions */
815	ecore_set_mcp_parity(sc, TRUE);
816}
817
818
819#endif /* ECORE_INIT_H */
820