1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
35a551c94aSIdo Barnea * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
36a551c94aSIdo Barnea */
37a551c94aSIdo Barnea
38a551c94aSIdo Barnea#include "e1000_api.h"
39a551c94aSIdo Barnea
40a551c94aSIdo BarneaSTATIC s32  e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
41a551c94aSIdo BarneaSTATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
42a551c94aSIdo BarneaSTATIC s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
43a551c94aSIdo BarneaSTATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
44a551c94aSIdo BarneaSTATIC s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
45a551c94aSIdo Barnea						   u32 offset,
46a551c94aSIdo Barnea						   u16 *data);
47a551c94aSIdo BarneaSTATIC s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
48a551c94aSIdo Barnea						    u32 offset,
49a551c94aSIdo Barnea						    u16 data);
50a551c94aSIdo BarneaSTATIC s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
51a551c94aSIdo Barnea					u16 words, u16 *data);
52a551c94aSIdo BarneaSTATIC s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
53a551c94aSIdo BarneaSTATIC s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
54a551c94aSIdo BarneaSTATIC s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
55a551c94aSIdo BarneaSTATIC s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
56a551c94aSIdo Barnea					       u16 *duplex);
57a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
58a551c94aSIdo BarneaSTATIC s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
59a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
60a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
61a551c94aSIdo BarneaSTATIC s32  e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
62a551c94aSIdo BarneaSTATIC s32  e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
63a551c94aSIdo BarneaSTATIC s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
64a551c94aSIdo BarneaSTATIC s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
65a551c94aSIdo BarneaSTATIC s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
66a551c94aSIdo Barnea					    u16 *data);
67a551c94aSIdo BarneaSTATIC s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68a551c94aSIdo Barnea					     u16 data);
69a551c94aSIdo BarneaSTATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
70a551c94aSIdo BarneaSTATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
71a551c94aSIdo BarneaSTATIC s32  e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
72a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea/* A table for the GG82563 cable length where the range is defined
75a551c94aSIdo Barnea * with a lower bound at "index" and the upper bound at
76a551c94aSIdo Barnea * "index + 5".
77a551c94aSIdo Barnea */
78a551c94aSIdo BarneaSTATIC const u16 e1000_gg82563_cable_length_table[] = {
79a551c94aSIdo Barnea	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
80a551c94aSIdo Barnea#define GG82563_CABLE_LENGTH_TABLE_SIZE \
81a551c94aSIdo Barnea		(sizeof(e1000_gg82563_cable_length_table) / \
82a551c94aSIdo Barnea		 sizeof(e1000_gg82563_cable_length_table[0]))
83a551c94aSIdo Barnea
84a551c94aSIdo Barnea/**
85a551c94aSIdo Barnea *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
86a551c94aSIdo Barnea *  @hw: pointer to the HW structure
87a551c94aSIdo Barnea **/
88a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
89a551c94aSIdo Barnea{
90a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
91a551c94aSIdo Barnea	s32 ret_val;
92a551c94aSIdo Barnea
93a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_80003es2lan");
94a551c94aSIdo Barnea
95a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper) {
96a551c94aSIdo Barnea		phy->type = e1000_phy_none;
97a551c94aSIdo Barnea		return E1000_SUCCESS;
98a551c94aSIdo Barnea	} else {
99a551c94aSIdo Barnea		phy->ops.power_up = e1000_power_up_phy_copper;
100a551c94aSIdo Barnea		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
101a551c94aSIdo Barnea	}
102a551c94aSIdo Barnea
103a551c94aSIdo Barnea	phy->addr		= 1;
104a551c94aSIdo Barnea	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
105a551c94aSIdo Barnea	phy->reset_delay_us	= 100;
106a551c94aSIdo Barnea	phy->type		= e1000_phy_gg82563;
107a551c94aSIdo Barnea
108a551c94aSIdo Barnea	phy->ops.acquire	= e1000_acquire_phy_80003es2lan;
109a551c94aSIdo Barnea	phy->ops.check_polarity	= e1000_check_polarity_m88;
110a551c94aSIdo Barnea	phy->ops.check_reset_block = e1000_check_reset_block_generic;
111a551c94aSIdo Barnea	phy->ops.commit		= e1000_phy_sw_reset_generic;
112a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_80003es2lan;
113a551c94aSIdo Barnea	phy->ops.get_info	= e1000_get_phy_info_m88;
114a551c94aSIdo Barnea	phy->ops.release	= e1000_release_phy_80003es2lan;
115a551c94aSIdo Barnea	phy->ops.reset		= e1000_phy_hw_reset_generic;
116a551c94aSIdo Barnea	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
117a551c94aSIdo Barnea
118a551c94aSIdo Barnea	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
119a551c94aSIdo Barnea	phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
120a551c94aSIdo Barnea	phy->ops.read_reg	= e1000_read_phy_reg_gg82563_80003es2lan;
121a551c94aSIdo Barnea	phy->ops.write_reg	= e1000_write_phy_reg_gg82563_80003es2lan;
122a551c94aSIdo Barnea
123a551c94aSIdo Barnea	phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
124a551c94aSIdo Barnea
125a551c94aSIdo Barnea	/* This can only be done after all function pointers are setup. */
126a551c94aSIdo Barnea	ret_val = e1000_get_phy_id(hw);
127a551c94aSIdo Barnea
128a551c94aSIdo Barnea	/* Verify phy id */
129a551c94aSIdo Barnea	if (phy->id != GG82563_E_PHY_ID)
130a551c94aSIdo Barnea		return -E1000_ERR_PHY;
131a551c94aSIdo Barnea
132a551c94aSIdo Barnea	return ret_val;
133a551c94aSIdo Barnea}
134a551c94aSIdo Barnea
135a551c94aSIdo Barnea/**
136a551c94aSIdo Barnea *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
137a551c94aSIdo Barnea *  @hw: pointer to the HW structure
138a551c94aSIdo Barnea **/
139a551c94aSIdo BarneaSTATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
140a551c94aSIdo Barnea{
141a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
142a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
143a551c94aSIdo Barnea	u16 size;
144a551c94aSIdo Barnea
145a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
146a551c94aSIdo Barnea
147a551c94aSIdo Barnea	nvm->opcode_bits = 8;
148a551c94aSIdo Barnea	nvm->delay_usec = 1;
149a551c94aSIdo Barnea	switch (nvm->override) {
150a551c94aSIdo Barnea	case e1000_nvm_override_spi_large:
151a551c94aSIdo Barnea		nvm->page_size = 32;
152a551c94aSIdo Barnea		nvm->address_bits = 16;
153a551c94aSIdo Barnea		break;
154a551c94aSIdo Barnea	case e1000_nvm_override_spi_small:
155a551c94aSIdo Barnea		nvm->page_size = 8;
156a551c94aSIdo Barnea		nvm->address_bits = 8;
157a551c94aSIdo Barnea		break;
158a551c94aSIdo Barnea	default:
159a551c94aSIdo Barnea		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
160a551c94aSIdo Barnea		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
161a551c94aSIdo Barnea		break;
162a551c94aSIdo Barnea	}
163a551c94aSIdo Barnea
164a551c94aSIdo Barnea	nvm->type = e1000_nvm_eeprom_spi;
165a551c94aSIdo Barnea
166a551c94aSIdo Barnea	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
167a551c94aSIdo Barnea		     E1000_EECD_SIZE_EX_SHIFT);
168a551c94aSIdo Barnea
169a551c94aSIdo Barnea	/* Added to a constant, "size" becomes the left-shift value
170a551c94aSIdo Barnea	 * for setting word_size.
171a551c94aSIdo Barnea	 */
172a551c94aSIdo Barnea	size += NVM_WORD_SIZE_BASE_SHIFT;
173a551c94aSIdo Barnea
174a551c94aSIdo Barnea	/* EEPROM access above 16k is unsupported */
175a551c94aSIdo Barnea	if (size > 14)
176a551c94aSIdo Barnea		size = 14;
177a551c94aSIdo Barnea	nvm->word_size = 1 << size;
178a551c94aSIdo Barnea
179a551c94aSIdo Barnea	/* Function Pointers */
180a551c94aSIdo Barnea	nvm->ops.acquire	= e1000_acquire_nvm_80003es2lan;
181a551c94aSIdo Barnea	nvm->ops.read		= e1000_read_nvm_eerd;
182a551c94aSIdo Barnea	nvm->ops.release	= e1000_release_nvm_80003es2lan;
183a551c94aSIdo Barnea	nvm->ops.update		= e1000_update_nvm_checksum_generic;
184a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
185a551c94aSIdo Barnea	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
186a551c94aSIdo Barnea	nvm->ops.write		= e1000_write_nvm_80003es2lan;
187a551c94aSIdo Barnea
188a551c94aSIdo Barnea	return E1000_SUCCESS;
189a551c94aSIdo Barnea}
190a551c94aSIdo Barnea
191a551c94aSIdo Barnea/**
192a551c94aSIdo Barnea *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
193a551c94aSIdo Barnea *  @hw: pointer to the HW structure
194a551c94aSIdo Barnea **/
195a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
196a551c94aSIdo Barnea{
197a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
198a551c94aSIdo Barnea
199a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_80003es2lan");
200a551c94aSIdo Barnea
201a551c94aSIdo Barnea	/* Set media type and media-dependent function pointers */
202a551c94aSIdo Barnea	switch (hw->device_id) {
203a551c94aSIdo Barnea	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
204a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_internal_serdes;
205a551c94aSIdo Barnea		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
206a551c94aSIdo Barnea		mac->ops.setup_physical_interface =
207a551c94aSIdo Barnea					e1000_setup_fiber_serdes_link_generic;
208a551c94aSIdo Barnea		break;
209a551c94aSIdo Barnea	default:
210a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_copper;
211a551c94aSIdo Barnea		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
212a551c94aSIdo Barnea		mac->ops.setup_physical_interface =
213a551c94aSIdo Barnea					e1000_setup_copper_link_80003es2lan;
214a551c94aSIdo Barnea		break;
215a551c94aSIdo Barnea	}
216a551c94aSIdo Barnea
217a551c94aSIdo Barnea	/* Set mta register count */
218a551c94aSIdo Barnea	mac->mta_reg_count = 128;
219a551c94aSIdo Barnea	/* Set rar entry count */
220a551c94aSIdo Barnea	mac->rar_entry_count = E1000_RAR_ENTRIES;
221a551c94aSIdo Barnea	/* Set if part includes ASF firmware */
222a551c94aSIdo Barnea	mac->asf_firmware_present = true;
223a551c94aSIdo Barnea	/* FWSM register */
224a551c94aSIdo Barnea	mac->has_fwsm = true;
225a551c94aSIdo Barnea	/* ARC supported; valid only if manageability features are enabled. */
226a551c94aSIdo Barnea	mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
227a551c94aSIdo Barnea				      E1000_FWSM_MODE_MASK);
228a551c94aSIdo Barnea	/* Adaptive IFS not supported */
229a551c94aSIdo Barnea	mac->adaptive_ifs = false;
230a551c94aSIdo Barnea
231a551c94aSIdo Barnea	/* Function pointers */
232a551c94aSIdo Barnea
233a551c94aSIdo Barnea	/* bus type/speed/width */
234a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
235a551c94aSIdo Barnea	/* reset */
236a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
237a551c94aSIdo Barnea	/* hw initialization */
238a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_80003es2lan;
239a551c94aSIdo Barnea	/* link setup */
240a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_generic;
241a551c94aSIdo Barnea	/* check management mode */
242a551c94aSIdo Barnea	mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
243a551c94aSIdo Barnea	/* multicast address update */
244a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
245a551c94aSIdo Barnea	/* writing VFTA */
246a551c94aSIdo Barnea	mac->ops.write_vfta = e1000_write_vfta_generic;
247a551c94aSIdo Barnea	/* clearing VFTA */
248a551c94aSIdo Barnea	mac->ops.clear_vfta = e1000_clear_vfta_generic;
249a551c94aSIdo Barnea	/* read mac address */
250a551c94aSIdo Barnea	mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
251a551c94aSIdo Barnea	/* ID LED init */
252a551c94aSIdo Barnea	mac->ops.id_led_init = e1000_id_led_init_generic;
253a551c94aSIdo Barnea	/* blink LED */
254a551c94aSIdo Barnea	mac->ops.blink_led = e1000_blink_led_generic;
255a551c94aSIdo Barnea	/* setup LED */
256a551c94aSIdo Barnea	mac->ops.setup_led = e1000_setup_led_generic;
257a551c94aSIdo Barnea	/* cleanup LED */
258a551c94aSIdo Barnea	mac->ops.cleanup_led = e1000_cleanup_led_generic;
259a551c94aSIdo Barnea	/* turn on/off LED */
260a551c94aSIdo Barnea	mac->ops.led_on = e1000_led_on_generic;
261a551c94aSIdo Barnea	mac->ops.led_off = e1000_led_off_generic;
262a551c94aSIdo Barnea	/* clear hardware counters */
263a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
264a551c94aSIdo Barnea	/* link info */
265a551c94aSIdo Barnea	mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
266a551c94aSIdo Barnea
267a551c94aSIdo Barnea	/* set lan id for port to determine which phy lock to use */
268a551c94aSIdo Barnea	hw->mac.ops.set_lan_id(hw);
269a551c94aSIdo Barnea
270a551c94aSIdo Barnea	return E1000_SUCCESS;
271a551c94aSIdo Barnea}
272a551c94aSIdo Barnea
273a551c94aSIdo Barnea/**
274a551c94aSIdo Barnea *  e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
275a551c94aSIdo Barnea *  @hw: pointer to the HW structure
276a551c94aSIdo Barnea *
277a551c94aSIdo Barnea *  Called to initialize all function pointers and parameters.
278a551c94aSIdo Barnea **/
279a551c94aSIdo Barneavoid e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
280a551c94aSIdo Barnea{
281a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
282a551c94aSIdo Barnea
283a551c94aSIdo Barnea	hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
284a551c94aSIdo Barnea	hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
285a551c94aSIdo Barnea	hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
286a551c94aSIdo Barnea}
287a551c94aSIdo Barnea
288a551c94aSIdo Barnea/**
289a551c94aSIdo Barnea *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
290a551c94aSIdo Barnea *  @hw: pointer to the HW structure
291a551c94aSIdo Barnea *
292a551c94aSIdo Barnea *  A wrapper to acquire access rights to the correct PHY.
293a551c94aSIdo Barnea **/
294a551c94aSIdo BarneaSTATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
295a551c94aSIdo Barnea{
296a551c94aSIdo Barnea	u16 mask;
297a551c94aSIdo Barnea
298a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_phy_80003es2lan");
299a551c94aSIdo Barnea
300a551c94aSIdo Barnea	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
301a551c94aSIdo Barnea	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
302a551c94aSIdo Barnea}
303a551c94aSIdo Barnea
304a551c94aSIdo Barnea/**
305a551c94aSIdo Barnea *  e1000_release_phy_80003es2lan - Release rights to access PHY
306a551c94aSIdo Barnea *  @hw: pointer to the HW structure
307a551c94aSIdo Barnea *
308a551c94aSIdo Barnea *  A wrapper to release access rights to the correct PHY.
309a551c94aSIdo Barnea **/
310a551c94aSIdo BarneaSTATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
311a551c94aSIdo Barnea{
312a551c94aSIdo Barnea	u16 mask;
313a551c94aSIdo Barnea
314a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_phy_80003es2lan");
315a551c94aSIdo Barnea
316a551c94aSIdo Barnea	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
317a551c94aSIdo Barnea	e1000_release_swfw_sync_80003es2lan(hw, mask);
318a551c94aSIdo Barnea}
319a551c94aSIdo Barnea
320a551c94aSIdo Barnea/**
321a551c94aSIdo Barnea *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
322a551c94aSIdo Barnea *  @hw: pointer to the HW structure
323a551c94aSIdo Barnea *
324a551c94aSIdo Barnea *  Acquire the semaphore to access the Kumeran interface.
325a551c94aSIdo Barnea *
326a551c94aSIdo Barnea **/
327a551c94aSIdo BarneaSTATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
328a551c94aSIdo Barnea{
329a551c94aSIdo Barnea	u16 mask;
330a551c94aSIdo Barnea
331a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
332a551c94aSIdo Barnea
333a551c94aSIdo Barnea	mask = E1000_SWFW_CSR_SM;
334a551c94aSIdo Barnea
335a551c94aSIdo Barnea	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
336a551c94aSIdo Barnea}
337a551c94aSIdo Barnea
338a551c94aSIdo Barnea/**
339a551c94aSIdo Barnea *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
340a551c94aSIdo Barnea *  @hw: pointer to the HW structure
341a551c94aSIdo Barnea *
342a551c94aSIdo Barnea *  Release the semaphore used to access the Kumeran interface
343a551c94aSIdo Barnea **/
344a551c94aSIdo BarneaSTATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
345a551c94aSIdo Barnea{
346a551c94aSIdo Barnea	u16 mask;
347a551c94aSIdo Barnea
348a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
349a551c94aSIdo Barnea
350a551c94aSIdo Barnea	mask = E1000_SWFW_CSR_SM;
351a551c94aSIdo Barnea
352a551c94aSIdo Barnea	e1000_release_swfw_sync_80003es2lan(hw, mask);
353a551c94aSIdo Barnea}
354a551c94aSIdo Barnea
355a551c94aSIdo Barnea/**
356a551c94aSIdo Barnea *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
357a551c94aSIdo Barnea *  @hw: pointer to the HW structure
358a551c94aSIdo Barnea *
359a551c94aSIdo Barnea *  Acquire the semaphore to access the EEPROM.
360a551c94aSIdo Barnea **/
361a551c94aSIdo BarneaSTATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
362a551c94aSIdo Barnea{
363a551c94aSIdo Barnea	s32 ret_val;
364a551c94aSIdo Barnea
365a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
366a551c94aSIdo Barnea
367a551c94aSIdo Barnea	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
368a551c94aSIdo Barnea	if (ret_val)
369a551c94aSIdo Barnea		return ret_val;
370a551c94aSIdo Barnea
371a551c94aSIdo Barnea	ret_val = e1000_acquire_nvm_generic(hw);
372a551c94aSIdo Barnea
373a551c94aSIdo Barnea	if (ret_val)
374a551c94aSIdo Barnea		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
375a551c94aSIdo Barnea
376a551c94aSIdo Barnea	return ret_val;
377a551c94aSIdo Barnea}
378a551c94aSIdo Barnea
379a551c94aSIdo Barnea/**
380a551c94aSIdo Barnea *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
381a551c94aSIdo Barnea *  @hw: pointer to the HW structure
382a551c94aSIdo Barnea *
383a551c94aSIdo Barnea *  Release the semaphore used to access the EEPROM.
384a551c94aSIdo Barnea **/
385a551c94aSIdo BarneaSTATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
386a551c94aSIdo Barnea{
387a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_nvm_80003es2lan");
388a551c94aSIdo Barnea
389a551c94aSIdo Barnea	e1000_release_nvm_generic(hw);
390a551c94aSIdo Barnea	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
391a551c94aSIdo Barnea}
392a551c94aSIdo Barnea
393a551c94aSIdo Barnea/**
394a551c94aSIdo Barnea *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
395a551c94aSIdo Barnea *  @hw: pointer to the HW structure
396a551c94aSIdo Barnea *  @mask: specifies which semaphore to acquire
397a551c94aSIdo Barnea *
398a551c94aSIdo Barnea *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
399a551c94aSIdo Barnea *  will also specify which port we're acquiring the lock for.
400a551c94aSIdo Barnea **/
401a551c94aSIdo BarneaSTATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
402a551c94aSIdo Barnea{
403a551c94aSIdo Barnea	u32 swfw_sync;
404a551c94aSIdo Barnea	u32 swmask = mask;
405a551c94aSIdo Barnea	u32 fwmask = mask << 16;
406a551c94aSIdo Barnea	s32 i = 0;
407a551c94aSIdo Barnea	s32 timeout = 50;
408a551c94aSIdo Barnea
409a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
410a551c94aSIdo Barnea
411a551c94aSIdo Barnea	while (i < timeout) {
412a551c94aSIdo Barnea		if (e1000_get_hw_semaphore_generic(hw))
413a551c94aSIdo Barnea			return -E1000_ERR_SWFW_SYNC;
414a551c94aSIdo Barnea
415a551c94aSIdo Barnea		swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
416a551c94aSIdo Barnea		if (!(swfw_sync & (fwmask | swmask)))
417a551c94aSIdo Barnea			break;
418a551c94aSIdo Barnea
419a551c94aSIdo Barnea		/* Firmware currently using resource (fwmask)
420a551c94aSIdo Barnea		 * or other software thread using resource (swmask)
421a551c94aSIdo Barnea		 */
422a551c94aSIdo Barnea		e1000_put_hw_semaphore_generic(hw);
423a551c94aSIdo Barnea		msec_delay_irq(5);
424a551c94aSIdo Barnea		i++;
425a551c94aSIdo Barnea	}
426a551c94aSIdo Barnea
427a551c94aSIdo Barnea	if (i == timeout) {
428a551c94aSIdo Barnea		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
429a551c94aSIdo Barnea		return -E1000_ERR_SWFW_SYNC;
430a551c94aSIdo Barnea	}
431a551c94aSIdo Barnea
432a551c94aSIdo Barnea	swfw_sync |= swmask;
433a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
434a551c94aSIdo Barnea
435a551c94aSIdo Barnea	e1000_put_hw_semaphore_generic(hw);
436a551c94aSIdo Barnea
437a551c94aSIdo Barnea	return E1000_SUCCESS;
438a551c94aSIdo Barnea}
439a551c94aSIdo Barnea
440a551c94aSIdo Barnea/**
441a551c94aSIdo Barnea *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
442a551c94aSIdo Barnea *  @hw: pointer to the HW structure
443a551c94aSIdo Barnea *  @mask: specifies which semaphore to acquire
444a551c94aSIdo Barnea *
445a551c94aSIdo Barnea *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
446a551c94aSIdo Barnea *  will also specify which port we're releasing the lock for.
447a551c94aSIdo Barnea **/
448a551c94aSIdo BarneaSTATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
449a551c94aSIdo Barnea{
450a551c94aSIdo Barnea	u32 swfw_sync;
451a551c94aSIdo Barnea
452a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
453a551c94aSIdo Barnea
454a551c94aSIdo Barnea	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
455a551c94aSIdo Barnea		; /* Empty */
456a551c94aSIdo Barnea
457a551c94aSIdo Barnea	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
458a551c94aSIdo Barnea	swfw_sync &= ~mask;
459a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
460a551c94aSIdo Barnea
461a551c94aSIdo Barnea	e1000_put_hw_semaphore_generic(hw);
462a551c94aSIdo Barnea}
463a551c94aSIdo Barnea
464a551c94aSIdo Barnea/**
465a551c94aSIdo Barnea *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
466a551c94aSIdo Barnea *  @hw: pointer to the HW structure
467a551c94aSIdo Barnea *  @offset: offset of the register to read
468a551c94aSIdo Barnea *  @data: pointer to the data returned from the operation
469a551c94aSIdo Barnea *
470a551c94aSIdo Barnea *  Read the GG82563 PHY register.
471a551c94aSIdo Barnea **/
472a551c94aSIdo BarneaSTATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
473a551c94aSIdo Barnea						  u32 offset, u16 *data)
474a551c94aSIdo Barnea{
475a551c94aSIdo Barnea	s32 ret_val;
476a551c94aSIdo Barnea	u32 page_select;
477a551c94aSIdo Barnea	u16 temp;
478a551c94aSIdo Barnea
479a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
480a551c94aSIdo Barnea
481a551c94aSIdo Barnea	ret_val = e1000_acquire_phy_80003es2lan(hw);
482a551c94aSIdo Barnea	if (ret_val)
483a551c94aSIdo Barnea		return ret_val;
484a551c94aSIdo Barnea
485a551c94aSIdo Barnea	/* Select Configuration Page */
486a551c94aSIdo Barnea	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
487a551c94aSIdo Barnea		page_select = GG82563_PHY_PAGE_SELECT;
488a551c94aSIdo Barnea	} else {
489a551c94aSIdo Barnea		/* Use Alternative Page Select register to access
490a551c94aSIdo Barnea		 * registers 30 and 31
491a551c94aSIdo Barnea		 */
492a551c94aSIdo Barnea		page_select = GG82563_PHY_PAGE_SELECT_ALT;
493a551c94aSIdo Barnea	}
494a551c94aSIdo Barnea
495a551c94aSIdo Barnea	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
496a551c94aSIdo Barnea	ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
497a551c94aSIdo Barnea	if (ret_val) {
498a551c94aSIdo Barnea		e1000_release_phy_80003es2lan(hw);
499a551c94aSIdo Barnea		return ret_val;
500a551c94aSIdo Barnea	}
501a551c94aSIdo Barnea
502a551c94aSIdo Barnea	if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
503a551c94aSIdo Barnea		/* The "ready" bit in the MDIC register may be incorrectly set
504a551c94aSIdo Barnea		 * before the device has completed the "Page Select" MDI
505a551c94aSIdo Barnea		 * transaction.  So we wait 200us after each MDI command...
506a551c94aSIdo Barnea		 */
507a551c94aSIdo Barnea		usec_delay(200);
508a551c94aSIdo Barnea
509a551c94aSIdo Barnea		/* ...and verify the command was successful. */
510a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
511a551c94aSIdo Barnea
512a551c94aSIdo Barnea		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
513a551c94aSIdo Barnea			e1000_release_phy_80003es2lan(hw);
514a551c94aSIdo Barnea			return -E1000_ERR_PHY;
515a551c94aSIdo Barnea		}
516a551c94aSIdo Barnea
517a551c94aSIdo Barnea		usec_delay(200);
518a551c94aSIdo Barnea
519a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_mdic(hw,
520a551c94aSIdo Barnea						  MAX_PHY_REG_ADDRESS & offset,
521a551c94aSIdo Barnea						  data);
522a551c94aSIdo Barnea
523a551c94aSIdo Barnea		usec_delay(200);
524a551c94aSIdo Barnea	} else {
525a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_mdic(hw,
526a551c94aSIdo Barnea						  MAX_PHY_REG_ADDRESS & offset,
527a551c94aSIdo Barnea						  data);
528a551c94aSIdo Barnea	}
529a551c94aSIdo Barnea
530a551c94aSIdo Barnea	e1000_release_phy_80003es2lan(hw);
531a551c94aSIdo Barnea
532a551c94aSIdo Barnea	return ret_val;
533a551c94aSIdo Barnea}
534a551c94aSIdo Barnea
535a551c94aSIdo Barnea/**
536a551c94aSIdo Barnea *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
537a551c94aSIdo Barnea *  @hw: pointer to the HW structure
538a551c94aSIdo Barnea *  @offset: offset of the register to read
539a551c94aSIdo Barnea *  @data: value to write to the register
540a551c94aSIdo Barnea *
541a551c94aSIdo Barnea *  Write to the GG82563 PHY register.
542a551c94aSIdo Barnea **/
543a551c94aSIdo BarneaSTATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
544a551c94aSIdo Barnea						   u32 offset, u16 data)
545a551c94aSIdo Barnea{
546a551c94aSIdo Barnea	s32 ret_val;
547a551c94aSIdo Barnea	u32 page_select;
548a551c94aSIdo Barnea	u16 temp;
549a551c94aSIdo Barnea
550a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
551a551c94aSIdo Barnea
552a551c94aSIdo Barnea	ret_val = e1000_acquire_phy_80003es2lan(hw);
553a551c94aSIdo Barnea	if (ret_val)
554a551c94aSIdo Barnea		return ret_val;
555a551c94aSIdo Barnea
556a551c94aSIdo Barnea	/* Select Configuration Page */
557a551c94aSIdo Barnea	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
558a551c94aSIdo Barnea		page_select = GG82563_PHY_PAGE_SELECT;
559a551c94aSIdo Barnea	} else {
560a551c94aSIdo Barnea		/* Use Alternative Page Select register to access
561a551c94aSIdo Barnea		 * registers 30 and 31
562a551c94aSIdo Barnea		 */
563a551c94aSIdo Barnea		page_select = GG82563_PHY_PAGE_SELECT_ALT;
564a551c94aSIdo Barnea	}
565a551c94aSIdo Barnea
566a551c94aSIdo Barnea	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
567a551c94aSIdo Barnea	ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
568a551c94aSIdo Barnea	if (ret_val) {
569a551c94aSIdo Barnea		e1000_release_phy_80003es2lan(hw);
570a551c94aSIdo Barnea		return ret_val;
571a551c94aSIdo Barnea	}
572a551c94aSIdo Barnea
573a551c94aSIdo Barnea	if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
574a551c94aSIdo Barnea		/* The "ready" bit in the MDIC register may be incorrectly set
575a551c94aSIdo Barnea		 * before the device has completed the "Page Select" MDI
576a551c94aSIdo Barnea		 * transaction.  So we wait 200us after each MDI command...
577a551c94aSIdo Barnea		 */
578a551c94aSIdo Barnea		usec_delay(200);
579a551c94aSIdo Barnea
580a551c94aSIdo Barnea		/* ...and verify the command was successful. */
581a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
582a551c94aSIdo Barnea
583a551c94aSIdo Barnea		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
584a551c94aSIdo Barnea			e1000_release_phy_80003es2lan(hw);
585a551c94aSIdo Barnea			return -E1000_ERR_PHY;
586a551c94aSIdo Barnea		}
587a551c94aSIdo Barnea
588a551c94aSIdo Barnea		usec_delay(200);
589a551c94aSIdo Barnea
590a551c94aSIdo Barnea		ret_val = e1000_write_phy_reg_mdic(hw,
591a551c94aSIdo Barnea						  MAX_PHY_REG_ADDRESS & offset,
592a551c94aSIdo Barnea						  data);
593a551c94aSIdo Barnea
594a551c94aSIdo Barnea		usec_delay(200);
595a551c94aSIdo Barnea	} else {
596a551c94aSIdo Barnea		ret_val = e1000_write_phy_reg_mdic(hw,
597a551c94aSIdo Barnea						  MAX_PHY_REG_ADDRESS & offset,
598a551c94aSIdo Barnea						  data);
599a551c94aSIdo Barnea	}
600a551c94aSIdo Barnea
601a551c94aSIdo Barnea	e1000_release_phy_80003es2lan(hw);
602a551c94aSIdo Barnea
603a551c94aSIdo Barnea	return ret_val;
604a551c94aSIdo Barnea}
605a551c94aSIdo Barnea
606a551c94aSIdo Barnea/**
607a551c94aSIdo Barnea *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
608a551c94aSIdo Barnea *  @hw: pointer to the HW structure
609a551c94aSIdo Barnea *  @offset: offset of the register to read
610a551c94aSIdo Barnea *  @words: number of words to write
611a551c94aSIdo Barnea *  @data: buffer of data to write to the NVM
612a551c94aSIdo Barnea *
613a551c94aSIdo Barnea *  Write "words" of data to the ESB2 NVM.
614a551c94aSIdo Barnea **/
615a551c94aSIdo BarneaSTATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
616a551c94aSIdo Barnea				       u16 words, u16 *data)
617a551c94aSIdo Barnea{
618a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_nvm_80003es2lan");
619a551c94aSIdo Barnea
620a551c94aSIdo Barnea	return e1000_write_nvm_spi(hw, offset, words, data);
621a551c94aSIdo Barnea}
622a551c94aSIdo Barnea
623a551c94aSIdo Barnea/**
624a551c94aSIdo Barnea *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
625a551c94aSIdo Barnea *  @hw: pointer to the HW structure
626a551c94aSIdo Barnea *
627a551c94aSIdo Barnea *  Wait a specific amount of time for manageability processes to complete.
628a551c94aSIdo Barnea *  This is a function pointer entry point called by the phy module.
629a551c94aSIdo Barnea **/
630a551c94aSIdo BarneaSTATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
631a551c94aSIdo Barnea{
632a551c94aSIdo Barnea	s32 timeout = PHY_CFG_TIMEOUT;
633a551c94aSIdo Barnea	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
634a551c94aSIdo Barnea
635a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
636a551c94aSIdo Barnea
637a551c94aSIdo Barnea	if (hw->bus.func == 1)
638a551c94aSIdo Barnea		mask = E1000_NVM_CFG_DONE_PORT_1;
639a551c94aSIdo Barnea
640a551c94aSIdo Barnea	while (timeout) {
641a551c94aSIdo Barnea		if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
642a551c94aSIdo Barnea			break;
643a551c94aSIdo Barnea		msec_delay(1);
644a551c94aSIdo Barnea		timeout--;
645a551c94aSIdo Barnea	}
646a551c94aSIdo Barnea	if (!timeout) {
647a551c94aSIdo Barnea		DEBUGOUT("MNG configuration cycle has not completed.\n");
648a551c94aSIdo Barnea		return -E1000_ERR_RESET;
649a551c94aSIdo Barnea	}
650a551c94aSIdo Barnea
651a551c94aSIdo Barnea	return E1000_SUCCESS;
652a551c94aSIdo Barnea}
653a551c94aSIdo Barnea
654a551c94aSIdo Barnea/**
655a551c94aSIdo Barnea *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
656a551c94aSIdo Barnea *  @hw: pointer to the HW structure
657a551c94aSIdo Barnea *
658a551c94aSIdo Barnea *  Force the speed and duplex settings onto the PHY.  This is a
659a551c94aSIdo Barnea *  function pointer entry point called by the phy module.
660a551c94aSIdo Barnea **/
661a551c94aSIdo BarneaSTATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
662a551c94aSIdo Barnea{
663a551c94aSIdo Barnea	s32 ret_val;
664a551c94aSIdo Barnea	u16 phy_data;
665a551c94aSIdo Barnea	bool link;
666a551c94aSIdo Barnea
667a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
668a551c94aSIdo Barnea
669a551c94aSIdo Barnea	if (!(hw->phy.ops.read_reg))
670a551c94aSIdo Barnea		return E1000_SUCCESS;
671a551c94aSIdo Barnea
672a551c94aSIdo Barnea	/* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
673a551c94aSIdo Barnea	 * forced whenever speed and duplex are forced.
674a551c94aSIdo Barnea	 */
675a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
676a551c94aSIdo Barnea	if (ret_val)
677a551c94aSIdo Barnea		return ret_val;
678a551c94aSIdo Barnea
679a551c94aSIdo Barnea	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
680a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
681a551c94aSIdo Barnea	if (ret_val)
682a551c94aSIdo Barnea		return ret_val;
683a551c94aSIdo Barnea
684a551c94aSIdo Barnea	DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
685a551c94aSIdo Barnea
686a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
687a551c94aSIdo Barnea	if (ret_val)
688a551c94aSIdo Barnea		return ret_val;
689a551c94aSIdo Barnea
690a551c94aSIdo Barnea	e1000_phy_force_speed_duplex_setup(hw, &phy_data);
691a551c94aSIdo Barnea
692a551c94aSIdo Barnea	/* Reset the phy to commit changes. */
693a551c94aSIdo Barnea	phy_data |= MII_CR_RESET;
694a551c94aSIdo Barnea
695a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
696a551c94aSIdo Barnea	if (ret_val)
697a551c94aSIdo Barnea		return ret_val;
698a551c94aSIdo Barnea
699a551c94aSIdo Barnea	usec_delay(1);
700a551c94aSIdo Barnea
701a551c94aSIdo Barnea	if (hw->phy.autoneg_wait_to_complete) {
702a551c94aSIdo Barnea		DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
703a551c94aSIdo Barnea
704a551c94aSIdo Barnea		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
705a551c94aSIdo Barnea						     100000, &link);
706a551c94aSIdo Barnea		if (ret_val)
707a551c94aSIdo Barnea			return ret_val;
708a551c94aSIdo Barnea
709a551c94aSIdo Barnea		if (!link) {
710a551c94aSIdo Barnea			/* We didn't get link.
711a551c94aSIdo Barnea			 * Reset the DSP and cross our fingers.
712a551c94aSIdo Barnea			 */
713a551c94aSIdo Barnea			ret_val = e1000_phy_reset_dsp_generic(hw);
714a551c94aSIdo Barnea			if (ret_val)
715a551c94aSIdo Barnea				return ret_val;
716a551c94aSIdo Barnea		}
717a551c94aSIdo Barnea
718a551c94aSIdo Barnea		/* Try once more */
719a551c94aSIdo Barnea		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
720a551c94aSIdo Barnea						     100000, &link);
721a551c94aSIdo Barnea		if (ret_val)
722a551c94aSIdo Barnea			return ret_val;
723a551c94aSIdo Barnea	}
724a551c94aSIdo Barnea
725a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
726a551c94aSIdo Barnea				       &phy_data);
727a551c94aSIdo Barnea	if (ret_val)
728a551c94aSIdo Barnea		return ret_val;
729a551c94aSIdo Barnea
730a551c94aSIdo Barnea	/* Resetting the phy means we need to verify the TX_CLK corresponds
731a551c94aSIdo Barnea	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
732a551c94aSIdo Barnea	 */
733a551c94aSIdo Barnea	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
734a551c94aSIdo Barnea	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
735a551c94aSIdo Barnea		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
736a551c94aSIdo Barnea	else
737a551c94aSIdo Barnea		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
738a551c94aSIdo Barnea
739a551c94aSIdo Barnea	/* In addition, we must re-enable CRS on Tx for both half and full
740a551c94aSIdo Barnea	 * duplex.
741a551c94aSIdo Barnea	 */
742a551c94aSIdo Barnea	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
743a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
744a551c94aSIdo Barnea					phy_data);
745a551c94aSIdo Barnea
746a551c94aSIdo Barnea	return ret_val;
747a551c94aSIdo Barnea}
748a551c94aSIdo Barnea
749a551c94aSIdo Barnea/**
750a551c94aSIdo Barnea *  e1000_get_cable_length_80003es2lan - Set approximate cable length
751a551c94aSIdo Barnea *  @hw: pointer to the HW structure
752a551c94aSIdo Barnea *
753a551c94aSIdo Barnea *  Find the approximate cable length as measured by the GG82563 PHY.
754a551c94aSIdo Barnea *  This is a function pointer entry point called by the phy module.
755a551c94aSIdo Barnea **/
756a551c94aSIdo BarneaSTATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
757a551c94aSIdo Barnea{
758a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
759a551c94aSIdo Barnea	s32 ret_val;
760a551c94aSIdo Barnea	u16 phy_data, index;
761a551c94aSIdo Barnea
762a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_cable_length_80003es2lan");
763a551c94aSIdo Barnea
764a551c94aSIdo Barnea	if (!(hw->phy.ops.read_reg))
765a551c94aSIdo Barnea		return E1000_SUCCESS;
766a551c94aSIdo Barnea
767a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
768a551c94aSIdo Barnea	if (ret_val)
769a551c94aSIdo Barnea		return ret_val;
770a551c94aSIdo Barnea
771a551c94aSIdo Barnea	index = phy_data & GG82563_DSPD_CABLE_LENGTH;
772a551c94aSIdo Barnea
773a551c94aSIdo Barnea	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
774a551c94aSIdo Barnea		return -E1000_ERR_PHY;
775a551c94aSIdo Barnea
776a551c94aSIdo Barnea	phy->min_cable_length = e1000_gg82563_cable_length_table[index];
777a551c94aSIdo Barnea	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
778a551c94aSIdo Barnea
779a551c94aSIdo Barnea	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
780a551c94aSIdo Barnea
781a551c94aSIdo Barnea	return E1000_SUCCESS;
782a551c94aSIdo Barnea}
783a551c94aSIdo Barnea
784a551c94aSIdo Barnea/**
785a551c94aSIdo Barnea *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
786a551c94aSIdo Barnea *  @hw: pointer to the HW structure
787a551c94aSIdo Barnea *  @speed: pointer to speed buffer
788a551c94aSIdo Barnea *  @duplex: pointer to duplex buffer
789a551c94aSIdo Barnea *
790a551c94aSIdo Barnea *  Retrieve the current speed and duplex configuration.
791a551c94aSIdo Barnea **/
792a551c94aSIdo BarneaSTATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
793a551c94aSIdo Barnea					      u16 *duplex)
794a551c94aSIdo Barnea{
795a551c94aSIdo Barnea	s32 ret_val;
796a551c94aSIdo Barnea
797a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
798a551c94aSIdo Barnea
799a551c94aSIdo Barnea	if (hw->phy.media_type == e1000_media_type_copper) {
800a551c94aSIdo Barnea		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
801a551c94aSIdo Barnea								    duplex);
802a551c94aSIdo Barnea		hw->phy.ops.cfg_on_link_up(hw);
803a551c94aSIdo Barnea	} else {
804a551c94aSIdo Barnea		ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
805a551c94aSIdo Barnea								  speed,
806a551c94aSIdo Barnea								  duplex);
807a551c94aSIdo Barnea	}
808a551c94aSIdo Barnea
809a551c94aSIdo Barnea	return ret_val;
810a551c94aSIdo Barnea}
811a551c94aSIdo Barnea
812a551c94aSIdo Barnea/**
813a551c94aSIdo Barnea *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
814a551c94aSIdo Barnea *  @hw: pointer to the HW structure
815a551c94aSIdo Barnea *
816a551c94aSIdo Barnea *  Perform a global reset to the ESB2 controller.
817a551c94aSIdo Barnea **/
818a551c94aSIdo BarneaSTATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
819a551c94aSIdo Barnea{
820a551c94aSIdo Barnea	u32 ctrl;
821a551c94aSIdo Barnea	s32 ret_val;
822a551c94aSIdo Barnea	u16 kum_reg_data;
823a551c94aSIdo Barnea
824a551c94aSIdo Barnea	DEBUGFUNC("e1000_reset_hw_80003es2lan");
825a551c94aSIdo Barnea
826a551c94aSIdo Barnea	/* Prevent the PCI-E bus from sticking if there is no TLP connection
827a551c94aSIdo Barnea	 * on the last TLP read/write transaction when MAC is reset.
828a551c94aSIdo Barnea	 */
829a551c94aSIdo Barnea	ret_val = e1000_disable_pcie_master_generic(hw);
830a551c94aSIdo Barnea	if (ret_val)
831a551c94aSIdo Barnea		DEBUGOUT("PCI-E Master disable polling has failed.\n");
832a551c94aSIdo Barnea
833a551c94aSIdo Barnea	DEBUGOUT("Masking off all interrupts\n");
834a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
835a551c94aSIdo Barnea
836a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RCTL, 0);
837a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
838a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
839a551c94aSIdo Barnea
840a551c94aSIdo Barnea	msec_delay(10);
841a551c94aSIdo Barnea
842a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
843a551c94aSIdo Barnea
844a551c94aSIdo Barnea	ret_val = e1000_acquire_phy_80003es2lan(hw);
845a551c94aSIdo Barnea	if (ret_val)
846a551c94aSIdo Barnea		return ret_val;
847a551c94aSIdo Barnea
848a551c94aSIdo Barnea	DEBUGOUT("Issuing a global reset to MAC\n");
849a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
850a551c94aSIdo Barnea	e1000_release_phy_80003es2lan(hw);
851a551c94aSIdo Barnea
852a551c94aSIdo Barnea	/* Disable IBIST slave mode (far-end loopback) */
853a551c94aSIdo Barnea	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
854a551c94aSIdo Barnea				E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
855a551c94aSIdo Barnea	if (!ret_val) {
856a551c94aSIdo Barnea		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
857a551c94aSIdo Barnea		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
858a551c94aSIdo Barnea						 E1000_KMRNCTRLSTA_INBAND_PARAM,
859a551c94aSIdo Barnea						 kum_reg_data);
860a551c94aSIdo Barnea		if (ret_val)
861a551c94aSIdo Barnea			DEBUGOUT("Error disabling far-end loopback\n");
862a551c94aSIdo Barnea	} else
863a551c94aSIdo Barnea		DEBUGOUT("Error disabling far-end loopback\n");
864a551c94aSIdo Barnea
865a551c94aSIdo Barnea	ret_val = e1000_get_auto_rd_done_generic(hw);
866a551c94aSIdo Barnea	if (ret_val)
867a551c94aSIdo Barnea		/* We don't want to continue accessing MAC registers. */
868a551c94aSIdo Barnea		return ret_val;
869a551c94aSIdo Barnea
870a551c94aSIdo Barnea	/* Clear any pending interrupt events. */
871a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
872a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ICR);
873a551c94aSIdo Barnea
874a551c94aSIdo Barnea	return e1000_check_alt_mac_addr_generic(hw);
875a551c94aSIdo Barnea}
876a551c94aSIdo Barnea
877a551c94aSIdo Barnea/**
878a551c94aSIdo Barnea *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
879a551c94aSIdo Barnea *  @hw: pointer to the HW structure
880a551c94aSIdo Barnea *
881a551c94aSIdo Barnea *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
882a551c94aSIdo Barnea **/
883a551c94aSIdo BarneaSTATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
884a551c94aSIdo Barnea{
885a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
886a551c94aSIdo Barnea	u32 reg_data;
887a551c94aSIdo Barnea	s32 ret_val;
888a551c94aSIdo Barnea	u16 kum_reg_data;
889a551c94aSIdo Barnea	u16 i;
890a551c94aSIdo Barnea
891a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_hw_80003es2lan");
892a551c94aSIdo Barnea
893a551c94aSIdo Barnea	e1000_initialize_hw_bits_80003es2lan(hw);
894a551c94aSIdo Barnea
895a551c94aSIdo Barnea	/* Initialize identification LED */
896a551c94aSIdo Barnea	ret_val = mac->ops.id_led_init(hw);
897a551c94aSIdo Barnea	/* An error is not fatal and we should not stop init due to this */
898a551c94aSIdo Barnea	if (ret_val)
899a551c94aSIdo Barnea		DEBUGOUT("Error initializing identification LED\n");
900a551c94aSIdo Barnea
901a551c94aSIdo Barnea	/* Disabling VLAN filtering */
902a551c94aSIdo Barnea	DEBUGOUT("Initializing the IEEE VLAN\n");
903a551c94aSIdo Barnea	mac->ops.clear_vfta(hw);
904a551c94aSIdo Barnea
905a551c94aSIdo Barnea	/* Setup the receive address. */
906a551c94aSIdo Barnea	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
907a551c94aSIdo Barnea
908a551c94aSIdo Barnea	/* Zero out the Multicast HASH table */
909a551c94aSIdo Barnea	DEBUGOUT("Zeroing the MTA\n");
910a551c94aSIdo Barnea	for (i = 0; i < mac->mta_reg_count; i++)
911a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
912a551c94aSIdo Barnea
913a551c94aSIdo Barnea	/* Setup link and flow control */
914a551c94aSIdo Barnea	ret_val = mac->ops.setup_link(hw);
915a551c94aSIdo Barnea	if (ret_val)
916a551c94aSIdo Barnea		return ret_val;
917a551c94aSIdo Barnea
918a551c94aSIdo Barnea	/* Disable IBIST slave mode (far-end loopback) */
919a551c94aSIdo Barnea	ret_val =
920a551c94aSIdo Barnea	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
921a551c94aSIdo Barnea					    &kum_reg_data);
922a551c94aSIdo Barnea	if (!ret_val) {
923a551c94aSIdo Barnea		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
924a551c94aSIdo Barnea		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
925a551c94aSIdo Barnea						 E1000_KMRNCTRLSTA_INBAND_PARAM,
926a551c94aSIdo Barnea						 kum_reg_data);
927a551c94aSIdo Barnea		if (ret_val)
928a551c94aSIdo Barnea			DEBUGOUT("Error disabling far-end loopback\n");
929a551c94aSIdo Barnea	} else
930a551c94aSIdo Barnea		DEBUGOUT("Error disabling far-end loopback\n");
931a551c94aSIdo Barnea
932a551c94aSIdo Barnea	/* Set the transmit descriptor write-back policy */
933a551c94aSIdo Barnea	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
934a551c94aSIdo Barnea	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
935a551c94aSIdo Barnea		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
936a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
937a551c94aSIdo Barnea
938a551c94aSIdo Barnea	/* ...for both queues. */
939a551c94aSIdo Barnea	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
940a551c94aSIdo Barnea	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
941a551c94aSIdo Barnea		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
942a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
943a551c94aSIdo Barnea
944a551c94aSIdo Barnea	/* Enable retransmit on late collisions */
945a551c94aSIdo Barnea	reg_data = E1000_READ_REG(hw, E1000_TCTL);
946a551c94aSIdo Barnea	reg_data |= E1000_TCTL_RTLC;
947a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
948a551c94aSIdo Barnea
949a551c94aSIdo Barnea	/* Configure Gigabit Carry Extend Padding */
950a551c94aSIdo Barnea	reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
951a551c94aSIdo Barnea	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
952a551c94aSIdo Barnea	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
953a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
954a551c94aSIdo Barnea
955a551c94aSIdo Barnea	/* Configure Transmit Inter-Packet Gap */
956a551c94aSIdo Barnea	reg_data = E1000_READ_REG(hw, E1000_TIPG);
957a551c94aSIdo Barnea	reg_data &= ~E1000_TIPG_IPGT_MASK;
958a551c94aSIdo Barnea	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
959a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
960a551c94aSIdo Barnea
961a551c94aSIdo Barnea	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
962a551c94aSIdo Barnea	reg_data &= ~0x00100000;
963a551c94aSIdo Barnea	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
964a551c94aSIdo Barnea
965a551c94aSIdo Barnea	/* default to true to enable the MDIC W/A */
966a551c94aSIdo Barnea	hw->dev_spec._80003es2lan.mdic_wa_enable = true;
967a551c94aSIdo Barnea
968a551c94aSIdo Barnea	ret_val =
969a551c94aSIdo Barnea	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
970a551c94aSIdo Barnea					    E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
971a551c94aSIdo Barnea	if (!ret_val) {
972a551c94aSIdo Barnea		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
973a551c94aSIdo Barnea		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
974a551c94aSIdo Barnea			hw->dev_spec._80003es2lan.mdic_wa_enable = false;
975a551c94aSIdo Barnea	}
976a551c94aSIdo Barnea
977a551c94aSIdo Barnea	/* Clear all of the statistics registers (clear on read).  It is
978a551c94aSIdo Barnea	 * important that we do this after we have tried to establish link
979a551c94aSIdo Barnea	 * because the symbol error count will increment wildly if there
980a551c94aSIdo Barnea	 * is no link.
981a551c94aSIdo Barnea	 */
982a551c94aSIdo Barnea	e1000_clear_hw_cntrs_80003es2lan(hw);
983a551c94aSIdo Barnea
984a551c94aSIdo Barnea	return ret_val;
985a551c94aSIdo Barnea}
986a551c94aSIdo Barnea
987a551c94aSIdo Barnea/**
988a551c94aSIdo Barnea *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
989a551c94aSIdo Barnea *  @hw: pointer to the HW structure
990a551c94aSIdo Barnea *
991a551c94aSIdo Barnea *  Initializes required hardware-dependent bits needed for normal operation.
992a551c94aSIdo Barnea **/
993a551c94aSIdo BarneaSTATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
994a551c94aSIdo Barnea{
995a551c94aSIdo Barnea	u32 reg;
996a551c94aSIdo Barnea
997a551c94aSIdo Barnea	DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
998a551c94aSIdo Barnea
999a551c94aSIdo Barnea	/* Transmit Descriptor Control 0 */
1000a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1001a551c94aSIdo Barnea	reg |= (1 << 22);
1002a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1003a551c94aSIdo Barnea
1004a551c94aSIdo Barnea	/* Transmit Descriptor Control 1 */
1005a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1006a551c94aSIdo Barnea	reg |= (1 << 22);
1007a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1008a551c94aSIdo Barnea
1009a551c94aSIdo Barnea	/* Transmit Arbitration Control 0 */
1010a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_TARC(0));
1011a551c94aSIdo Barnea	reg &= ~(0xF << 27); /* 30:27 */
1012a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper)
1013a551c94aSIdo Barnea		reg &= ~(1 << 20);
1014a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1015a551c94aSIdo Barnea
1016a551c94aSIdo Barnea	/* Transmit Arbitration Control 1 */
1017a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_TARC(1));
1018a551c94aSIdo Barnea	if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1019a551c94aSIdo Barnea		reg &= ~(1 << 28);
1020a551c94aSIdo Barnea	else
1021a551c94aSIdo Barnea		reg |= (1 << 28);
1022a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1023a551c94aSIdo Barnea
1024a551c94aSIdo Barnea	/* Disable IPv6 extension header parsing because some malformed
1025a551c94aSIdo Barnea	 * IPv6 headers can hang the Rx.
1026a551c94aSIdo Barnea	 */
1027a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_RFCTL);
1028a551c94aSIdo Barnea	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1029a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1030a551c94aSIdo Barnea
1031a551c94aSIdo Barnea	return;
1032a551c94aSIdo Barnea}
1033a551c94aSIdo Barnea
1034a551c94aSIdo Barnea/**
1035a551c94aSIdo Barnea *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1036a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1037a551c94aSIdo Barnea *
1038a551c94aSIdo Barnea *  Setup some GG82563 PHY registers for obtaining link
1039a551c94aSIdo Barnea **/
1040a551c94aSIdo BarneaSTATIC s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1041a551c94aSIdo Barnea{
1042a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1043a551c94aSIdo Barnea	s32 ret_val;
1044a551c94aSIdo Barnea	u32 reg;
1045a551c94aSIdo Barnea	u16 data;
1046a551c94aSIdo Barnea
1047a551c94aSIdo Barnea	DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1048a551c94aSIdo Barnea
1049a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1050a551c94aSIdo Barnea	if (ret_val)
1051a551c94aSIdo Barnea		return ret_val;
1052a551c94aSIdo Barnea
1053a551c94aSIdo Barnea	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1054a551c94aSIdo Barnea	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1055a551c94aSIdo Barnea	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1056a551c94aSIdo Barnea
1057a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1058a551c94aSIdo Barnea	if (ret_val)
1059a551c94aSIdo Barnea		return ret_val;
1060a551c94aSIdo Barnea
1061a551c94aSIdo Barnea	/* Options:
1062a551c94aSIdo Barnea	 *   MDI/MDI-X = 0 (default)
1063a551c94aSIdo Barnea	 *   0 - Auto for all speeds
1064a551c94aSIdo Barnea	 *   1 - MDI mode
1065a551c94aSIdo Barnea	 *   2 - MDI-X mode
1066a551c94aSIdo Barnea	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1067a551c94aSIdo Barnea	 */
1068a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1069a551c94aSIdo Barnea	if (ret_val)
1070a551c94aSIdo Barnea		return ret_val;
1071a551c94aSIdo Barnea
1072a551c94aSIdo Barnea	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1073a551c94aSIdo Barnea
1074a551c94aSIdo Barnea	switch (phy->mdix) {
1075a551c94aSIdo Barnea	case 1:
1076a551c94aSIdo Barnea		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1077a551c94aSIdo Barnea		break;
1078a551c94aSIdo Barnea	case 2:
1079a551c94aSIdo Barnea		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1080a551c94aSIdo Barnea		break;
1081a551c94aSIdo Barnea	case 0:
1082a551c94aSIdo Barnea	default:
1083a551c94aSIdo Barnea		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1084a551c94aSIdo Barnea		break;
1085a551c94aSIdo Barnea	}
1086a551c94aSIdo Barnea
1087a551c94aSIdo Barnea	/* Options:
1088a551c94aSIdo Barnea	 *   disable_polarity_correction = 0 (default)
1089a551c94aSIdo Barnea	 *       Automatic Correction for Reversed Cable Polarity
1090a551c94aSIdo Barnea	 *   0 - Disabled
1091a551c94aSIdo Barnea	 *   1 - Enabled
1092a551c94aSIdo Barnea	 */
1093a551c94aSIdo Barnea	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1094a551c94aSIdo Barnea	if (phy->disable_polarity_correction)
1095a551c94aSIdo Barnea		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1096a551c94aSIdo Barnea
1097a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1098a551c94aSIdo Barnea	if (ret_val)
1099a551c94aSIdo Barnea		return ret_val;
1100a551c94aSIdo Barnea
1101a551c94aSIdo Barnea	/* SW Reset the PHY so all changes take effect */
1102a551c94aSIdo Barnea	ret_val = hw->phy.ops.commit(hw);
1103a551c94aSIdo Barnea	if (ret_val) {
1104a551c94aSIdo Barnea		DEBUGOUT("Error Resetting the PHY\n");
1105a551c94aSIdo Barnea		return ret_val;
1106a551c94aSIdo Barnea	}
1107a551c94aSIdo Barnea
1108a551c94aSIdo Barnea	/* Bypass Rx and Tx FIFO's */
1109a551c94aSIdo Barnea	reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1110a551c94aSIdo Barnea	data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1111a551c94aSIdo Barnea		E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1112a551c94aSIdo Barnea	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1113a551c94aSIdo Barnea	if (ret_val)
1114a551c94aSIdo Barnea		return ret_val;
1115a551c94aSIdo Barnea
1116a551c94aSIdo Barnea	reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1117a551c94aSIdo Barnea	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1118a551c94aSIdo Barnea	if (ret_val)
1119a551c94aSIdo Barnea		return ret_val;
1120a551c94aSIdo Barnea	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1121a551c94aSIdo Barnea	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1122a551c94aSIdo Barnea	if (ret_val)
1123a551c94aSIdo Barnea		return ret_val;
1124a551c94aSIdo Barnea
1125a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1126a551c94aSIdo Barnea	if (ret_val)
1127a551c94aSIdo Barnea		return ret_val;
1128a551c94aSIdo Barnea
1129a551c94aSIdo Barnea	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1130a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1131a551c94aSIdo Barnea	if (ret_val)
1132a551c94aSIdo Barnea		return ret_val;
1133a551c94aSIdo Barnea
1134a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1135a551c94aSIdo Barnea	reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1136a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1137a551c94aSIdo Barnea
1138a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1139a551c94aSIdo Barnea	if (ret_val)
1140a551c94aSIdo Barnea		return ret_val;
1141a551c94aSIdo Barnea
1142a551c94aSIdo Barnea	/* Do not init these registers when the HW is in IAMT mode, since the
1143a551c94aSIdo Barnea	 * firmware will have already initialized them.  We only initialize
1144a551c94aSIdo Barnea	 * them if the HW is not in IAMT mode.
1145a551c94aSIdo Barnea	 */
1146a551c94aSIdo Barnea	if (!hw->mac.ops.check_mng_mode(hw)) {
1147a551c94aSIdo Barnea		/* Enable Electrical Idle on the PHY */
1148a551c94aSIdo Barnea		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1149a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1150a551c94aSIdo Barnea						data);
1151a551c94aSIdo Barnea		if (ret_val)
1152a551c94aSIdo Barnea			return ret_val;
1153a551c94aSIdo Barnea
1154a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1155a551c94aSIdo Barnea					       &data);
1156a551c94aSIdo Barnea		if (ret_val)
1157a551c94aSIdo Barnea			return ret_val;
1158a551c94aSIdo Barnea
1159a551c94aSIdo Barnea		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1160a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1161a551c94aSIdo Barnea						data);
1162a551c94aSIdo Barnea		if (ret_val)
1163a551c94aSIdo Barnea			return ret_val;
1164a551c94aSIdo Barnea	}
1165a551c94aSIdo Barnea
1166a551c94aSIdo Barnea	/* Workaround: Disable padding in Kumeran interface in the MAC
1167a551c94aSIdo Barnea	 * and in the PHY to avoid CRC errors.
1168a551c94aSIdo Barnea	 */
1169a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1170a551c94aSIdo Barnea	if (ret_val)
1171a551c94aSIdo Barnea		return ret_val;
1172a551c94aSIdo Barnea
1173a551c94aSIdo Barnea	data |= GG82563_ICR_DIS_PADDING;
1174a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1175a551c94aSIdo Barnea	if (ret_val)
1176a551c94aSIdo Barnea		return ret_val;
1177a551c94aSIdo Barnea
1178a551c94aSIdo Barnea	return E1000_SUCCESS;
1179a551c94aSIdo Barnea}
1180a551c94aSIdo Barnea
1181a551c94aSIdo Barnea/**
1182a551c94aSIdo Barnea *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1183a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1184a551c94aSIdo Barnea *
1185a551c94aSIdo Barnea *  Essentially a wrapper for setting up all things "copper" related.
1186a551c94aSIdo Barnea *  This is a function pointer entry point called by the mac module.
1187a551c94aSIdo Barnea **/
1188a551c94aSIdo BarneaSTATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1189a551c94aSIdo Barnea{
1190a551c94aSIdo Barnea	u32 ctrl;
1191a551c94aSIdo Barnea	s32 ret_val;
1192a551c94aSIdo Barnea	u16 reg_data;
1193a551c94aSIdo Barnea
1194a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1195a551c94aSIdo Barnea
1196a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1197a551c94aSIdo Barnea	ctrl |= E1000_CTRL_SLU;
1198a551c94aSIdo Barnea	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1199a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1200a551c94aSIdo Barnea
1201a551c94aSIdo Barnea	/* Set the mac to wait the maximum time between each
1202a551c94aSIdo Barnea	 * iteration and increase the max iterations when
1203a551c94aSIdo Barnea	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1204a551c94aSIdo Barnea	 */
1205a551c94aSIdo Barnea	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1206a551c94aSIdo Barnea						   0xFFFF);
1207a551c94aSIdo Barnea	if (ret_val)
1208a551c94aSIdo Barnea		return ret_val;
1209a551c94aSIdo Barnea	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1210a551c94aSIdo Barnea						  &reg_data);
1211a551c94aSIdo Barnea	if (ret_val)
1212a551c94aSIdo Barnea		return ret_val;
1213a551c94aSIdo Barnea	reg_data |= 0x3F;
1214a551c94aSIdo Barnea	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1215a551c94aSIdo Barnea						   reg_data);
1216a551c94aSIdo Barnea	if (ret_val)
1217a551c94aSIdo Barnea		return ret_val;
1218a551c94aSIdo Barnea	ret_val =
1219a551c94aSIdo Barnea	    e1000_read_kmrn_reg_80003es2lan(hw,
1220a551c94aSIdo Barnea					    E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1221a551c94aSIdo Barnea					    &reg_data);
1222a551c94aSIdo Barnea	if (ret_val)
1223a551c94aSIdo Barnea		return ret_val;
1224a551c94aSIdo Barnea	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1225a551c94aSIdo Barnea	ret_val =
1226a551c94aSIdo Barnea	    e1000_write_kmrn_reg_80003es2lan(hw,
1227a551c94aSIdo Barnea					     E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1228a551c94aSIdo Barnea					     reg_data);
1229a551c94aSIdo Barnea	if (ret_val)
1230a551c94aSIdo Barnea		return ret_val;
1231a551c94aSIdo Barnea
1232a551c94aSIdo Barnea	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1233a551c94aSIdo Barnea	if (ret_val)
1234a551c94aSIdo Barnea		return ret_val;
1235a551c94aSIdo Barnea
1236a551c94aSIdo Barnea	return e1000_setup_copper_link_generic(hw);
1237a551c94aSIdo Barnea}
1238a551c94aSIdo Barnea
1239a551c94aSIdo Barnea/**
1240a551c94aSIdo Barnea *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1241a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1242a551c94aSIdo Barnea *  @duplex: current duplex setting
1243a551c94aSIdo Barnea *
1244a551c94aSIdo Barnea *  Configure the KMRN interface by applying last minute quirks for
1245a551c94aSIdo Barnea *  10/100 operation.
1246a551c94aSIdo Barnea **/
1247a551c94aSIdo BarneaSTATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1248a551c94aSIdo Barnea{
1249a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1250a551c94aSIdo Barnea	u16 speed;
1251a551c94aSIdo Barnea	u16 duplex;
1252a551c94aSIdo Barnea
1253a551c94aSIdo Barnea	DEBUGFUNC("e1000_configure_on_link_up");
1254a551c94aSIdo Barnea
1255a551c94aSIdo Barnea	if (hw->phy.media_type == e1000_media_type_copper) {
1256a551c94aSIdo Barnea		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1257a551c94aSIdo Barnea								    &duplex);
1258a551c94aSIdo Barnea		if (ret_val)
1259a551c94aSIdo Barnea			return ret_val;
1260a551c94aSIdo Barnea
1261a551c94aSIdo Barnea		if (speed == SPEED_1000)
1262a551c94aSIdo Barnea			ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1263a551c94aSIdo Barnea		else
1264a551c94aSIdo Barnea			ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1265a551c94aSIdo Barnea	}
1266a551c94aSIdo Barnea
1267a551c94aSIdo Barnea	return ret_val;
1268a551c94aSIdo Barnea}
1269a551c94aSIdo Barnea
1270a551c94aSIdo Barnea/**
1271a551c94aSIdo Barnea *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1272a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1273a551c94aSIdo Barnea *  @duplex: current duplex setting
1274a551c94aSIdo Barnea *
1275a551c94aSIdo Barnea *  Configure the KMRN interface by applying last minute quirks for
1276a551c94aSIdo Barnea *  10/100 operation.
1277a551c94aSIdo Barnea **/
1278a551c94aSIdo BarneaSTATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1279a551c94aSIdo Barnea{
1280a551c94aSIdo Barnea	s32 ret_val;
1281a551c94aSIdo Barnea	u32 tipg;
1282a551c94aSIdo Barnea	u32 i = 0;
1283a551c94aSIdo Barnea	u16 reg_data, reg_data2;
1284a551c94aSIdo Barnea
1285a551c94aSIdo Barnea	DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1286a551c94aSIdo Barnea
1287a551c94aSIdo Barnea	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1288a551c94aSIdo Barnea	ret_val =
1289a551c94aSIdo Barnea	    e1000_write_kmrn_reg_80003es2lan(hw,
1290a551c94aSIdo Barnea					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1291a551c94aSIdo Barnea					     reg_data);
1292a551c94aSIdo Barnea	if (ret_val)
1293a551c94aSIdo Barnea		return ret_val;
1294a551c94aSIdo Barnea
1295a551c94aSIdo Barnea	/* Configure Transmit Inter-Packet Gap */
1296a551c94aSIdo Barnea	tipg = E1000_READ_REG(hw, E1000_TIPG);
1297a551c94aSIdo Barnea	tipg &= ~E1000_TIPG_IPGT_MASK;
1298a551c94aSIdo Barnea	tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1299a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1300a551c94aSIdo Barnea
1301a551c94aSIdo Barnea	do {
1302a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1303a551c94aSIdo Barnea					       &reg_data);
1304a551c94aSIdo Barnea		if (ret_val)
1305a551c94aSIdo Barnea			return ret_val;
1306a551c94aSIdo Barnea
1307a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1308a551c94aSIdo Barnea					       &reg_data2);
1309a551c94aSIdo Barnea		if (ret_val)
1310a551c94aSIdo Barnea			return ret_val;
1311a551c94aSIdo Barnea		i++;
1312a551c94aSIdo Barnea	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1313a551c94aSIdo Barnea
1314a551c94aSIdo Barnea	if (duplex == HALF_DUPLEX)
1315a551c94aSIdo Barnea		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1316a551c94aSIdo Barnea	else
1317a551c94aSIdo Barnea		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1318a551c94aSIdo Barnea
1319a551c94aSIdo Barnea	return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1320a551c94aSIdo Barnea}
1321a551c94aSIdo Barnea
1322a551c94aSIdo Barnea/**
1323a551c94aSIdo Barnea *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1324a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1325a551c94aSIdo Barnea *
1326a551c94aSIdo Barnea *  Configure the KMRN interface by applying last minute quirks for
1327a551c94aSIdo Barnea *  gigabit operation.
1328a551c94aSIdo Barnea **/
1329a551c94aSIdo BarneaSTATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1330a551c94aSIdo Barnea{
1331a551c94aSIdo Barnea	s32 ret_val;
1332a551c94aSIdo Barnea	u16 reg_data, reg_data2;
1333a551c94aSIdo Barnea	u32 tipg;
1334a551c94aSIdo Barnea	u32 i = 0;
1335a551c94aSIdo Barnea
1336a551c94aSIdo Barnea	DEBUGFUNC("e1000_configure_kmrn_for_1000");
1337a551c94aSIdo Barnea
1338a551c94aSIdo Barnea	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1339a551c94aSIdo Barnea	ret_val =
1340a551c94aSIdo Barnea	    e1000_write_kmrn_reg_80003es2lan(hw,
1341a551c94aSIdo Barnea					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1342a551c94aSIdo Barnea					     reg_data);
1343a551c94aSIdo Barnea	if (ret_val)
1344a551c94aSIdo Barnea		return ret_val;
1345a551c94aSIdo Barnea
1346a551c94aSIdo Barnea	/* Configure Transmit Inter-Packet Gap */
1347a551c94aSIdo Barnea	tipg = E1000_READ_REG(hw, E1000_TIPG);
1348a551c94aSIdo Barnea	tipg &= ~E1000_TIPG_IPGT_MASK;
1349a551c94aSIdo Barnea	tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1350a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1351a551c94aSIdo Barnea
1352a551c94aSIdo Barnea	do {
1353a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1354a551c94aSIdo Barnea					       &reg_data);
1355a551c94aSIdo Barnea		if (ret_val)
1356a551c94aSIdo Barnea			return ret_val;
1357a551c94aSIdo Barnea
1358a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1359a551c94aSIdo Barnea					       &reg_data2);
1360a551c94aSIdo Barnea		if (ret_val)
1361a551c94aSIdo Barnea			return ret_val;
1362a551c94aSIdo Barnea		i++;
1363a551c94aSIdo Barnea	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1364a551c94aSIdo Barnea
1365a551c94aSIdo Barnea	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1366a551c94aSIdo Barnea
1367a551c94aSIdo Barnea	return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1368a551c94aSIdo Barnea}
1369a551c94aSIdo Barnea
1370a551c94aSIdo Barnea/**
1371a551c94aSIdo Barnea *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1372a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1373a551c94aSIdo Barnea *  @offset: register offset to be read
1374a551c94aSIdo Barnea *  @data: pointer to the read data
1375a551c94aSIdo Barnea *
1376a551c94aSIdo Barnea *  Acquire semaphore, then read the PHY register at offset
1377a551c94aSIdo Barnea *  using the kumeran interface.  The information retrieved is stored in data.
1378a551c94aSIdo Barnea *  Release the semaphore before exiting.
1379a551c94aSIdo Barnea **/
1380a551c94aSIdo BarneaSTATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1381a551c94aSIdo Barnea					   u16 *data)
1382a551c94aSIdo Barnea{
1383a551c94aSIdo Barnea	u32 kmrnctrlsta;
1384a551c94aSIdo Barnea	s32 ret_val;
1385a551c94aSIdo Barnea
1386a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1387a551c94aSIdo Barnea
1388a551c94aSIdo Barnea	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1389a551c94aSIdo Barnea	if (ret_val)
1390a551c94aSIdo Barnea		return ret_val;
1391a551c94aSIdo Barnea
1392a551c94aSIdo Barnea	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1393a551c94aSIdo Barnea		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1394a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1395a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1396a551c94aSIdo Barnea
1397a551c94aSIdo Barnea	usec_delay(2);
1398a551c94aSIdo Barnea
1399a551c94aSIdo Barnea	kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1400a551c94aSIdo Barnea	*data = (u16)kmrnctrlsta;
1401a551c94aSIdo Barnea
1402a551c94aSIdo Barnea	e1000_release_mac_csr_80003es2lan(hw);
1403a551c94aSIdo Barnea
1404a551c94aSIdo Barnea	return ret_val;
1405a551c94aSIdo Barnea}
1406a551c94aSIdo Barnea
1407a551c94aSIdo Barnea/**
1408a551c94aSIdo Barnea *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1409a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1410a551c94aSIdo Barnea *  @offset: register offset to write to
1411a551c94aSIdo Barnea *  @data: data to write at register offset
1412a551c94aSIdo Barnea *
1413a551c94aSIdo Barnea *  Acquire semaphore, then write the data to PHY register
1414a551c94aSIdo Barnea *  at the offset using the kumeran interface.  Release semaphore
1415a551c94aSIdo Barnea *  before exiting.
1416a551c94aSIdo Barnea **/
1417a551c94aSIdo BarneaSTATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1418a551c94aSIdo Barnea					    u16 data)
1419a551c94aSIdo Barnea{
1420a551c94aSIdo Barnea	u32 kmrnctrlsta;
1421a551c94aSIdo Barnea	s32 ret_val;
1422a551c94aSIdo Barnea
1423a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1424a551c94aSIdo Barnea
1425a551c94aSIdo Barnea	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1426a551c94aSIdo Barnea	if (ret_val)
1427a551c94aSIdo Barnea		return ret_val;
1428a551c94aSIdo Barnea
1429a551c94aSIdo Barnea	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1430a551c94aSIdo Barnea		       E1000_KMRNCTRLSTA_OFFSET) | data;
1431a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1432a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1433a551c94aSIdo Barnea
1434a551c94aSIdo Barnea	usec_delay(2);
1435a551c94aSIdo Barnea
1436a551c94aSIdo Barnea	e1000_release_mac_csr_80003es2lan(hw);
1437a551c94aSIdo Barnea
1438a551c94aSIdo Barnea	return ret_val;
1439a551c94aSIdo Barnea}
1440a551c94aSIdo Barnea
1441a551c94aSIdo Barnea/**
1442a551c94aSIdo Barnea *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1443a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1444a551c94aSIdo Barnea **/
1445a551c94aSIdo BarneaSTATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1446a551c94aSIdo Barnea{
1447a551c94aSIdo Barnea	s32 ret_val;
1448a551c94aSIdo Barnea
1449a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1450a551c94aSIdo Barnea
1451a551c94aSIdo Barnea	/* If there's an alternate MAC address place it in RAR0
1452a551c94aSIdo Barnea	 * so that it will override the Si installed default perm
1453a551c94aSIdo Barnea	 * address.
1454a551c94aSIdo Barnea	 */
1455a551c94aSIdo Barnea	ret_val = e1000_check_alt_mac_addr_generic(hw);
1456a551c94aSIdo Barnea	if (ret_val)
1457a551c94aSIdo Barnea		return ret_val;
1458a551c94aSIdo Barnea
1459a551c94aSIdo Barnea	return e1000_read_mac_addr_generic(hw);
1460a551c94aSIdo Barnea}
1461a551c94aSIdo Barnea
1462a551c94aSIdo Barnea/**
1463a551c94aSIdo Barnea * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1464a551c94aSIdo Barnea * @hw: pointer to the HW structure
1465a551c94aSIdo Barnea *
1466a551c94aSIdo Barnea * In the case of a PHY power down to save power, or to turn off link during a
1467a551c94aSIdo Barnea * driver unload, or wake on lan is not enabled, remove the link.
1468a551c94aSIdo Barnea **/
1469a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1470a551c94aSIdo Barnea{
1471a551c94aSIdo Barnea	/* If the management interface is not enabled, then power down */
1472a551c94aSIdo Barnea	if (!(hw->mac.ops.check_mng_mode(hw) ||
1473a551c94aSIdo Barnea	      hw->phy.ops.check_reset_block(hw)))
1474a551c94aSIdo Barnea		e1000_power_down_phy_copper(hw);
1475a551c94aSIdo Barnea
1476a551c94aSIdo Barnea	return;
1477a551c94aSIdo Barnea}
1478a551c94aSIdo Barnea
1479a551c94aSIdo Barnea/**
1480a551c94aSIdo Barnea *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1481a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1482a551c94aSIdo Barnea *
1483a551c94aSIdo Barnea *  Clears the hardware counters by reading the counter registers.
1484a551c94aSIdo Barnea **/
1485a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)