1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*
35 * 82540EM Gigabit Ethernet Controller
36 * 82540EP Gigabit Ethernet Controller
37 * 82545EM Gigabit Ethernet Controller (Copper)
38 * 82545EM Gigabit Ethernet Controller (Fiber)
39 * 82545GM Gigabit Ethernet Controller
40 * 82546EB Gigabit Ethernet Controller (Copper)
41 * 82546EB Gigabit Ethernet Controller (Fiber)
42 * 82546GB Gigabit Ethernet Controller
43 */
44
45#include "e1000_api.h"
46
47STATIC s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
48STATIC s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
49STATIC s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
50STATIC s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
51STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
52STATIC s32  e1000_init_hw_82540(struct e1000_hw *hw);
53STATIC s32  e1000_reset_hw_82540(struct e1000_hw *hw);
54STATIC s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
55STATIC s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
56STATIC s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
57STATIC s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
58STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
59STATIC s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
60
61/**
62 * e1000_init_phy_params_82540 - Init PHY func ptrs.
63 * @hw: pointer to the HW structure
64 **/
65STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
66{
67	struct e1000_phy_info *phy = &hw->phy;
68	s32 ret_val;
69
70	phy->addr		= 1;
71	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
72	phy->reset_delay_us	= 10000;
73	phy->type		= e1000_phy_m88;
74
75	/* Function Pointers */
76	phy->ops.check_polarity	= e1000_check_polarity_m88;
77	phy->ops.commit		= e1000_phy_sw_reset_generic;
78	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
79	phy->ops.get_cable_length = e1000_get_cable_length_m88;
80	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
81	phy->ops.read_reg	= e1000_read_phy_reg_m88;
82	phy->ops.reset		= e1000_phy_hw_reset_generic;
83	phy->ops.write_reg	= e1000_write_phy_reg_m88;
84	phy->ops.get_info	= e1000_get_phy_info_m88;
85	phy->ops.power_up	= e1000_power_up_phy_copper;
86	phy->ops.power_down	= e1000_power_down_phy_copper_82540;
87
88	ret_val = e1000_get_phy_id(hw);
89	if (ret_val)
90		goto out;
91
92	/* Verify phy id */
93	switch (hw->mac.type) {
94	case e1000_82540:
95	case e1000_82545:
96	case e1000_82545_rev_3:
97	case e1000_82546:
98	case e1000_82546_rev_3:
99		if (phy->id == M88E1011_I_PHY_ID)
100			break;
101		/* Fall Through */
102	default:
103		ret_val = -E1000_ERR_PHY;
104		goto out;
105		break;
106	}
107
108out:
109	return ret_val;
110}
111
112/**
113 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
114 * @hw: pointer to the HW structure
115 **/
116STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
117{
118	struct e1000_nvm_info *nvm = &hw->nvm;
119	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
120
121	DEBUGFUNC("e1000_init_nvm_params_82540");
122
123	nvm->type = e1000_nvm_eeprom_microwire;
124	nvm->delay_usec = 50;
125	nvm->opcode_bits = 3;
126	switch (nvm->override) {
127	case e1000_nvm_override_microwire_large:
128		nvm->address_bits = 8;
129		nvm->word_size = 256;
130		break;
131	case e1000_nvm_override_microwire_small:
132		nvm->address_bits = 6;
133		nvm->word_size = 64;
134		break;
135	default:
136		nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
137		nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
138		break;
139	}
140
141	/* Function Pointers */
142	nvm->ops.acquire	= e1000_acquire_nvm_generic;
143	nvm->ops.read		= e1000_read_nvm_microwire;
144	nvm->ops.release	= e1000_release_nvm_generic;
145	nvm->ops.update		= e1000_update_nvm_checksum_generic;
146	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
147	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
148	nvm->ops.write		= e1000_write_nvm_microwire;
149
150	return E1000_SUCCESS;
151}
152
153/**
154 * e1000_init_mac_params_82540 - Init MAC func ptrs.
155 * @hw: pointer to the HW structure
156 **/
157STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
158{
159	struct e1000_mac_info *mac = &hw->mac;
160	s32 ret_val = E1000_SUCCESS;
161
162	DEBUGFUNC("e1000_init_mac_params_82540");
163
164	/* Set media type */
165	switch (hw->device_id) {
166	case E1000_DEV_ID_82545EM_FIBER:
167	case E1000_DEV_ID_82545GM_FIBER:
168	case E1000_DEV_ID_82546EB_FIBER:
169	case E1000_DEV_ID_82546GB_FIBER:
170		hw->phy.media_type = e1000_media_type_fiber;
171		break;
172	case E1000_DEV_ID_82545GM_SERDES:
173	case E1000_DEV_ID_82546GB_SERDES:
174		hw->phy.media_type = e1000_media_type_internal_serdes;
175		break;
176	default:
177		hw->phy.media_type = e1000_media_type_copper;
178		break;
179	}
180
181	/* Set mta register count */
182	mac->mta_reg_count = 128;
183	/* Set rar entry count */
184	mac->rar_entry_count = E1000_RAR_ENTRIES;
185
186	/* Function pointers */
187
188	/* bus type/speed/width */
189	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
190	/* function id */
191	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
192	/* reset */
193	mac->ops.reset_hw = e1000_reset_hw_82540;
194	/* hw initialization */
195	mac->ops.init_hw = e1000_init_hw_82540;
196	/* link setup */
197	mac->ops.setup_link = e1000_setup_link_generic;
198	/* physical interface setup */
199	mac->ops.setup_physical_interface =
200		(hw->phy.media_type == e1000_media_type_copper)
201			? e1000_setup_copper_link_82540
202			: e1000_setup_fiber_serdes_link_82540;
203	/* check for link */
204	switch (hw->phy.media_type) {
205	case e1000_media_type_copper:
206		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
207		break;
208	case e1000_media_type_fiber:
209		mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
210		break;
211	case e1000_media_type_internal_serdes:
212		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
213		break;
214	default:
215		ret_val = -E1000_ERR_CONFIG;
216		goto out;
217		break;
218	}
219	/* link info */
220	mac->ops.get_link_up_info =
221		(hw->phy.media_type == e1000_media_type_copper)
222			? e1000_get_speed_and_duplex_copper_generic
223			: e1000_get_speed_and_duplex_fiber_serdes_generic;
224	/* multicast address update */
225	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
226	/* writing VFTA */
227	mac->ops.write_vfta = e1000_write_vfta_generic;
228	/* clearing VFTA */
229	mac->ops.clear_vfta = e1000_clear_vfta_generic;
230	/* read mac address */
231	mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
232	/* ID LED init */
233	mac->ops.id_led_init = e1000_id_led_init_generic;
234	/* setup LED */
235	mac->ops.setup_led = e1000_setup_led_generic;
236	/* cleanup LED */
237	mac->ops.cleanup_led = e1000_cleanup_led_generic;
238	/* turn on/off LED */
239	mac->ops.led_on = e1000_led_on_generic;
240	mac->ops.led_off = e1000_led_off_generic;
241	/* clear hardware counters */
242	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
243
244out:
245	return ret_val;
246}
247
248/**
249 * e1000_init_function_pointers_82540 - Init func ptrs.
250 * @hw: pointer to the HW structure
251 *
252 * Called to initialize all function pointers and parameters.
253 **/
254void e1000_init_function_pointers_82540(struct e1000_hw *hw)
255{
256	DEBUGFUNC("e1000_init_function_pointers_82540");
257
258	hw->mac.ops.init_params = e1000_init_mac_params_82540;
259	hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
260	hw->phy.ops.init_params = e1000_init_phy_params_82540;
261}
262
263/**
264 *  e1000_reset_hw_82540 - Reset hardware
265 *  @hw: pointer to the HW structure
266 *
267 *  This resets the hardware into a known state.
268 **/
269STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)
270{
271	u32 ctrl, manc;
272	s32 ret_val = E1000_SUCCESS;
273
274	DEBUGFUNC("e1000_reset_hw_82540");
275
276	DEBUGOUT("Masking off all interrupts\n");
277	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
278
279	E1000_WRITE_REG(hw, E1000_RCTL, 0);
280	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
281	E1000_WRITE_FLUSH(hw);
282
283	/*
284	 * Delay to allow any outstanding PCI transactions to complete
285	 * before resetting the device.
286	 */
287	msec_delay(10);
288
289	ctrl = E1000_READ_REG(hw, E1000_CTRL);
290
291	DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
292	switch (hw->mac.type) {
293	case e1000_82545_rev_3:
294	case e1000_82546_rev_3:
295		E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
296		break;
297	default:
298		/*
299		 * These controllers can't ack the 64-bit write when
300		 * issuing the reset, so we use IO-mapping as a
301		 * workaround to issue the reset.
302		 */
303		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
304		break;
305	}
306
307	/* Wait for EEPROM reload */
308	msec_delay(5);
309
310	/* Disable HW ARPs on ASF enabled adapters */
311	manc = E1000_READ_REG(hw, E1000_MANC);
312	manc &= ~E1000_MANC_ARP_EN;
313	E1000_WRITE_REG(hw, E1000_MANC, manc);
314
315	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
316	E1000_READ_REG(hw, E1000_ICR);
317
318	return ret_val;
319}
320
321/**
322 *  e1000_init_hw_82540 - Initialize hardware
323 *  @hw: pointer to the HW structure
324 *
325 *  This inits the hardware readying it for operation.
326 **/
327STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)
328{
329	struct e1000_mac_info *mac = &hw->mac;
330	u32 txdctl, ctrl_ext;
331	s32 ret_val;
332	u16 i;
333
334	DEBUGFUNC("e1000_init_hw_82540");
335
336	/* Initialize identification LED */
337	ret_val = mac->ops.id_led_init(hw);
338	if (ret_val) {
339		DEBUGOUT("Error initializing identification LED\n");
340		/* This is not fatal and we should not stop init due to this */
341	}
342
343	/* Disabling VLAN filtering */
344	DEBUGOUT("Initializing the IEEE VLAN\n");
345	if (mac->type < e1000_82545_rev_3)
346		E1000_WRITE_REG(hw, E1000_VET, 0);
347
348	mac->ops.clear_vfta(hw);
349
350	/* Setup the receive address. */
351	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
352
353	/* Zero out the Multicast HASH table */
354	DEBUGOUT("Zeroing the MTA\n");
355	for (i = 0; i < mac->mta_reg_count; i++) {
356		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
357		/*
358		 * Avoid back to back register writes by adding the register
359		 * read (flush).  This is to protect against some strange
360		 * bridge configurations that may issue Memory Write Block
361		 * (MWB) to our register space.  The *_rev_3 hardware at
362		 * least doesn't respond correctly to every other dword in an
363		 * MWB to our register space.
364		 */
365		E1000_WRITE_FLUSH(hw);
366	}
367
368	if (mac->type < e1000_82545_rev_3)
369		e1000_pcix_mmrbc_workaround_generic(hw);
370
371	/* Setup link and flow control */
372	ret_val = mac->ops.setup_link(hw);
373
374	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
375	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
376		  E1000_TXDCTL_FULL_TX_DESC_WB;
377	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
378
379	/*
380	 * Clear all of the statistics registers (clear on read).  It is
381	 * important that we do this after we have tried to establish link
382	 * because the symbol error count will increment wildly if there
383	 * is no link.
384	 */
385	e1000_clear_hw_cntrs_82540(hw);
386
387	if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
388	    (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
389		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
390		/*
391		 * Relaxed ordering must be disabled to avoid a parity
392		 * error crash in a PCI slot.
393		 */
394		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
395		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
396	}
397
398	return ret_val;
399}
400
401/**
402 *  e1000_setup_copper_link_82540 - Configure copper link settings
403 *  @hw: pointer to the HW structure
404 *
405 *  Calls the appropriate function to configure the link for auto-neg or forced
406 *  speed and duplex.  Then we check for link, once link is established calls
407 *  to configure collision distance and flow control are called.  If link is
408 *  not established, we return -E1000_ERR_PHY (-2).
409 **/
410STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
411{
412	u32 ctrl;
413	s32 ret_val;
414	u16 data;
415
416	DEBUGFUNC("e1000_setup_copper_link_82540");
417
418	ctrl = E1000_READ_REG(hw, E1000_CTRL);
419	ctrl |= E1000_CTRL_SLU;
420	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
421	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
422
423	ret_val = e1000_set_phy_mode_82540(hw);
424	if (ret_val)
425		goto out;
426
427	if (hw->mac.type == e1000_82545_rev_3 ||
428	    hw->mac.type == e1000_82546_rev_3) {
429		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
430					       &data);
431		if (ret_val)
432			goto out;
433		data |= 0x00000008;
434		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
435						data);
436		if (ret_val)
437			goto out;
438	}
439
440	ret_val = e1000_copper_link_setup_m88(hw);
441	if (ret_val)
442		goto out;
443
444	ret_val = e1000_setup_copper_link_generic(hw);
445
446out:
447	return ret_val;
448}
449
450/**
451 *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
452 *  @hw: pointer to the HW structure
453 *
454 *  Set the output amplitude to the value in the EEPROM and adjust the VCO
455 *  speed to improve Bit Error Rate (BER) performance.  Configures collision
456 *  distance and flow control for fiber and serdes links.  Upon successful
457 *  setup, poll for link.
458 **/
459STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
460{
461	struct e1000_mac_info *mac = &hw->mac;
462	s32 ret_val = E1000_SUCCESS;
463
464	DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
465
466	switch (mac->type) {
467	case e1000_82545_rev_3:
468	case e1000_82546_rev_3:
469		if (hw->phy.media_type == e1000_media_type_internal_serdes) {
470			/*
471			 * If we're on serdes media, adjust the output
472			 * amplitude to value set in the EEPROM.
473			 */
474			ret_val = e1000_adjust_serdes_amplitude_82540(hw);
475			if (ret_val)
476				goto out;
477		}
478		/* Adjust VCO speed to improve BER performance */
479		ret_val = e1000_set_vco_speed_82540(hw);
480		if (ret_val)
481			goto out;
482	default:
483		break;
484	}
485
486	ret_val = e1000_setup_fiber_serdes_link_generic(hw);
487
488out:
489	return ret_val;
490}
491
492/**
493 *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
494 *  @hw: pointer to the HW structure
495 *
496 *  Adjust the SERDES output amplitude based on the EEPROM settings.
497 **/
498STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
499{
500	s32 ret_val;
501	u16 nvm_data;
502
503	DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
504
505	ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
506	if (ret_val)
507		goto out;
508
509	if (nvm_data != NVM_RESERVED_WORD) {
510		/* Adjust serdes output amplitude only. */
511		nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
512		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
513						nvm_data);
514		if (ret_val)
515			goto out;
516	}
517
518out:
519	return ret_val;
520}
521
522/**
523 *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
524 *  @hw: pointer to the HW structure
525 *
526 *  Set the VCO speed to improve Bit Error Rate (BER) performance.
527 **/
528STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
529{
530	s32  ret_val;
531	u16 default_page = 0;
532	u16 phy_data;
533
534	DEBUGFUNC("e1000_set_vco_speed_82540");
535
536	/* Set PHY register 30, page 5, bit 8 to 0 */
537
538	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
539				       &default_page);
540	if (ret_val)
541		goto out;
542
543	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
544	if (ret_val)
545		goto out;
546
547	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
548	if (ret_val)
549		goto out;
550
551	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
552	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
553	if (ret_val)
554		goto out;
555
556	/* Set PHY register 30, page 4, bit 11 to 1 */
557
558	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
559	if (ret_val)
560		goto out;
561
562	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
563	if (ret_val)
564		goto out;
565
566	phy_data |= M88E1000_PHY_VCO_REG_BIT11;
567	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
568	if (ret_val)
569		goto out;
570
571	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
572					default_page);
573
574out:
575	return ret_val;
576}
577
578/**
579 *  e1000_set_phy_mode_82540 - Set PHY to class A mode
580 *  @hw: pointer to the HW structure
581 *
582 *  Sets the PHY to class A mode and assumes the following operations will
583 *  follow to enable the new class mode:
584 *    1.  Do a PHY soft reset.
585 *    2.  Restart auto-negotiation or force link.
586 **/
587STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
588{
589	s32 ret_val = E1000_SUCCESS;
590	u16 nvm_data;
591
592	DEBUGFUNC("e1000_set_phy_mode_82540");
593
594	if (hw->mac.type != e1000_82545_rev_3)
595		goto out;
596
597	ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
598	if (ret_val) {
599		ret_val = -E1000_ERR_PHY;
600		goto out;
601	}
602
603	if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
604		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
605						0x000B);
606		if (ret_val) {
607			ret_val = -E1000_ERR_PHY;
608			goto out;
609		}
610		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
611						0x8104);
612		if (ret_val) {
613			ret_val = -E1000_ERR_PHY;
614			goto out;
615		}
616
617	}
618
619out:
620	return ret_val;
621}
622
623/**
624 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
625 * @hw: pointer to the HW structure
626 *
627 * In the case of a PHY power down to save power, or to turn off link during a
628 * driver unload, or wake on lan is not enabled, remove the link.
629 **/
630STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
631{
632	/* If the management interface is not enabled, then power down */
633	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
634		e1000_power_down_phy_copper(hw);
635
636	return;
637}
638
639/**
640 *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
641 *  @hw: pointer to the HW structure
642 *
643 *  Clears the hardware counters by reading the counter registers.
644 **/
645STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
646{
647	DEBUGFUNC("e1000_clear_hw_cntrs_82540");
648
649	e1000_clear_hw_cntrs_base_generic(hw);
650
651	E1000_READ_REG(hw, E1000_PRC64);
652	E1000_READ_REG(hw, E1000_PRC127);
653	E1000_READ_REG(hw, E1000_PRC255);
654	E1000_READ_REG(hw, E1000_PRC511);
655	E1000_READ_REG(hw, E1000_PRC1023);
656	E1000_READ_REG(hw, E1000_PRC1522);
657	E1000_READ_REG(hw, E1000_PTC64);
658	E1000_READ_REG(hw, E1000_PTC127);
659	E1000_READ_REG(hw, E1000_PTC255);
660	E1000_READ_REG(hw, E1000_PTC511);
661	E1000_READ_REG(hw, E1000_PTC1023);
662	E1000_READ_REG(hw, E1000_PTC1522);
663
664	E1000_READ_REG(hw, E1000_ALGNERRC);
665	E1000_READ_REG(hw, E1000_RXERRC);
666	E1000_READ_REG(hw, E1000_TNCRS);
667	E1000_READ_REG(hw, E1000_CEXTERR);
668	E1000_READ_REG(hw, E1000_TSCTC);
669	E1000_READ_REG(hw, E1000_TSCTFC);
670
671	E1000_READ_REG(hw, E1000_MGTPRC);
672	E1000_READ_REG(hw, E1000_MGTPDC);
673	E1000_READ_REG(hw, E1000_MGTPTC);
674}
675
676/**
677 *  e1000_read_mac_addr_82540 - Read device MAC address
678 *  @hw: pointer to the HW structure
679 *
680 *  Reads the device MAC address from the EEPROM and stores the value.
681 *  Since devices with two ports use the same EEPROM, we increment the
682 *  last bit in the MAC address for the second port.
683 *
684 *  This version is being used over generic because of customer issues
685 *  with VmWare and Virtual Box when using generic. It seems in
686 *  the emulated 82545, RAR[0] does NOT have a valid address after a
687 *  reset, this older method works and using this breaks nothing for
688 *  these legacy adapters.
689 **/
690s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
691{
692	s32  ret_val = E1000_SUCCESS;
693	u16 offset, nvm_data, i;
694
695	DEBUGFUNC("e1000_read_mac_addr");
696
697	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
698		offset = i >> 1;
699		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
700		if (ret_val) {
701			DEBUGOUT("NVM Read Error\n");
702			goto out;
703		}
704		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
705		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
706	}
707
708	/* Flip last bit of mac address if we're on second port */
709	if (hw->bus.func == E1000_FUNC_1)
710		hw->mac.perm_addr[5] ^= 1;
711
712	for (i = 0; i < ETH_ADDR_LEN; i++)
713		hw->mac.addr[i] = hw->mac.perm_addr[i];
714
715out:
716	return ret_val;
717}
718