1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/*
35a551c94aSIdo Barnea * 82540EM Gigabit Ethernet Controller
36a551c94aSIdo Barnea * 82540EP Gigabit Ethernet Controller
37a551c94aSIdo Barnea * 82545EM Gigabit Ethernet Controller (Copper)
38a551c94aSIdo Barnea * 82545EM Gigabit Ethernet Controller (Fiber)
39a551c94aSIdo Barnea * 82545GM Gigabit Ethernet Controller
40a551c94aSIdo Barnea * 82546EB Gigabit Ethernet Controller (Copper)
41a551c94aSIdo Barnea * 82546EB Gigabit Ethernet Controller (Fiber)
42a551c94aSIdo Barnea * 82546GB Gigabit Ethernet Controller
43a551c94aSIdo Barnea */
44a551c94aSIdo Barnea
45a551c94aSIdo Barnea#include "e1000_api.h"
46a551c94aSIdo Barnea
47a551c94aSIdo BarneaSTATIC s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
48a551c94aSIdo BarneaSTATIC s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
49a551c94aSIdo BarneaSTATIC s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
50a551c94aSIdo BarneaSTATIC s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
51a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
52a551c94aSIdo BarneaSTATIC s32  e1000_init_hw_82540(struct e1000_hw *hw);
53a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_82540(struct e1000_hw *hw);
54a551c94aSIdo BarneaSTATIC s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
55a551c94aSIdo BarneaSTATIC s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
56a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
57a551c94aSIdo BarneaSTATIC s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
58a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
59a551c94aSIdo BarneaSTATIC s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
60a551c94aSIdo Barnea
61a551c94aSIdo Barnea/**
62a551c94aSIdo Barnea * e1000_init_phy_params_82540 - Init PHY func ptrs.
63a551c94aSIdo Barnea * @hw: pointer to the HW structure
64a551c94aSIdo Barnea **/
65a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
66a551c94aSIdo Barnea{
67a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
68a551c94aSIdo Barnea	s32 ret_val;
69a551c94aSIdo Barnea
70a551c94aSIdo Barnea	phy->addr		= 1;
71a551c94aSIdo Barnea	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
72a551c94aSIdo Barnea	phy->reset_delay_us	= 10000;
73a551c94aSIdo Barnea	phy->type		= e1000_phy_m88;
74a551c94aSIdo Barnea
75a551c94aSIdo Barnea	/* Function Pointers */
76a551c94aSIdo Barnea	phy->ops.check_polarity	= e1000_check_polarity_m88;
77a551c94aSIdo Barnea	phy->ops.commit		= e1000_phy_sw_reset_generic;
78a551c94aSIdo Barnea	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
79a551c94aSIdo Barnea	phy->ops.get_cable_length = e1000_get_cable_length_m88;
80a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
81a551c94aSIdo Barnea	phy->ops.read_reg	= e1000_read_phy_reg_m88;
82a551c94aSIdo Barnea	phy->ops.reset		= e1000_phy_hw_reset_generic;
83a551c94aSIdo Barnea	phy->ops.write_reg	= e1000_write_phy_reg_m88;
84a551c94aSIdo Barnea	phy->ops.get_info	= e1000_get_phy_info_m88;
85a551c94aSIdo Barnea	phy->ops.power_up	= e1000_power_up_phy_copper;
86a551c94aSIdo Barnea	phy->ops.power_down	= e1000_power_down_phy_copper_82540;
87a551c94aSIdo Barnea
88a551c94aSIdo Barnea	ret_val = e1000_get_phy_id(hw);
89a551c94aSIdo Barnea	if (ret_val)
90a551c94aSIdo Barnea		goto out;
91a551c94aSIdo Barnea
92a551c94aSIdo Barnea	/* Verify phy id */
93a551c94aSIdo Barnea	switch (hw->mac.type) {
94a551c94aSIdo Barnea	case e1000_82540:
95a551c94aSIdo Barnea	case e1000_82545:
96a551c94aSIdo Barnea	case e1000_82545_rev_3:
97a551c94aSIdo Barnea	case e1000_82546:
98a551c94aSIdo Barnea	case e1000_82546_rev_3:
99a551c94aSIdo Barnea		if (phy->id == M88E1011_I_PHY_ID)
100a551c94aSIdo Barnea			break;
101a551c94aSIdo Barnea		/* Fall Through */
102a551c94aSIdo Barnea	default:
103a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
104a551c94aSIdo Barnea		goto out;
105a551c94aSIdo Barnea		break;
106a551c94aSIdo Barnea	}
107a551c94aSIdo Barnea
108a551c94aSIdo Barneaout:
109a551c94aSIdo Barnea	return ret_val;
110a551c94aSIdo Barnea}
111a551c94aSIdo Barnea
112a551c94aSIdo Barnea/**
113a551c94aSIdo Barnea * e1000_init_nvm_params_82540 - Init NVM func ptrs.
114a551c94aSIdo Barnea * @hw: pointer to the HW structure
115a551c94aSIdo Barnea **/
116a551c94aSIdo BarneaSTATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
117a551c94aSIdo Barnea{
118a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
119a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
120a551c94aSIdo Barnea
121a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_82540");
122a551c94aSIdo Barnea
123a551c94aSIdo Barnea	nvm->type = e1000_nvm_eeprom_microwire;
124a551c94aSIdo Barnea	nvm->delay_usec = 50;
125a551c94aSIdo Barnea	nvm->opcode_bits = 3;
126a551c94aSIdo Barnea	switch (nvm->override) {
127a551c94aSIdo Barnea	case e1000_nvm_override_microwire_large:
128a551c94aSIdo Barnea		nvm->address_bits = 8;
129a551c94aSIdo Barnea		nvm->word_size = 256;
130a551c94aSIdo Barnea		break;
131a551c94aSIdo Barnea	case e1000_nvm_override_microwire_small:
132a551c94aSIdo Barnea		nvm->address_bits = 6;
133a551c94aSIdo Barnea		nvm->word_size = 64;
134a551c94aSIdo Barnea		break;
135a551c94aSIdo Barnea	default:
136a551c94aSIdo Barnea		nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
137a551c94aSIdo Barnea		nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
138a551c94aSIdo Barnea		break;
139a551c94aSIdo Barnea	}
140a551c94aSIdo Barnea
141a551c94aSIdo Barnea	/* Function Pointers */
142a551c94aSIdo Barnea	nvm->ops.acquire	= e1000_acquire_nvm_generic;
143a551c94aSIdo Barnea	nvm->ops.read		= e1000_read_nvm_microwire;
144a551c94aSIdo Barnea	nvm->ops.release	= e1000_release_nvm_generic;
145a551c94aSIdo Barnea	nvm->ops.update		= e1000_update_nvm_checksum_generic;
146a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
147a551c94aSIdo Barnea	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
148a551c94aSIdo Barnea	nvm->ops.write		= e1000_write_nvm_microwire;
149a551c94aSIdo Barnea
150a551c94aSIdo Barnea	return E1000_SUCCESS;
151a551c94aSIdo Barnea}
152a551c94aSIdo Barnea
153a551c94aSIdo Barnea/**
154a551c94aSIdo Barnea * e1000_init_mac_params_82540 - Init MAC func ptrs.
155a551c94aSIdo Barnea * @hw: pointer to the HW structure
156a551c94aSIdo Barnea **/
157a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
158a551c94aSIdo Barnea{
159a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
160a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
161a551c94aSIdo Barnea
162a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_82540");
163a551c94aSIdo Barnea
164a551c94aSIdo Barnea	/* Set media type */
165a551c94aSIdo Barnea	switch (hw->device_id) {
166a551c94aSIdo Barnea	case E1000_DEV_ID_82545EM_FIBER:
167a551c94aSIdo Barnea	case E1000_DEV_ID_82545GM_FIBER:
168a551c94aSIdo Barnea	case E1000_DEV_ID_82546EB_FIBER:
169a551c94aSIdo Barnea	case E1000_DEV_ID_82546GB_FIBER:
170a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_fiber;
171a551c94aSIdo Barnea		break;
172a551c94aSIdo Barnea	case E1000_DEV_ID_82545GM_SERDES:
173a551c94aSIdo Barnea	case E1000_DEV_ID_82546GB_SERDES:
174a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_internal_serdes;
175a551c94aSIdo Barnea		break;
176a551c94aSIdo Barnea	default:
177a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_copper;
178a551c94aSIdo Barnea		break;
179a551c94aSIdo Barnea	}
180a551c94aSIdo Barnea
181a551c94aSIdo Barnea	/* Set mta register count */
182a551c94aSIdo Barnea	mac->mta_reg_count = 128;
183a551c94aSIdo Barnea	/* Set rar entry count */
184a551c94aSIdo Barnea	mac->rar_entry_count = E1000_RAR_ENTRIES;
185a551c94aSIdo Barnea
186a551c94aSIdo Barnea	/* Function pointers */
187a551c94aSIdo Barnea
188a551c94aSIdo Barnea	/* bus type/speed/width */
189a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
190a551c94aSIdo Barnea	/* function id */
191a551c94aSIdo Barnea	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
192a551c94aSIdo Barnea	/* reset */
193a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_82540;
194a551c94aSIdo Barnea	/* hw initialization */
195a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_82540;
196a551c94aSIdo Barnea	/* link setup */
197a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_generic;
198a551c94aSIdo Barnea	/* physical interface setup */
199a551c94aSIdo Barnea	mac->ops.setup_physical_interface =
200a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
201a551c94aSIdo Barnea			? e1000_setup_copper_link_82540
202a551c94aSIdo Barnea			: e1000_setup_fiber_serdes_link_82540;
203a551c94aSIdo Barnea	/* check for link */
204a551c94aSIdo Barnea	switch (hw->phy.media_type) {
205a551c94aSIdo Barnea	case e1000_media_type_copper:
206a551c94aSIdo Barnea		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
207a551c94aSIdo Barnea		break;
208a551c94aSIdo Barnea	case e1000_media_type_fiber:
209a551c94aSIdo Barnea		mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
210a551c94aSIdo Barnea		break;
211a551c94aSIdo Barnea	case e1000_media_type_internal_serdes:
212a551c94aSIdo Barnea		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
213a551c94aSIdo Barnea		break;
214a551c94aSIdo Barnea	default:
215a551c94aSIdo Barnea		ret_val = -E1000_ERR_CONFIG;
216a551c94aSIdo Barnea		goto out;
217a551c94aSIdo Barnea		break;
218a551c94aSIdo Barnea	}
219a551c94aSIdo Barnea	/* link info */
220a551c94aSIdo Barnea	mac->ops.get_link_up_info =
221a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
222a551c94aSIdo Barnea			? e1000_get_speed_and_duplex_copper_generic
223a551c94aSIdo Barnea			: e1000_get_speed_and_duplex_fiber_serdes_generic;
224a551c94aSIdo Barnea	/* multicast address update */
225a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
226a551c94aSIdo Barnea	/* writing VFTA */
227a551c94aSIdo Barnea	mac->ops.write_vfta = e1000_write_vfta_generic;
228a551c94aSIdo Barnea	/* clearing VFTA */
229a551c94aSIdo Barnea	mac->ops.clear_vfta = e1000_clear_vfta_generic;
230a551c94aSIdo Barnea	/* read mac address */
231a551c94aSIdo Barnea	mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
232a551c94aSIdo Barnea	/* ID LED init */
233a551c94aSIdo Barnea	mac->ops.id_led_init = e1000_id_led_init_generic;
234a551c94aSIdo Barnea	/* setup LED */
235a551c94aSIdo Barnea	mac->ops.setup_led = e1000_setup_led_generic;
236a551c94aSIdo Barnea	/* cleanup LED */
237a551c94aSIdo Barnea	mac->ops.cleanup_led = e1000_cleanup_led_generic;
238a551c94aSIdo Barnea	/* turn on/off LED */
239a551c94aSIdo Barnea	mac->ops.led_on = e1000_led_on_generic;
240a551c94aSIdo Barnea	mac->ops.led_off = e1000_led_off_generic;
241a551c94aSIdo Barnea	/* clear hardware counters */
242a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
243a551c94aSIdo Barnea
244a551c94aSIdo Barneaout:
245a551c94aSIdo Barnea	return ret_val;
246a551c94aSIdo Barnea}
247a551c94aSIdo Barnea
248a551c94aSIdo Barnea/**
249a551c94aSIdo Barnea * e1000_init_function_pointers_82540 - Init func ptrs.
250a551c94aSIdo Barnea * @hw: pointer to the HW structure
251a551c94aSIdo Barnea *
252a551c94aSIdo Barnea * Called to initialize all function pointers and parameters.
253a551c94aSIdo Barnea **/
254a551c94aSIdo Barneavoid e1000_init_function_pointers_82540(struct e1000_hw *hw)
255a551c94aSIdo Barnea{
256a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_function_pointers_82540");
257a551c94aSIdo Barnea
258a551c94aSIdo Barnea	hw->mac.ops.init_params = e1000_init_mac_params_82540;
259a551c94aSIdo Barnea	hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
260a551c94aSIdo Barnea	hw->phy.ops.init_params = e1000_init_phy_params_82540;
261a551c94aSIdo Barnea}
262a551c94aSIdo Barnea
263a551c94aSIdo Barnea/**
264a551c94aSIdo Barnea *  e1000_reset_hw_82540 - Reset hardware
265a551c94aSIdo Barnea *  @hw: pointer to the HW structure
266a551c94aSIdo Barnea *
267a551c94aSIdo Barnea *  This resets the hardware into a known state.
268a551c94aSIdo Barnea **/
269a551c94aSIdo BarneaSTATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)
270a551c94aSIdo Barnea{
271a551c94aSIdo Barnea	u32 ctrl, manc;
272a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
273a551c94aSIdo Barnea
274a551c94aSIdo Barnea	DEBUGFUNC("e1000_reset_hw_82540");
275a551c94aSIdo Barnea
276a551c94aSIdo Barnea	DEBUGOUT("Masking off all interrupts\n");
277a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
278a551c94aSIdo Barnea
279a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RCTL, 0);
280a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
281a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
282a551c94aSIdo Barnea
283a551c94aSIdo Barnea	/*
284a551c94aSIdo Barnea	 * Delay to allow any outstanding PCI transactions to complete
285a551c94aSIdo Barnea	 * before resetting the device.
286a551c94aSIdo Barnea	 */
287a551c94aSIdo Barnea	msec_delay(10);
288a551c94aSIdo Barnea
289a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
290a551c94aSIdo Barnea
291a551c94aSIdo Barnea	DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
292a551c94aSIdo Barnea	switch (hw->mac.type) {
293a551c94aSIdo Barnea	case e1000_82545_rev_3:
294a551c94aSIdo Barnea	case e1000_82546_rev_3:
295a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
296a551c94aSIdo Barnea		break;
297a551c94aSIdo Barnea	default:
298a551c94aSIdo Barnea		/*
299a551c94aSIdo Barnea		 * These controllers can't ack the 64-bit write when
300a551c94aSIdo Barnea		 * issuing the reset, so we use IO-mapping as a
301a551c94aSIdo Barnea		 * workaround to issue the reset.
302a551c94aSIdo Barnea		 */
303a551c94aSIdo Barnea		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
304a551c94aSIdo Barnea		break;
305a551c94aSIdo Barnea	}
306a551c94aSIdo Barnea
307a551c94aSIdo Barnea	/* Wait for EEPROM reload */
308a551c94aSIdo Barnea	msec_delay(5);
309a551c94aSIdo Barnea
310a551c94aSIdo Barnea	/* Disable HW ARPs on ASF enabled adapters */
311a551c94aSIdo Barnea	manc = E1000_READ_REG(hw, E1000_MANC);
312a551c94aSIdo Barnea	manc &= ~E1000_MANC_ARP_EN;
313a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_MANC, manc);
314a551c94aSIdo Barnea
315a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
316a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ICR);
317a551c94aSIdo Barnea
318a551c94aSIdo Barnea	return ret_val;
319a551c94aSIdo Barnea}
320a551c94aSIdo Barnea
321a551c94aSIdo Barnea/**
322a551c94aSIdo Barnea *  e1000_init_hw_82540 - Initialize hardware
323a551c94aSIdo Barnea *  @hw: pointer to the HW structure
324a551c94aSIdo Barnea *
325a551c94aSIdo Barnea *  This inits the hardware readying it for operation.
326a551c94aSIdo Barnea **/
327a551c94aSIdo BarneaSTATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)
328a551c94aSIdo Barnea{
329a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
330a551c94aSIdo Barnea	u32 txdctl, ctrl_ext;
331a551c94aSIdo Barnea	s32 ret_val;
332a551c94aSIdo Barnea	u16 i;
333a551c94aSIdo Barnea
334a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_hw_82540");
335a551c94aSIdo Barnea
336a551c94aSIdo Barnea	/* Initialize identification LED */
337a551c94aSIdo Barnea	ret_val = mac->ops.id_led_init(hw);
338a551c94aSIdo Barnea	if (ret_val) {
339a551c94aSIdo Barnea		DEBUGOUT("Error initializing identification LED\n");
340a551c94aSIdo Barnea		/* This is not fatal and we should not stop init due to this */
341a551c94aSIdo Barnea	}
342a551c94aSIdo Barnea
343a551c94aSIdo Barnea	/* Disabling VLAN filtering */
344a551c94aSIdo Barnea	DEBUGOUT("Initializing the IEEE VLAN\n");
345a551c94aSIdo Barnea	if (mac->type < e1000_82545_rev_3)
346a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_VET, 0);
347a551c94aSIdo Barnea
348a551c94aSIdo Barnea	mac->ops.clear_vfta(hw);
349a551c94aSIdo Barnea
350a551c94aSIdo Barnea	/* Setup the receive address. */
351a551c94aSIdo Barnea	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
352a551c94aSIdo Barnea
353a551c94aSIdo Barnea	/* Zero out the Multicast HASH table */
354a551c94aSIdo Barnea	DEBUGOUT("Zeroing the MTA\n");
355a551c94aSIdo Barnea	for (i = 0; i < mac->mta_reg_count; i++) {
356a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
357a551c94aSIdo Barnea		/*
358a551c94aSIdo Barnea		 * Avoid back to back register writes by adding the register
359a551c94aSIdo Barnea		 * read (flush).  This is to protect against some strange
360a551c94aSIdo Barnea		 * bridge configurations that may issue Memory Write Block
361a551c94aSIdo Barnea		 * (MWB) to our register space.  The *_rev_3 hardware at
362a551c94aSIdo Barnea		 * least doesn't respond correctly to every other dword in an
363a551c94aSIdo Barnea		 * MWB to our register space.
364a551c94aSIdo Barnea		 */
365a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
366a551c94aSIdo Barnea	}
367a551c94aSIdo Barnea
368a551c94aSIdo Barnea	if (mac->type < e1000_82545_rev_3)
369a551c94aSIdo Barnea		e1000_pcix_mmrbc_workaround_generic(hw);
370a551c94aSIdo Barnea
371a551c94aSIdo Barnea	/* Setup link and flow control */
372a551c94aSIdo Barnea	ret_val = mac->ops.setup_link(hw);
373a551c94aSIdo Barnea
374a551c94aSIdo Barnea	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
375a551c94aSIdo Barnea	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
376a551c94aSIdo Barnea		  E1000_TXDCTL_FULL_TX_DESC_WB;
377a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
378a551c94aSIdo Barnea
379a551c94aSIdo Barnea	/*
380a551c94aSIdo Barnea	 * Clear all of the statistics registers (clear on read).  It is
381a551c94aSIdo Barnea	 * important that we do this after we have tried to establish link
382a551c94aSIdo Barnea	 * because the symbol error count will increment wildly if there
383a551c94aSIdo Barnea	 * is no link.
384a551c94aSIdo Barnea	 */
385a551c94aSIdo Barnea	e1000_clear_hw_cntrs_82540(hw);
386a551c94aSIdo Barnea
387a551c94aSIdo Barnea	if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
388a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
389a551c94aSIdo Barnea		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
390a551c94aSIdo Barnea		/*
391a551c94aSIdo Barnea		 * Relaxed ordering must be disabled to avoid a parity
392a551c94aSIdo Barnea		 * error crash in a PCI slot.
393a551c94aSIdo Barnea		 */
394a551c94aSIdo Barnea		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
395a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
396a551c94aSIdo Barnea	}
397a551c94aSIdo Barnea
398a551c94aSIdo Barnea	return ret_val;
399a551c94aSIdo Barnea}
400a551c94aSIdo Barnea
401a551c94aSIdo Barnea/**
402a551c94aSIdo Barnea *  e1000_setup_copper_link_82540 - Configure copper link settings
403a551c94aSIdo Barnea *  @hw: pointer to the HW structure
404a551c94aSIdo Barnea *
405a551c94aSIdo Barnea *  Calls the appropriate function to configure the link for auto-neg or forced
406a551c94aSIdo Barnea *  speed and duplex.  Then we check for link, once link is established calls
407a551c94aSIdo Barnea *  to configure collision distance and flow control are called.  If link is
408a551c94aSIdo Barnea *  not established, we return -E1000_ERR_PHY (-2).
409a551c94aSIdo Barnea **/
410a551c94aSIdo BarneaSTATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
411a551c94aSIdo Barnea{
412a551c94aSIdo Barnea	u32 ctrl;
413a551c94aSIdo Barnea	s32 ret_val;
414a551c94aSIdo Barnea	u16 data;
415a551c94aSIdo Barnea
416a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_copper_link_82540");
417a551c94aSIdo Barnea
418a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
419a551c94aSIdo Barnea	ctrl |= E1000_CTRL_SLU;
420a551c94aSIdo Barnea	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
421a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
422a551c94aSIdo Barnea
423a551c94aSIdo Barnea	ret_val = e1000_set_phy_mode_82540(hw);
424a551c94aSIdo Barnea	if (ret_val)
425a551c94aSIdo Barnea		goto out;
426a551c94aSIdo Barnea
427a551c94aSIdo Barnea	if (hw->mac.type == e1000_82545_rev_3 ||
428a551c94aSIdo Barnea	    hw->mac.type == e1000_82546_rev_3) {
429a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
430a551c94aSIdo Barnea					       &data);
431a551c94aSIdo Barnea		if (ret_val)
432a551c94aSIdo Barnea			goto out;
433a551c94aSIdo Barnea		data |= 0x00000008;
434a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
435a551c94aSIdo Barnea						data);
436a551c94aSIdo Barnea		if (ret_val)
437a551c94aSIdo Barnea			goto out;
438a551c94aSIdo Barnea	}
439a551c94aSIdo Barnea
440a551c94aSIdo Barnea	ret_val = e1000_copper_link_setup_m88(hw);
441a551c94aSIdo Barnea	if (ret_val)
442a551c94aSIdo Barnea		goto out;
443a551c94aSIdo Barnea
444a551c94aSIdo Barnea	ret_val = e1000_setup_copper_link_generic(hw);
445a551c94aSIdo Barnea
446a551c94aSIdo Barneaout:
447a551c94aSIdo Barnea	return ret_val;
448a551c94aSIdo Barnea}
449a551c94aSIdo Barnea
450a551c94aSIdo Barnea/**
451a551c94aSIdo Barnea *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
452a551c94aSIdo Barnea *  @hw: pointer to the HW structure
453a551c94aSIdo Barnea *
454a551c94aSIdo Barnea *  Set the output amplitude to the value in the EEPROM and adjust the VCO
455a551c94aSIdo Barnea *  speed to improve Bit Error Rate (BER) performance.  Configures collision
456a551c94aSIdo Barnea *  distance and flow control for fiber and serdes links.  Upon successful
457a551c94aSIdo Barnea *  setup, poll for link.
458a551c94aSIdo Barnea **/
459a551c94aSIdo BarneaSTATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
460a551c94aSIdo Barnea{
461a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
462a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
463a551c94aSIdo Barnea
464a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
465a551c94aSIdo Barnea
466a551c94aSIdo Barnea	switch (mac->type) {
467a551c94aSIdo Barnea	case e1000_82545_rev_3:
468a551c94aSIdo Barnea	case e1000_82546_rev_3:
469a551c94aSIdo Barnea		if (hw->phy.media_type == e1000_media_type_internal_serdes) {
470a551c94aSIdo Barnea			/*
471a551c94aSIdo Barnea			 * If we're on serdes media, adjust the output
472a551c94aSIdo Barnea			 * amplitude to value set in the EEPROM.
473a551c94aSIdo Barnea			 */
474a551c94aSIdo Barnea			ret_val = e1000_adjust_serdes_amplitude_82540(hw);
475a551c94aSIdo Barnea			if (ret_val)
476a551c94aSIdo Barnea				goto out;
477a551c94aSIdo Barnea		}
478a551c94aSIdo Barnea		/* Adjust VCO speed to improve BER performance */
479a551c94aSIdo Barnea		ret_val = e1000_set_vco_speed_82540(hw);
480a551c94aSIdo Barnea		if (ret_val)
481a551c94aSIdo Barnea			goto out;
482a551c94aSIdo Barnea	default:
483a551c94aSIdo Barnea		break;
484a551c94aSIdo Barnea	}
485a551c94aSIdo Barnea
486a551c94aSIdo Barnea	ret_val = e1000_setup_fiber_serdes_link_generic(hw);
487a551c94aSIdo Barnea
488a551c94aSIdo Barneaout:
489a551c94aSIdo Barnea	return ret_val;
490a551c94aSIdo Barnea}
491a551c94aSIdo Barnea
492a551c94aSIdo Barnea/**
493a551c94aSIdo Barnea *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
494a551c94aSIdo Barnea *  @hw: pointer to the HW structure
495a551c94aSIdo Barnea *
496a551c94aSIdo Barnea *  Adjust the SERDES output amplitude based on the EEPROM settings.
497a551c94aSIdo Barnea **/
498a551c94aSIdo BarneaSTATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
499a551c94aSIdo Barnea{
500a551c94aSIdo Barnea	s32 ret_val;
501a551c94aSIdo Barnea	u16 nvm_data;
502a551c94aSIdo Barnea
503a551c94aSIdo Barnea	DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
504a551c94aSIdo Barnea
505a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
506a551c94aSIdo Barnea	if (ret_val)
507a551c94aSIdo Barnea		goto out;
508a551c94aSIdo Barnea
509a551c94aSIdo Barnea	if (nvm_data != NVM_RESERVED_WORD) {
510a551c94aSIdo Barnea		/* Adjust serdes output amplitude only. */
511a551c94aSIdo Barnea		nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
512a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
513a551c94aSIdo Barnea						nvm_data);
514a551c94aSIdo Barnea		if (ret_val)
515a551c94aSIdo Barnea			goto out;
516a551c94aSIdo Barnea	}
517a551c94aSIdo Barnea
518a551c94aSIdo Barneaout:
519a551c94aSIdo Barnea	return ret_val;
520a551c94aSIdo Barnea}
521a551c94aSIdo Barnea
522a551c94aSIdo Barnea/**
523a551c94aSIdo Barnea *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
524a551c94aSIdo Barnea *  @hw: pointer to the HW structure
525a551c94aSIdo Barnea *
526a551c94aSIdo Barnea *  Set the VCO speed to improve Bit Error Rate (BER) performance.
527a551c94aSIdo Barnea **/
528a551c94aSIdo BarneaSTATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
529a551c94aSIdo Barnea{
530a551c94aSIdo Barnea	s32  ret_val;
531a551c94aSIdo Barnea	u16 default_page = 0;
532a551c94aSIdo Barnea	u16 phy_data;
533a551c94aSIdo Barnea
534a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_vco_speed_82540");
535a551c94aSIdo Barnea
536a551c94aSIdo Barnea	/* Set PHY register 30, page 5, bit 8 to 0 */
537a551c94aSIdo Barnea
538a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
539a551c94aSIdo Barnea				       &default_page);
540a551c94aSIdo Barnea	if (ret_val)
541a551c94aSIdo Barnea		goto out;
542a551c94aSIdo Barnea
543a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
544a551c94aSIdo Barnea	if (ret_val)
545a551c94aSIdo Barnea		goto out;
546a551c94aSIdo Barnea
547a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
548a551c94aSIdo Barnea	if (ret_val)
549a551c94aSIdo Barnea		goto out;
550a551c94aSIdo Barnea
551a551c94aSIdo Barnea	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
552a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
553a551c94aSIdo Barnea	if (ret_val)
554a551c94aSIdo Barnea		goto out;
555a551c94aSIdo Barnea
556a551c94aSIdo Barnea	/* Set PHY register 30, page 4, bit 11 to 1 */
557a551c94aSIdo Barnea
558a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
559a551c94aSIdo Barnea	if (ret_val)
560a551c94aSIdo Barnea		goto out;
561a551c94aSIdo Barnea
562a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
563a551c94aSIdo Barnea	if (ret_val)
564a551c94aSIdo Barnea		goto out;
565a551c94aSIdo Barnea
566a551c94aSIdo Barnea	phy_data |= M88E1000_PHY_VCO_REG_BIT11;
567a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
568a551c94aSIdo Barnea	if (ret_val)
569a551c94aSIdo Barnea		goto out;
570a551c94aSIdo Barnea
571a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
572a551c94aSIdo Barnea					default_page);
573a551c94aSIdo Barnea
574a551c94aSIdo Barneaout:
575a551c94aSIdo Barnea	return ret_val;
576a551c94aSIdo Barnea}
577a551c94aSIdo Barnea
578a551c94aSIdo Barnea/**
579a551c94aSIdo Barnea *  e1000_set_phy_mode_82540 - Set PHY to class A mode
580a551c94aSIdo Barnea *  @hw: pointer to the HW structure
581a551c94aSIdo Barnea *
582a551c94aSIdo Barnea *  Sets the PHY to class A mode and assumes the following operations will
583a551c94aSIdo Barnea *  follow to enable the new class mode:
584a551c94aSIdo Barnea *    1.  Do a PHY soft reset.
585a551c94aSIdo Barnea *    2.  Restart auto-negotiation or force link.
586a551c94aSIdo Barnea **/
587a551c94aSIdo BarneaSTATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
588a551c94aSIdo Barnea{
589a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
590a551c94aSIdo Barnea	u16 nvm_data;
591a551c94aSIdo Barnea
592a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_phy_mode_82540");
593a551c94aSIdo Barnea
594a551c94aSIdo Barnea	if (hw->mac.type != e1000_82545_rev_3)
595a551c94aSIdo Barnea		goto out;
596a551c94aSIdo Barnea
597a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
598a551c94aSIdo Barnea	if (ret_val) {
599a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
600a551c94aSIdo Barnea		goto out;
601a551c94aSIdo Barnea	}
602a551c94aSIdo Barnea
603a551c94aSIdo Barnea	if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
604a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
605a551c94aSIdo Barnea						0x000B);
606a551c94aSIdo Barnea		if (ret_val) {
607a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
608a551c94aSIdo Barnea			goto out;
609a551c94aSIdo Barnea		}
610a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
611a551c94aSIdo Barnea						0x8104);
612a551c94aSIdo Barnea		if (ret_val) {
613a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
614a551c94aSIdo Barnea			goto out;
615a551c94aSIdo Barnea		}
616a551c94aSIdo Barnea
617a551c94aSIdo Barnea	}
618a551c94aSIdo Barnea
619a551c94aSIdo Barneaout:
620a551c94aSIdo Barnea	return ret_val;
621a551c94aSIdo Barnea}
622a551c94aSIdo Barnea
623a551c94aSIdo Barnea/**
624a551c94aSIdo Barnea * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
625a551c94aSIdo Barnea * @hw: pointer to the HW structure
626a551c94aSIdo Barnea *
627a551c94aSIdo Barnea * In the case of a PHY power down to save power, or to turn off link during a
628a551c94aSIdo Barnea * driver unload, or wake on lan is not enabled, remove the link.
629a551c94aSIdo Barnea **/
630a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
631a551c94aSIdo Barnea{
632a551c94aSIdo Barnea	/* If the management interface is not enabled, then power down */
633a551c94aSIdo Barnea	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
634a551c94aSIdo Barnea		e1000_power_down_phy_copper(hw);
635a551c94aSIdo Barnea
636a551c94aSIdo Barnea	return;
637a551c94aSIdo Barnea}
638a551c94aSIdo Barnea
639a551c94aSIdo Barnea/**
640a551c94aSIdo Barnea *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
641a551c94aSIdo Barnea *  @hw: pointer to the HW structure
642a551c94aSIdo Barnea *
643a551c94aSIdo Barnea *  Clears the hardware counters by reading the counter registers.
644a551c94aSIdo Barnea **/
645a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
646a551c94aSIdo Barnea{
647a551c94aSIdo Barnea	DEBUGFUNC("e1000_clear_hw_cntrs_82540");
648a551c94aSIdo Barnea
649a551c94aSIdo Barnea	e1000_clear_hw_cntrs_base_generic(hw);
650a551c94aSIdo Barnea
651a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC64);
652a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC127);
653a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC255);
654a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC511);
655a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC1023);
656a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC1522);
657a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC64);
658a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC127);
659a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC255);
660a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC511);
661a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC1023);
662a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC1522);
663a551c94aSIdo Barnea
664a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ALGNERRC);
665a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_RXERRC);
666a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_TNCRS);
667a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_CEXTERR);
668a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_TSCTC);
669a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_TSCTFC);
670a551c94aSIdo Barnea
671a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_MGTPRC);
672a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_MGTPDC);
673a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_MGTPTC);
674a551c94aSIdo Barnea}
675a551c94aSIdo Barnea
676a551c94aSIdo Barnea/**
677a551c94aSIdo Barnea *  e1000_read_mac_addr_82540 - Read device MAC address
678a551c94aSIdo Barnea *  @hw: pointer to the HW structure
679a551c94aSIdo Barnea *
680a551c94aSIdo Barnea *  Reads the device MAC address from the EEPROM and stores the value.
681a551c94aSIdo Barnea *  Since devices with two ports use the same EEPROM, we increment the
682a551c94aSIdo Barnea *  last bit in the MAC address for the second port.
683a551c94aSIdo Barnea *
684a551c94aSIdo Barnea *  This version is being used over generic because of customer issues
685a551c94aSIdo Barnea *  with VmWare and Virtual Box when using generic. It seems in
686a551c94aSIdo Barnea *  the emulated 82545, RAR[0] does NOT have a valid address after a
687a551c94aSIdo Barnea *  reset, this older method works and using this breaks nothing for
688a551c94aSIdo Barnea *  these legacy adapters.
689a551c94aSIdo Barnea **/
690a551c94aSIdo Barneas32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
691a551c94aSIdo Barnea{
692a551c94aSIdo Barnea	s32  ret_val = E1000_SUCCESS;
693a551c94aSIdo Barnea	u16 offset, nvm_data, i;
694a551c94aSIdo Barnea
695a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_mac_addr");
696a551c94aSIdo Barnea
697a551c94aSIdo Barnea	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
698a551c94aSIdo Barnea		offset = i >> 1;
699a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
700a551c94aSIdo Barnea		if (ret_val) {
701a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error\n");
702a551c94aSIdo Barnea			goto out;
703a551c94aSIdo Barnea		}
704a551c94aSIdo Barnea		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
705a551c94aSIdo Barnea		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
706a551c94aSIdo Barnea	}
707a551c94aSIdo Barnea
708a551c94aSIdo Barnea	/* Flip last bit of mac address if we're on second port */
709a551c94aSIdo Barnea	if (hw->bus.func == E1000_FUNC_1)
710a551c94aSIdo Barnea		hw->mac.perm_addr[5] ^= 1;
711a551c94aSIdo Barnea
712a551c94aSIdo Barnea	for (i = 0; i < ETH_ADDR_LEN; i++)
713a551c94aSIdo Barnea		hw->mac.addr[i] = hw->mac.perm_addr[i];
714a551c94aSIdo Barnea
715a551c94aSIdo Barneaout:
716a551c94aSIdo Barnea	return ret_val;
717a551c94aSIdo Barnea}