1/*******************************************************************************
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3Copyright (c) 2001-2015, Intel Corporation
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32***************************************************************************/
33
34#ifndef _E1000_82541_H_
35#define _E1000_82541_H_
36
37#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
38
39#define IGP01E1000_PHY_CHANNEL_NUM		4
40
41#define IGP01E1000_PHY_AGC_A			0x1172
42#define IGP01E1000_PHY_AGC_B			0x1272
43#define IGP01E1000_PHY_AGC_C			0x1472
44#define IGP01E1000_PHY_AGC_D			0x1872
45
46#define IGP01E1000_PHY_AGC_PARAM_A		0x1171
47#define IGP01E1000_PHY_AGC_PARAM_B		0x1271
48#define IGP01E1000_PHY_AGC_PARAM_C		0x1471
49#define IGP01E1000_PHY_AGC_PARAM_D		0x1871
50
51#define IGP01E1000_PHY_EDAC_MU_INDEX		0xC000
52#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS	0x8000
53
54#define IGP01E1000_PHY_DSP_RESET		0x1F33
55
56#define IGP01E1000_PHY_DSP_FFE			0x1F35
57#define IGP01E1000_PHY_DSP_FFE_CM_CP		0x0069
58#define IGP01E1000_PHY_DSP_FFE_DEFAULT		0x002A
59
60#define IGP01E1000_IEEE_FORCE_GIG		0x0140
61#define IGP01E1000_IEEE_RESTART_AUTONEG		0x3300
62
63#define IGP01E1000_AGC_LENGTH_SHIFT		7
64#define IGP01E1000_AGC_RANGE			10
65
66#define FFE_IDLE_ERR_COUNT_TIMEOUT_20		20
67#define FFE_IDLE_ERR_COUNT_TIMEOUT_100		100
68
69#define IGP01E1000_ANALOG_FUSE_STATUS		0x20D0
70#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS	0x20D1
71#define IGP01E1000_ANALOG_FUSE_CONTROL		0x20DC
72#define IGP01E1000_ANALOG_FUSE_BYPASS		0x20DE
73
74#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED	0x0100
75#define IGP01E1000_ANALOG_FUSE_FINE_MASK	0x0F80
76#define IGP01E1000_ANALOG_FUSE_COARSE_MASK	0x0070
77#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH	0x0040
78#define IGP01E1000_ANALOG_FUSE_COARSE_10	0x0010
79#define IGP01E1000_ANALOG_FUSE_FINE_1		0x0080
80#define IGP01E1000_ANALOG_FUSE_FINE_10		0x0500
81#define IGP01E1000_ANALOG_FUSE_POLY_MASK	0xF000
82#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
83
84#define IGP01E1000_MSE_CHANNEL_D		0x000F
85#define IGP01E1000_MSE_CHANNEL_C		0x00F0
86#define IGP01E1000_MSE_CHANNEL_B		0x0F00
87#define IGP01E1000_MSE_CHANNEL_A		0xF000
88
89
90void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);
91#endif
92