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3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
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7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
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9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
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16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
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20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_82541_H_
35a551c94aSIdo Barnea#define _E1000_82541_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barnea#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
38a551c94aSIdo Barnea
39a551c94aSIdo Barnea#define IGP01E1000_PHY_CHANNEL_NUM		4
40a551c94aSIdo Barnea
41a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_A			0x1172
42a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_B			0x1272
43a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_C			0x1472
44a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_D			0x1872
45a551c94aSIdo Barnea
46a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_PARAM_A		0x1171
47a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_PARAM_B		0x1271
48a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_PARAM_C		0x1471
49a551c94aSIdo Barnea#define IGP01E1000_PHY_AGC_PARAM_D		0x1871
50a551c94aSIdo Barnea
51a551c94aSIdo Barnea#define IGP01E1000_PHY_EDAC_MU_INDEX		0xC000
52a551c94aSIdo Barnea#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS	0x8000
53a551c94aSIdo Barnea
54a551c94aSIdo Barnea#define IGP01E1000_PHY_DSP_RESET		0x1F33
55a551c94aSIdo Barnea
56a551c94aSIdo Barnea#define IGP01E1000_PHY_DSP_FFE			0x1F35
57a551c94aSIdo Barnea#define IGP01E1000_PHY_DSP_FFE_CM_CP		0x0069
58a551c94aSIdo Barnea#define IGP01E1000_PHY_DSP_FFE_DEFAULT		0x002A
59a551c94aSIdo Barnea
60a551c94aSIdo Barnea#define IGP01E1000_IEEE_FORCE_GIG		0x0140
61a551c94aSIdo Barnea#define IGP01E1000_IEEE_RESTART_AUTONEG		0x3300
62a551c94aSIdo Barnea
63a551c94aSIdo Barnea#define IGP01E1000_AGC_LENGTH_SHIFT		7
64a551c94aSIdo Barnea#define IGP01E1000_AGC_RANGE			10
65a551c94aSIdo Barnea
66a551c94aSIdo Barnea#define FFE_IDLE_ERR_COUNT_TIMEOUT_20		20
67a551c94aSIdo Barnea#define FFE_IDLE_ERR_COUNT_TIMEOUT_100		100
68a551c94aSIdo Barnea
69a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_STATUS		0x20D0
70a551c94aSIdo Barnea#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS	0x20D1
71a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_CONTROL		0x20DC
72a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_BYPASS		0x20DE
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED	0x0100
75a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_FINE_MASK	0x0F80
76a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_COARSE_MASK	0x0070
77a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH	0x0040
78a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_COARSE_10	0x0010
79a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_FINE_1		0x0080
80a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_FINE_10		0x0500
81a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_POLY_MASK	0xF000
82a551c94aSIdo Barnea#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
83a551c94aSIdo Barnea
84a551c94aSIdo Barnea#define IGP01E1000_MSE_CHANNEL_D		0x000F
85a551c94aSIdo Barnea#define IGP01E1000_MSE_CHANNEL_C		0x00F0
86a551c94aSIdo Barnea#define IGP01E1000_MSE_CHANNEL_B		0x0F00
87a551c94aSIdo Barnea#define IGP01E1000_MSE_CHANNEL_A		0xF000
88a551c94aSIdo Barnea
89a551c94aSIdo Barnea
90a551c94aSIdo Barneavoid e1000_init_script_state_82541(struct e1000_hw *hw, bool state);
91a551c94aSIdo Barnea#endif
92