1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/*
35a551c94aSIdo Barnea * 82542 Gigabit Ethernet Controller
36a551c94aSIdo Barnea */
37a551c94aSIdo Barnea
38a551c94aSIdo Barnea#include "e1000_api.h"
39a551c94aSIdo Barnea
40a551c94aSIdo BarneaSTATIC s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
41a551c94aSIdo BarneaSTATIC s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
42a551c94aSIdo BarneaSTATIC s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
43a551c94aSIdo BarneaSTATIC s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
44a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_82542(struct e1000_hw *hw);
45a551c94aSIdo BarneaSTATIC s32  e1000_init_hw_82542(struct e1000_hw *hw);
46a551c94aSIdo BarneaSTATIC s32  e1000_setup_link_82542(struct e1000_hw *hw);
47a551c94aSIdo BarneaSTATIC s32  e1000_led_on_82542(struct e1000_hw *hw);
48a551c94aSIdo BarneaSTATIC s32  e1000_led_off_82542(struct e1000_hw *hw);
49a551c94aSIdo BarneaSTATIC int  e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
50a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
51a551c94aSIdo BarneaSTATIC s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
52a551c94aSIdo Barnea
53a551c94aSIdo Barnea/**
54a551c94aSIdo Barnea *  e1000_init_phy_params_82542 - Init PHY func ptrs.
55a551c94aSIdo Barnea *  @hw: pointer to the HW structure
56a551c94aSIdo Barnea **/
57a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
58a551c94aSIdo Barnea{
59a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
60a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
61a551c94aSIdo Barnea
62a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_82542");
63a551c94aSIdo Barnea
64a551c94aSIdo Barnea	phy->type = e1000_phy_none;
65a551c94aSIdo Barnea
66a551c94aSIdo Barnea	return ret_val;
67a551c94aSIdo Barnea}
68a551c94aSIdo Barnea
69a551c94aSIdo Barnea/**
70a551c94aSIdo Barnea *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
71a551c94aSIdo Barnea *  @hw: pointer to the HW structure
72a551c94aSIdo Barnea **/
73a551c94aSIdo BarneaSTATIC s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
74a551c94aSIdo Barnea{
75a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
76a551c94aSIdo Barnea
77a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_82542");
78a551c94aSIdo Barnea
79a551c94aSIdo Barnea	nvm->address_bits	=  6;
80a551c94aSIdo Barnea	nvm->delay_usec		= 50;
81a551c94aSIdo Barnea	nvm->opcode_bits	=  3;
82a551c94aSIdo Barnea	nvm->type		= e1000_nvm_eeprom_microwire;
83a551c94aSIdo Barnea	nvm->word_size		= 64;
84a551c94aSIdo Barnea
85a551c94aSIdo Barnea	/* Function Pointers */
86a551c94aSIdo Barnea	nvm->ops.read		= e1000_read_nvm_microwire;
87a551c94aSIdo Barnea	nvm->ops.release	= e1000_stop_nvm;
88a551c94aSIdo Barnea	nvm->ops.write		= e1000_write_nvm_microwire;
89a551c94aSIdo Barnea	nvm->ops.update		= e1000_update_nvm_checksum_generic;
90a551c94aSIdo Barnea	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
91a551c94aSIdo Barnea
92a551c94aSIdo Barnea	return E1000_SUCCESS;
93a551c94aSIdo Barnea}
94a551c94aSIdo Barnea
95a551c94aSIdo Barnea/**
96a551c94aSIdo Barnea *  e1000_init_mac_params_82542 - Init MAC func ptrs.
97a551c94aSIdo Barnea *  @hw: pointer to the HW structure
98a551c94aSIdo Barnea **/
99a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
100a551c94aSIdo Barnea{
101a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
102a551c94aSIdo Barnea
103a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_82542");
104a551c94aSIdo Barnea
105a551c94aSIdo Barnea	/* Set media type */
106a551c94aSIdo Barnea	hw->phy.media_type = e1000_media_type_fiber;
107a551c94aSIdo Barnea
108a551c94aSIdo Barnea	/* Set mta register count */
109a551c94aSIdo Barnea	mac->mta_reg_count = 128;
110a551c94aSIdo Barnea	/* Set rar entry count */
111a551c94aSIdo Barnea	mac->rar_entry_count = E1000_RAR_ENTRIES;
112a551c94aSIdo Barnea
113a551c94aSIdo Barnea	/* Function pointers */
114a551c94aSIdo Barnea
115a551c94aSIdo Barnea	/* bus type/speed/width */
116a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_82542;
117a551c94aSIdo Barnea	/* function id */
118a551c94aSIdo Barnea	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
119a551c94aSIdo Barnea	/* reset */
120a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_82542;
121a551c94aSIdo Barnea	/* hw initialization */
122a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_82542;
123a551c94aSIdo Barnea	/* link setup */
124a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_82542;
125a551c94aSIdo Barnea	/* phy/fiber/serdes setup */
126a551c94aSIdo Barnea	mac->ops.setup_physical_interface =
127a551c94aSIdo Barnea					e1000_setup_fiber_serdes_link_generic;
128a551c94aSIdo Barnea	/* check for link */
129a551c94aSIdo Barnea	mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
130a551c94aSIdo Barnea	/* multicast address update */
131a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
132a551c94aSIdo Barnea	/* writing VFTA */
133a551c94aSIdo Barnea	mac->ops.write_vfta = e1000_write_vfta_generic;
134a551c94aSIdo Barnea	/* clearing VFTA */
135a551c94aSIdo Barnea	mac->ops.clear_vfta = e1000_clear_vfta_generic;
136a551c94aSIdo Barnea	/* read mac address */
137a551c94aSIdo Barnea	mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
138a551c94aSIdo Barnea	/* set RAR */
139a551c94aSIdo Barnea	mac->ops.rar_set = e1000_rar_set_82542;
140a551c94aSIdo Barnea	/* turn on/off LED */
141a551c94aSIdo Barnea	mac->ops.led_on = e1000_led_on_82542;
142a551c94aSIdo Barnea	mac->ops.led_off = e1000_led_off_82542;
143a551c94aSIdo Barnea	/* clear hardware counters */
144a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
145a551c94aSIdo Barnea	/* link info */
146a551c94aSIdo Barnea	mac->ops.get_link_up_info =
147a551c94aSIdo Barnea				e1000_get_speed_and_duplex_fiber_serdes_generic;
148a551c94aSIdo Barnea
149a551c94aSIdo Barnea	return E1000_SUCCESS;
150a551c94aSIdo Barnea}
151a551c94aSIdo Barnea
152a551c94aSIdo Barnea/**
153a551c94aSIdo Barnea *  e1000_init_function_pointers_82542 - Init func ptrs.
154a551c94aSIdo Barnea *  @hw: pointer to the HW structure
155a551c94aSIdo Barnea *
156a551c94aSIdo Barnea *  Called to initialize all function pointers and parameters.
157a551c94aSIdo Barnea **/
158a551c94aSIdo Barneavoid e1000_init_function_pointers_82542(struct e1000_hw *hw)
159a551c94aSIdo Barnea{
160a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_function_pointers_82542");
161a551c94aSIdo Barnea
162a551c94aSIdo Barnea	hw->mac.ops.init_params = e1000_init_mac_params_82542;
163a551c94aSIdo Barnea	hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
164a551c94aSIdo Barnea	hw->phy.ops.init_params = e1000_init_phy_params_82542;
165a551c94aSIdo Barnea}
166a551c94aSIdo Barnea
167a551c94aSIdo Barnea/**
168a551c94aSIdo Barnea *  e1000_get_bus_info_82542 - Obtain bus information for adapter
169a551c94aSIdo Barnea *  @hw: pointer to the HW structure
170a551c94aSIdo Barnea *
171a551c94aSIdo Barnea *  This will obtain information about the HW bus for which the
172a551c94aSIdo Barnea *  adapter is attached and stores it in the hw structure.
173a551c94aSIdo Barnea **/
174a551c94aSIdo BarneaSTATIC s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
175a551c94aSIdo Barnea{
176a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_bus_info_82542");
177a551c94aSIdo Barnea
178a551c94aSIdo Barnea	hw->bus.type = e1000_bus_type_pci;
179a551c94aSIdo Barnea	hw->bus.speed = e1000_bus_speed_unknown;
180a551c94aSIdo Barnea	hw->bus.width = e1000_bus_width_unknown;
181a551c94aSIdo Barnea
182a551c94aSIdo Barnea	return E1000_SUCCESS;
183a551c94aSIdo Barnea}
184a551c94aSIdo Barnea
185a551c94aSIdo Barnea/**
186a551c94aSIdo Barnea *  e1000_reset_hw_82542 - Reset hardware
187a551c94aSIdo Barnea *  @hw: pointer to the HW structure
188a551c94aSIdo Barnea *
189a551c94aSIdo Barnea *  This resets the hardware into a known state.
190a551c94aSIdo Barnea **/
191a551c94aSIdo BarneaSTATIC s32 e1000_reset_hw_82542(struct e1000_hw *hw)
192a551c94aSIdo Barnea{
193a551c94aSIdo Barnea	struct e1000_bus_info *bus = &hw->bus;
194a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
195a551c94aSIdo Barnea	u32 ctrl;
196a551c94aSIdo Barnea
197a551c94aSIdo Barnea	DEBUGFUNC("e1000_reset_hw_82542");
198a551c94aSIdo Barnea
199a551c94aSIdo Barnea	if (hw->revision_id == E1000_REVISION_2) {
200a551c94aSIdo Barnea		DEBUGOUT("Disabling MWI on 82542 rev 2\n");
201a551c94aSIdo Barnea		e1000_pci_clear_mwi(hw);
202a551c94aSIdo Barnea	}
203a551c94aSIdo Barnea
204a551c94aSIdo Barnea	DEBUGOUT("Masking off all interrupts\n");
205a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
206a551c94aSIdo Barnea
207a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RCTL, 0);
208a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
209a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
210a551c94aSIdo Barnea
211a551c94aSIdo Barnea	/*
212a551c94aSIdo Barnea	 * Delay to allow any outstanding PCI transactions to complete before
213a551c94aSIdo Barnea	 * resetting the device
214a551c94aSIdo Barnea	 */
215a551c94aSIdo Barnea	msec_delay(10);
216a551c94aSIdo Barnea
217a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
218a551c94aSIdo Barnea
219a551c94aSIdo Barnea	DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
220a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
221a551c94aSIdo Barnea
222a551c94aSIdo Barnea	hw->nvm.ops.reload(hw);
223a551c94aSIdo Barnea	msec_delay(2);
224a551c94aSIdo Barnea
225a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
226a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ICR);
227a551c94aSIdo Barnea
228a551c94aSIdo Barnea	if (hw->revision_id == E1000_REVISION_2) {
229a551c94aSIdo Barnea		if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
230a551c94aSIdo Barnea			e1000_pci_set_mwi(hw);
231a551c94aSIdo Barnea	}
232a551c94aSIdo Barnea
233a551c94aSIdo Barnea	return ret_val;
234a551c94aSIdo Barnea}
235a551c94aSIdo Barnea
236a551c94aSIdo Barnea/**
237a551c94aSIdo Barnea *  e1000_init_hw_82542 - Initialize hardware
238a551c94aSIdo Barnea *  @hw: pointer to the HW structure
239a551c94aSIdo Barnea *
240a551c94aSIdo Barnea *  This inits the hardware readying it for operation.
241a551c94aSIdo Barnea **/
242a551c94aSIdo BarneaSTATIC s32 e1000_init_hw_82542(struct e1000_hw *hw)
243a551c94aSIdo Barnea{
244a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
245a551c94aSIdo Barnea	struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
246a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
247a551c94aSIdo Barnea	u32 ctrl;
248a551c94aSIdo Barnea	u16 i;
249a551c94aSIdo Barnea
250a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_hw_82542");
251a551c94aSIdo Barnea
252a551c94aSIdo Barnea	/* Disabling VLAN filtering */
253a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_VET, 0);
254a551c94aSIdo Barnea	mac->ops.clear_vfta(hw);
255a551c94aSIdo Barnea
256a551c94aSIdo Barnea	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
257a551c94aSIdo Barnea	if (hw->revision_id == E1000_REVISION_2) {
258a551c94aSIdo Barnea		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
259a551c94aSIdo Barnea		e1000_pci_clear_mwi(hw);
260a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
261a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
262a551c94aSIdo Barnea		msec_delay(5);
263a551c94aSIdo Barnea	}
264a551c94aSIdo Barnea
265a551c94aSIdo Barnea	/* Setup the receive address. */
266a551c94aSIdo Barnea	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
267a551c94aSIdo Barnea
268a551c94aSIdo Barnea	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
269a551c94aSIdo Barnea	if (hw->revision_id == E1000_REVISION_2) {
270a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_RCTL, 0);
271a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
272a551c94aSIdo Barnea		msec_delay(1);
273a551c94aSIdo Barnea		if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
274a551c94aSIdo Barnea			e1000_pci_set_mwi(hw);
275a551c94aSIdo Barnea	}
276a551c94aSIdo Barnea
277a551c94aSIdo Barnea	/* Zero out the Multicast HASH table */
278a551c94aSIdo Barnea	DEBUGOUT("Zeroing the MTA\n");
279a551c94aSIdo Barnea	for (i = 0; i < mac->mta_reg_count; i++)
280a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
281a551c94aSIdo Barnea
282a551c94aSIdo Barnea	/*
283a551c94aSIdo Barnea	 * Set the PCI priority bit correctly in the CTRL register.  This
284a551c94aSIdo Barnea	 * determines if the adapter gives priority to receives, or if it
285a551c94aSIdo Barnea	 * gives equal priority to transmits and receives.
286a551c94aSIdo Barnea	 */
287a551c94aSIdo Barnea	if (dev_spec->dma_fairness) {
288a551c94aSIdo Barnea		ctrl = E1000_READ_REG(hw, E1000_CTRL);
289a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
290a551c94aSIdo Barnea	}
291a551c94aSIdo Barnea
292a551c94aSIdo Barnea	/* Setup link and flow control */
293a551c94aSIdo Barnea	ret_val = e1000_setup_link_82542(hw);
294a551c94aSIdo Barnea
295a551c94aSIdo Barnea	/*
296a551c94aSIdo Barnea	 * Clear all of the statistics registers (clear on read).  It is
297a551c94aSIdo Barnea	 * important that we do this after we have tried to establish link
298a551c94aSIdo Barnea	 * because the symbol error count will increment wildly if there
299a551c94aSIdo Barnea	 * is no link.
300a551c94aSIdo Barnea	 */
301a551c94aSIdo Barnea	e1000_clear_hw_cntrs_82542(hw);
302a551c94aSIdo Barnea
303a551c94aSIdo Barnea	return ret_val;
304a551c94aSIdo Barnea}
305a551c94aSIdo Barnea
306a551c94aSIdo Barnea/**
307a551c94aSIdo Barnea *  e1000_setup_link_82542 - Setup flow control and link settings
308a551c94aSIdo Barnea *  @hw: pointer to the HW structure
309a551c94aSIdo Barnea *
310a551c94aSIdo Barnea *  Determines which flow control settings to use, then configures flow
311a551c94aSIdo Barnea *  control.  Calls the appropriate media-specific link configuration
312a551c94aSIdo Barnea *  function.  Assuming the adapter has a valid link partner, a valid link
313a551c94aSIdo Barnea *  should be established.  Assumes the hardware has previously been reset
314a551c94aSIdo Barnea *  and the transmitter and receiver are not enabled.
315a551c94aSIdo Barnea **/
316a551c94aSIdo BarneaSTATIC s32 e1000_setup_link_82542(struct e1000_hw *hw)
317a551c94aSIdo Barnea{
318a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
319a551c94aSIdo Barnea	s32 ret_val;
320a551c94aSIdo Barnea
321a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_link_82542");
322a551c94aSIdo Barnea
323a551c94aSIdo Barnea	ret_val = e1000_set_default_fc_generic(hw);
324a551c94aSIdo Barnea	if (ret_val)
325a551c94aSIdo Barnea		goto out;
326a551c94aSIdo Barnea
327a551c94aSIdo Barnea	hw->fc.requested_mode &= ~e1000_fc_tx_pause;
328a551c94aSIdo Barnea
329a551c94aSIdo Barnea	if (mac->report_tx_early)
330a551c94aSIdo Barnea		hw->fc.requested_mode &= ~e1000_fc_rx_pause;
331a551c94aSIdo Barnea
332a551c94aSIdo Barnea	/*
333a551c94aSIdo Barnea	 * Save off the requested flow control mode for use later.  Depending
334a551c94aSIdo Barnea	 * on the link partner's capabilities, we may or may not use this mode.
335a551c94aSIdo Barnea	 */
336a551c94aSIdo Barnea	hw->fc.current_mode = hw->fc.requested_mode;
337a551c94aSIdo Barnea
338a551c94aSIdo Barnea	DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
339a551c94aSIdo Barnea		  hw->fc.current_mode);
340a551c94aSIdo Barnea
341a551c94aSIdo Barnea	/* Call the necessary subroutine to configure the link. */
342a551c94aSIdo Barnea	ret_val = mac->ops.setup_physical_interface(hw);
343a551c94aSIdo Barnea	if (ret_val)
344a551c94aSIdo Barnea		goto out;
345a551c94aSIdo Barnea
346a551c94aSIdo Barnea	/*
347a551c94aSIdo Barnea	 * Initialize the flow control address, type, and PAUSE timer
348a551c94aSIdo Barnea	 * registers to their default values.  This is done even if flow
349a551c94aSIdo Barnea	 * control is disabled, because it does not hurt anything to
350a551c94aSIdo Barnea	 * initialize these registers.
351a551c94aSIdo Barnea	 */
352a551c94aSIdo Barnea	DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
353a551c94aSIdo Barnea
354a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
355a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
356a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
357a551c94aSIdo Barnea
358a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
359a551c94aSIdo Barnea
360a551c94aSIdo Barnea	ret_val = e1000_set_fc_watermarks_generic(hw);
361a551c94aSIdo Barnea
362a551c94aSIdo Barneaout:
363a551c94aSIdo Barnea	return ret_val;
364a551c94aSIdo Barnea}
365a551c94aSIdo Barnea
366a551c94aSIdo Barnea/**
367a551c94aSIdo Barnea *  e1000_led_on_82542 - Turn on SW controllable LED
368a551c94aSIdo Barnea *  @hw: pointer to the HW structure
369a551c94aSIdo Barnea *
370a551c94aSIdo Barnea *  Turns the SW defined LED on.
371a551c94aSIdo Barnea **/
372a551c94aSIdo BarneaSTATIC s32 e1000_led_on_82542(struct e1000_hw *hw)
373a551c94aSIdo Barnea{
374a551c94aSIdo Barnea	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
375a551c94aSIdo Barnea
376a551c94aSIdo Barnea	DEBUGFUNC("e1000_led_on_82542");
377a551c94aSIdo Barnea
378a551c94aSIdo Barnea	ctrl |= E1000_CTRL_SWDPIN0;
379a551c94aSIdo Barnea	ctrl |= E1000_CTRL_SWDPIO0;
380a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
381a551c94aSIdo Barnea
382a551c94aSIdo Barnea	return E1000_SUCCESS;
383a551c94aSIdo Barnea}
384a551c94aSIdo Barnea
385a551c94aSIdo Barnea/**
386a551c94aSIdo Barnea *  e1000_led_off_82542 - Turn off SW controllable LED
387a551c94aSIdo Barnea *  @hw: pointer to the HW structure
388a551c94aSIdo Barnea *
389a551c94aSIdo Barnea *  Turns the SW defined LED off.
390a551c94aSIdo Barnea **/
391a551c94aSIdo BarneaSTATIC s32 e1000_led_off_82542(struct e1000_hw *hw)
392a551c94aSIdo Barnea{
393a551c94aSIdo Barnea	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
394a551c94aSIdo Barnea
395a551c94aSIdo Barnea	DEBUGFUNC("e1000_led_off_82542");
396a551c94aSIdo Barnea
397a551c94aSIdo Barnea	ctrl &= ~E1000_CTRL_SWDPIN0;
398a551c94aSIdo Barnea	ctrl |= E1000_CTRL_SWDPIO0;
399a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
400a551c94aSIdo Barnea
401a551c94aSIdo Barnea	return E1000_SUCCESS;
402a551c94aSIdo Barnea}
403a551c94aSIdo Barnea
404a551c94aSIdo Barnea/**
405a551c94aSIdo Barnea *  e1000_rar_set_82542 - Set receive address register
406a551c94aSIdo Barnea *  @hw: pointer to the HW structure
407a551c94aSIdo Barnea *  @addr: pointer to the receive address
408a551c94aSIdo Barnea *  @index: receive address array register
409a551c94aSIdo Barnea *
410a551c94aSIdo Barnea *  Sets the receive address array register at index to the address passed
411a551c94aSIdo Barnea *  in by addr.
412a551c94aSIdo Barnea **/
413a551c94aSIdo BarneaSTATIC int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
414a551c94aSIdo Barnea{
415a551c94aSIdo Barnea	u32 rar_low, rar_high;
416a551c94aSIdo Barnea
417a551c94aSIdo Barnea	DEBUGFUNC("e1000_rar_set_82542");
418a551c94aSIdo Barnea
419a551c94aSIdo Barnea	/*
420a551c94aSIdo Barnea	 * HW expects these in little endian so we reverse the byte order
421a551c94aSIdo Barnea	 * from network order (big endian) to little endian
422a551c94aSIdo Barnea	 */
423a551c94aSIdo Barnea	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
424a551c94aSIdo Barnea		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
425a551c94aSIdo Barnea
426a551c94aSIdo Barnea	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
427a551c94aSIdo Barnea
428a551c94aSIdo Barnea	/* If MAC address zero, no need to set the AV bit */
429a551c94aSIdo Barnea	if (rar_low || rar_high)
430a551c94aSIdo Barnea		rar_high |= E1000_RAH_AV;
431a551c94aSIdo Barnea
432a551c94aSIdo Barnea	E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
433a551c94aSIdo Barnea	E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
434a551c94aSIdo Barnea
435a551c94aSIdo Barnea	return E1000_SUCCESS;
436a551c94aSIdo Barnea}
437a551c94aSIdo Barnea
438a551c94aSIdo Barnea/**
439a551c94aSIdo Barnea *  e1000_translate_register_82542 - Translate the proper register offset
440a551c94aSIdo Barnea *  @reg: e1000 register to be read
441a551c94aSIdo Barnea *
442a551c94aSIdo Barnea *  Registers in 82542 are located in different offsets than other adapters
443a551c94aSIdo Barnea *  even though they function in the same manner.  This function takes in
444a551c94aSIdo Barnea *  the name of the register to read and returns the correct offset for
445a551c94aSIdo Barnea *  82542 silicon.
446a551c94aSIdo Barnea **/
447a551c94aSIdo Barneau32 e1000_translate_register_82542(u32 reg)
448a551c94aSIdo Barnea{
449a551c94aSIdo Barnea	/*
450a551c94aSIdo Barnea	 * Some of the 82542 registers are located at different
451a551c94aSIdo Barnea	 * offsets than they are in newer adapters.
452a551c94aSIdo Barnea	 * Despite the difference in location, the registers
453a551c94aSIdo Barnea	 * function in the same manner.
454a551c94aSIdo Barnea	 */
455a551c94aSIdo Barnea	switch (reg) {
456a551c94aSIdo Barnea	case E1000_RA:
457a551c94aSIdo Barnea		reg = 0x00040;
458a551c94aSIdo Barnea		break;
459a551c94aSIdo Barnea	case E1000_RDTR:
460a551c94aSIdo Barnea		reg = 0x00108;
461a551c94aSIdo Barnea		break;
462a551c94aSIdo Barnea	case E1000_RDBAL(0):
463a551c94aSIdo Barnea		reg = 0x00110;
464a551c94aSIdo Barnea		break;
465a551c94aSIdo Barnea	case E1000_RDBAH(0):
466a551c94aSIdo Barnea		reg = 0x00114;
467a551c94aSIdo Barnea		break;
468a551c94aSIdo Barnea	case E1000_RDLEN(0):
469a551c94aSIdo Barnea		reg = 0x00118;
470a551c94aSIdo Barnea		break;
471a551c94aSIdo Barnea	case E1000_RDH(0):
472a551c94aSIdo Barnea		reg = 0x00120;
473a551c94aSIdo Barnea		break;
474a551c94aSIdo Barnea	case E1000_RDT(0):
475a551c94aSIdo Barnea		reg = 0x00128;
476a551c94aSIdo Barnea		break;
477a551c94aSIdo Barnea	case E1000_RDBAL(1):
478a551c94aSIdo Barnea		reg = 0x00138;
479a551c94aSIdo Barnea		break;
480a551c94aSIdo Barnea	case E1000_RDBAH(1):
481a551c94aSIdo Barnea		reg = 0x0013C;
482a551c94aSIdo Barnea		break;
483a551c94aSIdo Barnea	case E1000_RDLEN(1):
484a551c94aSIdo Barnea		reg = 0x00140;
485a551c94aSIdo Barnea		break;
486a551c94aSIdo Barnea	case E1000_RDH(1):
487a551c94aSIdo Barnea		reg = 0x00148;
488a551c94aSIdo Barnea		break;
489a551c94aSIdo Barnea	case E1000_RDT(1):
490a551c94aSIdo Barnea		reg = 0x00150;
491a551c94aSIdo Barnea		break;
492a551c94aSIdo Barnea	case E1000_FCRTH:
493a551c94aSIdo Barnea		reg = 0x00160;
494a551c94aSIdo Barnea		break;
495a551c94aSIdo Barnea	case E1000_FCRTL:
496a551c94aSIdo Barnea		reg = 0x00168;
497a551c94aSIdo Barnea		break;
498a551c94aSIdo Barnea	case E1000_MTA:
499a551c94aSIdo Barnea		reg = 0x00200;
500a551c94aSIdo Barnea		break;
501a551c94aSIdo Barnea	case E1000_TDBAL(0):
502a551c94aSIdo Barnea		reg = 0x00420;
503a551c94aSIdo Barnea		break;
504a551c94aSIdo Barnea	case E1000_TDBAH(0):
505a551c94aSIdo Barnea		reg = 0x00424;
506a551c94aSIdo Barnea		break;
507a551c94aSIdo Barnea	case E1000_TDLEN(0):
508a551c94aSIdo Barnea		reg = 0x00428;
509a551c94aSIdo Barnea		break;
510a551c94aSIdo Barnea	case E1000_TDH(0):
511a551c94aSIdo Barnea		reg = 0x00430;
512a551c94aSIdo Barnea		break;
513a551c94aSIdo Barnea	case E1000_TDT(0):
514a551c94aSIdo Barnea		reg = 0x00438;
515a551c94aSIdo Barnea		break;
516a551c94aSIdo Barnea	case E1000_TIDV:
517a551c94aSIdo Barnea		reg = 0x00440;
518a551c94aSIdo Barnea		break;
519a551c94aSIdo Barnea	case E1000_VFTA:
520a551c94aSIdo Barnea		reg = 0x00600;
521a551c94aSIdo Barnea		break;
522a551c94aSIdo Barnea	case E1000_TDFH:
523a551c94aSIdo Barnea		reg = 0x08010;
524a551c94aSIdo Barnea		break;
525a551c94aSIdo Barnea	case E1000_TDFT:
526a551c94aSIdo Barnea		reg = 0x08018;
527a551c94aSIdo Barnea		break;
528a551c94aSIdo Barnea	default:
529a551c94aSIdo Barnea		break;
530a551c94aSIdo Barnea	}
531a551c94aSIdo Barnea
532a551c94aSIdo Barnea	return reg;
533a551c94aSIdo Barnea}
534a551c94aSIdo Barnea
535a551c94aSIdo Barnea/**
536a551c94aSIdo Barnea *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
537a551c94aSIdo Barnea *  @hw: pointer to the HW structure
538a551c94aSIdo Barnea *
539a551c94aSIdo Barnea *  Clears the hardware counters by reading the counter registers.
540a551c94aSIdo Barnea **/
541a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
542a551c94aSIdo Barnea{
543a551c94aSIdo Barnea	DEBUGFUNC("e1000_clear_hw_cntrs_82542");
544a551c94aSIdo Barnea
545a551c94aSIdo Barnea	e1000_clear_hw_cntrs_base_generic(hw);
546a551c94aSIdo Barnea
547a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC64);
548a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC127);
549a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC255);
550a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC511);
551a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC1023);
552a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PRC1522);
553a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC64);
554a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC127);
555a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC255);
556a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC511);
557a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC1023);
558a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_PTC1522);
559a551c94aSIdo Barnea}
560a551c94aSIdo Barnea
561a551c94aSIdo Barnea/**
562a551c94aSIdo Barnea *  e1000_read_mac_addr_82542 - Read device MAC address
563a551c94aSIdo Barnea *  @hw: pointer to the HW structure
564a551c94aSIdo Barnea *
565a551c94aSIdo Barnea *  Reads the device MAC address from the EEPROM and stores the value.
566a551c94aSIdo Barnea **/
567a551c94aSIdo Barneas32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
568a551c94aSIdo Barnea{
569a551c94aSIdo Barnea	s32  ret_val = E1000_SUCCESS;
570a551c94aSIdo Barnea	u16 offset, nvm_data, i;
571a551c94aSIdo Barnea
572a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_mac_addr");
573a551c94aSIdo Barnea
574a551c94aSIdo Barnea	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
575a551c94aSIdo Barnea		offset = i >> 1;
576a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
577a551c94aSIdo Barnea		if (ret_val) {
578a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error\n");
579a551c94aSIdo Barnea			goto out;
580a551c94aSIdo Barnea		}
581a551c94aSIdo Barnea		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
582a551c94aSIdo Barnea		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
583a551c94aSIdo Barnea	}
584a551c94aSIdo Barnea
585a551c94aSIdo Barnea	for (i = 0; i < ETH_ADDR_LEN; i++)
586a551c94aSIdo Barnea		hw->mac.addr[i] = hw->mac.perm_addr[i];
587a551c94aSIdo Barnea
588a551c94aSIdo Barneaout:
589a551c94aSIdo Barnea	return ret_val;
590a551c94aSIdo Barnea}
591