1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*
35 * 82543GC Gigabit Ethernet Controller (Fiber)
36 * 82543GC Gigabit Ethernet Controller (Copper)
37 * 82544EI Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Fiber)
39 * 82544GC Gigabit Ethernet Controller (Copper)
40 * 82544GC Gigabit Ethernet Controller (LOM)
41 */
42
43#include "e1000_api.h"
44
45STATIC s32  e1000_init_phy_params_82543(struct e1000_hw *hw);
46STATIC s32  e1000_init_nvm_params_82543(struct e1000_hw *hw);
47STATIC s32  e1000_init_mac_params_82543(struct e1000_hw *hw);
48STATIC s32  e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
49				     u16 *data);
50STATIC s32  e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51				      u16 data);
52STATIC s32  e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
53STATIC s32  e1000_phy_hw_reset_82543(struct e1000_hw *hw);
54STATIC s32  e1000_reset_hw_82543(struct e1000_hw *hw);
55STATIC s32  e1000_init_hw_82543(struct e1000_hw *hw);
56STATIC s32  e1000_setup_link_82543(struct e1000_hw *hw);
57STATIC s32  e1000_setup_copper_link_82543(struct e1000_hw *hw);
58STATIC s32  e1000_setup_fiber_link_82543(struct e1000_hw *hw);
59STATIC s32  e1000_check_for_copper_link_82543(struct e1000_hw *hw);
60STATIC s32  e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
61STATIC s32  e1000_led_on_82543(struct e1000_hw *hw);
62STATIC s32  e1000_led_off_82543(struct e1000_hw *hw);
63STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
64				   u32 value);
65STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
66STATIC s32  e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
67STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
68STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
69STATIC s32  e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
70STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
71STATIC u16  e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
72STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
73					   u16 count);
74STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
75STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
76
77/**
78 *  e1000_init_phy_params_82543 - Init PHY func ptrs.
79 *  @hw: pointer to the HW structure
80 **/
81STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
82{
83	struct e1000_phy_info *phy = &hw->phy;
84	s32 ret_val = E1000_SUCCESS;
85
86	DEBUGFUNC("e1000_init_phy_params_82543");
87
88	if (hw->phy.media_type != e1000_media_type_copper) {
89		phy->type = e1000_phy_none;
90		goto out;
91	} else {
92		phy->ops.power_up = e1000_power_up_phy_copper;
93		phy->ops.power_down = e1000_power_down_phy_copper;
94	}
95
96	phy->addr		= 1;
97	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
98	phy->reset_delay_us	= 10000;
99	phy->type		= e1000_phy_m88;
100
101	/* Function Pointers */
102	phy->ops.check_polarity	= e1000_check_polarity_m88;
103	phy->ops.commit		= e1000_phy_sw_reset_generic;
104	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
105	phy->ops.get_cable_length = e1000_get_cable_length_m88;
106	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
107	phy->ops.read_reg	= (hw->mac.type == e1000_82543)
108				  ? e1000_read_phy_reg_82543
109				  : e1000_read_phy_reg_m88;
110	phy->ops.reset		= (hw->mac.type == e1000_82543)
111				  ? e1000_phy_hw_reset_82543
112				  : e1000_phy_hw_reset_generic;
113	phy->ops.write_reg	= (hw->mac.type == e1000_82543)
114				  ? e1000_write_phy_reg_82543
115				  : e1000_write_phy_reg_m88;
116	phy->ops.get_info	= e1000_get_phy_info_m88;
117
118	/*
119	 * The external PHY of the 82543 can be in a funky state.
120	 * Resetting helps us read the PHY registers for acquiring
121	 * the PHY ID.
122	 */
123	if (!e1000_init_phy_disabled_82543(hw)) {
124		ret_val = phy->ops.reset(hw);
125		if (ret_val) {
126			DEBUGOUT("Resetting PHY during init failed.\n");
127			goto out;
128		}
129		msec_delay(20);
130	}
131
132	ret_val = e1000_get_phy_id(hw);
133	if (ret_val)
134		goto out;
135
136	/* Verify phy id */
137	switch (hw->mac.type) {
138	case e1000_82543:
139		if (phy->id != M88E1000_E_PHY_ID) {
140			ret_val = -E1000_ERR_PHY;
141			goto out;
142		}
143		break;
144	case e1000_82544:
145		if (phy->id != M88E1000_I_PHY_ID) {
146			ret_val = -E1000_ERR_PHY;
147			goto out;
148		}
149		break;
150	default:
151		ret_val = -E1000_ERR_PHY;
152		goto out;
153		break;
154	}
155
156out:
157	return ret_val;
158}
159
160/**
161 *  e1000_init_nvm_params_82543 - Init NVM func ptrs.
162 *  @hw: pointer to the HW structure
163 **/
164STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
165{
166	struct e1000_nvm_info *nvm = &hw->nvm;
167
168	DEBUGFUNC("e1000_init_nvm_params_82543");
169
170	nvm->type		= e1000_nvm_eeprom_microwire;
171	nvm->word_size		= 64;
172	nvm->delay_usec		= 50;
173	nvm->address_bits	=  6;
174	nvm->opcode_bits	=  3;
175
176	/* Function Pointers */
177	nvm->ops.read		= e1000_read_nvm_microwire;
178	nvm->ops.update		= e1000_update_nvm_checksum_generic;
179	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
180	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
181	nvm->ops.write		= e1000_write_nvm_microwire;
182
183	return E1000_SUCCESS;
184}
185
186/**
187 *  e1000_init_mac_params_82543 - Init MAC func ptrs.
188 *  @hw: pointer to the HW structure
189 **/
190STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
191{
192	struct e1000_mac_info *mac = &hw->mac;
193
194	DEBUGFUNC("e1000_init_mac_params_82543");
195
196	/* Set media type */
197	switch (hw->device_id) {
198	case E1000_DEV_ID_82543GC_FIBER:
199	case E1000_DEV_ID_82544EI_FIBER:
200		hw->phy.media_type = e1000_media_type_fiber;
201		break;
202	default:
203		hw->phy.media_type = e1000_media_type_copper;
204		break;
205	}
206
207	/* Set mta register count */
208	mac->mta_reg_count = 128;
209	/* Set rar entry count */
210	mac->rar_entry_count = E1000_RAR_ENTRIES;
211
212	/* Function pointers */
213
214	/* bus type/speed/width */
215	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
216	/* function id */
217	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
218	/* reset */
219	mac->ops.reset_hw = e1000_reset_hw_82543;
220	/* hw initialization */
221	mac->ops.init_hw = e1000_init_hw_82543;
222	/* link setup */
223	mac->ops.setup_link = e1000_setup_link_82543;
224	/* physical interface setup */
225	mac->ops.setup_physical_interface =
226		(hw->phy.media_type == e1000_media_type_copper)
227		 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;
228	/* check for link */
229	mac->ops.check_for_link =
230		(hw->phy.media_type == e1000_media_type_copper)
231		 ? e1000_check_for_copper_link_82543
232		 : e1000_check_for_fiber_link_82543;
233	/* link info */
234	mac->ops.get_link_up_info =
235		(hw->phy.media_type == e1000_media_type_copper)
236		 ? e1000_get_speed_and_duplex_copper_generic
237		 : e1000_get_speed_and_duplex_fiber_serdes_generic;
238	/* multicast address update */
239	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
240	/* writing VFTA */
241	mac->ops.write_vfta = e1000_write_vfta_82543;
242	/* clearing VFTA */
243	mac->ops.clear_vfta = e1000_clear_vfta_generic;
244	/* turn on/off LED */
245	mac->ops.led_on = e1000_led_on_82543;
246	mac->ops.led_off = e1000_led_off_82543;
247	/* clear hardware counters */
248	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
249
250	/* Set tbi compatibility */
251	if ((hw->mac.type != e1000_82543) ||
252	    (hw->phy.media_type == e1000_media_type_fiber))
253		e1000_set_tbi_compatibility_82543(hw, false);
254
255	return E1000_SUCCESS;
256}
257
258/**
259 *  e1000_init_function_pointers_82543 - Init func ptrs.
260 *  @hw: pointer to the HW structure
261 *
262 *  Called to initialize all function pointers and parameters.
263 **/
264void e1000_init_function_pointers_82543(struct e1000_hw *hw)
265{
266	DEBUGFUNC("e1000_init_function_pointers_82543");
267
268	hw->mac.ops.init_params = e1000_init_mac_params_82543;
269	hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
270	hw->phy.ops.init_params = e1000_init_phy_params_82543;
271}
272
273/**
274 *  e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
275 *  @hw: pointer to the HW structure
276 *
277 *  Returns the current status of 10-bit Interface (TBI) compatibility
278 *  (enabled/disabled).
279 **/
280STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
281{
282	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
283	bool state = false;
284
285	DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
286
287	if (hw->mac.type != e1000_82543) {
288		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
289		goto out;
290	}
291
292	state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);
293
294out:
295	return state;
296}
297
298/**
299 *  e1000_set_tbi_compatibility_82543 - Set TBI compatibility
300 *  @hw: pointer to the HW structure
301 *  @state: enable/disable TBI compatibility
302 *
303 *  Enables or disabled 10-bit Interface (TBI) compatibility.
304 **/
305void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
306{
307	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
308
309	DEBUGFUNC("e1000_set_tbi_compatibility_82543");
310
311	if (hw->mac.type != e1000_82543) {
312		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
313		goto out;
314	}
315
316	if (state)
317		dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
318	else
319		dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
320
321out:
322	return;
323}
324
325/**
326 *  e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
327 *  @hw: pointer to the HW structure
328 *
329 *  Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
330 *  (enabled/disabled).
331 **/
332bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
333{
334	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
335	bool state = false;
336
337	DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
338
339	if (hw->mac.type != e1000_82543) {
340		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
341		goto out;
342	}
343
344	state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);
345
346out:
347	return state;
348}
349
350/**
351 *  e1000_set_tbi_sbp_82543 - Set TBI SBP
352 *  @hw: pointer to the HW structure
353 *  @state: enable/disable TBI store bad packet
354 *
355 *  Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
356 **/
357STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
358{
359	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
360
361	DEBUGFUNC("e1000_set_tbi_sbp_82543");
362
363	if (state && e1000_tbi_compatibility_enabled_82543(hw))
364		dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
365	else
366		dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
367
368	return;
369}
370
371/**
372 *  e1000_init_phy_disabled_82543 - Returns init PHY status
373 *  @hw: pointer to the HW structure
374 *
375 *  Returns the current status of whether PHY initialization is disabled.
376 *  True if PHY initialization is disabled else false.
377 **/
378STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
379{
380	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
381	bool ret_val;
382
383	DEBUGFUNC("e1000_init_phy_disabled_82543");
384
385	if (hw->mac.type != e1000_82543) {
386		ret_val = false;
387		goto out;
388	}
389
390	ret_val = dev_spec->init_phy_disabled;
391
392out:
393	return ret_val;
394}
395
396/**
397 *  e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
398 *  @hw: pointer to the HW structure
399 *  @stats: Struct containing statistic register values
400 *  @frame_len: The length of the frame in question
401 *  @mac_addr: The Ethernet destination address of the frame in question
402 *  @max_frame_size: The maximum frame size
403 *
404 *  Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
405 **/
406void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
407				  struct e1000_hw_stats *stats, u32 frame_len,
408				  u8 *mac_addr, u32 max_frame_size)
409{
410	if (!(e1000_tbi_sbp_enabled_82543(hw)))
411		goto out;
412
413	/* First adjust the frame length. */
414	frame_len--;
415	/*
416	 * We need to adjust the statistics counters, since the hardware
417	 * counters overcount this packet as a CRC error and undercount
418	 * the packet as a good packet
419	 */
420	/* This packet should not be counted as a CRC error. */
421	stats->crcerrs--;
422	/* This packet does count as a Good Packet Received. */
423	stats->gprc++;
424
425	/* Adjust the Good Octets received counters */
426	stats->gorc += frame_len;
427
428	/*
429	 * Is this a broadcast or multicast?  Check broadcast first,
430	 * since the test for a multicast frame will test positive on
431	 * a broadcast frame.
432	 */
433	if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
434		/* Broadcast packet */
435		stats->bprc++;
436	else if (*mac_addr & 0x01)
437		/* Multicast packet */
438		stats->mprc++;
439
440	/*
441	 * In this case, the hardware has over counted the number of
442	 * oversize frames.
443	 */
444	if ((frame_len == max_frame_size) && (stats->roc > 0))
445		stats->roc--;
446
447	/*
448	 * Adjust the bin counters when the extra byte put the frame in the
449	 * wrong bin. Remember that the frame_len was adjusted above.
450	 */
451	if (frame_len == 64) {
452		stats->prc64++;
453		stats->prc127--;
454	} else if (frame_len == 127) {
455		stats->prc127++;
456		stats->prc255--;
457	} else if (frame_len == 255) {
458		stats->prc255++;
459		stats->prc511--;
460	} else if (frame_len == 511) {
461		stats->prc511++;
462		stats->prc1023--;
463	} else if (frame_len == 1023) {
464		stats->prc1023++;
465		stats->prc1522--;
466	} else if (frame_len == 1522) {
467		stats->prc1522++;
468	}
469
470out:
471	return;
472}
473
474/**
475 *  e1000_read_phy_reg_82543 - Read PHY register
476 *  @hw: pointer to the HW structure
477 *  @offset: register offset to be read
478 *  @data: pointer to the read data
479 *
480 *  Reads the PHY at offset and stores the information read to data.
481 **/
482STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
483{
484	u32 mdic;
485	s32 ret_val = E1000_SUCCESS;
486
487	DEBUGFUNC("e1000_read_phy_reg_82543");
488
489	if (offset > MAX_PHY_REG_ADDRESS) {
490		DEBUGOUT1("PHY Address %d is out of range\n", offset);
491		ret_val = -E1000_ERR_PARAM;
492		goto out;
493	}
494
495	/*
496	 * We must first send a preamble through the MDIO pin to signal the
497	 * beginning of an MII instruction.  This is done by sending 32
498	 * consecutive "1" bits.
499	 */
500	e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
501
502	/*
503	 * Now combine the next few fields that are required for a read
504	 * operation.  We use this method instead of calling the
505	 * e1000_shift_out_mdi_bits routine five different times.  The format
506	 * of an MII read instruction consists of a shift out of 14 bits and
507	 * is defined as follows:
508	 *         <Preamble><SOF><Op Code><Phy Addr><Offset>
509	 * followed by a shift in of 18 bits.  This first two bits shifted in
510	 * are TurnAround bits used to avoid contention on the MDIO pin when a
511	 * READ operation is performed.  These two bits are thrown away
512	 * followed by a shift in of 16 bits which contains the desired data.
513	 */
514	mdic = (offset | (hw->phy.addr << 5) |
515		(PHY_OP_READ << 10) | (PHY_SOF << 12));
516
517	e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
518
519	/*
520	 * Now that we've shifted out the read command to the MII, we need to
521	 * "shift in" the 16-bit value (18 total bits) of the requested PHY
522	 * register address.
523	 */
524	*data = e1000_shift_in_mdi_bits_82543(hw);
525
526out:
527	return ret_val;
528}
529
530/**
531 *  e1000_write_phy_reg_82543 - Write PHY register
532 *  @hw: pointer to the HW structure
533 *  @offset: register offset to be written
534 *  @data: pointer to the data to be written at offset
535 *
536 *  Writes data to the PHY at offset.
537 **/
538STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
539{
540	u32 mdic;
541	s32 ret_val = E1000_SUCCESS;
542
543	DEBUGFUNC("e1000_write_phy_reg_82543");
544
545	if (offset > MAX_PHY_REG_ADDRESS) {
546		DEBUGOUT1("PHY Address %d is out of range\n", offset);
547		ret_val = -E1000_ERR_PARAM;
548		goto out;
549	}
550
551	/*
552	 * We'll need to use the SW defined pins to shift the write command
553	 * out to the PHY. We first send a preamble to the PHY to signal the
554	 * beginning of the MII instruction.  This is done by sending 32
555	 * consecutive "1" bits.
556	 */
557	e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
558
559	/*
560	 * Now combine the remaining required fields that will indicate a
561	 * write operation. We use this method instead of calling the
562	 * e1000_shift_out_mdi_bits routine for each field in the command. The
563	 * format of a MII write instruction is as follows:
564	 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
565	 */
566	mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
567		(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
568	mdic <<= 16;
569	mdic |= (u32)data;
570
571	e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
572
573out:
574	return ret_val;
575}
576
577/**
578 *  e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
579 *  @hw: pointer to the HW structure
580 *  @ctrl: pointer to the control register
581 *
582 *  Raise the management data input clock by setting the MDC bit in the control
583 *  register.
584 **/
585STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
586{
587	/*
588	 * Raise the clock input to the Management Data Clock (by setting the
589	 * MDC bit), and then delay a sufficient amount of time.
590	 */
591	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
592	E1000_WRITE_FLUSH(hw);
593	usec_delay(10);
594}
595
596/**
597 *  e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
598 *  @hw: pointer to the HW structure
599 *  @ctrl: pointer to the control register
600 *
601 *  Lower the management data input clock by clearing the MDC bit in the
602 *  control register.
603 **/
604STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
605{
606	/*
607	 * Lower the clock input to the Management Data Clock (by clearing the
608	 * MDC bit), and then delay a sufficient amount of time.
609	 */
610	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
611	E1000_WRITE_FLUSH(hw);
612	usec_delay(10);
613}
614
615/**
616 *  e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
617 *  @hw: pointer to the HW structure
618 *  @data: data to send to the PHY
619 *  @count: number of bits to shift out
620 *
621 *  We need to shift 'count' bits out to the PHY.  So, the value in the
622 *  "data" parameter will be shifted out to the PHY one bit at a time.
623 *  In order to do this, "data" must be broken down into bits.
624 **/
625STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
626					   u16 count)
627{
628	u32 ctrl, mask;
629
630	/*
631	 * We need to shift "count" number of bits out to the PHY.  So, the
632	 * value in the "data" parameter will be shifted out to the PHY one
633	 * bit at a time.  In order to do this, "data" must be broken down
634	 * into bits.
635	 */
636	mask = 0x01;
637	mask <<= (count - 1);
638
639	ctrl = E1000_READ_REG(hw, E1000_CTRL);
640
641	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
642	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
643
644	while (mask) {
645		/*
646		 * A "1" is shifted out to the PHY by setting the MDIO bit to
647		 * "1" and then raising and lowering the Management Data Clock.
648		 * A "0" is shifted out to the PHY by setting the MDIO bit to
649		 * "0" and then raising and lowering the clock.
650		 */
651		if (data & mask)
652			ctrl |= E1000_CTRL_MDIO;
653		else
654			ctrl &= ~E1000_CTRL_MDIO;
655
656		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
657		E1000_WRITE_FLUSH(hw);
658
659		usec_delay(10);
660
661		e1000_raise_mdi_clk_82543(hw, &ctrl);
662		e1000_lower_mdi_clk_82543(hw, &ctrl);
663
664		mask >>= 1;
665	}
666}
667
668/**
669 *  e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
670 *  @hw: pointer to the HW structure
671 *
672 *  In order to read a register from the PHY, we need to shift 18 bits
673 *  in from the PHY.  Bits are "shifted in" by raising the clock input to
674 *  the PHY (setting the MDC bit), and then reading the value of the data out
675 *  MDIO bit.
676 **/
677STATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
678{
679	u32 ctrl;
680	u16 data = 0;
681	u8 i;
682
683	/*
684	 * In order to read a register from the PHY, we need to shift in a
685	 * total of 18 bits from the PHY.  The first two bit (turnaround)
686	 * times are used to avoid contention on the MDIO pin when a read
687	 * operation is performed.  These two bits are ignored by us and
688	 * thrown away.  Bits are "shifted in" by raising the input to the
689	 * Management Data Clock (setting the MDC bit) and then reading the
690	 * value of the MDIO bit.
691	 */
692	ctrl = E1000_READ_REG(hw, E1000_CTRL);
693
694	/*
695	 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
696	 * input.
697	 */
698	ctrl &= ~E1000_CTRL_MDIO_DIR;
699	ctrl &= ~E1000_CTRL_MDIO;
700
701	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
702	E1000_WRITE_FLUSH(hw);
703
704	/*
705	 * Raise and lower the clock before reading in the data.  This accounts
706	 * for the turnaround bits.  The first clock occurred when we clocked
707	 * out the last bit of the Register Address.
708	 */
709	e1000_raise_mdi_clk_82543(hw, &ctrl);
710	e1000_lower_mdi_clk_82543(hw, &ctrl);
711
712	for (data = 0, i = 0; i < 16; i++) {
713		data <<= 1;
714		e1000_raise_mdi_clk_82543(hw, &ctrl);
715		ctrl = E1000_READ_REG(hw, E1000_CTRL);
716		/* Check to see if we shifted in a "1". */
717		if (ctrl & E1000_CTRL_MDIO)
718			data |= 1;
719		e1000_lower_mdi_clk_82543(hw, &ctrl);
720	}
721
722	e1000_raise_mdi_clk_82543(hw, &ctrl);
723	e1000_lower_mdi_clk_82543(hw, &ctrl);
724
725	return data;
726}
727
728/**
729 *  e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
730 *  @hw: pointer to the HW structure
731 *
732 *  Calls the function to force speed and duplex for the m88 PHY, and
733 *  if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
734 *  then call the function for polarity reversal workaround.
735 **/
736STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
737{
738	s32 ret_val;
739
740	DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
741
742	ret_val = e1000_phy_force_speed_duplex_m88(hw);
743	if (ret_val)
744		goto out;
745
746	if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
747	    E1000_ALL_10_SPEED))
748		ret_val = e1000_polarity_reversal_workaround_82543(hw);
749
750out:
751	return ret_val;
752}
753
754/**
755 *  e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
756 *  @hw: pointer to the HW structure
757 *
758 *  When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
759 *  inadvertently.  To workaround the issue, we disable the transmitter on
760 *  the PHY until we have established the link partner's link parameters.
761 **/
762STATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
763{
764	s32 ret_val = E1000_SUCCESS;
765	u16 mii_status_reg;
766	u16 i;
767	bool link;
768
769	if (!(hw->phy.ops.write_reg))
770		goto out;
771
772	/* Polarity reversal workaround for forced 10F/10H links. */
773
774	/* Disable the transmitter on the PHY */
775
776	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
777	if (ret_val)
778		goto out;
779	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
780	if (ret_val)
781		goto out;
782
783	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
784	if (ret_val)
785		goto out;
786
787	/*
788	 * This loop will early-out if the NO link condition has been met.
789	 * In other words, DO NOT use e1000_phy_has_link_generic() here.
790	 */
791	for (i = PHY_FORCE_TIME; i > 0; i--) {
792		/*
793		 * Read the MII Status Register and wait for Link Status bit
794		 * to be clear.
795		 */
796
797		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
798		if (ret_val)
799			goto out;
800
801		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
802		if (ret_val)
803			goto out;
804
805		if (!(mii_status_reg & ~MII_SR_LINK_STATUS))
806			break;
807		msec_delay_irq(100);
808	}
809
810	/* Recommended delay time after link has been lost */
811	msec_delay_irq(1000);
812
813	/* Now we will re-enable the transmitter on the PHY */
814
815	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
816	if (ret_val)
817		goto out;
818	msec_delay_irq(50);
819	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
820	if (ret_val)
821		goto out;
822	msec_delay_irq(50);
823	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
824	if (ret_val)
825		goto out;
826	msec_delay_irq(50);
827	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
828	if (ret_val)
829		goto out;
830
831	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
832	if (ret_val)
833		goto out;
834
835	/*
836	 * Read the MII Status Register and wait for Link Status bit
837	 * to be set.
838	 */
839	ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
840	if (ret_val)
841		goto out;
842
843out:
844	return ret_val;
845}
846
847/**
848 *  e1000_phy_hw_reset_82543 - PHY hardware reset
849 *  @hw: pointer to the HW structure
850 *
851 *  Sets the PHY_RESET_DIR bit in the extended device control register
852 *  to put the PHY into a reset and waits for completion.  Once the reset
853 *  has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
854 *  of reset.
855 **/
856STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
857{
858	u32 ctrl_ext;
859	s32 ret_val;
860
861	DEBUGFUNC("e1000_phy_hw_reset_82543");
862
863	/*
864	 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
865	 * bit to put the PHY into reset...
866	 */
867	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
868	ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
869	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
870	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
871	E1000_WRITE_FLUSH(hw);
872
873	msec_delay(10);
874
875	/* ...then take it out of reset. */
876	ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
877	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
878	E1000_WRITE_FLUSH(hw);
879
880	usec_delay(150);
881
882	if (!(hw->phy.ops.get_cfg_done))
883		return E1000_SUCCESS;
884
885	ret_val = hw->phy.ops.get_cfg_done(hw);
886
887	return ret_val;
888}
889
890/**
891 *  e1000_reset_hw_82543 - Reset hardware
892 *  @hw: pointer to the HW structure
893 *
894 *  This resets the hardware into a known state.
895 **/
896STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw)
897{
898	u32 ctrl;
899	s32 ret_val = E1000_SUCCESS;
900
901	DEBUGFUNC("e1000_reset_hw_82543");
902
903	DEBUGOUT("Masking off all interrupts\n");
904	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
905
906	E1000_WRITE_REG(hw, E1000_RCTL, 0);
907	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
908	E1000_WRITE_FLUSH(hw);
909
910	e1000_set_tbi_sbp_82543(hw, false);
911
912	/*
913	 * Delay to allow any outstanding PCI transactions to complete before
914	 * resetting the device
915	 */
916	msec_delay(10);
917
918	ctrl = E1000_READ_REG(hw, E1000_CTRL);
919
920	DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
921	if (hw->mac.type == e1000_82543) {
922		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
923	} else {
924		/*
925		 * The 82544 can't ACK the 64-bit write when issuing the
926		 * reset, so use IO-mapping as a workaround.
927		 */
928		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
929	}
930
931	/*
932	 * After MAC reset, force reload of NVM to restore power-on
933	 * settings to device.
934	 */
935	hw->nvm.ops.reload(hw);
936	msec_delay(2);
937
938	/* Masking off and clearing any pending interrupts */
939	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
940	E1000_READ_REG(hw, E1000_ICR);
941
942	return ret_val;
943}
944
945/**
946 *  e1000_init_hw_82543 - Initialize hardware
947 *  @hw: pointer to the HW structure
948 *
949 *  This inits the hardware readying it for operation.
950 **/
951STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw)
952{
953	struct e1000_mac_info *mac = &hw->mac;
954	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
955	u32 ctrl;
956	s32 ret_val;
957	u16 i;
958
959	DEBUGFUNC("e1000_init_hw_82543");
960
961	/* Disabling VLAN filtering */
962	E1000_WRITE_REG(hw, E1000_VET, 0);
963	mac->ops.clear_vfta(hw);
964
965	/* Setup the receive address. */
966	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
967
968	/* Zero out the Multicast HASH table */
969	DEBUGOUT("Zeroing the MTA\n");
970	for (i = 0; i < mac->mta_reg_count; i++) {
971		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
972		E1000_WRITE_FLUSH(hw);
973	}
974
975	/*
976	 * Set the PCI priority bit correctly in the CTRL register.  This
977	 * determines if the adapter gives priority to receives, or if it
978	 * gives equal priority to transmits and receives.
979	 */
980	if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
981		ctrl = E1000_READ_REG(hw, E1000_CTRL);
982		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
983	}
984
985	e1000_pcix_mmrbc_workaround_generic(hw);
986
987	/* Setup link and flow control */
988	ret_val = mac->ops.setup_link(hw);
989
990	/*
991	 * Clear all of the statistics registers (clear on read).  It is
992	 * important that we do this after we have tried to establish link
993	 * because the symbol error count will increment wildly if there
994	 * is no link.
995	 */
996	e1000_clear_hw_cntrs_82543(hw);
997
998	return ret_val;
999}
1000
1001/**
1002 *  e1000_setup_link_82543 - Setup flow control and link settings
1003 *  @hw: pointer to the HW structure
1004 *
1005 *  Read the EEPROM to determine the initial polarity value and write the
1006 *  extended device control register with the information before calling
1007 *  the generic setup link function, which does the following:
1008 *  Determines which flow control settings to use, then configures flow
1009 *  control.  Calls the appropriate media-specific link configuration
1010 *  function.  Assuming the adapter has a valid link partner, a valid link
1011 *  should be established.  Assumes the hardware has previously been reset
1012 *  and the transmitter and receiver are not enabled.
1013 **/
1014STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw)
1015{
1016	u32 ctrl_ext;
1017	s32  ret_val;
1018	u16 data;
1019
1020	DEBUGFUNC("e1000_setup_link_82543");
1021
1022	/*
1023	 * Take the 4 bits from NVM word 0xF that determine the initial
1024	 * polarity value for the SW controlled pins, and setup the
1025	 * Extended Device Control reg with that info.
1026	 * This is needed because one of the SW controlled pins is used for
1027	 * signal detection.  So this should be done before phy setup.
1028	 */
1029	if (hw->mac.type == e1000_82543) {
1030		ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1031		if (ret_val) {
1032			DEBUGOUT("NVM Read Error\n");
1033			ret_val = -E1000_ERR_NVM;
1034			goto out;
1035		}
1036		ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1037			    NVM_SWDPIO_EXT_SHIFT);
1038		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1039	}
1040
1041	ret_val = e1000_setup_link_generic(hw);
1042
1043out:
1044	return ret_val;
1045}
1046
1047/**
1048 *  e1000_setup_copper_link_82543 - Configure copper link settings
1049 *  @hw: pointer to the HW structure
1050 *
1051 *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1052 *  for link, once link is established calls to configure collision distance
1053 *  and flow control are called.
1054 **/
1055STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1056{
1057	u32 ctrl;
1058	s32 ret_val;
1059	bool link;
1060
1061	DEBUGFUNC("e1000_setup_copper_link_82543");
1062
1063	ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1064	/*
1065	 * With 82543, we need to force speed and duplex on the MAC
1066	 * equal to what the PHY speed and duplex configuration is.
1067	 * In addition, we need to perform a hardware reset on the
1068	 * PHY to take it out of reset.
1069	 */
1070	if (hw->mac.type == e1000_82543) {
1071		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1072		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1073		ret_val = hw->phy.ops.reset(hw);
1074		if (ret_val)
1075			goto out;
1076	} else {
1077		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1078		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079	}
1080
1081	/* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1082	ret_val = e1000_copper_link_setup_m88(hw);
1083	if (ret_val)
1084		goto out;
1085
1086	if (hw->mac.autoneg) {
1087		/*
1088		 * Setup autoneg and flow control advertisement and perform
1089		 * autonegotiation.
1090		 */
1091		ret_val = e1000_copper_link_autoneg(hw);
1092		if (ret_val)
1093			goto out;
1094	} else {
1095		/*
1096		 * PHY will be set to 10H, 10F, 100H or 100F
1097		 * depending on user settings.
1098		 */
1099		DEBUGOUT("Forcing Speed and Duplex\n");
1100		ret_val = e1000_phy_force_speed_duplex_82543(hw);
1101		if (ret_val) {
1102			DEBUGOUT("Error Forcing Speed and Duplex\n");
1103			goto out;
1104		}
1105	}
1106
1107	/*
1108	 * Check link status. Wait up to 100 microseconds for link to become
1109	 * valid.
1110	 */
1111	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1112					     &link);
1113	if (ret_val)
1114		goto out;
1115
1116
1117	if (link) {
1118		DEBUGOUT("Valid link established!!!\n");
1119		/* Config the MAC and PHY after link is up */
1120		if (hw->mac.type == e1000_82544) {
1121			hw->mac.ops.config_collision_dist(hw);
1122		} else {
1123			ret_val = e1000_config_mac_to_phy_82543(hw);
1124			if (ret_val)
1125				goto out;
1126		}
1127		ret_val = e1000_config_fc_after_link_up_generic(hw);
1128	} else {
1129		DEBUGOUT("Unable to establish link!!!\n");
1130	}
1131
1132out:
1133	return ret_val;
1134}
1135
1136/**
1137 *  e1000_setup_fiber_link_82543 - Setup link for fiber
1138 *  @hw: pointer to the HW structure
1139 *
1140 *  Configures collision distance and flow control for fiber links.  Upon
1141 *  successful setup, poll for link.
1142 **/
1143STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1144{
1145	u32 ctrl;
1146	s32 ret_val;
1147
1148	DEBUGFUNC("e1000_setup_fiber_link_82543");
1149
1150	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1151
1152	/* Take the link out of reset */
1153	ctrl &= ~E1000_CTRL_LRST;
1154
1155	hw->mac.ops.config_collision_dist(hw);
1156
1157	ret_val = e1000_commit_fc_settings_generic(hw);
1158	if (ret_val)
1159		goto out;
1160
1161	DEBUGOUT("Auto-negotiation enabled\n");
1162
1163	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1164	E1000_WRITE_FLUSH(hw);
1165	msec_delay(1);
1166
1167	/*
1168	 * For these adapters, the SW definable pin 1 is cleared when the
1169	 * optics detect a signal.  If we have a signal, then poll for a
1170	 * "Link-Up" indication.
1171	 */
1172	if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
1173		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1174	else
1175		DEBUGOUT("No signal detected\n");
1176
1177out:
1178	return ret_val;
1179}
1180
1181/**
1182 *  e1000_check_for_copper_link_82543 - Check for link (Copper)
1183 *  @hw: pointer to the HW structure
1184 *
1185 *  Checks the phy for link, if link exists, do the following:
1186 *   - check for downshift
1187 *   - do polarity workaround (if necessary)
1188 *   - configure collision distance
1189 *   - configure flow control after link up
1190 *   - configure tbi compatibility
1191 **/
1192STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1193{
1194	struct e1000_mac_info *mac = &hw->mac;
1195	u32 icr, rctl;
1196	s32 ret_val;
1197	u16 speed, duplex;
1198	bool link;
1199
1200	DEBUGFUNC("e1000_check_for_copper_link_82543");
1201
1202	if (!mac->get_link_status) {
1203		ret_val = E1000_SUCCESS;
1204		goto out;
1205	}
1206
1207	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1208	if (ret_val)
1209		goto out;
1210
1211	if (!link)
1212		goto out; /* No link detected */
1213
1214	mac->get_link_status = false;
1215
1216	e1000_check_downshift_generic(hw);
1217
1218	/*
1219	 * If we are forcing speed/duplex, then we can return since
1220	 * we have already determined whether we have link or not.
1221	 */
1222	if (!mac->autoneg) {
1223		/*
1224		 * If speed and duplex are forced to 10H or 10F, then we will
1225		 * implement the polarity reversal workaround.  We disable
1226		 * interrupts first, and upon returning, place the devices
1227		 * interrupt state to its previous value except for the link
1228		 * status change interrupt which will happened due to the
1229		 * execution of this workaround.
1230		 */
1231		if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1232			E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1233			ret_val = e1000_polarity_reversal_workaround_82543(hw);
1234			icr = E1000_READ_REG(hw, E1000_ICR);
1235			E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1236			E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1237		}
1238
1239		ret_val = -E1000_ERR_CONFIG;
1240		goto out;
1241	}
1242
1243	/*
1244	 * We have a M88E1000 PHY and Auto-Neg is enabled.  If we
1245	 * have Si on board that is 82544 or newer, Auto
1246	 * Speed Detection takes care of MAC speed/duplex
1247	 * configuration.  So we only need to configure Collision
1248	 * Distance in the MAC.  Otherwise, we need to force
1249	 * speed/duplex on the MAC to the current PHY speed/duplex
1250	 * settings.
1251	 */
1252	if (mac->type == e1000_82544)
1253		hw->mac.ops.config_collision_dist(hw);
1254	else {
1255		ret_val = e1000_config_mac_to_phy_82543(hw);
1256		if (ret_val) {
1257			DEBUGOUT("Error configuring MAC to PHY settings\n");
1258			goto out;
1259		}
1260	}
1261
1262	/*
1263	 * Configure Flow Control now that Auto-Neg has completed.
1264	 * First, we need to restore the desired flow control
1265	 * settings because we may have had to re-autoneg with a
1266	 * different link partner.
1267	 */
1268	ret_val = e1000_config_fc_after_link_up_generic(hw);
1269	if (ret_val)
1270		DEBUGOUT("Error configuring flow control\n");
1271
1272	/*
1273	 * At this point we know that we are on copper and we have
1274	 * auto-negotiated link.  These are conditions for checking the link
1275	 * partner capability register.  We use the link speed to determine if
1276	 * TBI compatibility needs to be turned on or off.  If the link is not
1277	 * at gigabit speed, then TBI compatibility is not needed.  If we are
1278	 * at gigabit speed, we turn on TBI compatibility.
1279	 */
1280	if (e1000_tbi_compatibility_enabled_82543(hw)) {
1281		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1282		if (ret_val) {
1283			DEBUGOUT("Error getting link speed and duplex\n");
1284			return ret_val;
1285		}
1286		if (speed != SPEED_1000) {
1287			/*
1288			 * If link speed is not set to gigabit speed,
1289			 * we do not need to enable TBI compatibility.
1290			 */
1291			if (e1000_tbi_sbp_enabled_82543(hw)) {
1292				/*
1293				 * If we previously were in the mode,
1294				 * turn it off.
1295				 */
1296				e1000_set_tbi_sbp_82543(hw, false);
1297				rctl = E1000_READ_REG(hw, E1000_RCTL);
1298				rctl &= ~E1000_RCTL_SBP;
1299				E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1300			}
1301		} else {
1302			/*
1303			 * If TBI compatibility is was previously off,
1304			 * turn it on. For compatibility with a TBI link
1305			 * partner, we will store bad packets. Some
1306			 * frames have an additional byte on the end and
1307			 * will look like CRC errors to to the hardware.
1308			 */
1309			if (!e1000_tbi_sbp_enabled_82543(hw)) {
1310				e1000_set_tbi_sbp_82543(hw, true);
1311				rctl = E1000_READ_REG(hw, E1000_RCTL);
1312				rctl |= E1000_RCTL_SBP;
1313				E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314			}
1315		}
1316	}
1317out:
1318	return ret_val;
1319}
1320
1321/**
1322 *  e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1323 *  @hw: pointer to the HW structure
1324 *
1325 *  Checks for link up on the hardware.  If link is not up and we have
1326 *  a signal, then we need to force link up.
1327 **/
1328STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1329{
1330	struct e1000_mac_info *mac = &hw->mac;
1331	u32 rxcw, ctrl, status;
1332	s32 ret_val = E1000_SUCCESS;
1333
1334	DEBUGFUNC("e1000_check_for_fiber_link_82543");
1335
1336	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1337	status = E1000_READ_REG(hw, E1000_STATUS);
1338	rxcw = E1000_READ_REG(hw, E1000_RXCW);
1339
1340	/*
1341	 * If we don't have link (auto-negotiation failed or link partner
1342	 * cannot auto-negotiate), the cable is plugged in (we have signal),
1343	 * and our link partner is not trying to auto-negotiate with us (we
1344	 * are receiving idles or data), we need to force link up. We also
1345	 * need to give auto-negotiation time to complete, in case the cable
1346	 * was just plugged in. The autoneg_failed flag does this.
1347	 */
1348	/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1349	if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1350	    (!(status & E1000_STATUS_LU)) &&
1351	    (!(rxcw & E1000_RXCW_C))) {
1352		if (!mac->autoneg_failed) {
1353			mac->autoneg_failed = true;
1354			ret_val = 0;
1355			goto out;
1356		}
1357		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1358
1359		/* Disable auto-negotiation in the TXCW register */
1360		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1361
1362		/* Force link-up and also force full-duplex. */
1363		ctrl = E1000_READ_REG(hw, E1000_CTRL);
1364		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1365		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1366
1367		/* Configure Flow Control after forcing link up. */
1368		ret_val = e1000_config_fc_after_link_up_generic(hw);
1369		if (ret_val) {
1370			DEBUGOUT("Error configuring flow control\n");
1371			goto out;
1372		}
1373	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1374		/*
1375		 * If we are forcing link and we are receiving /C/ ordered
1376		 * sets, re-enable auto-negotiation in the TXCW register
1377		 * and disable forced link in the Device Control register
1378		 * in an attempt to auto-negotiate with our link partner.
1379		 */
1380		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1381		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1382		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1383
1384		mac->serdes_has_link = true;
1385	}
1386
1387out:
1388	return ret_val;
1389}
1390
1391/**
1392 *  e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1393 *  @hw: pointer to the HW structure
1394 *
1395 *  For the 82543 silicon, we need to set the MAC to match the settings
1396 *  of the PHY, even if the PHY is auto-negotiating.
1397 **/
1398STATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1399{
1400	u32 ctrl;
1401	s32 ret_val = E1000_SUCCESS;
1402	u16 phy_data;
1403
1404	DEBUGFUNC("e1000_config_mac_to_phy_82543");
1405
1406	if (!(hw->phy.ops.read_reg))
1407		goto out;
1408
1409	/* Set the bits to force speed and duplex */
1410	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1411	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1412	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1413
1414	/*
1415	 * Set up duplex in the Device Control and Transmit Control
1416	 * registers depending on negotiated values.
1417	 */
1418	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1419	if (ret_val)
1420		goto out;
1421
1422	ctrl &= ~E1000_CTRL_FD;
1423	if (phy_data & M88E1000_PSSR_DPLX)
1424		ctrl |= E1000_CTRL_FD;
1425
1426	hw->mac.ops.config_collision_dist(hw);
1427
1428	/*
1429	 * Set up speed in the Device Control register depending on
1430	 * negotiated values.
1431	 */
1432	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1433		ctrl |= E1000_CTRL_SPD_1000;
1434	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1435		ctrl |= E1000_CTRL_SPD_100;
1436
1437	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1438
1439out:
1440	return ret_val;
1441}
1442
1443/**
1444 *  e1000_write_vfta_82543 - Write value to VLAN filter table
1445 *  @hw: pointer to the HW structure
1446 *  @offset: the 32-bit offset in which to write the value to.
1447 *  @value: the 32-bit value to write at location offset.
1448 *
1449 *  This writes a 32-bit value to a 32-bit offset in the VLAN filter
1450 *  table.
1451 **/
1452STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1453{
1454	u32 temp;
1455
1456	DEBUGFUNC("e1000_write_vfta_82543");
1457
1458	if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1459		temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1460		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1461		E1000_WRITE_FLUSH(hw);
1462		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1463		E1000_WRITE_FLUSH(hw);
1464	} else {
1465		e1000_write_vfta_generic(hw, offset, value);
1466	}
1467}
1468
1469/**
1470 *  e1000_led_on_82543 - Turn on SW controllable LED
1471 *  @hw: pointer to the HW structure
1472 *
1473 *  Turns the SW defined LED on.
1474 **/
1475STATIC s32 e1000_led_on_82543(struct e1000_hw *hw)
1476{
1477	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1478
1479	DEBUGFUNC("e1000_led_on_82543");
1480
1481	if (hw->mac.type == e1000_82544 &&
1482	    hw->phy.media_type == e1000_media_type_copper) {
1483		/* Clear SW-definable Pin 0 to turn on the LED */
1484		ctrl &= ~E1000_CTRL_SWDPIN0;
1485		ctrl |= E1000_CTRL_SWDPIO0;
1486	} else {
1487		/* Fiber 82544 and all 82543 use this method */
1488		ctrl |= E1000_CTRL_SWDPIN0;
1489		ctrl |= E1000_CTRL_SWDPIO0;
1490	}
1491	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1492
1493	return E1000_SUCCESS;
1494}
1495
1496/**
1497 *  e1000_led_off_82543 - Turn off SW controllable LED
1498 *  @hw: pointer to the HW structure
1499 *
1500 *  Turns the SW defined LED off.
1501 **/
1502STATIC s32 e1000_led_off_82543(struct e1000_hw *hw)
1503{
1504	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1505
1506	DEBUGFUNC("e1000_led_off_82543");
1507
1508	if (hw->mac.type == e1000_82544 &&
1509	    hw->phy.media_type == e1000_media_type_copper) {
1510		/* Set SW-definable Pin 0 to turn off the LED */
1511		ctrl |= E1000_CTRL_SWDPIN0;
1512		ctrl |= E1000_CTRL_SWDPIO0;
1513	} else {
1514		ctrl &= ~E1000_CTRL_SWDPIN0;
1515		ctrl |= E1000_CTRL_SWDPIO0;
1516	}
1517	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1518
1519	return E1000_SUCCESS;
1520}
1521
1522/**
1523 *  e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1524 *  @hw: pointer to the HW structure
1525 *
1526 *  Clears the hardware counters by reading the counter registers.
1527 **/
1528STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1529{
1530	DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1531
1532	e1000_clear_hw_cntrs_base_generic(hw);
1533
1534	E1000_READ_REG(hw, E1000_PRC64);
1535	E1000_READ_REG(hw, E1000_PRC127);
1536	E1000_READ_REG(hw, E1000_PRC255);
1537	E1000_READ_REG(hw, E1000_PRC511);
1538	E1000_READ_REG(hw, E1000_PRC1023);
1539	E1000_READ_REG(hw, E1000_PRC1522);
1540	E1000_READ_REG(hw, E1000_PTC64);
1541	E1000_READ_REG(hw, E1000_PTC127);
1542	E1000_READ_REG(hw, E1000_PTC255);
1543	E1000_READ_REG(hw, E1000_PTC511);
1544	E1000_READ_REG(hw, E1000_PTC1023);
1545	E1000_READ_REG(hw, E1000_PTC1522);
1546
1547	E1000_READ_REG(hw, E1000_ALGNERRC);
1548	E1000_READ_REG(hw, E1000_RXERRC);
1549	E1000_READ_REG(hw, E1000_TNCRS);
1550	E1000_READ_REG(hw, E1000_CEXTERR);
1551	E1000_READ_REG(hw, E1000_TSCTC);
1552	E1000_READ_REG(hw, E1000_TSCTFC);
1553}
1554