1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/*
35a551c94aSIdo Barnea * 82543GC Gigabit Ethernet Controller (Fiber)
36a551c94aSIdo Barnea * 82543GC Gigabit Ethernet Controller (Copper)
37a551c94aSIdo Barnea * 82544EI Gigabit Ethernet Controller (Copper)
38a551c94aSIdo Barnea * 82544EI Gigabit Ethernet Controller (Fiber)
39a551c94aSIdo Barnea * 82544GC Gigabit Ethernet Controller (Copper)
40a551c94aSIdo Barnea * 82544GC Gigabit Ethernet Controller (LOM)
41a551c94aSIdo Barnea */
42a551c94aSIdo Barnea
43a551c94aSIdo Barnea#include "e1000_api.h"
44a551c94aSIdo Barnea
45a551c94aSIdo BarneaSTATIC s32  e1000_init_phy_params_82543(struct e1000_hw *hw);
46a551c94aSIdo BarneaSTATIC s32  e1000_init_nvm_params_82543(struct e1000_hw *hw);
47a551c94aSIdo BarneaSTATIC s32  e1000_init_mac_params_82543(struct e1000_hw *hw);
48a551c94aSIdo BarneaSTATIC s32  e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
49a551c94aSIdo Barnea				     u16 *data);
50a551c94aSIdo BarneaSTATIC s32  e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51a551c94aSIdo Barnea				      u16 data);
52a551c94aSIdo BarneaSTATIC s32  e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
53a551c94aSIdo BarneaSTATIC s32  e1000_phy_hw_reset_82543(struct e1000_hw *hw);
54a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_82543(struct e1000_hw *hw);
55a551c94aSIdo BarneaSTATIC s32  e1000_init_hw_82543(struct e1000_hw *hw);
56a551c94aSIdo BarneaSTATIC s32  e1000_setup_link_82543(struct e1000_hw *hw);
57a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_82543(struct e1000_hw *hw);
58a551c94aSIdo BarneaSTATIC s32  e1000_setup_fiber_link_82543(struct e1000_hw *hw);
59a551c94aSIdo BarneaSTATIC s32  e1000_check_for_copper_link_82543(struct e1000_hw *hw);
60a551c94aSIdo BarneaSTATIC s32  e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
61a551c94aSIdo BarneaSTATIC s32  e1000_led_on_82543(struct e1000_hw *hw);
62a551c94aSIdo BarneaSTATIC s32  e1000_led_off_82543(struct e1000_hw *hw);
63a551c94aSIdo BarneaSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
64a551c94aSIdo Barnea				   u32 value);
65a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
66a551c94aSIdo BarneaSTATIC s32  e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
67a551c94aSIdo BarneaSTATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
68a551c94aSIdo BarneaSTATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
69a551c94aSIdo BarneaSTATIC s32  e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
70a551c94aSIdo BarneaSTATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
71a551c94aSIdo BarneaSTATIC u16  e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
72a551c94aSIdo BarneaSTATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
73a551c94aSIdo Barnea					   u16 count);
74a551c94aSIdo BarneaSTATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
75a551c94aSIdo BarneaSTATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
76a551c94aSIdo Barnea
77a551c94aSIdo Barnea/**
78a551c94aSIdo Barnea *  e1000_init_phy_params_82543 - Init PHY func ptrs.
79a551c94aSIdo Barnea *  @hw: pointer to the HW structure
80a551c94aSIdo Barnea **/
81a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
82a551c94aSIdo Barnea{
83a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
84a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
85a551c94aSIdo Barnea
86a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_82543");
87a551c94aSIdo Barnea
88a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper) {
89a551c94aSIdo Barnea		phy->type = e1000_phy_none;
90a551c94aSIdo Barnea		goto out;
91a551c94aSIdo Barnea	} else {
92a551c94aSIdo Barnea		phy->ops.power_up = e1000_power_up_phy_copper;
93a551c94aSIdo Barnea		phy->ops.power_down = e1000_power_down_phy_copper;
94a551c94aSIdo Barnea	}
95a551c94aSIdo Barnea
96a551c94aSIdo Barnea	phy->addr		= 1;
97a551c94aSIdo Barnea	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
98a551c94aSIdo Barnea	phy->reset_delay_us	= 10000;
99a551c94aSIdo Barnea	phy->type		= e1000_phy_m88;
100a551c94aSIdo Barnea
101a551c94aSIdo Barnea	/* Function Pointers */
102a551c94aSIdo Barnea	phy->ops.check_polarity	= e1000_check_polarity_m88;
103a551c94aSIdo Barnea	phy->ops.commit		= e1000_phy_sw_reset_generic;
104a551c94aSIdo Barnea	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
105a551c94aSIdo Barnea	phy->ops.get_cable_length = e1000_get_cable_length_m88;
106a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
107a551c94aSIdo Barnea	phy->ops.read_reg	= (hw->mac.type == e1000_82543)
108a551c94aSIdo Barnea				  ? e1000_read_phy_reg_82543
109a551c94aSIdo Barnea				  : e1000_read_phy_reg_m88;
110a551c94aSIdo Barnea	phy->ops.reset		= (hw->mac.type == e1000_82543)
111a551c94aSIdo Barnea				  ? e1000_phy_hw_reset_82543
112a551c94aSIdo Barnea				  : e1000_phy_hw_reset_generic;
113a551c94aSIdo Barnea	phy->ops.write_reg	= (hw->mac.type == e1000_82543)
114a551c94aSIdo Barnea				  ? e1000_write_phy_reg_82543
115a551c94aSIdo Barnea				  : e1000_write_phy_reg_m88;
116a551c94aSIdo Barnea	phy->ops.get_info	= e1000_get_phy_info_m88;
117a551c94aSIdo Barnea
118a551c94aSIdo Barnea	/*
119a551c94aSIdo Barnea	 * The external PHY of the 82543 can be in a funky state.
120a551c94aSIdo Barnea	 * Resetting helps us read the PHY registers for acquiring
121a551c94aSIdo Barnea	 * the PHY ID.
122a551c94aSIdo Barnea	 */
123a551c94aSIdo Barnea	if (!e1000_init_phy_disabled_82543(hw)) {
124a551c94aSIdo Barnea		ret_val = phy->ops.reset(hw);
125a551c94aSIdo Barnea		if (ret_val) {
126a551c94aSIdo Barnea			DEBUGOUT("Resetting PHY during init failed.\n");
127a551c94aSIdo Barnea			goto out;
128a551c94aSIdo Barnea		}
129a551c94aSIdo Barnea		msec_delay(20);
130a551c94aSIdo Barnea	}
131a551c94aSIdo Barnea
132a551c94aSIdo Barnea	ret_val = e1000_get_phy_id(hw);
133a551c94aSIdo Barnea	if (ret_val)
134a551c94aSIdo Barnea		goto out;
135a551c94aSIdo Barnea
136a551c94aSIdo Barnea	/* Verify phy id */
137a551c94aSIdo Barnea	switch (hw->mac.type) {
138a551c94aSIdo Barnea	case e1000_82543:
139a551c94aSIdo Barnea		if (phy->id != M88E1000_E_PHY_ID) {
140a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
141a551c94aSIdo Barnea			goto out;
142a551c94aSIdo Barnea		}
143a551c94aSIdo Barnea		break;
144a551c94aSIdo Barnea	case e1000_82544:
145a551c94aSIdo Barnea		if (phy->id != M88E1000_I_PHY_ID) {
146a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
147a551c94aSIdo Barnea			goto out;
148a551c94aSIdo Barnea		}
149a551c94aSIdo Barnea		break;
150a551c94aSIdo Barnea	default:
151a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
152a551c94aSIdo Barnea		goto out;
153a551c94aSIdo Barnea		break;
154a551c94aSIdo Barnea	}
155a551c94aSIdo Barnea
156a551c94aSIdo Barneaout:
157a551c94aSIdo Barnea	return ret_val;
158a551c94aSIdo Barnea}
159a551c94aSIdo Barnea
160a551c94aSIdo Barnea/**
161a551c94aSIdo Barnea *  e1000_init_nvm_params_82543 - Init NVM func ptrs.
162a551c94aSIdo Barnea *  @hw: pointer to the HW structure
163a551c94aSIdo Barnea **/
164a551c94aSIdo BarneaSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
165a551c94aSIdo Barnea{
166a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
167a551c94aSIdo Barnea
168a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_82543");
169a551c94aSIdo Barnea
170a551c94aSIdo Barnea	nvm->type		= e1000_nvm_eeprom_microwire;
171a551c94aSIdo Barnea	nvm->word_size		= 64;
172a551c94aSIdo Barnea	nvm->delay_usec		= 50;
173a551c94aSIdo Barnea	nvm->address_bits	=  6;
174a551c94aSIdo Barnea	nvm->opcode_bits	=  3;
175a551c94aSIdo Barnea
176a551c94aSIdo Barnea	/* Function Pointers */
177a551c94aSIdo Barnea	nvm->ops.read		= e1000_read_nvm_microwire;
178a551c94aSIdo Barnea	nvm->ops.update		= e1000_update_nvm_checksum_generic;
179a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
180a551c94aSIdo Barnea	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
181a551c94aSIdo Barnea	nvm->ops.write		= e1000_write_nvm_microwire;
182a551c94aSIdo Barnea
183a551c94aSIdo Barnea	return E1000_SUCCESS;
184a551c94aSIdo Barnea}
185a551c94aSIdo Barnea
186a551c94aSIdo Barnea/**
187a551c94aSIdo Barnea *  e1000_init_mac_params_82543 - Init MAC func ptrs.
188a551c94aSIdo Barnea *  @hw: pointer to the HW structure
189a551c94aSIdo Barnea **/
190a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
191a551c94aSIdo Barnea{
192a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
193a551c94aSIdo Barnea
194a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_82543");
195a551c94aSIdo Barnea
196a551c94aSIdo Barnea	/* Set media type */
197a551c94aSIdo Barnea	switch (hw->device_id) {
198a551c94aSIdo Barnea	case E1000_DEV_ID_82543GC_FIBER:
199a551c94aSIdo Barnea	case E1000_DEV_ID_82544EI_FIBER:
200a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_fiber;
201a551c94aSIdo Barnea		break;
202a551c94aSIdo Barnea	default:
203a551c94aSIdo Barnea		hw->phy.media_type = e1000_media_type_copper;
204a551c94aSIdo Barnea		break;
205a551c94aSIdo Barnea	}
206a551c94aSIdo Barnea
207a551c94aSIdo Barnea	/* Set mta register count */
208a551c94aSIdo Barnea	mac->mta_reg_count = 128;
209a551c94aSIdo Barnea	/* Set rar entry count */
210a551c94aSIdo Barnea	mac->rar_entry_count = E1000_RAR_ENTRIES;
211a551c94aSIdo Barnea
212a551c94aSIdo Barnea	/* Function pointers */
213a551c94aSIdo Barnea
214a551c94aSIdo Barnea	/* bus type/speed/width */
215a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
216a551c94aSIdo Barnea	/* function id */
217a551c94aSIdo Barnea	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
218a551c94aSIdo Barnea	/* reset */
219a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_82543;
220a551c94aSIdo Barnea	/* hw initialization */
221a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_82543;
222a551c94aSIdo Barnea	/* link setup */
223a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_82543;
224a551c94aSIdo Barnea	/* physical interface setup */
225a551c94aSIdo Barnea	mac->ops.setup_physical_interface =
226a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
227a551c94aSIdo Barnea		 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;
228a551c94aSIdo Barnea	/* check for link */
229a551c94aSIdo Barnea	mac->ops.check_for_link =
230a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
231a551c94aSIdo Barnea		 ? e1000_check_for_copper_link_82543
232a551c94aSIdo Barnea		 : e1000_check_for_fiber_link_82543;
233a551c94aSIdo Barnea	/* link info */
234a551c94aSIdo Barnea	mac->ops.get_link_up_info =
235a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
236a551c94aSIdo Barnea		 ? e1000_get_speed_and_duplex_copper_generic
237a551c94aSIdo Barnea		 : e1000_get_speed_and_duplex_fiber_serdes_generic;
238a551c94aSIdo Barnea	/* multicast address update */
239a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
240a551c94aSIdo Barnea	/* writing VFTA */
241a551c94aSIdo Barnea	mac->ops.write_vfta = e1000_write_vfta_82543;
242a551c94aSIdo Barnea	/* clearing VFTA */
243a551c94aSIdo Barnea	mac->ops.clear_vfta = e1000_clear_vfta_generic;
244a551c94aSIdo Barnea	/* turn on/off LED */
245a551c94aSIdo Barnea	mac->ops.led_on = e1000_led_on_82543;
246a551c94aSIdo Barnea	mac->ops.led_off = e1000_led_off_82543;
247a551c94aSIdo Barnea	/* clear hardware counters */
248a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
249a551c94aSIdo Barnea
250a551c94aSIdo Barnea	/* Set tbi compatibility */
251a551c94aSIdo Barnea	if ((hw->mac.type != e1000_82543) ||
252a551c94aSIdo Barnea	    (hw->phy.media_type == e1000_media_type_fiber))
253a551c94aSIdo Barnea		e1000_set_tbi_compatibility_82543(hw, false);
254a551c94aSIdo Barnea
255a551c94aSIdo Barnea	return E1000_SUCCESS;
256a551c94aSIdo Barnea}
257a551c94aSIdo Barnea
258a551c94aSIdo Barnea/**
259a551c94aSIdo Barnea *  e1000_init_function_pointers_82543 - Init func ptrs.
260a551c94aSIdo Barnea *  @hw: pointer to the HW structure
261a551c94aSIdo Barnea *
262a551c94aSIdo Barnea *  Called to initialize all function pointers and parameters.
263a551c94aSIdo Barnea **/
264a551c94aSIdo Barneavoid e1000_init_function_pointers_82543(struct e1000_hw *hw)
265a551c94aSIdo Barnea{
266a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_function_pointers_82543");
267a551c94aSIdo Barnea
268a551c94aSIdo Barnea	hw->mac.ops.init_params = e1000_init_mac_params_82543;
269a551c94aSIdo Barnea	hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
270a551c94aSIdo Barnea	hw->phy.ops.init_params = e1000_init_phy_params_82543;
271a551c94aSIdo Barnea}
272a551c94aSIdo Barnea
273a551c94aSIdo Barnea/**
274a551c94aSIdo Barnea *  e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
275a551c94aSIdo Barnea *  @hw: pointer to the HW structure
276a551c94aSIdo Barnea *
277a551c94aSIdo Barnea *  Returns the current status of 10-bit Interface (TBI) compatibility
278a551c94aSIdo Barnea *  (enabled/disabled).
279a551c94aSIdo Barnea **/
280a551c94aSIdo BarneaSTATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
281a551c94aSIdo Barnea{
282a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
283a551c94aSIdo Barnea	bool state = false;
284a551c94aSIdo Barnea
285a551c94aSIdo Barnea	DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
286a551c94aSIdo Barnea
287a551c94aSIdo Barnea	if (hw->mac.type != e1000_82543) {
288a551c94aSIdo Barnea		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
289a551c94aSIdo Barnea		goto out;
290a551c94aSIdo Barnea	}
291a551c94aSIdo Barnea
292a551c94aSIdo Barnea	state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);
293a551c94aSIdo Barnea
294a551c94aSIdo Barneaout:
295a551c94aSIdo Barnea	return state;
296a551c94aSIdo Barnea}
297a551c94aSIdo Barnea
298a551c94aSIdo Barnea/**
299a551c94aSIdo Barnea *  e1000_set_tbi_compatibility_82543 - Set TBI compatibility
300a551c94aSIdo Barnea *  @hw: pointer to the HW structure
301a551c94aSIdo Barnea *  @state: enable/disable TBI compatibility
302a551c94aSIdo Barnea *
303a551c94aSIdo Barnea *  Enables or disabled 10-bit Interface (TBI) compatibility.
304a551c94aSIdo Barnea **/
305a551c94aSIdo Barneavoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
306a551c94aSIdo Barnea{
307a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
308a551c94aSIdo Barnea
309a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_tbi_compatibility_82543");
310a551c94aSIdo Barnea
311a551c94aSIdo Barnea	if (hw->mac.type != e1000_82543) {
312a551c94aSIdo Barnea		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
313a551c94aSIdo Barnea		goto out;
314a551c94aSIdo Barnea	}
315a551c94aSIdo Barnea
316a551c94aSIdo Barnea	if (state)
317a551c94aSIdo Barnea		dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
318a551c94aSIdo Barnea	else
319a551c94aSIdo Barnea		dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
320a551c94aSIdo Barnea
321a551c94aSIdo Barneaout:
322a551c94aSIdo Barnea	return;
323a551c94aSIdo Barnea}
324a551c94aSIdo Barnea
325a551c94aSIdo Barnea/**
326a551c94aSIdo Barnea *  e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
327a551c94aSIdo Barnea *  @hw: pointer to the HW structure
328a551c94aSIdo Barnea *
329a551c94aSIdo Barnea *  Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
330a551c94aSIdo Barnea *  (enabled/disabled).
331a551c94aSIdo Barnea **/
332a551c94aSIdo Barneabool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
333a551c94aSIdo Barnea{
334a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
335a551c94aSIdo Barnea	bool state = false;
336a551c94aSIdo Barnea
337a551c94aSIdo Barnea	DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
338a551c94aSIdo Barnea
339a551c94aSIdo Barnea	if (hw->mac.type != e1000_82543) {
340a551c94aSIdo Barnea		DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
341a551c94aSIdo Barnea		goto out;
342a551c94aSIdo Barnea	}
343a551c94aSIdo Barnea
344a551c94aSIdo Barnea	state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);
345a551c94aSIdo Barnea
346a551c94aSIdo Barneaout:
347a551c94aSIdo Barnea	return state;
348a551c94aSIdo Barnea}
349a551c94aSIdo Barnea
350a551c94aSIdo Barnea/**
351a551c94aSIdo Barnea *  e1000_set_tbi_sbp_82543 - Set TBI SBP
352a551c94aSIdo Barnea *  @hw: pointer to the HW structure
353a551c94aSIdo Barnea *  @state: enable/disable TBI store bad packet
354a551c94aSIdo Barnea *
355a551c94aSIdo Barnea *  Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
356a551c94aSIdo Barnea **/
357a551c94aSIdo BarneaSTATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
358a551c94aSIdo Barnea{
359a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
360a551c94aSIdo Barnea
361a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_tbi_sbp_82543");
362a551c94aSIdo Barnea
363a551c94aSIdo Barnea	if (state && e1000_tbi_compatibility_enabled_82543(hw))
364a551c94aSIdo Barnea		dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
365a551c94aSIdo Barnea	else
366a551c94aSIdo Barnea		dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
367a551c94aSIdo Barnea
368a551c94aSIdo Barnea	return;
369a551c94aSIdo Barnea}
370a551c94aSIdo Barnea
371a551c94aSIdo Barnea/**
372a551c94aSIdo Barnea *  e1000_init_phy_disabled_82543 - Returns init PHY status
373a551c94aSIdo Barnea *  @hw: pointer to the HW structure
374a551c94aSIdo Barnea *
375a551c94aSIdo Barnea *  Returns the current status of whether PHY initialization is disabled.
376a551c94aSIdo Barnea *  True if PHY initialization is disabled else false.
377a551c94aSIdo Barnea **/
378a551c94aSIdo BarneaSTATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
379a551c94aSIdo Barnea{
380a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
381a551c94aSIdo Barnea	bool ret_val;
382a551c94aSIdo Barnea
383a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_disabled_82543");
384a551c94aSIdo Barnea
385a551c94aSIdo Barnea	if (hw->mac.type != e1000_82543) {
386a551c94aSIdo Barnea		ret_val = false;
387a551c94aSIdo Barnea		goto out;
388a551c94aSIdo Barnea	}
389a551c94aSIdo Barnea
390a551c94aSIdo Barnea	ret_val = dev_spec->init_phy_disabled;
391a551c94aSIdo Barnea
392a551c94aSIdo Barneaout:
393a551c94aSIdo Barnea	return ret_val;
394a551c94aSIdo Barnea}
395a551c94aSIdo Barnea
396a551c94aSIdo Barnea/**
397a551c94aSIdo Barnea *  e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
398a551c94aSIdo Barnea *  @hw: pointer to the HW structure
399a551c94aSIdo Barnea *  @stats: Struct containing statistic register values
400a551c94aSIdo Barnea *  @frame_len: The length of the frame in question
401a551c94aSIdo Barnea *  @mac_addr: The Ethernet destination address of the frame in question
402a551c94aSIdo Barnea *  @max_frame_size: The maximum frame size
403a551c94aSIdo Barnea *
404a551c94aSIdo Barnea *  Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
405a551c94aSIdo Barnea **/
406a551c94aSIdo Barneavoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
407a551c94aSIdo Barnea				  struct e1000_hw_stats *stats, u32 frame_len,
408a551c94aSIdo Barnea				  u8 *mac_addr, u32 max_frame_size)
409a551c94aSIdo Barnea{
410a551c94aSIdo Barnea	if (!(e1000_tbi_sbp_enabled_82543(hw)))
411a551c94aSIdo Barnea		goto out;
412a551c94aSIdo Barnea
413a551c94aSIdo Barnea	/* First adjust the frame length. */
414a551c94aSIdo Barnea	frame_len--;
415a551c94aSIdo Barnea	/*
416a551c94aSIdo Barnea	 * We need to adjust the statistics counters, since the hardware
417a551c94aSIdo Barnea	 * counters overcount this packet as a CRC error and undercount
418a551c94aSIdo Barnea	 * the packet as a good packet
419a551c94aSIdo Barnea	 */
420a551c94aSIdo Barnea	/* This packet should not be counted as a CRC error. */
421a551c94aSIdo Barnea	stats->crcerrs--;
422a551c94aSIdo Barnea	/* This packet does count as a Good Packet Received. */
423a551c94aSIdo Barnea	stats->gprc++;
424a551c94aSIdo Barnea
425a551c94aSIdo Barnea	/* Adjust the Good Octets received counters */
426a551c94aSIdo Barnea	stats->gorc += frame_len;
427a551c94aSIdo Barnea
428a551c94aSIdo Barnea	/*
429a551c94aSIdo Barnea	 * Is this a broadcast or multicast?  Check broadcast first,
430a551c94aSIdo Barnea	 * since the test for a multicast frame will test positive on
431a551c94aSIdo Barnea	 * a broadcast frame.
432a551c94aSIdo Barnea	 */
433a551c94aSIdo Barnea	if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
434a551c94aSIdo Barnea		/* Broadcast packet */
435a551c94aSIdo Barnea		stats->bprc++;
436a551c94aSIdo Barnea	else if (*mac_addr & 0x01)
437a551c94aSIdo Barnea		/* Multicast packet */
438a551c94aSIdo Barnea		stats->mprc++;
439a551c94aSIdo Barnea
440a551c94aSIdo Barnea	/*
441a551c94aSIdo Barnea	 * In this case, the hardware has over counted the number of
442a551c94aSIdo Barnea	 * oversize frames.
443a551c94aSIdo Barnea	 */
444a551c94aSIdo Barnea	if ((frame_len == max_frame_size) && (stats->roc > 0))
445a551c94aSIdo Barnea		stats->roc--;
446a551c94aSIdo Barnea
447a551c94aSIdo Barnea	/*
448a551c94aSIdo Barnea	 * Adjust the bin counters when the extra byte put the frame in the
449a551c94aSIdo Barnea	 * wrong bin. Remember that the frame_len was adjusted above.
450a551c94aSIdo Barnea	 */
451a551c94aSIdo Barnea	if (frame_len == 64) {
452a551c94aSIdo Barnea		stats->prc64++;
453a551c94aSIdo Barnea		stats->prc127--;
454a551c94aSIdo Barnea	} else if (frame_len == 127) {
455a551c94aSIdo Barnea		stats->prc127++;
456a551c94aSIdo Barnea		stats->prc255--;
457a551c94aSIdo Barnea	} else if (frame_len == 255) {
458a551c94aSIdo Barnea		stats->prc255++;
459a551c94aSIdo Barnea		stats->prc511--;
460a551c94aSIdo Barnea	} else if (frame_len == 511) {
461a551c94aSIdo Barnea		stats->prc511++;
462a551c94aSIdo Barnea		stats->prc1023--;
463a551c94aSIdo Barnea	} else if (frame_len == 1023) {
464a551c94aSIdo Barnea		stats->prc1023++;
465a551c94aSIdo Barnea		stats->prc1522--;
466a551c94aSIdo Barnea	} else if (frame_len == 1522) {
467a551c94aSIdo Barnea		stats->prc1522++;
468a551c94aSIdo Barnea	}
469a551c94aSIdo Barnea
470a551c94aSIdo Barneaout:
471a551c94aSIdo Barnea	return;
472a551c94aSIdo Barnea}
473a551c94aSIdo Barnea
474a551c94aSIdo Barnea/**
475a551c94aSIdo Barnea *  e1000_read_phy_reg_82543 - Read PHY register
476a551c94aSIdo Barnea *  @hw: pointer to the HW structure
477a551c94aSIdo Barnea *  @offset: register offset to be read
478a551c94aSIdo Barnea *  @data: pointer to the read data
479a551c94aSIdo Barnea *
480a551c94aSIdo Barnea *  Reads the PHY at offset and stores the information read to data.
481a551c94aSIdo Barnea **/
482a551c94aSIdo BarneaSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
483a551c94aSIdo Barnea{
484a551c94aSIdo Barnea	u32 mdic;
485a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
486a551c94aSIdo Barnea
487a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_82543");
488a551c94aSIdo Barnea
489a551c94aSIdo Barnea	if (offset > MAX_PHY_REG_ADDRESS) {
490a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %d is out of range\n", offset);
491a551c94aSIdo Barnea		ret_val = -E1000_ERR_PARAM;
492a551c94aSIdo Barnea		goto out;
493a551c94aSIdo Barnea	}
494a551c94aSIdo Barnea
495a551c94aSIdo Barnea	/*
496a551c94aSIdo Barnea	 * We must first send a preamble through the MDIO pin to signal the
497a551c94aSIdo Barnea	 * beginning of an MII instruction.  This is done by sending 32
498a551c94aSIdo Barnea	 * consecutive "1" bits.
499a551c94aSIdo Barnea	 */
500a551c94aSIdo Barnea	e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
501a551c94aSIdo Barnea
502a551c94aSIdo Barnea	/*
503a551c94aSIdo Barnea	 * Now combine the next few fields that are required for a read
504a551c94aSIdo Barnea	 * operation.  We use this method instead of calling the
505a551c94aSIdo Barnea	 * e1000_shift_out_mdi_bits routine five different times.  The format
506a551c94aSIdo Barnea	 * of an MII read instruction consists of a shift out of 14 bits and
507a551c94aSIdo Barnea	 * is defined as follows:
508a551c94aSIdo Barnea	 *         <Preamble><SOF><Op Code><Phy Addr><Offset>
509a551c94aSIdo Barnea	 * followed by a shift in of 18 bits.  This first two bits shifted in
510a551c94aSIdo Barnea	 * are TurnAround bits used to avoid contention on the MDIO pin when a
511a551c94aSIdo Barnea	 * READ operation is performed.  These two bits are thrown away
512a551c94aSIdo Barnea	 * followed by a shift in of 16 bits which contains the desired data.
513a551c94aSIdo Barnea	 */
514a551c94aSIdo Barnea	mdic = (offset | (hw->phy.addr << 5) |
515a551c94aSIdo Barnea		(PHY_OP_READ << 10) | (PHY_SOF << 12));
516a551c94aSIdo Barnea
517a551c94aSIdo Barnea	e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
518a551c94aSIdo Barnea
519a551c94aSIdo Barnea	/*
520a551c94aSIdo Barnea	 * Now that we've shifted out the read command to the MII, we need to
521a551c94aSIdo Barnea	 * "shift in" the 16-bit value (18 total bits) of the requested PHY
522a551c94aSIdo Barnea	 * register address.
523a551c94aSIdo Barnea	 */
524a551c94aSIdo Barnea	*data = e1000_shift_in_mdi_bits_82543(hw);
525a551c94aSIdo Barnea
526a551c94aSIdo Barneaout:
527a551c94aSIdo Barnea	return ret_val;
528a551c94aSIdo Barnea}
529a551c94aSIdo Barnea
530a551c94aSIdo Barnea/**
531a551c94aSIdo Barnea *  e1000_write_phy_reg_82543 - Write PHY register
532a551c94aSIdo Barnea *  @hw: pointer to the HW structure
533a551c94aSIdo Barnea *  @offset: register offset to be written
534a551c94aSIdo Barnea *  @data: pointer to the data to be written at offset
535a551c94aSIdo Barnea *
536a551c94aSIdo Barnea *  Writes data to the PHY at offset.
537a551c94aSIdo Barnea **/
538a551c94aSIdo BarneaSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
539a551c94aSIdo Barnea{
540a551c94aSIdo Barnea	u32 mdic;
541a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
542a551c94aSIdo Barnea
543a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_82543");
544a551c94aSIdo Barnea
545a551c94aSIdo Barnea	if (offset > MAX_PHY_REG_ADDRESS) {
546a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %d is out of range\n", offset);
547a551c94aSIdo Barnea		ret_val = -E1000_ERR_PARAM;
548a551c94aSIdo Barnea		goto out;
549a551c94aSIdo Barnea	}
550a551c94aSIdo Barnea
551a551c94aSIdo Barnea	/*
552a551c94aSIdo Barnea	 * We'll need to use the SW defined pins to shift the write command
553a551c94aSIdo Barnea	 * out to the PHY. We first send a preamble to the PHY to signal the
554a551c94aSIdo Barnea	 * beginning of the MII instruction.  This is done by sending 32
555a551c94aSIdo Barnea	 * consecutive "1" bits.
556a551c94aSIdo Barnea	 */
557a551c94aSIdo Barnea	e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
558a551c94aSIdo Barnea
559a551c94aSIdo Barnea	/*
560a551c94aSIdo Barnea	 * Now combine the remaining required fields that will indicate a
561a551c94aSIdo Barnea	 * write operation. We use this method instead of calling the
562a551c94aSIdo Barnea	 * e1000_shift_out_mdi_bits routine for each field in the command. The
563a551c94aSIdo Barnea	 * format of a MII write instruction is as follows:
564a551c94aSIdo Barnea	 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
565a551c94aSIdo Barnea	 */
566a551c94aSIdo Barnea	mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
567a551c94aSIdo Barnea		(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
568a551c94aSIdo Barnea	mdic <<= 16;
569a551c94aSIdo Barnea	mdic |= (u32)data;
570a551c94aSIdo Barnea
571a551c94aSIdo Barnea	e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
572a551c94aSIdo Barnea
573a551c94aSIdo Barneaout:
574a551c94aSIdo Barnea	return ret_val;
575a551c94aSIdo Barnea}
576a551c94aSIdo Barnea
577a551c94aSIdo Barnea/**
578a551c94aSIdo Barnea *  e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
579a551c94aSIdo Barnea *  @hw: pointer to the HW structure
580a551c94aSIdo Barnea *  @ctrl: pointer to the control register
581a551c94aSIdo Barnea *
582a551c94aSIdo Barnea *  Raise the management data input clock by setting the MDC bit in the control
583a551c94aSIdo Barnea *  register.
584a551c94aSIdo Barnea **/
585a551c94aSIdo BarneaSTATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
586a551c94aSIdo Barnea{
587a551c94aSIdo Barnea	/*
588a551c94aSIdo Barnea	 * Raise the clock input to the Management Data Clock (by setting the
589a551c94aSIdo Barnea	 * MDC bit), and then delay a sufficient amount of time.
590a551c94aSIdo Barnea	 */
591a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
592a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
593a551c94aSIdo Barnea	usec_delay(10);
594a551c94aSIdo Barnea}
595a551c94aSIdo Barnea
596a551c94aSIdo Barnea/**
597a551c94aSIdo Barnea *  e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
598a551c94aSIdo Barnea *  @hw: pointer to the HW structure
599a551c94aSIdo Barnea *  @ctrl: pointer to the control register
600a551c94aSIdo Barnea *
601a551c94aSIdo Barnea *  Lower the management data input clock by clearing the MDC bit in the
602a551c94aSIdo Barnea *  control register.
603a551c94aSIdo Barnea **/
604a551c94aSIdo BarneaSTATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
605a551c94aSIdo Barnea{
606a551c94aSIdo Barnea	/*
607a551c94aSIdo Barnea	 * Lower the clock input to the Management Data Clock (by clearing the
608a551c94aSIdo Barnea	 * MDC bit), and then delay a sufficient amount of time.
609a551c94aSIdo Barnea	 */
610a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
611a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
612a551c94aSIdo Barnea	usec_delay(10);
613a551c94aSIdo Barnea}
614a551c94aSIdo Barnea
615a551c94aSIdo Barnea/**
616a551c94aSIdo Barnea *  e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
617a551c94aSIdo Barnea *  @hw: pointer to the HW structure
618a551c94aSIdo Barnea *  @data: data to send to the PHY
619a551c94aSIdo Barnea *  @count: number of bits to shift out
620a551c94aSIdo Barnea *
621a551c94aSIdo Barnea *  We need to shift 'count' bits out to the PHY.  So, the value in the
622a551c94aSIdo Barnea *  "data" parameter will be shifted out to the PHY one bit at a time.
623a551c94aSIdo Barnea *  In order to do this, "data" must be broken down into bits.
624a551c94aSIdo Barnea **/
625a551c94aSIdo BarneaSTATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
626a551c94aSIdo Barnea					   u16 count)
627a551c94aSIdo Barnea{
628a551c94aSIdo Barnea	u32 ctrl, mask;
629a551c94aSIdo Barnea
630a551c94aSIdo Barnea	/*
631a551c94aSIdo Barnea	 * We need to shift "count" number of bits out to the PHY.  So, the
632a551c94aSIdo Barnea	 * value in the "data" parameter will be shifted out to the PHY one
633a551c94aSIdo Barnea	 * bit at a time.  In order to do this, "data" must be broken down
634a551c94aSIdo Barnea	 * into bits.
635a551c94aSIdo Barnea	 */
636a551c94aSIdo Barnea	mask = 0x01;
637a551c94aSIdo Barnea	mask <<= (count - 1);
638a551c94aSIdo Barnea
639a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
640a551c94aSIdo Barnea
641a551c94aSIdo Barnea	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
642a551c94aSIdo Barnea	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
643a551c94aSIdo Barnea
644a551c94aSIdo Barnea	while (mask) {
645a551c94aSIdo Barnea		/*
646a551c94aSIdo Barnea		 * A "1" is shifted out to the PHY by setting the MDIO bit to
647a551c94aSIdo Barnea		 * "1" and then raising and lowering the Management Data Clock.
648a551c94aSIdo Barnea		 * A "0" is shifted out to the PHY by setting the MDIO bit to
649a551c94aSIdo Barnea		 * "0" and then raising and lowering the clock.
650a551c94aSIdo Barnea		 */
651a551c94aSIdo Barnea		if (data & mask)
652a551c94aSIdo Barnea			ctrl |= E1000_CTRL_MDIO;
653a551c94aSIdo Barnea		else
654a551c94aSIdo Barnea			ctrl &= ~E1000_CTRL_MDIO;
655a551c94aSIdo Barnea
656a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
657a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
658a551c94aSIdo Barnea
659a551c94aSIdo Barnea		usec_delay(10);
660a551c94aSIdo Barnea
661a551c94aSIdo Barnea		e1000_raise_mdi_clk_82543(hw, &ctrl);
662a551c94aSIdo Barnea		e1000_lower_mdi_clk_82543(hw, &ctrl);
663a551c94aSIdo Barnea
664a551c94aSIdo Barnea		mask >>= 1;
665a551c94aSIdo Barnea	}
666a551c94aSIdo Barnea}
667a551c94aSIdo Barnea
668a551c94aSIdo Barnea/**
669a551c94aSIdo Barnea *  e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
670a551c94aSIdo Barnea *  @hw: pointer to the HW structure
671a551c94aSIdo Barnea *
672a551c94aSIdo Barnea *  In order to read a register from the PHY, we need to shift 18 bits
673a551c94aSIdo Barnea *  in from the PHY.  Bits are "shifted in" by raising the clock input to
674a551c94aSIdo Barnea *  the PHY (setting the MDC bit), and then reading the value of the data out
675a551c94aSIdo Barnea *  MDIO bit.
676a551c94aSIdo Barnea **/
677a551c94aSIdo BarneaSTATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
678a551c94aSIdo Barnea{
679a551c94aSIdo Barnea	u32 ctrl;
680a551c94aSIdo Barnea	u16 data = 0;
681a551c94aSIdo Barnea	u8 i;
682a551c94aSIdo Barnea
683a551c94aSIdo Barnea	/*
684a551c94aSIdo Barnea	 * In order to read a register from the PHY, we need to shift in a
685a551c94aSIdo Barnea	 * total of 18 bits from the PHY.  The first two bit (turnaround)
686a551c94aSIdo Barnea	 * times are used to avoid contention on the MDIO pin when a read
687a551c94aSIdo Barnea	 * operation is performed.  These two bits are ignored by us and
688a551c94aSIdo Barnea	 * thrown away.  Bits are "shifted in" by raising the input to the
689a551c94aSIdo Barnea	 * Management Data Clock (setting the MDC bit) and then reading the
690a551c94aSIdo Barnea	 * value of the MDIO bit.
691a551c94aSIdo Barnea	 */
692a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
693a551c94aSIdo Barnea
694a551c94aSIdo Barnea	/*
695a551c94aSIdo Barnea	 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
696a551c94aSIdo Barnea	 * input.
697a551c94aSIdo Barnea	 */
698a551c94aSIdo Barnea	ctrl &= ~E1000_CTRL_MDIO_DIR;
699a551c94aSIdo Barnea	ctrl &= ~E1000_CTRL_MDIO;
700a551c94aSIdo Barnea
701a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
702a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
703a551c94aSIdo Barnea
704a551c94aSIdo Barnea	/*
705a551c94aSIdo Barnea	 * Raise and lower the clock before reading in the data.  This accounts
706a551c94aSIdo Barnea	 * for the turnaround bits.  The first clock occurred when we clocked
707a551c94aSIdo Barnea	 * out the last bit of the Register Address.
708a551c94aSIdo Barnea	 */
709a551c94aSIdo Barnea	e1000_raise_mdi_clk_82543(hw, &ctrl);
710a551c94aSIdo Barnea	e1000_lower_mdi_clk_82543(hw, &ctrl);
711a551c94aSIdo Barnea
712a551c94aSIdo Barnea	for (data = 0, i = 0; i < 16; i++) {
713a551c94aSIdo Barnea		data <<= 1;
714a551c94aSIdo Barnea		e1000_raise_mdi_clk_82543(hw, &ctrl);
715a551c94aSIdo Barnea		ctrl = E1000_READ_REG(hw, E1000_CTRL);
716a551c94aSIdo Barnea		/* Check to see if we shifted in a "1". */
717a551c94aSIdo Barnea		if (ctrl & E1000_CTRL_MDIO)
718a551c94aSIdo Barnea			data |= 1;
719a551c94aSIdo Barnea		e1000_lower_mdi_clk_82543(hw, &ctrl);
720a551c94aSIdo Barnea	}
721a551c94aSIdo Barnea
722a551c94aSIdo Barnea	e1000_raise_mdi_clk_82543(hw, &ctrl);
723a551c94aSIdo Barnea	e1000_lower_mdi_clk_82543(hw, &ctrl);
724a551c94aSIdo Barnea
725a551c94aSIdo Barnea	return data;
726a551c94aSIdo Barnea}
727a551c94aSIdo Barnea
728a551c94aSIdo Barnea/**
729a551c94aSIdo Barnea *  e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
730a551c94aSIdo Barnea *  @hw: pointer to the HW structure
731a551c94aSIdo Barnea *
732a551c94aSIdo Barnea *  Calls the function to force speed and duplex for the m88 PHY, and
733a551c94aSIdo Barnea *  if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
734a551c94aSIdo Barnea *  then call the function for polarity reversal workaround.
735a551c94aSIdo Barnea **/
736a551c94aSIdo BarneaSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
737a551c94aSIdo Barnea{
738a551c94aSIdo Barnea	s32 ret_val;
739a551c94aSIdo Barnea
740a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
741a551c94aSIdo Barnea
742a551c94aSIdo Barnea	ret_val = e1000_phy_force_speed_duplex_m88(hw);
743a551c94aSIdo Barnea	if (ret_val)
744a551c94aSIdo Barnea		goto out;
745a551c94aSIdo Barnea
746a551c94aSIdo Barnea	if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
747a551c94aSIdo Barnea	    E1000_ALL_10_SPEED))
748a551c94aSIdo Barnea		ret_val = e1000_polarity_reversal_workaround_82543(hw);
749a551c94aSIdo Barnea
750a551c94aSIdo Barneaout:
751a551c94aSIdo Barnea	return ret_val;
752a551c94aSIdo Barnea}
753a551c94aSIdo Barnea
754a551c94aSIdo Barnea/**
755a551c94aSIdo Barnea *  e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
756a551c94aSIdo Barnea *  @hw: pointer to the HW structure
757a551c94aSIdo Barnea *
758a551c94aSIdo Barnea *  When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
759a551c94aSIdo Barnea *  inadvertently.  To workaround the issue, we disable the transmitter on
760a551c94aSIdo Barnea *  the PHY until we have established the link partner's link parameters.
761a551c94aSIdo Barnea **/
762a551c94aSIdo BarneaSTATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
763a551c94aSIdo Barnea{
764a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
765a551c94aSIdo Barnea	u16 mii_status_reg;
766a551c94aSIdo Barnea	u16 i;
767a551c94aSIdo Barnea	bool link;
768a551c94aSIdo Barnea
769a551c94aSIdo Barnea	if (!(hw->phy.ops.write_reg))
770a551c94aSIdo Barnea		goto out;
771a551c94aSIdo Barnea
772a551c94aSIdo Barnea	/* Polarity reversal workaround for forced 10F/10H links. */
773a551c94aSIdo Barnea
774a551c94aSIdo Barnea	/* Disable the transmitter on the PHY */
775a551c94aSIdo Barnea
776a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
777a551c94aSIdo Barnea	if (ret_val)
778a551c94aSIdo Barnea		goto out;
779a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
780a551c94aSIdo Barnea	if (ret_val)
781a551c94aSIdo Barnea		goto out;
782a551c94aSIdo Barnea
783a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
784a551c94aSIdo Barnea	if (ret_val)
785a551c94aSIdo Barnea		goto out;
786a551c94aSIdo Barnea
787a551c94aSIdo Barnea	/*
788a551c94aSIdo Barnea	 * This loop will early-out if the NO link condition has been met.
789a551c94aSIdo Barnea	 * In other words, DO NOT use e1000_phy_has_link_generic() here.
790a551c94aSIdo Barnea	 */
791a551c94aSIdo Barnea	for (i = PHY_FORCE_TIME; i > 0; i--) {
792a551c94aSIdo Barnea		/*
793a551c94aSIdo Barnea		 * Read the MII Status Register and wait for Link Status bit
794a551c94aSIdo Barnea		 * to be clear.
795a551c94aSIdo Barnea		 */
796a551c94aSIdo Barnea
797a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
798a551c94aSIdo Barnea		if (ret_val)
799a551c94aSIdo Barnea			goto out;
800a551c94aSIdo Barnea
801a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
802a551c94aSIdo Barnea		if (ret_val)
803a551c94aSIdo Barnea			goto out;
804a551c94aSIdo Barnea
805a551c94aSIdo Barnea		if (!(mii_status_reg & ~MII_SR_LINK_STATUS))
806a551c94aSIdo Barnea			break;
807a551c94aSIdo Barnea		msec_delay_irq(100);
808a551c94aSIdo Barnea	}
809a551c94aSIdo Barnea
810a551c94aSIdo Barnea	/* Recommended delay time after link has been lost */
811a551c94aSIdo Barnea	msec_delay_irq(1000);
812a551c94aSIdo Barnea
813a551c94aSIdo Barnea	/* Now we will re-enable the transmitter on the PHY */
814a551c94aSIdo Barnea
815a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
816a551c94aSIdo Barnea	if (ret_val)
817a551c94aSIdo Barnea		goto out;
818a551c94aSIdo Barnea	msec_delay_irq(50);
819a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
820a551c94aSIdo Barnea	if (ret_val)
821a551c94aSIdo Barnea		goto out;
822a551c94aSIdo Barnea	msec_delay_irq(50);
823a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
824a551c94aSIdo Barnea	if (ret_val)
825a551c94aSIdo Barnea		goto out;
826a551c94aSIdo Barnea	msec_delay_irq(50);
827a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
828a551c94aSIdo Barnea	if (ret_val)
829a551c94aSIdo Barnea		goto out;
830a551c94aSIdo Barnea
831a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
832a551c94aSIdo Barnea	if (ret_val)
833a551c94aSIdo Barnea		goto out;
834a551c94aSIdo Barnea
835a551c94aSIdo Barnea	/*
836a551c94aSIdo Barnea	 * Read the MII Status Register and wait for Link Status bit
837a551c94aSIdo Barnea	 * to be set.
838a551c94aSIdo Barnea	 */
839a551c94aSIdo Barnea	ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
840a551c94aSIdo Barnea	if (ret_val)
841a551c94aSIdo Barnea		goto out;
842a551c94aSIdo Barnea
843a551c94aSIdo Barneaout:
844a551c94aSIdo Barnea	return ret_val;
845a551c94aSIdo Barnea}
846a551c94aSIdo Barnea
847a551c94aSIdo Barnea/**
848a551c94aSIdo Barnea *  e1000_phy_hw_reset_82543 - PHY hardware reset
849a551c94aSIdo Barnea *  @hw: pointer to the HW structure
850a551c94aSIdo Barnea *
851a551c94aSIdo Barnea *  Sets the PHY_RESET_DIR bit in the extended device control register
852a551c94aSIdo Barnea *  to put the PHY into a reset and waits for completion.  Once the reset
853a551c94aSIdo Barnea *  has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
854a551c94aSIdo Barnea *  of reset.
855a551c94aSIdo Barnea **/
856a551c94aSIdo BarneaSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
857a551c94aSIdo Barnea{
858a551c94aSIdo Barnea	u32 ctrl_ext;
859a551c94aSIdo Barnea	s32 ret_val;
860a551c94aSIdo Barnea
861a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_hw_reset_82543");
862a551c94aSIdo Barnea
863a551c94aSIdo Barnea	/*
864a551c94aSIdo Barnea	 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
865a551c94aSIdo Barnea	 * bit to put the PHY into reset...
866a551c94aSIdo Barnea	 */
867a551c94aSIdo Barnea	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
868a551c94aSIdo Barnea	ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
869a551c94aSIdo Barnea	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
870a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
871a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
872a551c94aSIdo Barnea
873a551c94aSIdo Barnea	msec_delay(10);
874a551c94aSIdo Barnea
875a551c94aSIdo Barnea	/* ...then take it out of reset. */
876a551c94aSIdo Barnea	ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
877a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
878a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
879a551c94aSIdo Barnea
880a551c94aSIdo Barnea	usec_delay(150);
881a551c94aSIdo Barnea
882a551c94aSIdo Barnea	if (!(hw->phy.ops.get_cfg_done))
883a551c94aSIdo Barnea		return E1000_SUCCESS;
884a551c94aSIdo Barnea
885a551c94aSIdo Barnea	ret_val = hw->phy.ops.get_cfg_done(hw);
886a551c94aSIdo Barnea
887a551c94aSIdo Barnea	return ret_val;
888a551c94aSIdo Barnea}
889a551c94aSIdo Barnea
890a551c94aSIdo Barnea/**
891a551c94aSIdo Barnea *  e1000_reset_hw_82543 - Reset hardware
892a551c94aSIdo Barnea *  @hw: pointer to the HW structure
893a551c94aSIdo Barnea *
894a551c94aSIdo Barnea *  This resets the hardware into a known state.
895a551c94aSIdo Barnea **/
896a551c94aSIdo BarneaSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw)
897a551c94aSIdo Barnea{
898a551c94aSIdo Barnea	u32 ctrl;
899a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
900a551c94aSIdo Barnea
901a551c94aSIdo Barnea	DEBUGFUNC("e1000_reset_hw_82543");
902a551c94aSIdo Barnea
903a551c94aSIdo Barnea	DEBUGOUT("Masking off all interrupts\n");
904a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
905a551c94aSIdo Barnea
906a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RCTL, 0);
907a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
908a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
909a551c94aSIdo Barnea
910a551c94aSIdo Barnea	e1000_set_tbi_sbp_82543(hw, false);
911a551c94aSIdo Barnea
912a551c94aSIdo Barnea	/*
913a551c94aSIdo Barnea	 * Delay to allow any outstanding PCI transactions to complete before
914a551c94aSIdo Barnea	 * resetting the device
915a551c94aSIdo Barnea	 */
916a551c94aSIdo Barnea	msec_delay(10);
917a551c94aSIdo Barnea
918a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
919a551c94aSIdo Barnea
920a551c94aSIdo Barnea	DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
921a551c94aSIdo Barnea	if (hw->mac.type == e1000_82543) {
922a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
923a551c94aSIdo Barnea	} else {
924a551c94aSIdo Barnea		/*
925a551c94aSIdo Barnea		 * The 82544 can't ACK the 64-bit write when issuing the
926a551c94aSIdo Barnea		 * reset, so use IO-mapping as a workaround.
927a551c94aSIdo Barnea		 */
928a551c94aSIdo Barnea		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
929a551c94aSIdo Barnea	}
930a551c94aSIdo Barnea
931a551c94aSIdo Barnea	/*
932a551c94aSIdo Barnea	 * After MAC reset, force reload of NVM to restore power-on
933a551c94aSIdo Barnea	 * settings to device.
934a551c94aSIdo Barnea	 */
935a551c94aSIdo Barnea	hw->nvm.ops.reload(hw);
936a551c94aSIdo Barnea	msec_delay(2);
937a551c94aSIdo Barnea
938a551c94aSIdo Barnea	/* Masking off and clearing any pending interrupts */
939a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
940a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ICR);
941a551c94aSIdo Barnea
942a551c94aSIdo Barnea	return ret_val;
943a551c94aSIdo Barnea}
944a551c94aSIdo Barnea
945a551c94aSIdo Barnea/**
946a551c94aSIdo Barnea *  e1000_init_hw_82543 - Initialize hardware
947a551c94aSIdo Barnea *  @hw: pointer to the HW structure
948a551c94aSIdo Barnea *
949a551c94aSIdo Barnea *  This inits the hardware readying it for operation.
950a551c94aSIdo Barnea **/
951a551c94aSIdo BarneaSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw)
952a551c94aSIdo Barnea{
953a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
954a551c94aSIdo Barnea	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
955a551c94aSIdo Barnea	u32 ctrl;
956a551c94aSIdo Barnea	s32 ret_val;
957a551c94aSIdo Barnea	u16 i;
958a551c94aSIdo Barnea
959a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_hw_82543");
960a551c94aSIdo Barnea
961a551c94aSIdo Barnea	/* Disabling VLAN filtering */
962a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_VET, 0);
963a551c94aSIdo Barnea	mac->ops.clear_vfta(hw);
964a551c94aSIdo Barnea
965a551c94aSIdo Barnea	/* Setup the receive address. */
966a551c94aSIdo Barnea	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
967a551c94aSIdo Barnea
968a551c94aSIdo Barnea	/* Zero out the Multicast HASH table */
969a551c94aSIdo Barnea	DEBUGOUT("Zeroing the MTA\n");
970a551c94aSIdo Barnea	for (i = 0; i < mac->mta_reg_count; i++) {
971a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
972a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
973a551c94aSIdo Barnea	}
974a551c94aSIdo Barnea
975a551c94aSIdo Barnea	/*
976a551c94aSIdo Barnea	 * Set the PCI priority bit correctly in the CTRL register.  This
977a551c94aSIdo Barnea	 * determines if the adapter gives priority to receives, or if it
978a551c94aSIdo Barnea	 * gives equal priority to transmits and receives.
979a551c94aSIdo Barnea	 */
980a551c94aSIdo Barnea	if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
981a551c94aSIdo Barnea		ctrl = E1000_READ_REG(hw, E1000_CTRL);
982a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
983a551c94aSIdo Barnea	}
984a551c94aSIdo Barnea
985a551c94aSIdo Barnea	e1000_pcix_mmrbc_workaround_generic(hw);
986a551c94aSIdo Barnea
987a551c94aSIdo Barnea	/* Setup link and flow control */
988a551c94aSIdo Barnea	ret_val = mac->ops.setup_link(hw);
989a551c94aSIdo Barnea
990a551c94aSIdo Barnea	/*
991a551c94aSIdo Barnea	 * Clear all of the statistics registers (clear on read).  It is
992a551c94aSIdo Barnea	 * important that we do this after we have tried to establish link
993a551c94aSIdo Barnea	 * because the symbol error count will increment wildly if there
994a551c94aSIdo Barnea	 * is no link.
995a551c94aSIdo Barnea	 */
996a551c94aSIdo Barnea	e1000_clear_hw_cntrs_82543(hw);
997a551c94aSIdo Barnea
998a551c94aSIdo Barnea	return ret_val;
999a551c94aSIdo Barnea}
1000a551c94aSIdo Barnea
1001a551c94aSIdo Barnea/**
1002a551c94aSIdo Barnea *  e1000_setup_link_82543 - Setup flow control and link settings
1003a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1004a551c94aSIdo Barnea *
1005a551c94aSIdo Barnea *  Read the EEPROM to determine the initial polarity value and write the
1006a551c94aSIdo Barnea *  extended device control register with the information before calling
1007a551c94aSIdo Barnea *  the generic setup link function, which does the following:
1008a551c94aSIdo Barnea *  Determines which flow control settings to use, then configures flow
1009a551c94aSIdo Barnea *  control.  Calls the appropriate media-specific link configuration
1010a551c94aSIdo Barnea *  function.  Assuming the adapter has a valid link partner, a valid link
1011a551c94aSIdo Barnea *  should be established.  Assumes the hardware has previously been reset
1012a551c94aSIdo Barnea *  and the transmitter and receiver are not enabled.
1013a551c94aSIdo Barnea **/
1014a551c94aSIdo BarneaSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw)
1015a551c94aSIdo Barnea{
1016a551c94aSIdo Barnea	u32 ctrl_ext;
1017a551c94aSIdo Barnea	s32  ret_val;
1018a551c94aSIdo Barnea	u16 data;
1019a551c94aSIdo Barnea
1020a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_link_82543");
1021a551c94aSIdo Barnea
1022a551c94aSIdo Barnea	/*
1023a551c94aSIdo Barnea	 * Take the 4 bits from NVM word 0xF that determine the initial
1024a551c94aSIdo Barnea	 * polarity value for the SW controlled pins, and setup the
1025a551c94aSIdo Barnea	 * Extended Device Control reg with that info.
1026a551c94aSIdo Barnea	 * This is needed because one of the SW controlled pins is used for
1027a551c94aSIdo Barnea	 * signal detection.  So this should be done before phy setup.
1028a551c94aSIdo Barnea	 */
1029a551c94aSIdo Barnea	if (hw->mac.type == e1000_82543) {
1030a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1031a551c94aSIdo Barnea		if (ret_val) {
1032a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error\n");
1033a551c94aSIdo Barnea			ret_val = -E1000_ERR_NVM;
1034a551c94aSIdo Barnea			goto out;
1035a551c94aSIdo Barnea		}
1036a551c94aSIdo Barnea		ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1037a551c94aSIdo Barnea			    NVM_SWDPIO_EXT_SHIFT);
1038a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1039a551c94aSIdo Barnea	}
1040a551c94aSIdo Barnea
1041a551c94aSIdo Barnea	ret_val = e1000_setup_link_generic(hw);
1042a551c94aSIdo Barnea
1043a551c94aSIdo Barneaout:
1044a551c94aSIdo Barnea	return ret_val;
1045a551c94aSIdo Barnea}
1046a551c94aSIdo Barnea
1047a551c94aSIdo Barnea/**
1048a551c94aSIdo Barnea *  e1000_setup_copper_link_82543 - Configure copper link settings
1049a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1050a551c94aSIdo Barnea *
1051a551c94aSIdo Barnea *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1052a551c94aSIdo Barnea *  for link, once link is established calls to configure collision distance
1053a551c94aSIdo Barnea *  and flow control are called.
1054a551c94aSIdo Barnea **/
1055a551c94aSIdo BarneaSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1056a551c94aSIdo Barnea{
1057a551c94aSIdo Barnea	u32 ctrl;
1058a551c94aSIdo Barnea	s32 ret_val;
1059a551c94aSIdo Barnea	bool link;
1060a551c94aSIdo Barnea
1061a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_copper_link_82543");
1062a551c94aSIdo Barnea
1063a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1064a551c94aSIdo Barnea	/*
1065a551c94aSIdo Barnea	 * With 82543, we need to force speed and duplex on the MAC
1066a551c94aSIdo Barnea	 * equal to what the PHY speed and duplex configuration is.
1067a551c94aSIdo Barnea	 * In addition, we need to perform a hardware reset on the
1068a551c94aSIdo Barnea	 * PHY to take it out of reset.
1069a551c94aSIdo Barnea	 */
1070a551c94aSIdo Barnea	if (hw->mac.type == e1000_82543) {
1071a551c94aSIdo Barnea		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1072a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1073a551c94aSIdo Barnea		ret_val = hw->phy.ops.reset(hw);
1074a551c94aSIdo Barnea		if (ret_val)
1075a551c94aSIdo Barnea			goto out;
1076a551c94aSIdo Barnea	} else {
1077a551c94aSIdo Barnea		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1078a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079a551c94aSIdo Barnea	}
1080a551c94aSIdo Barnea
1081a551c94aSIdo Barnea	/* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1082a551c94aSIdo Barnea	ret_val = e1000_copper_link_setup_m88(hw);
1083a551c94aSIdo Barnea	if (ret_val)
1084a551c94aSIdo Barnea		goto out;
1085a551c94aSIdo Barnea
1086a551c94aSIdo Barnea	if (hw->mac.autoneg) {
1087a551c94aSIdo Barnea		/*
1088a551c94aSIdo Barnea		 * Setup autoneg and flow control advertisement and perform
1089a551c94aSIdo Barnea		 * autonegotiation.
1090a551c94aSIdo Barnea		 */
1091a551c94aSIdo Barnea		ret_val = e1000_copper_link_autoneg(hw);
1092a551c94aSIdo Barnea		if (ret_val)
1093a551c94aSIdo Barnea			goto out;
1094a551c94aSIdo Barnea	} else {
1095a551c94aSIdo Barnea		/*
1096a551c94aSIdo Barnea		 * PHY will be set to 10H, 10F, 100H or 100F
1097a551c94aSIdo Barnea		 * depending on user settings.
1098a551c94aSIdo Barnea		 */
1099a551c94aSIdo Barnea		DEBUGOUT("Forcing Speed and Duplex\n");
1100a551c94aSIdo Barnea		ret_val = e1000_phy_force_speed_duplex_82543(hw);
1101a551c94aSIdo Barnea		if (ret_val) {
1102a551c94aSIdo Barnea			DEBUGOUT("Error Forcing Speed and Duplex\n");
1103a551c94aSIdo Barnea			goto out;
1104a551c94aSIdo Barnea		}
1105a551c94aSIdo Barnea	}
1106a551c94aSIdo Barnea
1107a551c94aSIdo Barnea	/*
1108a551c94aSIdo Barnea	 * Check link status. Wait up to 100 microseconds for link to become
1109a551c94aSIdo Barnea	 * valid.
1110a551c94aSIdo Barnea	 */
1111a551c94aSIdo Barnea	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1112a551c94aSIdo Barnea					     &link);
1113a551c94aSIdo Barnea	if (ret_val)
1114a551c94aSIdo Barnea		goto out;
1115a551c94aSIdo Barnea
1116a551c94aSIdo Barnea
1117a551c94aSIdo Barnea	if (link) {
1118a551c94aSIdo Barnea		DEBUGOUT("Valid link established!!!\n");
1119a551c94aSIdo Barnea		/* Config the MAC and PHY after link is up */
1120a551c94aSIdo Barnea		if (hw->mac.type == e1000_82544) {
1121a551c94aSIdo Barnea			hw->mac.ops.config_collision_dist(hw);
1122a551c94aSIdo Barnea		} else {
1123a551c94aSIdo Barnea			ret_val = e1000_config_mac_to_phy_82543(hw);
1124a551c94aSIdo Barnea			if (ret_val)
1125a551c94aSIdo Barnea				goto out;
1126a551c94aSIdo Barnea		}
1127a551c94aSIdo Barnea		ret_val = e1000_config_fc_after_link_up_generic(hw);
1128a551c94aSIdo Barnea	} else {
1129a551c94aSIdo Barnea		DEBUGOUT("Unable to establish link!!!\n");
1130a551c94aSIdo Barnea	}
1131a551c94aSIdo Barnea
1132a551c94aSIdo Barneaout:
1133a551c94aSIdo Barnea	return ret_val;
1134a551c94aSIdo Barnea}
1135a551c94aSIdo Barnea
1136a551c94aSIdo Barnea/**
1137a551c94aSIdo Barnea *  e1000_setup_fiber_link_82543 - Setup link for fiber
1138a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1139a551c94aSIdo Barnea *
1140a551c94aSIdo Barnea *  Configures collision distance and flow control for fiber links.  Upon
1141a551c94aSIdo Barnea *  successful setup, poll for link.
1142a551c94aSIdo Barnea **/
1143a551c94aSIdo BarneaSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1144a551c94aSIdo Barnea{
1145a551c94aSIdo Barnea	u32 ctrl;
1146a551c94aSIdo Barnea	s32 ret_val;
1147a551c94aSIdo Barnea
1148a551c94aSIdo Barnea	DEBUGFUNC("e1000_setup_fiber_link_82543");
1149a551c94aSIdo Barnea
1150a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1151a551c94aSIdo Barnea
1152a551c94aSIdo Barnea	/* Take the link out of reset */
1153a551c94aSIdo Barnea	ctrl &= ~E1000_CTRL_LRST;
1154a551c94aSIdo Barnea
1155a551c94aSIdo Barnea	hw->mac.ops.config_collision_dist(hw);
1156a551c94aSIdo Barnea
1157a551c94aSIdo Barnea	ret_val = e1000_commit_fc_settings_generic(hw);
1158a551c94aSIdo Barnea	if (ret_val)
1159a551c94aSIdo Barnea		goto out;
1160a551c94aSIdo Barnea
1161a551c94aSIdo Barnea	DEBUGOUT("Auto-negotiation enabled\n");
1162a551c94aSIdo Barnea
1163a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1164a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1165a551c94aSIdo Barnea	msec_delay(1);
1166a551c94aSIdo Barnea
1167a551c94aSIdo Barnea	/*
1168a551c94aSIdo Barnea	 * For these adapters, the SW definable pin 1 is cleared when the
1169a551c94aSIdo Barnea	 * optics detect a signal.  If we have a signal, then poll for a
1170a551c94aSIdo Barnea	 * "Link-Up" indication.
1171a551c94aSIdo Barnea	 */
1172a551c94aSIdo Barnea	if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
1173a551c94aSIdo Barnea		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1174a551c94aSIdo Barnea	else
1175a551c94aSIdo Barnea		DEBUGOUT("No signal detected\n");
1176a551c94aSIdo Barnea
1177a551c94aSIdo Barneaout:
1178a551c94aSIdo Barnea	return ret_val;
1179a551c94aSIdo Barnea}
1180a551c94aSIdo Barnea
1181a551c94aSIdo Barnea/**
1182a551c94aSIdo Barnea *  e1000_check_for_copper_link_82543 - Check for link (Copper)
1183a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1184a551c94aSIdo Barnea *
1185a551c94aSIdo Barnea *  Checks the phy for link, if link exists, do the following:
1186a551c94aSIdo Barnea *   - check for downshift
1187a551c94aSIdo Barnea *   - do polarity workaround (if necessary)
1188a551c94aSIdo Barnea *   - configure collision distance
1189a551c94aSIdo Barnea *   - configure flow control after link up
1190a551c94aSIdo Barnea *   - configure tbi compatibility
1191a551c94aSIdo Barnea **/
1192a551c94aSIdo BarneaSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1193a551c94aSIdo Barnea{
1194a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
1195a551c94aSIdo Barnea	u32 icr, rctl;
1196a551c94aSIdo Barnea	s32 ret_val;
1197a551c94aSIdo Barnea	u16 speed, duplex;
1198a551c94aSIdo Barnea	bool link;
1199a551c94aSIdo Barnea
1200a551c94aSIdo Barnea	DEBUGFUNC("e1000_check_for_copper_link_82543");
1201a551c94aSIdo Barnea
1202a551c94aSIdo Barnea	if (!mac->get_link_status) {
1203a551c94aSIdo Barnea		ret_val = E1000_SUCCESS;
1204a551c94aSIdo Barnea		goto out;
1205a551c94aSIdo Barnea	}
1206a551c94aSIdo Barnea
1207a551c94aSIdo Barnea	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1208a551c94aSIdo Barnea	if (ret_val)
1209a551c94aSIdo Barnea		goto out;
1210a551c94aSIdo Barnea
1211a551c94aSIdo Barnea	if (!link)
1212a551c94aSIdo Barnea		goto out; /* No link detected */
1213a551c94aSIdo Barnea
1214a551c94aSIdo Barnea	mac->get_link_status = false;
1215a551c94aSIdo Barnea
1216a551c94aSIdo Barnea	e1000_check_downshift_generic(hw);
1217a551c94aSIdo Barnea
1218a551c94aSIdo Barnea	/*
1219a551c94aSIdo Barnea	 * If we are forcing speed/duplex, then we can return since
1220a551c94aSIdo Barnea	 * we have already determined whether we have link or not.
1221a551c94aSIdo Barnea	 */
1222a551c94aSIdo Barnea	if (!mac->autoneg) {
1223a551c94aSIdo Barnea		/*
1224a551c94aSIdo Barnea		 * If speed and duplex are forced to 10H or 10F, then we will
1225a551c94aSIdo Barnea		 * implement the polarity reversal workaround.  We disable
1226a551c94aSIdo Barnea		 * interrupts first, and upon returning, place the devices
1227a551c94aSIdo Barnea		 * interrupt state to its previous value except for the link
1228a551c94aSIdo Barnea		 * status change interrupt which will happened due to the
1229a551c94aSIdo Barnea		 * execution of this workaround.
1230a551c94aSIdo Barnea		 */
1231a551c94aSIdo Barnea		if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1232a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1233a551c94aSIdo Barnea			ret_val = e1000_polarity_reversal_workaround_82543(hw);
1234a551c94aSIdo Barnea			icr = E1000_READ_REG(hw, E1000_ICR);
1235a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1236a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1237a551c94aSIdo Barnea		}
1238a551c94aSIdo Barnea
1239a551c94aSIdo Barnea		ret_val = -E1000_ERR_CONFIG;
1240a551c94aSIdo Barnea		goto out;
1241a551c94aSIdo Barnea	}
1242a551c94aSIdo Barnea
1243a551c94aSIdo Barnea	/*
1244a551c94aSIdo Barnea	 * We have a M88E1000 PHY and Auto-Neg is enabled.  If we
1245a551c94aSIdo Barnea	 * have Si on board that is 82544 or newer, Auto
1246a551c94aSIdo Barnea	 * Speed Detection takes care of MAC speed/duplex
1247a551c94aSIdo Barnea	 * configuration.  So we only need to configure Collision
1248a551c94aSIdo Barnea	 * Distance in the MAC.  Otherwise, we need to force
1249a551c94aSIdo Barnea	 * speed/duplex on the MAC to the current PHY speed/duplex
1250a551c94aSIdo Barnea	 * settings.
1251a551c94aSIdo Barnea	 */
1252a551c94aSIdo Barnea	if (mac->type == e1000_82544)
1253a551c94aSIdo Barnea		hw->mac.ops.config_collision_dist(hw);
1254a551c94aSIdo Barnea	else {
1255a551c94aSIdo Barnea		ret_val = e1000_config_mac_to_phy_82543(hw);
1256a551c94aSIdo Barnea		if (ret_val) {
1257a551c94aSIdo Barnea			DEBUGOUT("Error configuring MAC to PHY settings\n");
1258a551c94aSIdo Barnea			goto out;
1259a551c94aSIdo Barnea		}
1260a551c94aSIdo Barnea	}
1261a551c94aSIdo Barnea
1262a551c94aSIdo Barnea	/*
1263a551c94aSIdo Barnea	 * Configure Flow Control now that Auto-Neg has completed.
1264a551c94aSIdo Barnea	 * First, we need to restore the desired flow control
1265a551c94aSIdo Barnea	 * settings because we may have had to re-autoneg with a
1266a551c94aSIdo Barnea	 * different link partner.
1267a551c94aSIdo Barnea	 */
1268a551c94aSIdo Barnea	ret_val = e1000_config_fc_after_link_up_generic(hw);
1269a551c94aSIdo Barnea	if (ret_val)
1270a551c94aSIdo Barnea		DEBUGOUT("Error configuring flow control\n");
1271a551c94aSIdo Barnea
1272a551c94aSIdo Barnea	/*
1273a551c94aSIdo Barnea	 * At this point we know that we are on copper and we have
1274a551c94aSIdo Barnea	 * auto-negotiated link.  These are conditions for checking the link
1275a551c94aSIdo Barnea	 * partner capability register.  We use the link speed to determine if
1276a551c94aSIdo Barnea	 * TBI compatibility needs to be turned on or off.  If the link is not
1277a551c94aSIdo Barnea	 * at gigabit speed, then TBI compatibility is not needed.  If we are
1278a551c94aSIdo Barnea	 * at gigabit speed, we turn on TBI compatibility.
1279a551c94aSIdo Barnea	 */
1280a551c94aSIdo Barnea	if (e1000_tbi_compatibility_enabled_82543(hw)) {
1281a551c94aSIdo Barnea		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1282a551c94aSIdo Barnea		if (ret_val) {
1283a551c94aSIdo Barnea			DEBUGOUT("Error getting link speed and duplex\n");
1284a551c94aSIdo Barnea			return ret_val;
1285a551c94aSIdo Barnea		}
1286a551c94aSIdo Barnea		if (speed != SPEED_1000) {
1287a551c94aSIdo Barnea			/*
1288a551c94aSIdo Barnea			 * If link speed is not set to gigabit speed,
1289a551c94aSIdo Barnea			 * we do not need to enable TBI compatibility.
1290a551c94aSIdo Barnea			 */
1291a551c94aSIdo Barnea			if (e1000_tbi_sbp_enabled_82543(hw)) {
1292a551c94aSIdo Barnea				/*
1293a551c94aSIdo Barnea				 * If we previously were in the mode,
1294a551c94aSIdo Barnea				 * turn it off.
1295a551c94aSIdo Barnea				 */
1296a551c94aSIdo Barnea				e1000_set_tbi_sbp_82543(hw, false);
1297a551c94aSIdo Barnea				rctl = E1000_READ_REG(hw, E1000_RCTL);
1298a551c94aSIdo Barnea				rctl &= ~E1000_RCTL_SBP;
1299a551c94aSIdo Barnea				E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1300a551c94aSIdo Barnea			}
1301a551c94aSIdo Barnea		} else {
1302a551c94aSIdo Barnea			/*
1303a551c94aSIdo Barnea			 * If TBI compatibility is was previously off,
1304a551c94aSIdo Barnea			 * turn it on. For compatibility with a TBI link
1305a551c94aSIdo Barnea			 * partner, we will store bad packets. Some
1306a551c94aSIdo Barnea			 * frames have an additional byte on the end and
1307a551c94aSIdo Barnea			 * will look like CRC errors to to the hardware.
1308a551c94aSIdo Barnea			 */
1309a551c94aSIdo Barnea			if (!e1000_tbi_sbp_enabled_82543(hw)) {
1310a551c94aSIdo Barnea				e1000_set_tbi_sbp_82543(hw, true);
1311a551c94aSIdo Barnea				rctl = E1000_READ_REG(hw, E1000_RCTL);
1312a551c94aSIdo Barnea				rctl |= E1000_RCTL_SBP;
1313a551c94aSIdo Barnea				E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314a551c94aSIdo Barnea			}
1315a551c94aSIdo Barnea		}
1316a551c94aSIdo Barnea	}
1317a551c94aSIdo Barneaout:
1318a551c94aSIdo Barnea	return ret_val;
1319a551c94aSIdo Barnea}
1320a551c94aSIdo Barnea
1321a551c94aSIdo Barnea/**
1322a551c94aSIdo Barnea *  e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1323a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1324a551c94aSIdo Barnea *
1325a551c94aSIdo Barnea *  Checks for link up on the hardware.  If link is not up and we have
1326a551c94aSIdo Barnea *  a signal, then we need to force link up.
1327a551c94aSIdo Barnea **/
1328a551c94aSIdo BarneaSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1329a551c94aSIdo Barnea{
1330a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
1331a551c94aSIdo Barnea	u32 rxcw, ctrl, status;
1332a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1333a551c94aSIdo Barnea
1334a551c94aSIdo Barnea	DEBUGFUNC("e1000_check_for_fiber_link_82543");
1335a551c94aSIdo Barnea
1336a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1337a551c94aSIdo Barnea	status = E1000_READ_REG(hw, E1000_STATUS);
1338a551c94aSIdo Barnea	rxcw = E1000_READ_REG(hw, E1000_RXCW);
1339a551c94aSIdo Barnea
1340a551c94aSIdo Barnea	/*
1341a551c94aSIdo Barnea	 * If we don't have link (auto-negotiation failed or link partner
1342a551c94aSIdo Barnea	 * cannot auto-negotiate), the cable is plugged in (we have signal),
1343a551c94aSIdo Barnea	 * and our link partner is not trying to auto-negotiate with us (we
1344a551c94aSIdo Barnea	 * are receiving idles or data), we need to force link up. We also
1345a551c94aSIdo Barnea	 * need to give auto-negotiation time to complete, in case the cable
1346a551c94aSIdo Barnea	 * was just plugged in. The autoneg_failed flag does this.
1347a551c94aSIdo Barnea	 */
1348a551c94aSIdo Barnea	/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1349a551c94aSIdo Barnea	if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1350a551c94aSIdo Barnea	    (!(status & E1000_STATUS_LU)) &&
1351a551c94aSIdo Barnea	    (!(rxcw & E1000_RXCW_C))) {
1352a551c94aSIdo Barnea		if (!mac->autoneg_failed) {
1353a551c94aSIdo Barnea			mac->autoneg_failed = true;
1354a551c94aSIdo Barnea			ret_val = 0;
1355a551c94aSIdo Barnea			goto out;
1356a551c94aSIdo Barnea		}
1357a551c94aSIdo Barnea		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1358a551c94aSIdo Barnea
1359a551c94aSIdo Barnea		/* Disable auto-negotiation in the TXCW register */
1360a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1361a551c94aSIdo Barnea
1362a551c94aSIdo Barnea		/* Force link-up and also force full-duplex. */
1363a551c94aSIdo Barnea		ctrl = E1000_READ_REG(hw, E1000_CTRL);
1364a551c94aSIdo Barnea		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1365a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1366a551c94aSIdo Barnea
1367a551c94aSIdo Barnea		/* Configure Flow Control after forcing link up. */
1368a551c94aSIdo Barnea		ret_val = e1000_config_fc_after_link_up_generic(hw);
1369a551c94aSIdo Barnea		if (ret_val) {
1370a551c94aSIdo Barnea			DEBUGOUT("Error configuring flow control\n");
1371a551c94aSIdo Barnea			goto out;
1372a551c94aSIdo Barnea		}
1373a551c94aSIdo Barnea	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1374a551c94aSIdo Barnea		/*
1375a551c94aSIdo Barnea		 * If we are forcing link and we are receiving /C/ ordered
1376a551c94aSIdo Barnea		 * sets, re-enable auto-negotiation in the TXCW register
1377a551c94aSIdo Barnea		 * and disable forced link in the Device Control register
1378a551c94aSIdo Barnea		 * in an attempt to auto-negotiate with our link partner.
1379a551c94aSIdo Barnea		 */
1380a551c94aSIdo Barnea		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1381a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1382a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1383a551c94aSIdo Barnea
1384a551c94aSIdo Barnea		mac->serdes_has_link = true;
1385a551c94aSIdo Barnea	}
1386a551c94aSIdo Barnea
1387a551c94aSIdo Barneaout:
1388a551c94aSIdo Barnea	return ret_val;
1389a551c94aSIdo Barnea}
1390a551c94aSIdo Barnea
1391a551c94aSIdo Barnea/**
1392a551c94aSIdo Barnea *  e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1393a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1394a551c94aSIdo Barnea *
1395a551c94aSIdo Barnea *  For the 82543 silicon, we need to set the MAC to match the settings
1396a551c94aSIdo Barnea *  of the PHY, even if the PHY is auto-negotiating.
1397a551c94aSIdo Barnea **/
1398a551c94aSIdo BarneaSTATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1399a551c94aSIdo Barnea{
1400a551c94aSIdo Barnea	u32 ctrl;
1401a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1402a551c94aSIdo Barnea	u16 phy_data;
1403a551c94aSIdo Barnea
1404a551c94aSIdo Barnea	DEBUGFUNC("e1000_config_mac_to_phy_82543");
1405a551c94aSIdo Barnea
1406a551c94aSIdo Barnea	if (!(hw->phy.ops.read_reg))
1407a551c94aSIdo Barnea		goto out;
1408a551c94aSIdo Barnea
1409a551c94aSIdo Barnea	/* Set the bits to force speed and duplex */
1410a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1411a551c94aSIdo Barnea	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1412a551c94aSIdo Barnea	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1413a551c94aSIdo Barnea
1414a551c94aSIdo Barnea	/*
1415a551c94aSIdo Barnea	 * Set up duplex in the Device Control and Transmit Control
1416a551c94aSIdo Barnea	 * registers depending on negotiated values.
1417a551c94aSIdo Barnea	 */
1418a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1419a551c94aSIdo Barnea	if (ret_val)
1420a551c94aSIdo Barnea		goto out;
1421a551c94aSIdo Barnea
1422a551c94aSIdo Barnea	ctrl &= ~E1000_CTRL_FD;
1423a551c94aSIdo Barnea	if (phy_data & M88E1000_PSSR_DPLX)
1424a551c94aSIdo Barnea		ctrl |= E1000_CTRL_FD;
1425a551c94aSIdo Barnea
1426a551c94aSIdo Barnea	hw->mac.ops.config_collision_dist(hw);
1427a551c94aSIdo Barnea
1428a551c94aSIdo Barnea	/*
1429a551c94aSIdo Barnea	 * Set up speed in the Device Control register depending on
1430a551c94aSIdo Barnea	 * negotiated values.
1431a551c94aSIdo Barnea	 */
1432a551c94aSIdo Barnea	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1433a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SPD_1000;
1434a551c94aSIdo Barnea	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1435a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SPD_100;
1436a551c94aSIdo Barnea
1437a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1438a551c94aSIdo Barnea
1439a551c94aSIdo Barneaout:
1440a551c94aSIdo Barnea	return ret_val;
1441a551c94aSIdo Barnea}
1442a551c94aSIdo Barnea
1443a551c94aSIdo Barnea/**
1444a551c94aSIdo Barnea *  e1000_write_vfta_82543 - Write value to VLAN filter table
1445a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1446a551c94aSIdo Barnea *  @offset: the 32-bit offset in which to write the value to.
1447a551c94aSIdo Barnea *  @value: the 32-bit value to write at location offset.
1448a551c94aSIdo Barnea *
1449a551c94aSIdo Barnea *  This writes a 32-bit value to a 32-bit offset in the VLAN filter
1450a551c94aSIdo Barnea *  table.
1451a551c94aSIdo Barnea **/
1452a551c94aSIdo BarneaSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1453a551c94aSIdo Barnea{
1454a551c94aSIdo Barnea	u32 temp;
1455a551c94aSIdo Barnea
1456a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_vfta_82543");
1457a551c94aSIdo Barnea
1458a551c94aSIdo Barnea	if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1459a551c94aSIdo Barnea		temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1460a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1461a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
1462a551c94aSIdo Barnea		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1463a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
1464a551c94aSIdo Barnea	} else {
1465a551c94aSIdo Barnea		e1000_write_vfta_generic(hw, offset, value);
1466a551c94aSIdo Barnea	}
1467a551c94aSIdo Barnea}
1468a551c94aSIdo Barnea
1469a551c94aSIdo Barnea/**
1470a551c94aSIdo Barnea *  e1000_led_on_82543 - Turn on SW controllable LED
1471a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1472a551c94aSIdo Barnea *
1473a551c94aSIdo Barnea *  Turns the SW defined LED on.
1474a551c94aSIdo Barnea **/
1475a551c94aSIdo BarneaSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw)
1476a551c94aSIdo Barnea{
1477a551c94aSIdo Barnea	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1478a551c94aSIdo Barnea
1479a551c94aSIdo Barnea	DEBUGFUNC("e1000_led_on_82543");
1480a551c94aSIdo Barnea
1481a551c94aSIdo Barnea	if (hw->mac.type == e1000_82544 &&
1482a551c94aSIdo Barnea	    hw->phy.media_type == e1000_media_type_copper) {
1483a551c94aSIdo Barnea		/* Clear SW-definable Pin 0 to turn on the LED */
1484a551c94aSIdo Barnea		ctrl &= ~E1000_CTRL_SWDPIN0;
1485a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIO0;
1486a551c94aSIdo Barnea	} else {
1487a551c94aSIdo Barnea		/* Fiber 82544 and all 82543 use this method */
1488a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIN0;
1489a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIO0;
1490a551c94aSIdo Barnea	}
1491a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1492a551c94aSIdo Barnea
1493a551c94aSIdo Barnea	return E1000_SUCCESS;
1494a551c94aSIdo Barnea}
1495a551c94aSIdo Barnea
1496a551c94aSIdo Barnea/**
1497a551c94aSIdo Barnea *  e1000_led_off_82543 - Turn off SW controllable LED
1498a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1499a551c94aSIdo Barnea *
1500a551c94aSIdo Barnea *  Turns the SW defined LED off.
1501a551c94aSIdo Barnea **/
1502a551c94aSIdo BarneaSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw)
1503a551c94aSIdo Barnea{
1504a551c94aSIdo Barnea	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1505a551c94aSIdo Barnea
1506a551c94aSIdo Barnea	DEBUGFUNC("e1000_led_off_82543");
1507a551c94aSIdo Barnea
1508a551c94aSIdo Barnea	if (hw->mac.type == e1000_82544 &&
1509a551c94aSIdo Barnea	    hw->phy.media_type == e1000_media_type_copper) {
1510a551c94aSIdo Barnea		/* Set SW-definable Pin 0 to turn off the LED */
1511a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIN0;
1512a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIO0;
1513a551c94aSIdo Barnea	} else {
1514a551c94aSIdo Barnea		ctrl &= ~E1000_CTRL_SWDPIN0;
1515a551c94aSIdo Barnea		ctrl |= E1000_CTRL_SWDPIO0;
1516a551c94aSIdo Barnea	}
1517a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1518a551c94aSIdo Barnea
1519a551c94aSIdo Barnea	return E1000_SUCCESS;
1520a551c94aSIdo Barnea}
1521a551c94aSIdo Barnea
1522a551c94aSIdo Barnea/**
1523a551c94aSIdo Barnea *  e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1524a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1525a551c94aSIdo Barnea *
1526a551c94aSIdo Barnea *  Clears the hardware counters by reading the counter registers.
1527a5