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9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
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32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_82571_H_
35a551c94aSIdo Barnea#define _E1000_82571_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barnea#define ID_LED_RESERVED_F746	0xF746
38a551c94aSIdo Barnea#define ID_LED_DEFAULT_82573	((ID_LED_DEF1_DEF2 << 12) | \
39a551c94aSIdo Barnea				 (ID_LED_OFF1_ON2  <<  8) | \
40a551c94aSIdo Barnea				 (ID_LED_DEF1_DEF2 <<  4) | \
41a551c94aSIdo Barnea				 (ID_LED_DEF1_DEF2))
42a551c94aSIdo Barnea
43a551c94aSIdo Barnea#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX	0x08000000
44a551c94aSIdo Barnea#define AN_RETRY_COUNT		5 /* Autoneg Retry Count value */
45a551c94aSIdo Barnea
46a551c94aSIdo Barnea/* Intr Throttling - RW */
47a551c94aSIdo Barnea#define E1000_EITR_82574(_n)	(0x000E8 + (0x4 * (_n)))
48a551c94aSIdo Barnea
49a551c94aSIdo Barnea#define E1000_EIAC_82574	0x000DC /* Ext. Interrupt Auto Clear - RW */
50a551c94aSIdo Barnea#define E1000_EIAC_MASK_82574	0x01F00000
51a551c94aSIdo Barnea
52a551c94aSIdo Barnea#define E1000_IVAR_INT_ALLOC_VALID	0x8
53a551c94aSIdo Barnea
54a551c94aSIdo Barnea/* Manageability Operation Mode mask */
55a551c94aSIdo Barnea#define E1000_NVM_INIT_CTRL2_MNGM	0x6000
56a551c94aSIdo Barnea
57a551c94aSIdo Barnea#define E1000_BASE1000T_STATUS		10
58a551c94aSIdo Barnea#define E1000_IDLE_ERROR_COUNT_MASK	0xFF
59a551c94aSIdo Barnea#define E1000_RECEIVE_ERROR_COUNTER	21
60a551c94aSIdo Barnea#define E1000_RECEIVE_ERROR_MAX		0xFFFF
61a551c94aSIdo Barneabool e1000_check_phy_82574(struct e1000_hw *hw);
62a551c94aSIdo Barneabool e1000_get_laa_state_82571(struct e1000_hw *hw);
63a551c94aSIdo Barneavoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);
64a551c94aSIdo Barnea
65a551c94aSIdo Barnea#endif
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