1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
42 */
43
44#include "e1000_api.h"
45#include "e1000_i210.h"
46
47STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
48STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
49STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
50STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
52STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
54STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
55STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
56STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57					 u16 *duplex);
58STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60					   u16 *data);
61STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
62STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
63STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
64				     u32 offset, u16 *data);
65STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
66				      u32 offset, u16 data);
67STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
68					  bool active);
69STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
70					  bool active);
71STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
72					  bool active);
73STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
74STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
76STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79					    u32 offset, u16 data);
80STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83						 u16 *speed, u16 *duplex);
84STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
85STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
88STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
89STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
98						 u16 offset);
99STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
100						   u16 offset);
101STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
104
105STATIC void e1000_i2c_start(struct e1000_hw *hw);
106STATIC void e1000_i2c_stop(struct e1000_hw *hw);
107STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
108STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
109STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
110STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
111STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
112STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
113STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
115STATIC bool e1000_get_i2c_data(u32 *i2cctl);
116
117STATIC const u16 e1000_82580_rxpbs_table[] = {
118	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
119#define E1000_82580_RXPBS_TABLE_SIZE \
120	(sizeof(e1000_82580_rxpbs_table) / \
121	 sizeof(e1000_82580_rxpbs_table[0]))
122
123
124/**
125 *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
126 *  @hw: pointer to the HW structure
127 *
128 *  Called to determine if the I2C pins are being used for I2C or as an
129 *  external MDIO interface since the two options are mutually exclusive.
130 **/
131STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
132{
133	u32 reg = 0;
134	bool ext_mdio = false;
135
136	DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
137
138	switch (hw->mac.type) {
139	case e1000_82575:
140	case e1000_82576:
141		reg = E1000_READ_REG(hw, E1000_MDIC);
142		ext_mdio = !!(reg & E1000_MDIC_DEST);
143		break;
144	case e1000_82580:
145	case e1000_i350:
146	case e1000_i354:
147	case e1000_i210:
148	case e1000_i211:
149		reg = E1000_READ_REG(hw, E1000_MDICNFG);
150		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
151		break;
152	default:
153		break;
154	}
155	return ext_mdio;
156}
157
158/**
159 *  e1000_init_phy_params_82575 - Init PHY func ptrs.
160 *  @hw: pointer to the HW structure
161 **/
162STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
163{
164	struct e1000_phy_info *phy = &hw->phy;
165	s32 ret_val = E1000_SUCCESS;
166	u32 ctrl_ext;
167
168	DEBUGFUNC("e1000_init_phy_params_82575");
169
170	phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171	phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
172
173	if (hw->phy.media_type != e1000_media_type_copper) {
174		phy->type = e1000_phy_none;
175		goto out;
176	}
177
178	phy->ops.power_up   = e1000_power_up_phy_copper;
179	phy->ops.power_down = e1000_power_down_phy_copper_82575;
180
181	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
182	phy->reset_delay_us	= 100;
183
184	phy->ops.acquire	= e1000_acquire_phy_82575;
185	phy->ops.check_reset_block = e1000_check_reset_block_generic;
186	phy->ops.commit		= e1000_phy_sw_reset_generic;
187	phy->ops.get_cfg_done	= e1000_get_cfg_done_82575;
188	phy->ops.release	= e1000_release_phy_82575;
189
190	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
191
192	if (e1000_sgmii_active_82575(hw)) {
193		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194		ctrl_ext |= E1000_CTRL_I2C_ENA;
195	} else {
196		phy->ops.reset = e1000_phy_hw_reset_generic;
197		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
198	}
199
200	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201	e1000_reset_mdicnfg_82580(hw);
202
203	if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
206	} else {
207		switch (hw->mac.type) {
208		case e1000_82580:
209		case e1000_i350:
210		case e1000_i354:
211			phy->ops.read_reg = e1000_read_phy_reg_82580;
212			phy->ops.write_reg = e1000_write_phy_reg_82580;
213			break;
214		case e1000_i210:
215		case e1000_i211:
216			phy->ops.read_reg = e1000_read_phy_reg_gs40g;
217			phy->ops.write_reg = e1000_write_phy_reg_gs40g;
218			break;
219		default:
220			phy->ops.read_reg = e1000_read_phy_reg_igp;
221			phy->ops.write_reg = e1000_write_phy_reg_igp;
222		}
223	}
224
225	/* Set phy->phy_addr and phy->id. */
226	ret_val = e1000_get_phy_id_82575(hw);
227
228	/* Verify phy id and set remaining function pointers */
229	switch (phy->id) {
230	case M88E1543_E_PHY_ID:
231	case M88E1512_E_PHY_ID:
232	case I347AT4_E_PHY_ID:
233	case M88E1112_E_PHY_ID:
234	case M88E1340M_E_PHY_ID:
235	case M88E1111_I_PHY_ID:
236		phy->type		= e1000_phy_m88;
237		phy->ops.check_polarity	= e1000_check_polarity_m88;
238		phy->ops.get_info	= e1000_get_phy_info_m88;
239		if (phy->id == I347AT4_E_PHY_ID ||
240		    phy->id == M88E1112_E_PHY_ID ||
241		    phy->id == M88E1340M_E_PHY_ID)
242			phy->ops.get_cable_length =
243					 e1000_get_cable_length_m88_gen2;
244		else if (phy->id == M88E1543_E_PHY_ID ||
245			 phy->id == M88E1512_E_PHY_ID)
246			phy->ops.get_cable_length =
247					 e1000_get_cable_length_m88_gen2;
248		else
249			phy->ops.get_cable_length = e1000_get_cable_length_m88;
250		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
251		/* Check if this PHY is confgured for media swap. */
252		if (phy->id == M88E1112_E_PHY_ID) {
253			u16 data;
254
255			ret_val = phy->ops.write_reg(hw,
256						     E1000_M88E1112_PAGE_ADDR,
257						     2);
258			if (ret_val)
259				goto out;
260
261			ret_val = phy->ops.read_reg(hw,
262						    E1000_M88E1112_MAC_CTRL_1,
263						    &data);
264			if (ret_val)
265				goto out;
266
267			data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
268			       E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
269			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
270			    data == E1000_M88E1112_AUTO_COPPER_BASEX)
271				hw->mac.ops.check_for_link =
272						e1000_check_for_link_media_swap;
273		}
274		if (phy->id == M88E1512_E_PHY_ID) {
275			ret_val = e1000_initialize_M88E1512_phy(hw);
276			if (ret_val)
277				goto out;
278		}
279		if (phy->id == M88E1543_E_PHY_ID) {
280			ret_val = e1000_initialize_M88E1543_phy(hw);
281			if (ret_val)
282				goto out;
283		}
284		break;
285	case IGP03E1000_E_PHY_ID:
286	case IGP04E1000_E_PHY_ID:
287		phy->type = e1000_phy_igp_3;
288		phy->ops.check_polarity = e1000_check_polarity_igp;
289		phy->ops.get_info = e1000_get_phy_info_igp;
290		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
291		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
292		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
293		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
294		break;
295	case I82580_I_PHY_ID:
296	case I350_I_PHY_ID:
297		phy->type = e1000_phy_82580;
298		phy->ops.check_polarity = e1000_check_polarity_82577;
299		phy->ops.force_speed_duplex =
300					 e1000_phy_force_speed_duplex_82577;
301		phy->ops.get_cable_length = e1000_get_cable_length_82577;
302		phy->ops.get_info = e1000_get_phy_info_82577;
303		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
305		break;
306	case I210_I_PHY_ID:
307		phy->type		= e1000_phy_i210;
308		phy->ops.check_polarity	= e1000_check_polarity_m88;
309		phy->ops.get_info	= e1000_get_phy_info_m88;
310		phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
311		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
312		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
313		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
314		break;
315	default:
316		ret_val = -E1000_ERR_PHY;
317		goto out;
318	}
319
320out:
321	return ret_val;
322}
323
324/**
325 *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
326 *  @hw: pointer to the HW structure
327 **/
328s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
329{
330	struct e1000_nvm_info *nvm = &hw->nvm;
331	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
332	u16 size;
333
334	DEBUGFUNC("e1000_init_nvm_params_82575");
335
336	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
337		     E1000_EECD_SIZE_EX_SHIFT);
338	/*
339	 * Added to a constant, "size" becomes the left-shift value
340	 * for setting word_size.
341	 */
342	size += NVM_WORD_SIZE_BASE_SHIFT;
343
344	/* Just in case size is out of range, cap it to the largest
345	 * EEPROM size supported
346	 */
347	if (size > 15)
348		size = 15;
349
350	nvm->word_size = 1 << size;
351	if (hw->mac.type < e1000_i210) {
352		nvm->opcode_bits = 8;
353		nvm->delay_usec = 1;
354
355		switch (nvm->override) {
356		case e1000_nvm_override_spi_large:
357			nvm->page_size = 32;
358			nvm->address_bits = 16;
359			break;
360		case e1000_nvm_override_spi_small:
361			nvm->page_size = 8;
362			nvm->address_bits = 8;
363			break;
364		default:
365			nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
366			nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
367					    16 : 8;
368			break;
369		}
370		if (nvm->word_size == (1 << 15))
371			nvm->page_size = 128;
372
373		nvm->type = e1000_nvm_eeprom_spi;
374	} else {
375		nvm->type = e1000_nvm_flash_hw;
376	}
377
378	/* Function Pointers */
379	nvm->ops.acquire = e1000_acquire_nvm_82575;
380	nvm->ops.release = e1000_release_nvm_82575;
381	if (nvm->word_size < (1 << 15))
382		nvm->ops.read = e1000_read_nvm_eerd;
383	else
384		nvm->ops.read = e1000_read_nvm_spi;
385
386	nvm->ops.write = e1000_write_nvm_spi;
387	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
388	nvm->ops.update = e1000_update_nvm_checksum_generic;
389	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
390
391	/* override generic family function pointers for specific descendants */
392	switch (hw->mac.type) {
393	case e1000_82580:
394		nvm->ops.validate = e1000_validate_nvm_checksum_82580;
395		nvm->ops.update = e1000_update_nvm_checksum_82580;
396		break;
397	case e1000_i350:
398	case e1000_i354:
399		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
400		nvm->ops.update = e1000_update_nvm_checksum_i350;
401		break;
402	default:
403		break;
404	}
405
406	return E1000_SUCCESS;
407}
408
409/**
410 *  e1000_init_mac_params_82575 - Init MAC func ptrs.
411 *  @hw: pointer to the HW structure
412 **/
413STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
414{
415	struct e1000_mac_info *mac = &hw->mac;
416	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
417
418	DEBUGFUNC("e1000_init_mac_params_82575");
419
420	/* Derives media type */
421	e1000_get_media_type_82575(hw);
422	/* Set mta register count */
423	mac->mta_reg_count = 128;
424	/* Set uta register count */
425	mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
426	/* Set rar entry count */
427	mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
428	if (mac->type == e1000_82576)
429		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
430	if (mac->type == e1000_82580)
431		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
432	if (mac->type == e1000_i350 || mac->type == e1000_i354)
433		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
434
435	/* Enable EEE default settings for EEE supported devices */
436	if (mac->type >= e1000_i350)
437		dev_spec->eee_disable = false;
438
439	/* Allow a single clear of the SW semaphore on I210 and newer */
440	if (mac->type >= e1000_i210)
441		dev_spec->clear_semaphore_once = true;
442
443	/* Set if part includes ASF firmware */
444	mac->asf_firmware_present = true;
445	/* FWSM register */
446	mac->has_fwsm = true;
447	/* ARC supported; valid only if manageability features are enabled. */
448	mac->arc_subsystem_valid =
449		!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
450
451	/* Function pointers */
452
453	/* bus type/speed/width */
454	mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
455	/* reset */
456	if (mac->type >= e1000_82580)
457		mac->ops.reset_hw = e1000_reset_hw_82580;
458	else
459	mac->ops.reset_hw = e1000_reset_hw_82575;
460	/* hw initialization */
461	if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
462		mac->ops.init_hw = e1000_init_hw_i210;
463	else
464	mac->ops.init_hw = e1000_init_hw_82575;
465	/* link setup */
466	mac->ops.setup_link = e1000_setup_link_generic;
467	/* physical interface link setup */
468	mac->ops.setup_physical_interface =
469		(hw->phy.media_type == e1000_media_type_copper)
470		? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
471	/* physical interface shutdown */
472	mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
473	/* physical interface power up */
474	mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
475	/* check for link */
476	mac->ops.check_for_link = e1000_check_for_link_82575;
477	/* read mac address */
478	mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
479	/* configure collision distance */
480	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
481	/* multicast address update */
482	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
483	if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
484		/* writing VFTA */
485		mac->ops.write_vfta = e1000_write_vfta_i350;
486		/* clearing VFTA */
487		mac->ops.clear_vfta = e1000_clear_vfta_i350;
488	} else {
489		/* writing VFTA */
490		mac->ops.write_vfta = e1000_write_vfta_generic;
491		/* clearing VFTA */
492		mac->ops.clear_vfta = e1000_clear_vfta_generic;
493	}
494	if (hw->mac.type >= e1000_82580)
495		mac->ops.validate_mdi_setting =
496				e1000_validate_mdi_setting_crossover_generic;
497	/* ID LED init */
498	mac->ops.id_led_init = e1000_id_led_init_generic;
499	/* blink LED */
500	mac->ops.blink_led = e1000_blink_led_generic;
501	/* setup LED */
502	mac->ops.setup_led = e1000_setup_led_generic;
503	/* cleanup LED */
504	mac->ops.cleanup_led = e1000_cleanup_led_generic;
505	/* turn on/off LED */
506	mac->ops.led_on = e1000_led_on_generic;
507	mac->ops.led_off = e1000_led_off_generic;
508	/* clear hardware counters */
509	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
510	/* link info */
511	mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
512	/* acquire SW_FW sync */
513	mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
514	mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
515	if (mac->type >= e1000_i210) {
516		mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
517		mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
518	}
519
520	/* set lan id for port to determine which phy lock to use */
521	hw->mac.ops.set_lan_id(hw);
522
523	return E1000_SUCCESS;
524}
525
526/**
527 *  e1000_init_function_pointers_82575 - Init func ptrs.
528 *  @hw: pointer to the HW structure
529 *
530 *  Called to initialize all function pointers and parameters.
531 **/
532void e1000_init_function_pointers_82575(struct e1000_hw *hw)
533{
534	DEBUGFUNC("e1000_init_function_pointers_82575");
535
536	hw->mac.ops.init_params = e1000_init_mac_params_82575;
537	hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
538	hw->phy.ops.init_params = e1000_init_phy_params_82575;
539	hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
540}
541
542/**
543 *  e1000_acquire_phy_82575 - Acquire rights to access PHY
544 *  @hw: pointer to the HW structure
545 *
546 *  Acquire access rights to the correct PHY.
547 **/
548STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
549{
550	u16 mask = E1000_SWFW_PHY0_SM;
551
552	DEBUGFUNC("e1000_acquire_phy_82575");
553
554	if (hw->bus.func == E1000_FUNC_1)
555		mask = E1000_SWFW_PHY1_SM;
556	else if (hw->bus.func == E1000_FUNC_2)
557		mask = E1000_SWFW_PHY2_SM;
558	else if (hw->bus.func == E1000_FUNC_3)
559		mask = E1000_SWFW_PHY3_SM;
560
561	return hw->mac.ops.acquire_swfw_sync(hw, mask);
562}
563
564/**
565 *  e1000_release_phy_82575 - Release rights to access PHY
566 *  @hw: pointer to the HW structure
567 *
568 *  A wrapper to release access rights to the correct PHY.
569 **/
570STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
571{
572	u16 mask = E1000_SWFW_PHY0_SM;
573
574	DEBUGFUNC("e1000_release_phy_82575");
575
576	if (hw->bus.func == E1000_FUNC_1)
577		mask = E1000_SWFW_PHY1_SM;
578	else if (hw->bus.func == E1000_FUNC_2)
579		mask = E1000_SWFW_PHY2_SM;
580	else if (hw->bus.func == E1000_FUNC_3)
581		mask = E1000_SWFW_PHY3_SM;
582
583	hw->mac.ops.release_swfw_sync(hw, mask);
584}
585
586/**
587 *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
588 *  @hw: pointer to the HW structure
589 *  @offset: register offset to be read
590 *  @data: pointer to the read data
591 *
592 *  Reads the PHY register at offset using the serial gigabit media independent
593 *  interface and stores the retrieved information in data.
594 **/
595STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
596					  u16 *data)
597{
598	s32 ret_val = -E1000_ERR_PARAM;
599
600	DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
601
602	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
603		DEBUGOUT1("PHY Address %u is out of range\n", offset);
604		goto out;
605	}
606
607	ret_val = hw->phy.ops.acquire(hw);
608	if (ret_val)
609		goto out;
610
611	ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
612
613	hw->phy.ops.release(hw);
614
615out:
616	return ret_val;
617}
618
619/**
620 *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
621 *  @hw: pointer to the HW structure
622 *  @offset: register offset to write to
623 *  @data: data to write at register offset
624 *
625 *  Writes the data to PHY register at the offset using the serial gigabit
626 *  media independent interface.
627 **/
628STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
629					   u16 data)
630{
631	s32 ret_val = -E1000_ERR_PARAM;
632
633	DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
634
635	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
636		DEBUGOUT1("PHY Address %d is out of range\n", offset);
637		goto out;
638	}
639
640	ret_val = hw->phy.ops.acquire(hw);
641	if (ret_val)
642		goto out;
643
644	ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
645
646	hw->phy.ops.release(hw);
647
648out:
649	return ret_val;
650}
651
652/**
653 *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
654 *  @hw: pointer to the HW structure
655 *
656 *  Retrieves the PHY address and ID for both PHY's which do and do not use
657 *  sgmi interface.
658 **/
659STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
660{
661	struct e1000_phy_info *phy = &hw->phy;
662	s32  ret_val = E1000_SUCCESS;
663	u16 phy_id;
664	u32 ctrl_ext;
665	u32 mdic;
666
667	DEBUGFUNC("e1000_get_phy_id_82575");
668
669	/* some i354 devices need an extra read for phy id */
670	if (hw->mac.type == e1000_i354)
671		e1000_get_phy_id(hw);
672
673	/*
674	 * For SGMII PHYs, we try the list of possible addresses until
675	 * we find one that works.  For non-SGMII PHYs
676	 * (e.g. integrated copper PHYs), an address of 1 should
677	 * work.  The result of this function should mean phy->phy_addr
678	 * and phy->id are set correctly.
679	 */
680	if (!e1000_sgmii_active_82575(hw)) {
681		phy->addr = 1;
682		ret_val = e1000_get_phy_id(hw);
683		goto out;
684	}
685
686	if (e1000_sgmii_uses_mdio_82575(hw)) {
687		switch (hw->mac.type) {
688		case e1000_82575:
689		case e1000_82576:
690			mdic = E1000_READ_REG(hw, E1000_MDIC);
691			mdic &= E1000_MDIC_PHY_MASK;
692			phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
693			break;
694		case e1000_82580:
695		case e1000_i350:
696		case e1000_i354:
697		case e1000_i210:
698		case e1000_i211:
699			mdic = E1000_READ_REG(hw, E1000_MDICNFG);
700			mdic &= E1000_MDICNFG_PHY_MASK;
701			phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
702			break;
703		default:
704			ret_val = -E1000_ERR_PHY;
705			goto out;
706			break;
707		}
708		ret_val = e1000_get_phy_id(hw);
709		goto out;
710	}
711
712	/* Power on sgmii phy if it is disabled */
713	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
714	E1000_WRITE_REG(hw, E1000_CTRL_EXT,
715			ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
716	E1000_WRITE_FLUSH(hw);
717	msec_delay(300);
718
719	/*
720	 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
721	 * Therefore, we need to test 1-7
722	 */
723	for (phy->addr = 1; phy->addr < 8; phy->addr++) {
724		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
725		if (ret_val == E1000_SUCCESS) {
726			DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
727				  phy_id, phy->addr);
728			/*
729			 * At the time of this writing, The M88 part is
730			 * the only supported SGMII PHY product.
731			 */
732			if (phy_id == M88_VENDOR)
733				break;
734		} else {
735			DEBUGOUT1("PHY address %u was unreadable\n",
736				  phy->addr);
737		}
738	}
739
740	/* A valid PHY type couldn't be found. */
741	if (phy->addr == 8) {
742		phy->addr = 0;
743		ret_val = -E1000_ERR_PHY;
744	} else {
745		ret_val = e1000_get_phy_id(hw);
746	}
747
748	/* restore previous sfp cage power state */
749	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
750
751out:
752	return ret_val;
753}
754
755/**
756 *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
757 *  @hw: pointer to the HW structure
758 *
759 *  Resets the PHY using the serial gigabit media independent interface.
760 **/
761STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
762{
763	s32 ret_val = E1000_SUCCESS;
764	struct e1000_phy_info *phy = &hw->phy;
765
766	DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
767
768	/*
769	 * This isn't a true "hard" reset, but is the only reset
770	 * available to us at this time.
771	 */
772
773	DEBUGOUT("Soft resetting SGMII attached PHY...\n");
774
775	if (!(hw->phy.ops.write_reg))
776		goto out;
777
778	/*
779	 * SFP documentation requires the following to configure the SPF module
780	 * to work on SGMII.  No further documentation is given.
781	 */
782	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
783	if (ret_val)
784		goto out;
785
786	ret_val = hw->phy.ops.commit(hw);
787	if (ret_val)
788		goto out;
789
790	if (phy->id == M88E1512_E_PHY_ID)
791		ret_val = e1000_initialize_M88E1512_phy(hw);
792out:
793	return ret_val;
794}
795
796/**
797 *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
798 *  @hw: pointer to the HW structure
799 *  @active: true to enable LPLU, false to disable
800 *
801 *  Sets the LPLU D0 state according to the active flag.  When
802 *  activating LPLU this function also disables smart speed
803 *  and vice versa.  LPLU will not be activated unless the
804 *  device autonegotiation advertisement meets standards of
805 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
806 *  This is a function pointer entry point only called by
807 *  PHY setup routines.
808 **/
809STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
810{
811	struct e1000_phy_info *phy = &hw->phy;
812	s32 ret_val = E1000_SUCCESS;
813	u16 data;
814
815	DEBUGFUNC("e1000_set_d0_lplu_state_82575");
816
817	if (!(hw->phy.ops.read_reg))
818		goto out;
819
820	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
821	if (ret_val)
822		goto out;
823
824	if (active) {
825		data |= IGP02E1000_PM_D0_LPLU;
826		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827					     data);
828		if (ret_val)
829			goto out;
830
831		/* When LPLU is enabled, we should disable SmartSpeed */
832		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
833					    &data);
834		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
835		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836					     data);
837		if (ret_val)
838			goto out;
839	} else {
840		data &= ~IGP02E1000_PM_D0_LPLU;
841		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
842					     data);
843		/*
844		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
845		 * during Dx states where the power conservation is most
846		 * important.  During driver activity we should enable
847		 * SmartSpeed, so performance is maintained.
848		 */
849		if (phy->smart_speed == e1000_smart_speed_on) {
850			ret_val = phy->ops.read_reg(hw,
851						    IGP01E1000_PHY_PORT_CONFIG,
852						    &data);
853			if (ret_val)
854				goto out;
855
856			data |= IGP01E1000_PSCFR_SMART_SPEED;
857			ret_val = phy->ops.write_reg(hw,
858						     IGP01E1000_PHY_PORT_CONFIG,
859						     data);
860			if (ret_val)
861				goto out;
862		} else if (phy->smart_speed == e1000_smart_speed_off) {
863			ret_val = phy->ops.read_reg(hw,
864						    IGP01E1000_PHY_PORT_CONFIG,
865						    &data);
866			if (ret_val)
867				goto out;
868
869			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
870			ret_val = phy->ops.write_reg(hw,
871						     IGP01E1000_PHY_PORT_CONFIG,
872						     data);
873			if (ret_val)
874				goto out;
875		}
876	}
877
878out:
879	return ret_val;
880}
881
882/**
883 *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
884 *  @hw: pointer to the HW structure
885 *  @active: true to enable LPLU, false to disable
886 *
887 *  Sets the LPLU D0 state according to the active flag.  When
888 *  activating LPLU this function also disables smart speed
889 *  and vice versa.  LPLU will not be activated unless the
890 *  device autonegotiation advertisement meets standards of
891 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
892 *  This is a function pointer entry point only called by
893 *  PHY setup routines.
894 **/
895STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
896{
897	struct e1000_phy_info *phy = &hw->phy;
898	u32 data;
899
900	DEBUGFUNC("e1000_set_d0_lplu_state_82580");
901
902	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
903
904	if (active) {
905		data |= E1000_82580_PM_D0_LPLU;
906
907		/* When LPLU is enabled, we should disable SmartSpeed */
908		data &= ~E1000_82580_PM_SPD;
909	} else {
910		data &= ~E1000_82580_PM_D0_LPLU;
911
912		/*
913		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
914		 * during Dx states where the power conservation is most
915		 * important.  During driver activity we should enable
916		 * SmartSpeed, so performance is maintained.
917		 */
918		if (phy->smart_speed == e1000_smart_speed_on)
919			data |= E1000_82580_PM_SPD;
920		else if (phy->smart_speed == e1000_smart_speed_off)
921			data &= ~E1000_82580_PM_SPD;
922	}
923
924	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
925	return E1000_SUCCESS;
926}
927
928/**
929 *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
930 *  @hw: pointer to the HW structure
931 *  @active: boolean used to enable/disable lplu
932 *
933 *  Success returns 0, Failure returns 1
934 *
935 *  The low power link up (lplu) state is set to the power management level D3
936 *  and SmartSpeed is disabled when active is true, else clear lplu for D3
937 *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
938 *  is used during Dx states where the power conservation is most important.
939 *  During driver activity, SmartSpeed should be enabled so performance is
940 *  maintained.
941 **/
942s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
943{
944	struct e1000_phy_info *phy = &hw->phy;
945	u32 data;
946
947	DEBUGFUNC("e1000_set_d3_lplu_state_82580");
948
949	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
950
951	if (!active) {
952		data &= ~E1000_82580_PM_D3_LPLU;
953		/*
954		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
955		 * during Dx states where the power conservation is most
956		 * important.  During driver activity we should enable
957		 * SmartSpeed, so performance is maintained.
958		 */
959		if (phy->smart_speed == e1000_smart_speed_on)
960			data |= E1000_82580_PM_SPD;
961		else if (phy->smart_speed == e1000_smart_speed_off)
962			data &= ~E1000_82580_PM_SPD;
963	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
964		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
965		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
966		data |= E1000_82580_PM_D3_LPLU;
967		/* When LPLU is enabled, we should disable SmartSpeed */
968		data &= ~E1000_82580_PM_SPD;
969	}
970
971	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
972	return E1000_SUCCESS;
973}
974
975/**
976 *  e1000_acquire_nvm_82575 - Request for access to EEPROM
977 *  @hw: pointer to the HW structure
978 *
979 *  Acquire the necessary semaphores for exclusive access to the EEPROM.
980 *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
981 *  Return successful if access grant bit set, else clear the request for
982 *  EEPROM access and return -E1000_ERR_NVM (-1).
983 **/
984STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
985{
986	s32 ret_val = E1000_SUCCESS;
987
988	DEBUGFUNC("e1000_acquire_nvm_82575");
989
990	ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
991	if (ret_val)
992		goto out;
993
994	/*
995	 * Check if there is some access
996	 * error this access may hook on
997	 */
998	if (hw->mac.type == e1000_i350) {
999		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1000		if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
1001		    E1000_EECD_TIMEOUT)) {
1002			/* Clear all access error flags */
1003			E1000_WRITE_REG(hw, E1000_EECD, eecd |
1004					E1000_EECD_ERROR_CLR);
1005			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1006		}
1007	}
1008
1009	if (hw->mac.type == e1000_82580) {
1010		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1011		if (eecd & E1000_EECD_BLOCKED) {
1012			/* Clear access error flag */
1013			E1000_WRITE_REG(hw, E1000_EECD, eecd |
1014					E1000_EECD_BLOCKED);
1015			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1016		}
1017	}
1018
1019	ret_val = e1000_acquire_nvm_generic(hw);
1020	if (ret_val)
1021		e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1022
1023out:
1024	return ret_val;
1025}
1026
1027/**
1028 *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1029 *  @hw: pointer to the HW structure
1030 *
1031 *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1032 *  then release the semaphores acquired.
1033 **/
1034STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1035{
1036	DEBUGFUNC("e1000_release_nvm_82575");
1037
1038	e1000_release_nvm_generic(hw);
1039
1040	e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1041}
1042
1043/**
1044 *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1045 *  @hw: pointer to the HW structure
1046 *  @mask: specifies which semaphore to acquire
1047 *
1048 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1049 *  will also specify which port we're acquiring the lock for.
1050 **/
1051STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1052{
1053	u32 swfw_sync;
1054	u32 swmask = mask;
1055	u32 fwmask = mask << 16;
1056	s32 ret_val = E1000_SUCCESS;
1057	s32 i = 0, timeout = 200;
1058
1059	DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1060
1061	while (i < timeout) {
1062		if (e1000_get_hw_semaphore_generic(hw)) {
1063			ret_val = -E1000_ERR_SWFW_SYNC;
1064			goto out;
1065		}
1066
1067		swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1068		if (!(swfw_sync & (fwmask | swmask)))
1069			break;
1070
1071		/*
1072		 * Firmware currently using resource (fwmask)
1073		 * or other software thread using resource (swmask)
1074		 */
1075		e1000_put_hw_semaphore_generic(hw);
1076		msec_delay_irq(5);
1077		i++;
1078	}
1079
1080	if (i == timeout) {
1081		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1082		ret_val = -E1000_ERR_SWFW_SYNC;
1083		goto out;
1084	}
1085
1086	swfw_sync |= swmask;
1087	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1088
1089	e1000_put_hw_semaphore_generic(hw);
1090
1091out:
1092	return ret_val;
1093}
1094
1095/**
1096 *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1097 *  @hw: pointer to the HW structure
1098 *  @mask: specifies which semaphore to acquire
1099 *
1100 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1101 *  will also specify which port we're releasing the lock for.
1102 **/
1103STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1104{
1105	u32 swfw_sync;
1106
1107	DEBUGFUNC("e1000_release_swfw_sync_82575");
1108
1109	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1110		; /* Empty */
1111
1112	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1113	swfw_sync &= ~mask;
1114	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1115
1116	e1000_put_hw_semaphore_generic(hw);
1117}
1118
1119/**
1120 *  e1000_get_cfg_done_82575 - Read config done bit
1121 *  @hw: pointer to the HW structure
1122 *
1123 *  Read the management control register for the config done bit for
1124 *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1125 *  to read the config done bit, so an error is *ONLY* logged and returns
1126 *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1127 *  would not be able to be reset or change link.
1128 **/
1129STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1130{
1131	s32 timeout = PHY_CFG_TIMEOUT;
1132	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1133
1134	DEBUGFUNC("e1000_get_cfg_done_82575");
1135
1136	if (hw->bus.func == E1000_FUNC_1)
1137		mask = E1000_NVM_CFG_DONE_PORT_1;
1138	else if (hw->bus.func == E1000_FUNC_2)
1139		mask = E1000_NVM_CFG_DONE_PORT_2;
1140	else if (hw->bus.func == E1000_FUNC_3)
1141		mask = E1000_NVM_CFG_DONE_PORT_3;
1142	while (timeout) {
1143		if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1144			break;
1145		msec_delay(1);
1146		timeout--;
1147	}
1148	if (!timeout)
1149		DEBUGOUT("MNG configuration cycle has not completed.\n");
1150
1151	/* If EEPROM is not marked present, init the PHY manually */
1152	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1153	    (hw->phy.type == e1000_phy_igp_3))
1154		e1000_phy_init_script_igp3(hw);
1155
1156	return E1000_SUCCESS;
1157}
1158
1159/**
1160 *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1161 *  @hw: pointer to the HW structure
1162 *  @speed: stores the current speed
1163 *  @duplex: stores the current duplex
1164 *
1165 *  This is a wrapper function, if using the serial gigabit media independent
1166 *  interface, use PCS to retrieve the link speed and duplex information.
1167 *  Otherwise, use the generic function to get the link speed and duplex info.
1168 **/
1169STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1170					u16 *duplex)
1171{
1172	s32 ret_val;
1173
1174	DEBUGFUNC("e1000_get_link_up_info_82575");
1175
1176	if (hw->phy.media_type != e1000_media_type_copper)
1177		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1178							       duplex);
1179	else
1180		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1181								    duplex);
1182
1183	return ret_val;
1184}
1185
1186/**
1187 *  e1000_check_for_link_82575 - Check for link
1188 *  @hw: pointer to the HW structure
1189 *
1190 *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1191 *  use the generic interface for determining link.
1192 **/
1193STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1194{
1195	s32 ret_val;
1196	u16 speed, duplex;
1197
1198	DEBUGFUNC("e1000_check_for_link_82575");
1199
1200	if (hw->phy.media_type != e1000_media_type_copper) {
1201		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1202							       &duplex);
1203		/*
1204		 * Use this flag to determine if link needs to be checked or
1205		 * not.  If we have link clear the flag so that we do not
1206		 * continue to check for link.
1207		 */
1208		hw->mac.get_link_status = !hw->mac.serdes_has_link;
1209
1210		/*
1211		 * Configure Flow Control now that Auto-Neg has completed.
1212		 * First, we need to restore the desired flow control
1213		 * settings because we may have had to re-autoneg with a
1214		 * different link partner.
1215		 */
1216		ret_val = e1000_config_fc_after_link_up_generic(hw);
1217		if (ret_val)
1218			DEBUGOUT("Error configuring flow control\n");
1219	} else {
1220		ret_val = e1000_check_for_copper_link_generic(hw);
1221	}
1222
1223	return ret_val;
1224}
1225
1226/**
1227 *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1228 *  @hw: pointer to the HW structure
1229 *
1230 *  Poll the M88E1112 interfaces to see which interface achieved link.
1231 */
1232STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1233{
1234	struct e1000_phy_info *phy = &hw->phy;
1235	s32 ret_val;
1236	u16 data;
1237	u8 port = 0;
1238
1239	DEBUGFUNC("e1000_check_for_link_media_swap");
1240
1241	/* Check for copper. */
1242	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1243	if (ret_val)
1244		return ret_val;
1245
1246	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1247	if (ret_val)
1248		return ret_val;
1249
1250	if (data & E1000_M88E1112_STATUS_LINK)
1251		port = E1000_MEDIA_PORT_COPPER;
1252
1253	/* Check for other. */
1254	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1255	if (ret_val)
1256		return ret_val;
1257
1258	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1259	if (ret_val)
1260		return ret_val;
1261
1262	if (data & E1000_M88E1112_STATUS_LINK)
1263		port = E1000_MEDIA_PORT_OTHER;
1264
1265	/* Determine if a swap needs to happen. */
1266	if (port && (hw->dev_spec._82575.media_port != port)) {
1267		hw->dev_spec._82575.media_port = port;
1268		hw->dev_spec._82575.media_changed = true;
1269	}
1270
1271	if (port == E1000_MEDIA_PORT_COPPER) {
1272		/* reset page to 0 */
1273		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1274		if (ret_val)
1275			return ret_val;
1276		e1000_check_for_link_82575(hw);
1277	} else {
1278		e1000_check_for_link_82575(hw);
1279		/* reset page to 0 */
1280		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1281		if (ret_val)
1282			return ret_val;
1283	}
1284
1285	return E1000_SUCCESS;
1286}
1287
1288/**
1289 *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1290 *  @hw: pointer to the HW structure
1291 **/
1292STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1293{
1294	u32 reg;
1295
1296	DEBUGFUNC("e1000_power_up_serdes_link_82575");
1297
1298	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1299	    !e1000_sgmii_active_82575(hw))
1300		return;
1301
1302	/* Enable PCS to turn on link */
1303	reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1304	reg |= E1000_PCS_CFG_PCS_EN;
1305	E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1306
1307	/* Power up the laser */
1308	reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1309	reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1310	E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1311
1312	/* flush the write to verify completion */
1313	E1000_WRITE_FLUSH(hw);
1314	msec_delay(1);
1315}
1316
1317/**
1318 *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1319 *  @hw: pointer to the HW structure
1320 *  @speed: stores the current speed
1321 *  @duplex: stores the current duplex
1322 *
1323 *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1324 *  duplex, then store the values in the pointers provided.
1325 **/
1326STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1327						u16 *speed, u16 *duplex)
1328{
1329	struct e1000_mac_info *mac = &hw->mac;
1330	u32 pcs;
1331	u32 status;
1332
1333	DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1334
1335	/*
1336	 * Read the PCS Status register for link state. For non-copper mode,
1337	 * the status register is not accurate. The PCS status register is
1338	 * used instead.
1339	 */
1340	pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1341
1342	/*
1343	 * The link up bit determines when link is up on autoneg.
1344	 */
1345	if (pcs & E1000_PCS_LSTS_LINK_OK) {
1346		mac->serdes_has_link = true;
1347
1348		/* Detect and store PCS speed */
1349		if (pcs & E1000_PCS_LSTS_SPEED_1000)
1350			*speed = SPEED_1000;
1351		else if (pcs & E1000_PCS_LSTS_SPEED_100)
1352			*speed = SPEED_100;
1353		else
1354			*speed = SPEED_10;
1355
1356		/* Detect and store PCS duplex */
1357		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1358			*duplex = FULL_DUPLEX;
1359		else
1360			*duplex = HALF_DUPLEX;
1361
1362		/* Check if it is an I354 2.5Gb backplane connection. */
1363		if (mac->type == e1000_i354) {
1364			status = E1000_READ_REG(hw, E1000_STATUS);
1365			if ((status & E1000_STATUS_2P5_SKU) &&
1366			    !(status & E1000_STATUS_2P5_SKU_OVER)) {
1367				*speed = SPEED_2500;
1368				*duplex = FULL_DUPLEX;
1369				DEBUGOUT("2500 Mbs, ");
1370				DEBUGOUT("Full Duplex\n");
1371			}
1372		}
1373
1374	} else {
1375		mac->serdes_has_link = false;
1376		*speed = 0;
1377		*duplex = 0;
1378	}
1379
1380	return E1000_SUCCESS;
1381}
1382
1383/**
1384 *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1385 *  @hw: pointer to the HW structure
1386 *
1387 *  In the case of serdes shut down sfp and PCS on driver unload
1388 *  when management pass thru is not enabled.
1389 **/
1390void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1391{
1392	u32 reg;
1393
1394	DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1395
1396	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1397	    !e1000_sgmii_active_82575(hw))
1398		return;
1399
1400	if (!e1000_enable_mng_pass_thru(hw)) {
1401		/* Disable PCS to turn off link */
1402		reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1403		reg &= ~E1000_PCS_CFG_PCS_EN;
1404		E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1405
1406		/* shutdown the laser */
1407		reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1408		reg |= E1000_CTRL_EXT_SDP3_DATA;
1409		E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1410
1411		/* flush the write to verify completion */
1412		E1000_WRITE_FLUSH(hw);
1413		msec_delay(1);
1414	}
1415
1416	return;
1417}
1418
1419/**
1420 *  e1000_reset_hw_82575 - Reset hardware
1421 *  @hw: pointer to the HW structure
1422 *
1423 *  This resets the hardware into a known state.
1424 **/
1425STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1426{
1427	u32 ctrl;
1428	s32 ret_val;
1429
1430	DEBUGFUNC("e1000_reset_hw_82575");
1431
1432	/*
1433	 * Prevent the PCI-E bus from sticking if there is no TLP connection
1434	 * on the last TLP read/write transaction when MAC is reset.
1435	 */
1436	ret_val = e1000_disable_pcie_master_generic(hw);
1437	if (ret_val)
1438		DEBUGOUT("PCI-E Master disable polling has failed.\n");
1439
1440	/* set the completion timeout for interface */
1441	ret_val = e1000_set_pcie_completion_timeout(hw);
1442	if (ret_val)
1443		DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1444
1445	DEBUGOUT("Masking off all interrupts\n");
1446	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1447
1448	E1000_WRITE_REG(hw, E1000_RCTL, 0);
1449	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1450	E1000_WRITE_FLUSH(hw);
1451
1452	msec_delay(10);
1453
1454	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1455
1456	DEBUGOUT("Issuing a global reset to MAC\n");
1457	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1458
1459	ret_val = e1000_get_auto_rd_done_generic(hw);
1460	if (ret_val) {
1461		/*
1462		 * When auto config read does not complete, do not
1463		 * return with an error. This can happen in situations
1464		 * where there is no eeprom and prevents getting link.
1465		 */
1466		DEBUGOUT("Auto Read Done did not complete\n");
1467	}
1468
1469	/* If EEPROM is not present, run manual init scripts */
1470	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1471		e1000_reset_init_script_82575(hw);
1472
1473	/* Clear any pending interrupt events. */
1474	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1475	E1000_READ_REG(hw, E1000_ICR);
1476
1477	/* Install any alternate MAC address into RAR0 */
1478	ret_val = e1000_check_alt_mac_addr_generic(hw);
1479
1480	return ret_val;
1481}
1482
1483/**
1484 *  e1000_init_hw_82575 - Initialize hardware
1485 *  @hw: pointer to the HW structure
1486 *
1487 *  This inits the hardware readying it for operation.
1488 **/
1489s32 e1000_init_hw_82575(struct e1000_hw *hw)
1490{
1491	struct e1000_mac_info *mac = &hw->mac;
1492	s32 ret_val;
1493	u16 i, rar_count = mac->rar_entry_count;
1494
1495	DEBUGFUNC("e1000_init_hw_82575");
1496
1497	/* Initialize identification LED */
1498	ret_val = mac->ops.id_led_init(hw);
1499	if (ret_val) {
1500		DEBUGOUT("Error initializing identification LED\n");
1501		/* This is not fatal and we should not stop init due to this */
1502	}
1503
1504	/* Disabling VLAN filtering */
1505	DEBUGOUT("Initializing the IEEE VLAN\n");
1506	mac->ops.clear_vfta(hw);
1507
1508	/* Setup the receive address */
1509	e1000_init_rx_addrs_generic(hw, rar_count);
1510
1511	/* Zero out the Multicast HASH table */
1512	DEBUGOUT("Zeroing the MTA\n");
1513	for (i = 0; i < mac->mta_reg_count; i++)
1514		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1515
1516	/* Zero out the Unicast HASH table */
1517	DEBUGOUT("Zeroing the UTA\n");
1518	for (i = 0; i < mac->uta_reg_count; i++)
1519		E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1520
1521	/* Setup link and flow control */
1522	ret_val = mac->ops.setup_link(hw);
1523
1524	/* Set the default MTU size */
1525	hw->dev_spec._82575.mtu = 1500;
1526
1527	/*
1528	 * Clear all of the statistics registers (clear on read).  It is
1529	 * important that we do this after we have tried to establish link
1530	 * because the symbol error count will increment wildly if there
1531	 * is no link.
1532	 */
1533	e1000_clear_hw_cntrs_82575(hw);
1534
1535	return ret_val;
1536}
1537
1538/**
1539 *  e1000_setup_copper_link_82575 - Configure copper link settings
1540 *  @hw: pointer to the HW structure
1541 *
1542 *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1543 *  for link, once link is established calls to configure collision distance
1544 *  and flow control are called.
1545 **/
1546STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1547{
1548	u32 ctrl;
1549	s32 ret_val;
1550	u32 phpm_reg;
1551
1552	DEBUGFUNC("e1000_setup_copper_link_82575");
1553
1554	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1555	ctrl |= E1000_CTRL_SLU;
1556	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1557	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1558
1559	/* Clear Go Link Disconnect bit on supported devices */
1560	switch (hw->mac.type) {
1561	case e1000_82580:
1562	case e1000_i350:
1563	case e1000_i210:
1564	case e1000_i211:
1565		phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1566		phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1567		E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1568		break;
1569	default:
1570		break;
1571	}
1572
1573	ret_val = e1000_setup_serdes_link_82575(hw);
1574	if (ret_val)
1575		goto out;
1576
1577	if (e1000_sgmii_active_82575(hw)) {
1578		/* allow time for SFP cage time to power up phy */
1579		msec_delay(300);
1580
1581		ret_val = hw->phy.ops.reset(hw);
1582		if (ret_val) {
1583			DEBUGOUT("Error resetting the PHY.\n");
1584			goto out;
1585		}
1586	}
1587	switch (hw->phy.type) {
1588	case e1000_phy_i210:
1589	case e1000_phy_m88:
1590		switch (hw->phy.id) {
1591		case I347AT4_E_PHY_ID:
1592		case M88E1112_E_PHY_ID:
1593		case M88E1340M_E_PHY_ID:
1594		case M88E1543_E_PHY_ID:
1595		case M88E1512_E_PHY_ID:
1596		case I210_I_PHY_ID:
1597			ret_val = e1000_copper_link_setup_m88_gen2(hw);
1598			break;
1599		default:
1600			ret_val = e1000_copper_link_setup_m88(hw);
1601			break;
1602		}
1603		break;
1604	case e1000_phy_igp_3:
1605		ret_val = e1000_copper_link_setup_igp(hw);
1606		break;
1607	case e1000_phy_82580:
1608		ret_val = e1000_copper_link_setup_82577(hw);
1609		break;
1610	default:
1611		ret_val = -E1000_ERR_PHY;
1612		break;
1613	}
1614
1615	if (ret_val)
1616		goto out;
1617
1618	ret_val = e1000_setup_copper_link_generic(hw);
1619out:
1620	return ret_val;
1621}
1622
1623/**
1624 *  e1000_setup_serdes_link_82575 - Setup link for serdes
1625 *  @hw: pointer to the HW structure
1626 *
1627 *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1628 *  used on copper connections where the serialized gigabit media independent
1629 *  interface (sgmii), or serdes fiber is being used.  Configures the link
1630 *  for auto-negotiation or forces speed/duplex.
1631 **/
1632STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1633{
1634	u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1635	bool pcs_autoneg;
1636	s32 ret_val = E1000_SUCCESS;
1637	u16 data;
1638
1639	DEBUGFUNC("e1000_setup_serdes_link_82575");
1640
1641	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1642	    !e1000_sgmii_active_82575(hw))
1643		return ret_val;
1644
1645	/*
1646	 * On the 82575, SerDes loopback mode persists until it is
1647	 * explicitly turned off or a power cycle is performed.  A read to
1648	 * the register does not indicate its status.  Therefore, we ensure
1649	 * loopback mode is disabled during initialization.
1650	 */
1651	E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1652
1653	/* power on the sfp cage if present */
1654	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1655	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1656	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1657
1658	ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1659	ctrl_reg |= E1000_CTRL_SLU;
1660
1661	/* set both sw defined pins on 82575/82576*/
1662	if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1663		ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1664
1665	reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1666
1667	/* default pcs_autoneg to the same setting as mac autoneg */
1668	pcs_autoneg = hw->mac.autoneg;
1669
1670	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1671	case E1000_CTRL_EXT_LINK_MODE_SGMII:
1672		/* sgmii mode lets the phy handle forcing speed/duplex */
1673		pcs_autoneg = true;
1674		/* autoneg time out should be disabled for SGMII mode */
1675		reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1676		break;
1677	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1678		/* disable PCS autoneg and support parallel detect only */
1679		pcs_autoneg = false;
1680		/* fall through to default case */
1681	default:
1682		if (hw->mac.type == e1000_82575 ||
1683		    hw->mac.type == e1000_82576) {
1684			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1685			if (ret_val) {
1686				DEBUGOUT("NVM Read Error\n");
1687				return ret_val;
1688			}
1689
1690			if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1691				pcs_autoneg = false;
1692		}
1693
1694		/*
1695		 * non-SGMII modes only supports a speed of 1000/Full for the
1696		 * link so it is best to just force the MAC and let the pcs
1697		 * link either autoneg or be forced to 1000/Full
1698		 */
1699		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1700			    E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1701
1702		/* set speed of 1000/Full if speed/duplex is forced */
1703		reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1704		break;
1705	}
1706
1707	E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1708
1709	/*
1710	 * New SerDes mode allows for forcing speed or autonegotiating speed
1711	 * at 1gb. Autoneg should be default set by most drivers. This is the
1712	 * mode that will be compatible with older link partners and switches.
1713	 * However, both are supported by the hardware and some drivers/tools.
1714	 */
1715	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1716		 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1717
1718	if (pcs_autoneg) {
1719		/* Set PCS register for autoneg */
1720		reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1721		       E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1722
1723		/* Disable force flow control for autoneg */
1724		reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1725
1726		/* Configure flow control advertisement for autoneg */
1727		anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1728		anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1729
1730		switch (hw->fc.requested_mode) {
1731		case e1000_fc_full:
1732		case e1000_fc_rx_pause:
1733			anadv_reg |= E1000_TXCW_ASM_DIR;
1734			anadv_reg |= E1000_TXCW_PAUSE;
1735			break;
1736		case e1000_fc_tx_pause:
1737			anadv_reg |= E1000_TXCW_ASM_DIR;
1738			break;
1739		default:
1740			break;
1741		}
1742
1743		E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1744
1745		DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1746	} else {
1747		/* Set PCS register for forced link */
1748		reg |= E1000_PCS_LCTL_FSD;	/* Force Speed */
1749
1750		/* Force flow control for forced link */
1751		reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1752
1753		DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1754	}
1755
1756	E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1757
1758	if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1759		e1000_force_mac_fc_generic(hw);
1760
1761	return ret_val;
1762}
1763
1764/**
1765 *  e1000_get_media_type_82575 - derives current media type.
1766 *  @hw: pointer to the HW structure
1767 *
1768 *  The media type is chosen reflecting few settings.
1769 *  The following are taken into account:
1770 *  - link mode set in the current port Init Control Word #3
1771 *  - current link mode settings in CSR register
1772 *  - MDIO vs. I2C PHY control interface chosen
1773 *  - SFP module media type
1774 **/
1775STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1776{
1777	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1778	s32 ret_val = E1000_SUCCESS;
1779	u32 ctrl_ext = 0;
1780	u32 link_mode = 0;
1781
1782	/* Set internal phy as default */
1783	dev_spec->sgmii_active = false;
1784	dev_spec->module_plugged = false;
1785
1786	/* Get CSR setting */
1787	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1788
1789	/* extract link mode setting */
1790	link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1791
1792	switch (link_mode) {
1793	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1794		hw->phy.media_type = e1000_media_type_internal_serdes;
1795		break;
1796	case E1000_CTRL_EXT_LINK_MODE_GMII:
1797		hw->phy.media_type = e1000_media_type_copper;
1798		break;
1799	case E1000_CTRL_EXT_LINK_MODE_SGMII:
1800		/* Get phy control interface type set (MDIO vs. I2C)*/
1801		if (e1000_sgmii_uses_mdio_82575(hw)) {
1802			hw->phy.media_type = e1000_media_type_copper;
1803			dev_spec->sgmii_active = true;
1804			break;
1805		}
1806		/* fall through for I2C based SGMII */
1807	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1808		/* read media type from SFP EEPROM */
1809		ret_val = e1000_set_sfp_media_type_82575(hw);
1810		if ((ret_val != E1000_SUCCESS) ||
1811		    (hw->phy.media_type == e1000_media_type_unknown)) {
1812			/*
1813			 * If media type was not identified then return media
1814			 * type defined by the CTRL_EXT settings.
1815			 */
1816			hw->phy.media_type = e1000_media_type_internal_serdes;
1817
1818			if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1819				hw->phy.media_type = e1000_media_type_copper;
1820				dev_spec->sgmii_active = true;
1821			}
1822
1823			break;
1824		}
1825
1826		/* do not change link mode for 100BaseFX */
1827		if (dev_spec->eth_flags.e100_base_fx)
1828			break;
1829
1830		/* change current link mode setting */
1831		ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1832
1833		if (hw->phy.media_type == e1000_media_type_copper)
1834			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1835		else
1836			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1837
1838		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1839
1840		break;
1841	}
1842
1843	return ret_val;
1844}
1845
1846/**
1847 *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1848 *  @hw: pointer to the HW structure
1849 *
1850 *  The media type is chosen based on SFP module.
1851 *  compatibility flags retrieved from SFP ID EEPROM.
1852 **/
1853STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1854{
1855	s32 ret_val = E1000_ERR_CONFIG;
1856	u32 ctrl_ext = 0;
1857	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1858	struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1859	u8 tranceiver_type = 0;
1860	s32 timeout = 3;
1861
1862	/* Turn I2C interface ON and power on sfp cage */
1863	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1864	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1865	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1866
1867	E1000_WRITE_FLUSH(hw);
1868
1869	/* Read SFP module data */
1870	while (timeout) {
1871		ret_val = e1000_read_sfp_data_byte(hw,
1872			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1873			&tranceiver_type);
1874		if (ret_val == E1000_SUCCESS)
1875			break;
1876		msec_delay(100);
1877		timeout--;
1878	}
1879	if (ret_val != E1000_SUCCESS)
1880		goto out;
1881
1882	ret_val = e1000_read_sfp_data_byte(hw,
1883			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1884			(u8 *)eth_flags);
1885	if (ret_val != E1000_SUCCESS)
1886		goto out;
1887
1888	/* Check if there is some SFP module plugged and powered */
1889	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1890	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1891		dev_spec->module_plugged = true;
1892		if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1893			hw->phy.media_type = e1000_media_type_internal_serdes;
1894		} else if (eth_flags->e100_base_fx) {
1895			dev_spec->sgmii_active = true;
1896			hw->phy.media_type = e1000_media_type_internal_serdes;
1897		} else if (eth_flags->e1000_base_t) {
1898			dev_spec->sgmii_active = true;
1899			hw->phy.media_type = e1000_media_type_copper;
1900		} else {
1901			hw->phy.media_type = e1000_media_type_unknown;
1902			DEBUGOUT("PHY module has not been recognized\n");
1903			goto out;
1904		}
1905	} else {
1906		hw->phy.media_type = e1000_media_type_unknown;
1907	}
1908	ret_val = E1000_SUCCESS;
1909out:
1910	/* Restore I2C interface setting */
1911	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1912	return ret_val;
1913}
1914
1915/**
1916 *  e1000_valid_led_default_82575 - Verify a valid default LED config
1917 *  @hw: pointer to the HW structure
1918 *  @data: pointer to the NVM (EEPROM)
1919 *
1920 *  Read the EEPROM for the current default LED configuration.  If the
1921 *  LED configuration is not valid, set to a valid LED configuration.
1922 **/
1923STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1924{
1925	s32 ret_val;
1926
1927	DEBUGFUNC("e1000_valid_led_default_82575");
1928
1929	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1930	if (ret_val) {
1931		DEBUGOUT("NVM Read Error\n");
1932		goto out;
1933	}
1934
1935	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1936		switch (hw->phy.media_type) {
1937		case e1000_media_type_internal_serdes:
1938			*data = ID_LED_DEFAULT_82575_SERDES;
1939			break;
1940		case e1000_media_type_copper:
1941		default:
1942			*data = ID_LED_DEFAULT;
1943			break;
1944		}
1945	}
1946out:
1947	return ret_val;
1948}
1949
1950/**
1951 *  e1000_sgmii_active_82575 - Return sgmii state
1952 *  @hw: pointer to the HW structure
1953 *
1954 *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1955 *  which can be enabled for use in the embedded applications.  Simply
1956 *  return the current state of the sgmii interface.
1957 **/
1958STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1959{
1960	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1961	return dev_spec->sgmii_active;
1962}
1963
1964/**
1965 *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1966 *  @hw: pointer to the HW structure
1967 *
1968 *  Inits recommended HW defaults after a reset when there is no EEPROM
1969 *  detected. This is only for the 82575.
1970 **/
1971STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1972{
1973	DEBUGFUNC("e1000_reset_init_script_82575");
1974
1975	if (hw->mac.type == e1000_82575) {
1976		DEBUGOUT("Running reset init script for 82575\n");
1977		/* SerDes configuration via SERDESCTRL */
1978		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1979		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1980		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1981		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1982
1983		/* CCM configuration via CCMCTL register */
1984		e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1985		e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1986
1987		/* PCIe lanes configuration */
1988		e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1989		e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1990		e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1991		e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1992
1993		/* PCIe PLL Configuration */
1994		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1995		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1996		e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1997	}
1998
1999	return E1000_SUCCESS;
2000}
2001
2002/**
2003 *  e1000_read_mac_addr_82575 - Read device MAC address
2004 *  @hw: pointer to the HW structure
2005 **/
2006STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2007{
2008	s32 ret_val;
2009
2010	DEBUGFUNC("e1000_read_mac_addr_82575");
2011
2012	/*
2013	 * If there's an alternate MAC address place it in RAR0
2014	 * so that it will override the Si installed default perm
2015	 * address.
2016	 */
2017	ret_val = e1000_check_alt_mac_addr_generic(hw);
2018	if (ret_val)
2019		goto out;
2020
2021	ret_val = e1000_read_mac_addr_generic(hw);
2022
2023out:
2024	return ret_val;
2025}
2026
2027/**
2028 *  e1000_config_collision_dist_82575 - Configure collision distance
2029 *  @hw: pointer to the HW structure
2030 *
2031 *  Configures the collision distance to the default value and is used
2032 *  during link setup.
2033 **/
2034STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2035{
2036	u32 tctl_ext;
2037
2038	DEBUGFUNC("e1000_config_collision_dist_82575");
2039
2040	tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2041
2042	tctl_ext &= ~E1000_TCTL_EXT_COLD;
2043	tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2044
2045	E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2046	E1000_WRITE_FLUSH(hw);
2047}
2048
2049/**
2050 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2051 * @hw: pointer to the HW structure
2052 *
2053 * In the case of a PHY power down to save power, or to turn off link during a
2054 * driver unload, or wake on lan is not enabled, remove the link.
2055 **/
2056STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2057{
2058	struct e1000_phy_info *phy = &hw->phy;
2059
2060	if (!(phy->ops.check_reset_block))
2061		return;
2062
2063	/* If the management interface is not enabled, then power down */
2064	if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2065		e1000_power_down_phy_copper(hw);
2066
2067	return;
2068}
2069
2070/**
2071 *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2072 *  @hw: pointer to the HW structure
2073 *
2074 *  Clears the hardware counters by reading the counter registers.
2075 **/
2076STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2077{
2078	DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2079
2080	e1000_clear_hw_cntrs_base_generic(hw);
2081
2082	E1000_READ_REG(hw, E1000_PRC64);
2083	E1000_READ_REG(hw, E1000_PRC127);
2084	E1000_READ_REG(hw, E1000_PRC255);
2085	E1000_READ_REG(hw, E1000_PRC511);
2086	E1000_READ_REG(hw, E1000_PRC1023);
2087	E1000_READ_REG(hw, E1000_PRC1522);
2088	E1000_READ_REG(hw, E1000_PTC64);
2089	E1000_READ_REG(hw, E1000_PTC127);
2090	E1000_READ_REG(hw, E1000_PTC255);
2091	E1000_READ_REG(hw, E1000_PTC511);
2092	E1000_READ_REG(hw, E1000_PTC1023);
2093	E1000_READ_REG(hw, E1000_PTC1522);
2094
2095	E1000_READ_REG(hw, E1000_ALGNERRC);
2096	E1000_READ_REG(hw, E1000_RXERRC);
2097	E1000_READ_REG(hw, E1000_TNCRS);
2098	E1000_READ_REG(hw, E1000_CEXTERR);
2099	E1000_READ_REG(hw, E1000_TSCTC);
2100	E1000_READ_REG(hw, E1000_TSCTFC);
2101
2102	E1000_READ_REG(hw, E1000_MGTPRC);
2103	E1000_READ_REG(hw, E1000_MGTPDC);
2104	E1000_READ_REG(hw, E1000_MGTPTC);
2105
2106	E1000_READ_REG(hw, E1000_IAC);
2107	E1000_READ_REG(hw, E1000_ICRXOC);
2108
2109	E1000_READ_REG(hw, E1000_ICRXPTC);
2110	E1000_READ_REG(hw, E1000_ICRXATC);
2111	E1000_READ_REG(hw, E1000_ICTXPTC);
2112	E1000_READ_REG(hw, E1000_ICTXATC);
2113	E1000_READ_REG(hw, E1000_ICTXQEC);
2114	E1000_READ_REG(hw, E1000_ICTXQMTC);
2115	E1000_READ_REG(hw, E1000_ICRXDMTC);
2116
2117	E1000_READ_REG(hw, E1000_CBTMPC);
2118	E1000_READ_REG(hw, E1000_HTDPMC);
2119	E1000_READ_REG(hw, E1000_CBRMPC);
2120	E1000_READ_REG(hw, E1000_RPTHC);
2121	E1000_READ_REG(hw, E1000_HGPTC);
2122	E1000_READ_REG(hw, E1000_HTCBDPC);
2123	E1000_READ_REG(hw, E1000_HGORCL);
2124	E1000_READ_REG(hw, E1000_HGORCH);
2125	E1000_READ_REG(hw, E1000_HGOTCL);
2126	E1000_READ_REG(hw, E1000_HGOTCH);
2127	E1000_READ_REG(hw, E1000_LENERRS);
2128
2129	/* This register should not be read in copper configurations */
2130	if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2131	    e1000_sgmii_active_82575(hw))
2132		E1000_READ_REG(hw, E1000_SCVPC);
2133}
2134
2135/**
2136 *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2137 *  @hw: pointer to the HW structure
2138 *
2139 *  After Rx enable, if manageability is enabled then there is likely some
2140 *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2141 *  function clears the fifos and flushes any packets that came in as rx was
2142 *  being enabled.
2143 **/
2144void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2145{
2146	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2147	int i, ms_wait;
2148
2149	DEBUGFUNC("e1000_rx_fifo_flush_82575");
2150
2151	/* disable IPv6 options as per hardware errata */
2152	rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2153	rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2154	E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2155
2156	if (hw->mac.type != e1000_82575 ||
2157	    !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2158		return;
2159
2160	/* Disable all Rx queues */
2161	for (i = 0; i < 4; i++) {
2162		rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2163		E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2164				rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2165	}
2166	/* Poll all queues to verify they have shut down */
2167	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2168		msec_delay(1);
2169		rx_enabled = 0;
2170		for (i = 0; i < 4; i++)
2171			rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2172		if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2173			break;
2174	}
2175
2176	if (ms_wait == 10)
2177		DEBUGOUT("Queue disable timed out after 10ms\n");
2178
2179	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2180	 * incoming packets are rejected.  Set enable and wait 2ms so that
2181	 * any packet that was coming in as RCTL.EN was set is flushed
2182	 */
2183	E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2184
2185	rlpml = E1000_READ_REG(hw, E1000_RLPML);
2186	E1000_WRITE_REG(hw, E1000_RLPML, 0);
2187
2188	rctl = E1000_READ_REG(hw, E1000_RCTL);
2189	temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2190	temp_rctl |= E1000_RCTL_LPE;
2191
2192	E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2193	E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2194	E1000_WRITE_FLUSH(hw);
2195	msec_delay(2);
2196
2197	/* Enable Rx queues that were previously enabled and restore our
2198	 * previous state
2199	 */
2200	for (i = 0; i < 4; i++)
2201		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2202	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2203	E1000_WRITE_FLUSH(hw);
2204
2205	E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2206	E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2207
2208	/* Flush receive errors generated by workaround */
2209	E1000_READ_REG(hw, E1000_ROC);
2210	E1000_READ_REG(hw, E1000_RNBC);
2211	E1000_READ_REG(hw, E1000_MPC);
2212}
2213
2214/**
2215 *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2216 *  @hw: pointer to the HW structure
2217 *
2218 *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2219 *  however the hardware default for these parts is 500us to 1ms which is less
2220 *  than the 10ms recommended by the pci-e spec.  To address this we need to
2221 *  increase the value to either 10ms to 200ms for capability version 1 config,
2222 *  or 16ms to 55ms for version 2.
2223 **/
2224STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2225{
2226	u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2227	s32 ret_val = E1000_SUCCESS;
2228	u16 pcie_devctl2;
2229
2230	/* only take action if timeout value is defaulted to 0 */
2231	if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2232		goto out;
2233
2234	/*
2235	 * if capababilities version is type 1 we can write the
2236	 * timeout of 10ms to 200ms through the GCR register
2237	 */
2238	if (!(gcr & E1000_GCR_CAP_VER2)) {
2239		gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2240		goto out;
2241	}
2242
2243	/*
2244	 * for version 2 capabilities we need to write the config space
2245	 * directly in order to set the completion timeout value for
2246	 * 16ms to 55ms
2247	 */
2248	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2249					  &pcie_devctl2);
2250	if (ret_val)
2251		goto out;
2252
2253	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2254
2255	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2256					   &pcie_devctl2);
2257out:
2258	/* disable completion timeout resend */
2259	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2260
2261	E1000_WRITE_REG(hw, E1000_GCR, gcr);
2262	return ret_val;
2263}
2264
2265/**
2266 *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2267 *  @hw: pointer to the hardware struct
2268 *  @enable: state to enter, either enabled or disabled
2269 *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2270 *
2271 *  enables/disables L2 switch anti-spoofing functionality.
2272 **/
2273void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2274{
2275	u32 reg_val, reg_offset;
2276
2277	switch (hw->mac.type) {
2278	case e1000_82576:
2279		reg_offset = E1000_DTXSWC;
2280		break;
2281	case e1000_i350:
2282	case e1000_i354:
2283		reg_offset = E1000_TXSWC;
2284		break;
2285	default:
2286		return;
2287	}
2288
2289	reg_val = E1000_READ_REG(hw, reg_offset);
2290	if (enable) {
2291		reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2292			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2293		/* The PF can spoof - it has to in order to
2294		 * support emulation mode NICs
2295		 */
2296		reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2297	} else {
2298		reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2299			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2300	}
2301	E1000_WRITE_REG(hw, reg_offset, reg_val);
2302}
2303
2304/**
2305 *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2306 *  @hw: pointer to the hardware struct
2307 *  @enable: state to enter, either enabled or disabled
2308 *
2309 *  enables/disables L2 switch loopback functionality.
2310 **/
2311void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2312{
2313	u32 dtxswc;
2314
2315	switch (hw->mac.type) {
2316	case e1000_82576:
2317		dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2318		if (enable)
2319			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2320		else
2321			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2322		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2323		break;
2324	case e1000_i350:
2325	case e1000_i354:
2326		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2327		if (enable)
2328			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2329		else
2330			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2331		E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2332		break;
2333	default:
2334		/* Currently no other hardware supports loopback */
2335		break;
2336	}
2337
2338
2339}
2340
2341/**
2342 *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2343 *  @hw: pointer to the hardware struct
2344 *  @enable: state to enter, either enabled or disabled
2345 *
2346 *  enables/disables replication of packets across multiple pools.
2347 **/
2348void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2349{
2350	u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2351
2352	if (enable)
2353		vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2354	else
2355		vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2356
2357	E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2358}
2359
2360/**
2361 *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2362 *  @hw: pointer to the HW structure
2363 *  @offset: register offset to be read
2364 *  @data: pointer to the read data
2365 *
2366 *  Reads the MDI control register in the PHY at offset and stores the
2367 *  information read to data.
2368 **/
2369STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2370{
2371	s32 ret_val;
2372
2373	DEBUGFUNC("e1000_read_phy_reg_82580");
2374
2375	ret_val = hw->phy.ops.acquire(hw);
2376	if (ret_val)
2377		goto out;
2378
2379	ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2380
2381	hw->phy.ops.release(hw);
2382
2383out:
2384	return ret_val;
2385}
2386
2387/**
2388 *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2389 *  @hw: pointer to the HW structure
2390 *  @offset: register offset to write to
2391 *  @data: data to write to register at offset
2392 *
2393 *  Writes data to MDI control register in the PHY at offset.
2394 **/
2395STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2396{
2397	s32 ret_val;
2398
2399	DEBUGFUNC("e1000_write_phy_reg_82580");
2400
2401	ret_val = hw->phy.ops.acquire(hw);
2402	if (ret_val)
2403		goto out;
2404
2405	ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2406
2407	hw->phy.ops.release(hw);
2408
2409out:
2410	return ret_val;
2411}
2412
2413/**
2414 *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2415 *  @hw: pointer to the HW structure
2416 *
2417 *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2418 *  the values found in the EEPROM.  This addresses an issue in which these
2419 *  bits are not restored from EEPROM after reset.
2420 **/
2421STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2422{
2423	s32 ret_val = E1000_SUCCESS;
2424	u32 mdicnfg;
2425	u16 nvm_data = 0;
2426
2427	DEBUGFUNC("e1000_reset_mdicnfg_82580");
2428
2429	if (hw->mac.type != e1000_82580)
2430		goto out;
2431	if (!e1000_sgmii_active_82575(hw))
2432		goto out;
2433
2434	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2435				   NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2436				   &nvm_data);
2437	if (ret_val) {
2438		DEBUGOUT("NVM Read Error\n");
2439		goto out;
2440	}
2441
2442	mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2443	if (nvm_data & NVM_WORD24_EXT_MDIO)
2444		mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2445	if (nvm_data & NVM_WORD24_COM_MDIO)
2446		mdicnfg |= E1000_MDICNFG_COM_MDIO;
2447	E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2448out:
2449	return ret_val;
2450}
2451
2452/**
2453 *  e1000_reset_hw_82580 - Reset hardware
2454 *  @hw: pointer to the HW structure
2455 *
2456 *  This resets function or entire device (all ports, etc.)
2457 *  to a known state.
2458 **/
2459STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2460{
2461	s32 ret_val = E1000_SUCCESS;
2462	/* BH SW mailbox bit in SW_FW_SYNC */
2463	u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2464	u32 ctrl;
2465	bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2466
2467	DEBUGFUNC("e1000_reset_hw_82580");
2468
2469	hw->dev_spec._82575.global_device_reset = false;
2470
2471	/* 82580 does not reliably do global_device_reset due to hw errata */
2472	if (hw->mac.type == e1000_82580)
2473		global_device_reset = false;
2474
2475	/* Get current control state. */
2476	ctrl = E1000_READ_REG(hw, E1000_CTRL);
2477
2478	/*
2479	 * Prevent the PCI-E bus from sticking if there is no TLP connection
2480	 * on the last TLP read/write transaction when MAC is reset.
2481	 */
2482	ret_val = e1000_disable_pcie_master_generic(hw);
2483	if (ret_val)
2484		DEBUGOUT("PCI-E Master disable polling has failed.\n");
2485
2486	DEBUGOUT("Masking off all interrupts\n");
2487	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2488	E1000_WRITE_REG(hw, E1000_RCTL, 0);
2489	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2490	E1000_WRITE_FLUSH(hw);
2491
2492	msec_delay(10);
2493
2494	/* Determine whether or not a global dev reset is requested */
2495	if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2496	    swmbsw_mask))
2497			global_device_reset = false;
2498
2499	if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2500	    E1000_STAT_DEV_RST_SET))
2501		ctrl |= E1000_CTRL_DEV_RST;
2502	else
2503		ctrl |= E1000_CTRL_RST;
2504
2505	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2506
2507	switch (hw->device_id) {
2508	case E1000_DEV_ID_DH89XXCC_SGMII:
2509		break;
2510	default:
2511		E1000_WRITE_FLUSH(hw);
2512		break;
2513	}
2514
2515	/* Add delay to insure DEV_RST or RST has time to complete */
2516	msec_delay(5);
2517
2518	ret_val = e1000_get_auto_rd_done_generic(hw);
2519	if (ret_val) {
2520		/*
2521		 * When auto config read does not complete, do not
2522		 * return with an error. This can happen in situations
2523		 * where there is no eeprom and prevents getting link.
2524		 */
2525		DEBUGOUT("Auto Read Done did not complete\n");
2526	}
2527
2528	/* clear global device reset status bit */
2529	E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2530
2531	/* Clear any pending interrupt events. */
2532	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2533	E1000_READ_REG(hw, E1000_ICR);
2534
2535	ret_val = e1000_reset_mdicnfg_82580(hw);
2536	if (ret_val)
2537		DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2538
2539	/* Install any alternate MAC address into RAR0 */
2540	ret_val = e1000_check_alt_mac_addr_generic(hw);
2541
2542	/* Release semaphore */
2543	if (global_device_reset)
2544		hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2545
2546	return ret_val;
2547}
2548
2549/**
2550 *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2551 *  @data: data received by reading RXPBS register
2552 *
2553 *  The 82580 uses a table based approach for packet buffer allocation sizes.
2554 *  This function converts the retrieved value into the correct table value
2555 *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2556 *  0x0 36  72 144   1   2   4   8  16
2557 *  0x8 35  70 140 rsv rsv rsv rsv rsv
2558 */
2559u16 e1000_rxpbs_adjust_82580(u32 data)
2560{
2561	u16 ret_val = 0;
2562
2563	if (data < E1000_82580_RXPBS_TABLE_SIZE)
2564		ret_val = e1000_82580_rxpbs_table[data];
2565
2566	return ret_val;
2567}
2568
2569/**
2570 *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2571 *  checksum
2572 *  @hw: pointer to the HW structure
2573 *  @offset: offset in words of the checksum protected region
2574 *
2575 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2576 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2577 **/
2578s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2579{
2580	s32 ret_val = E1000_SUCCESS;
2581	u16 checksum = 0;
2582	u16 i, nvm_data;
2583
2584	DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2585
2586	for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2587		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2588		if (ret_val) {
2589			DEBUGOUT("NVM Read Error\n");
2590			goto out;
2591		}
2592		checksum += nvm_data;
2593	}
2594
2595	if (checksum != (u16) NVM_SUM) {
2596		DEBUGOUT("NVM Checksum Invalid\n");
2597		ret_val = -E1000_ERR_NVM;
2598		goto out;
2599	}
2600
2601out:
2602	return ret_val;
2603}
2604
2605/**
2606 *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2607 *  checksum
2608 *  @hw: pointer to the HW structure
2609 *  @offset: offset in words of the checksum protected region
2610 *
2611 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2612 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2613 *  value to the EEPROM.
2614 **/
2615s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2616{
2617	s32 ret_val;
2618	u16 checksum = 0;
2619	u16 i, nvm_data;
2620
2621	DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2622
2623	for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2624		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2625		if (ret_val) {
2626			DEBUGOUT("NVM Read Error while updating checksum.\n");
2627			goto out;
2628		}
2629		checksum += nvm_data;
2630	}
2631	checksum = (u16) NVM_SUM - checksum;
2632	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2633				    &checksum);
2634	if (ret_val)
2635		DEBUGOUT("NVM Write Error while updating checksum.\n");
2636
2637out:
2638	return ret_val;
2639}
2640
2641/**
2642 *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2643 *  @hw: pointer to the HW structure
2644 *
2645 *  Calculates the EEPROM section checksum by reading/adding each word of
2646 *  the EEPROM and then verifies that the sum of the EEPROM is
2647 *  equal to 0xBABA.
2648 **/
2649STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2650{
2651	s32 ret_val;
2652	u16 eeprom_regions_count = 1;
2653	u16 j, nvm_data;
2654	u16 nvm_offset;
2655
2656	DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2657
2658	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2659	if (ret_val) {
2660		DEBUGOUT("NVM Read Error\n");
2661		goto out;
2662	}
2663
2664	if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2665		/* if chekcsums compatibility bit is set validate checksums
2666		 * for all 4 ports. */
2667		eeprom_regions_count = 4;
2668	}
2669
2670	for (j = 0; j < eeprom_regions_count; j++) {
2671		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2672		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2673								  nvm_offset);
2674		if (ret_val != E1000_SUCCESS)
2675			goto out;
2676	}
2677
2678out:
2679	return ret_val;
2680}
2681
2682/**
2683 *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2684 *  @hw: pointer to the HW structure
2685 *
2686 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2687 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2688 *  checksum and writes the value to the EEPROM.
2689 **/
2690STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2691{
2692	s32 ret_val;
2693	u16 j, nvm_data;
2694	u16 nvm_offset;
2695
2696	DEBUGFUNC("e1000_update_nvm_checksum_82580");
2697
2698	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2699	if (ret_val) {
2700		DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2701		goto out;
2702	}
2703
2704	if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2705		/* set compatibility bit to validate checksums appropriately */
2706		nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2707		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2708					    &nvm_data);
2709		if (ret_val) {
2710			DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2711			goto out;
2712		}
2713	}
2714
2715	for (j = 0; j < 4; j++) {
2716		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2717		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2718		if (ret_val)
2719			goto out;
2720	}
2721
2722out:
2723	return ret_val;
2724}
2725
2726/**
2727 *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2728 *  @hw: pointer to the HW structure
2729 *
2730 *  Calculates the EEPROM section checksum by reading/adding each word of
2731 *  the EEPROM and then verifies that the sum of the EEPROM is
2732 *  equal to 0xBABA.
2733 **/
2734STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2735{
2736	s32 ret_val = E1000_SUCCESS;
2737	u16 j;
2738	u16 nvm_offset;
2739
2740	DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2741
2742	for (j = 0; j < 4; j++) {
2743		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2744		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2745								  nvm_offset);
2746		if (ret_val != E1000_SUCCESS)
2747			goto out;
2748	}
2749
2750out:
2751	return ret_val;
2752}
2753
2754/**
2755 *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2756 *  @hw: pointer to the HW structure
2757 *
2758 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2759 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2760 *  checksum and writes the value to the EEPROM.
2761 **/
2762STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2763{
2764	s32 ret_val = E1000_SUCCESS;
2765	u16 j;
2766	u16 nvm_offset;
2767
2768	DEBUGFUNC("e1000_update_nvm_checksum_i350");
2769
2770	for (j = 0; j < 4; j++) {
2771		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2772		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2773		if (ret_val != E1000_SUCCESS)
2774			goto out;
2775	}
2776
2777out:
2778	return ret_val;
2779}
2780
2781/**
2782 *  __e1000_access_emi_reg - Read/write EMI register
2783 *  @hw: pointer to the HW structure
2784 *  @addr: EMI address to program
2785 *  @data: pointer to value to read/write from/to the EMI address
2786 *  @read: boolean flag to indicate read or write
2787 **/
2788STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2789				  u16 *data, bool read)
2790{
2791	s32 ret_val;
2792
2793	DEBUGFUNC("__e1000_access_emi_reg");
2794
2795	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2796	if (ret_val)
2797		return ret_val;
2798
2799	if (read)
2800		ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2801	else
2802		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2803
2804	return ret_val;
2805}
2806
2807/**
2808 *  e1000_read_emi_reg - Read Extended Management Interface register
2809 *  @hw: pointer to the HW structure
2810 *  @addr: EMI address to program
2811 *  @data: value to be read from the EMI address
2812 **/
2813s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2814{
2815	DEBUGFUNC("e1000_read_emi_reg");
2816
2817	return __e1000_access_emi_reg(hw, addr, data, true);
2818}
2819
2820/**
2821 *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2822 *  @hw: pointer to the HW structure
2823 *
2824 *  Initialize Marvell 1512 to work correctly with Avoton.
2825 **/
2826s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2827{
2828	struct e1000_phy_info *phy = &hw->phy;
2829	s32 ret_val = E1000_SUCCESS;
2830
2831	DEBUGFUNC("e1000_initialize_M88E1512_phy");
2832
2833	/* Check if this is correct PHY. */
2834	if (phy->id != M88E1512_E_PHY_ID)
2835		goto out;
2836
2837	/* Switch to PHY page 0xFF. */
2838	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2839	if (ret_val)
2840		goto out;
2841
2842	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2843	if (ret_val)
2844		goto out;
2845
2846	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2847	if (ret_val)
2848		goto out;
2849
2850	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2851	if (ret_val)
2852		goto out;
2853
2854	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2855	if (ret_val)
2856		goto out;
2857
2858	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2859	if (ret_val)
2860		goto out;
2861
2862	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2863	if (ret_val)
2864		goto out;
2865
2866	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2867	if (ret_val)
2868		goto out;
2869
2870	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2871	if (ret_val)
2872		goto out;
2873
2874	/* Switch to PHY page 0xFB. */
2875	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2876	if (ret_val)
2877		goto out;
2878
2879	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2880	if (ret_val)
2881		goto out;
2882
2883	/* Switch to PHY page 0x12. */
2884	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2885	if (ret_val)
2886		goto out;
2887
2888	/* Change mode to SGMII-to-Copper */
2889	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2890	if (ret_val)
2891		goto out;
2892
2893	/* Return the PHY to page 0. */
2894	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2895	if (ret_val)
2896		goto out;
2897
2898	ret_val = phy->ops.commit(hw);
2899	if (ret_val) {
2900		DEBUGOUT("Error committing the PHY changes\n");
2901		return ret_val;
2902	}
2903
2904	msec_delay(1000);
2905out:
2906	return ret_val;
2907}
2908
2909/**
2910 *  e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2911 *  @hw: pointer to the HW structure
2912 *
2913 *  Initialize Marvell 1543 to work correctly with Avoton.
2914 **/
2915s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2916{
2917	struct e1000_phy_info *phy = &hw->phy;
2918	s32 ret_val = E1000_SUCCESS;
2919
2920	DEBUGFUNC("e1000_initialize_M88E1543_phy");
2921
2922	/* Check if this is correct PHY. */
2923	if (phy->id != M88E1543_E_PHY_ID)
2924		goto out;
2925
2926	/* Switch to PHY page 0xFF. */
2927	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2928	if (ret_val)
2929		goto out;
2930
2931	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2932	if (ret_val)
2933		goto out;
2934
2935	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2936	if (ret_val)
2937		goto out;
2938
2939	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2940	if (ret_val)
2941		goto out;
2942
2943	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2944	if (ret_val)
2945		goto out;
2946
2947	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2948	if (ret_val)
2949		goto out;
2950
2951	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2952	if (ret_val)
2953		goto out;
2954
2955	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2956	if (ret_val)
2957		goto out;
2958
2959	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2960	if (ret_val)
2961		goto out;
2962
2963	/* Switch to PHY page 0xFB. */
2964	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2965	if (ret_val)
2966		goto out;
2967
2968	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2969	if (ret_val)
2970		goto out;
2971
2972	/* Switch to PHY page 0x12. */
2973	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2974	if (ret_val)
2975		goto out;
2976
2977	/* Change mode to SGMII-to-Copper */
2978	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2979	if (ret_val)
2980		goto out;
2981
2982	/* Switch to PHY page 1. */
2983	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2984	if (ret_val)
2985		goto out;
2986
2987	/* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2988	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2989	if (ret_val)
2990		goto out;
2991
2992	/* Return the PHY to page 0. */
2993	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2994	if (ret_val)
2995		goto out;
2996
2997	ret_val = phy->ops.commit(hw);
2998	if (ret_val) {
2999		DEBUGOUT("Error committing the PHY changes\n");
3000		return ret_val;
3001	}
3002
3003	msec_delay(1000);
3004out:
3005	return ret_val;
3006}
3007
3008/**
3009 *  e1000_set_eee_i350 - Enable/disable EEE support
3010 *  @hw: pointer to the HW structure
3011 *  @adv1g: boolean flag enabling 1G EEE advertisement
3012 *  @adv100m: boolean flag enabling 100M EEE advertisement
3013 *
3014 *  Enable/disable EEE based on setting in dev_spec structure.
3015 *
3016 **/
3017s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3018{
3019	u32 ipcnfg, eeer;
3020
3021	DEBUGFUNC("e1000_set_eee_i350");
3022
3023	if ((hw->mac.type < e1000_i350) ||
3024	    (hw->phy.media_type != e1000_media_type_copper))
3025		goto out;
3026	ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3027	eeer = E1000_READ_REG(hw, E1000_EEER);
3028
3029	/* enable or disable per user setting */
3030	if (!(hw->dev_spec._82575.eee_disable)) {
3031		u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3032
3033		if (adv100M)
3034			ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3035		else
3036			ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3037
3038		if (adv1G)
3039			ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3040		else
3041			ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3042
3043		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3044			 E1000_EEER_LPI_FC);
3045
3046		/* This bit should not be set in normal operation. */
3047		if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3048			DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3049	} else {
3050		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3051		eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3052			  E1000_EEER_LPI_FC);
3053	}
3054	E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3055	E1000_WRITE_REG(hw, E1000_EEER, eeer);
3056	E1000_READ_REG(hw, E1000_IPCNFG);
3057	E1000_READ_REG(hw, E1000_EEER);
3058out:
3059
3060	return E1000_SUCCESS;
3061}
3062
3063/**
3064 *  e1000_set_eee_i354 - Enable/disable EEE support
3065 *  @hw: pointer to the HW structure
3066 *  @adv1g: boolean flag enabling 1G EEE advertisement
3067 *  @adv100m: boolean flag enabling 100M EEE advertisement
3068 *
3069 *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
3070 *
3071 **/
3072s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3073{
3074	struct e1000_phy_info *phy = &hw->phy;
3075	s32 ret_val = E1000_SUCCESS;
3076	u16 phy_data;
3077
3078	DEBUGFUNC("e1000_set_eee_i354");
3079
3080	if ((hw->phy.media_type != e1000_media_type_copper) ||
3081	    ((phy->id != M88E1543_E_PHY_ID) &&
3082	    (phy->id != M88E1512_E_PHY_ID)))
3083		goto out;
3084
3085	if (!hw->dev_spec._82575.eee_disable) {
3086		/* Switch to PHY page 18. */
3087		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3088		if (ret_val)
3089			goto out;
3090
3091		ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3092					    &phy_data);
3093		if (ret_val)
3094			goto out;
3095
3096		phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3097		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3098					     phy_data);
3099		if (ret_val)
3100			goto out;
3101
3102		/* Return the PHY to page 0. */
3103		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3104		if (ret_val)
3105			goto out;
3106
3107		/* Turn on EEE advertisement. */
3108		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3109					       E1000_EEE_ADV_DEV_I354,
3110					       &phy_data);
3111		if (ret_val)
3112			goto out;
3113
3114		if (adv100M)
3115			phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3116		else
3117			phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3118
3119		if (adv1G)
3120			phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3121		else
3122			phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3123
3124		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3125						E1000_EEE_ADV_DEV_I354,
3126						phy_data);
3127	} else {
3128		/* Turn off EEE advertisement. */
3129		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3130					       E1000_EEE_ADV_DEV_I354,
3131					       &phy_data);
3132		if (ret_val)
3133			goto out;
3134
3135		phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3136			      E1000_EEE_ADV_1000_SUPPORTED);
3137		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3138						E1000_EEE_ADV_DEV_I354,
3139						phy_data);
3140	}
3141
3142out:
3143	return ret_val;
3144}
3145
3146/**
3147 *  e1000_get_eee_status_i354 - Get EEE status
3148 *  @hw: pointer to the HW structure
3149 *  @status: EEE status
3150 *
3151 *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3152 *  been received.
3153 **/
3154s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3155{
3156	struct e1000_phy_info *phy = &hw->phy;
3157	s32 ret_val = E1000_SUCCESS;
3158	u16 phy_data;
3159
3160	DEBUGFUNC("e1000_get_eee_status_i354");
3161
3162	/* Check if EEE is supported on this device. */
3163	if ((hw->phy.media_type != e1000_media_type_copper) ||
3164	    ((phy->id != M88E1543_E_PHY_ID) &&
3165	    (phy->id != M88E1512_E_PHY_ID)))
3166		goto out;
3167
3168	ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3169				       E1000_PCS_STATUS_DEV_I354,
3170				       &phy_data);
3171	if (ret_val)
3172		goto out;
3173
3174	*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3175			      E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3176
3177out:
3178	return ret_val;
3179}
3180
3181/* Due to a hw errata, if the host tries to  configure the VFTA register
3182 * while performing queries from the BMC or DMA, then the VFTA in some
3183 * cases won't be written.
3184 */
3185
3186/**
3187 *  e1000_clear_vfta_i350 - Clear VLAN filter table
3188 *  @hw: pointer to the HW structure
3189 *
3190 *  Clears the register array which contains the VLAN filter table by
3191 *  setting all the values to 0.
3192 **/
3193void e1000_clear_vfta_i350(struct e1000_hw *hw)
3194{
3195	u32 offset;
3196	int i;
3197
3198	DEBUGFUNC("e1000_clear_vfta_350");
3199
3200	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3201		for (i = 0; i < 10; i++)
3202			E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3203
3204		E1000_WRITE_FLUSH(hw);
3205	}
3206}
3207
3208/**
3209 *  e1000_write_vfta_i350 - Write value to VLAN filter table
3210 *  @hw: pointer to the HW structure
3211 *  @offset: register offset in VLAN filter table
3212 *  @value: register value written to VLAN filter table
3213 *
3214 *  Writes value at the given offset in the register array which stores
3215 *  the VLAN filter table.
3216 **/
3217void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3218{
3219	int i;
3220
3221	DEBUGFUNC("e1000_write_vfta_350");
3222
3223	for (i = 0; i < 10; i++)
3224		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3225
3226	E1000_WRITE_FLUSH(hw);
3227}
3228
3229
3230/**
3231 *  e1000_set_i2c_bb - Enable I2C bit-bang
3232 *  @hw: pointer to the HW structure
3233 *
3234 *  Enable I2C bit-bang interface
3235 *
3236 **/
3237s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3238{
3239	s32 ret_val = E1000_SUCCESS;
3240	u32 ctrl_ext, i2cparams;
3241
3242	DEBUGFUNC("e1000_set_i2c_bb");
3243
3244	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3245	ctrl_ext |= E1000_CTRL_I2C_ENA;
3246	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3247	E1000_WRITE_FLUSH(hw);
3248
3249	i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3250	i2cparams |= E1000_I2CBB_EN;
3251	i2cparams |= E1000_I2C_DATA_OE_N;
3252	i2cparams |= E1000_I2C_CLK_OE_N;
3253	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3254	E1000_WRITE_FLUSH(hw);
3255
3256	return ret_val;
3257}
3258
3259/**
3260 *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3261 *  @hw: pointer to hardware structure
3262 *  @byte_offset: byte offset to read
3263 *  @dev_addr: device address
3264 *  @data: value read
3265 *
3266 *  Performs byte read operation over I2C interface at
3267 *  a specified device address.
3268 **/
3269s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3270				u8 dev_addr, u8 *data)
3271{
3272	s32 status = E1000_SUCCESS;
3273	u32 max_retry = 10;
3274	u32 retry = 1;
3275	u16 swfw_mask = 0;
3276
3277	bool nack = true;
3278
3279	DEBUGFUNC("e1000_read_i2c_byte_generic");
3280
3281	swfw_mask = E1000_SWFW_PHY0_SM;
3282
3283	do {
3284		if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3285		    != E1000_SUCCESS) {
3286			status = E1000_ERR_SWFW_SYNC;
3287			goto read_byte_out;
3288		}
3289
3290		e1000_i2c_start(hw);
3291
3292		/* Device Address and write indication */
3293		status = e1000_clock_out_i2c_byte(hw, dev_addr);
3294		if (status != E1000_SUCCESS)
3295			goto fail;
3296
3297		status = e1000_get_i2c_ack(hw);
3298		if (status != E1000_SUCCESS)
3299			goto fail;
3300
3301		status = e1000_clock_out_i2c_byte(hw, byte_offset);
3302		if (status != E1000_SUCCESS)
3303			goto fail;
3304
3305		status = e1000_get_i2c_ack(hw);
3306		if (status != E1000_SUCCESS)
3307			goto fail;
3308
3309		e1000_i2c_start(hw);
3310
3311		/* Device Address and read indication */
3312		status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3313		if (status != E1000_SUCCESS)
3314			goto fail;
3315
3316		status = e1000_get_i2c_ack(hw);
3317		if (status != E1000_SUCCESS)
3318			goto fail;
3319
3320		status = e1000_clock_in_i2c_byte(hw, data);
3321		if (status != E1000_SUCCESS)
3322			goto fail;
3323
3324		status = e1000_clock_out_i2c_bit(hw, nack);
3325		if (status != E1000_SUCCESS)
3326			goto fail;
3327
3328		e1000_i2c_stop(hw);
3329		break;
3330
3331fail:
3332		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3333		msec_delay(100);
3334		e1000_i2c_bus_clear(hw);
3335		retry++;
3336		if (retry < max_retry)
3337			DEBUGOUT("I2C byte read error - Retrying.\n");
3338		else
3339			DEBUGOUT("I2C byte read error.\n");
3340
3341	} while (retry < max_retry);
3342
3343	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3344
3345read_byte_out:
3346
3347	return status;
3348}
3349
3350/**
3351 *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3352 *  @hw: pointer to hardware structure
3353 *  @byte_offset: byte offset to write
3354 *  @dev_addr: device address
3355 *  @data: value to write
3356 *
3357 *  Performs byte write operation over I2C interface at
3358 *  a specified device address.
3359 **/
3360s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3361				 u8 dev_addr, u8 data)
3362{
3363	s32 status = E1000_SUCCESS;
3364	u32 max_retry = 1;
3365	u32 retry = 0;
3366	u16 swfw_mask = 0;
3367
3368	DEBUGFUNC("e1000_write_i2c_byte_generic");
3369
3370	swfw_mask = E1000_SWFW_PHY0_SM;
3371
3372	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3373		status = E1000_ERR_SWFW_SYNC;
3374		goto write_byte_out;
3375	}
3376
3377	do {
3378		e1000_i2c_start(hw);
3379
3380		status = e1000_clock_out_i2c_byte(hw, dev_addr);
3381		if (status != E1000_SUCCESS)
3382			goto fail;
3383
3384		status = e1000_get_i2c_ack(hw);
3385		if (status != E1000_SUCCESS)
3386			goto fail;
3387
3388		status = e1000_clock_out_i2c_byte(hw, byte_offset);
3389		if (status != E1000_SUCCESS)
3390			goto fail;
3391
3392		status = e1000_get_i2c_ack(hw);
3393		if (status != E1000_SUCCESS)
3394			goto fail;
3395
3396		status = e1000_clock_out_i2c_byte(hw, data);
3397		if (status != E1000_SUCCESS)
3398			goto fail;
3399
3400		status = e1000_get_i2c_ack(hw);
3401		if (status != E1000_SUCCESS)
3402			goto fail;
3403
3404		e1000_i2c_stop(hw);
3405		break;
3406
3407fail:
3408		e1000_i2c_bus_clear(hw);
3409		retry++;
3410		if (retry < max_retry)
3411			DEBUGOUT("I2C byte write error - Retrying.\n");
3412		else
3413			DEBUGOUT("I2C byte write error.\n");
3414	} while (retry < max_retry);
3415
3416	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3417
3418write_byte_out:
3419
3420	return status;
3421}
3422
3423/**
3424 *  e1000_i2c_start - Sets I2C start condition
3425 *  @hw: pointer to hardware structure
3426 *
3427 *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3428 **/
3429STATIC void e1000_i2c_start(struct e1000_hw *hw)
3430{
3431	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3432
3433	DEBUGFUNC("e1000_i2c_start");
3434
3435	/* Start condition must begin with data and clock high */
3436	e1000_set_i2c_data(hw, &i2cctl, 1);
3437	e1000_raise_i2c_clk(hw, &i2cctl);
3438
3439	/* Setup time for start condition (4.7us) */
3440	usec_delay(E1000_I2C_T_SU_STA);
3441
3442	e1000_set_i2c_data(hw, &i2cctl, 0);
3443
3444	/* Hold time for start condition (4us) */
3445	usec_delay(E1000_I2C_T_HD_STA);
3446
3447	e1000_lower_i2c_clk(hw, &i2cctl);
3448
3449	/* Minimum low period of clock is 4.7 us */
3450	usec_delay(E1000_I2C_T_LOW);
3451
3452}
3453
3454/**
3455 *  e1000_i2c_stop - Sets I2C stop condition
3456 *  @hw: pointer to hardware structure
3457 *
3458 *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3459 **/
3460STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3461{
3462	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3463
3464	DEBUGFUNC("e1000_i2c_stop");
3465
3466	/* Stop condition must begin with data low and clock high */
3467	e1000_set_i2c_data(hw, &i2cctl, 0);
3468	e1000_raise_i2c_clk(hw, &i2cctl);
3469
3470	/* Setup time for stop condition (4us) */
3471	usec_delay(E1000_I2C_T_SU_STO);
3472
3473	e1000_set_i2c_data(hw, &i2cctl, 1);
3474
3475	/* bus free time between stop and start (4.7us)*/
3476	usec_delay(E1000_I2C_T_BUF);
3477}
3478
3479/**
3480 *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3481 *  @hw: pointer to hardware structure
3482 *  @data: data byte to clock in
3483 *
3484 *  Clocks in one byte data via I2C data/clock
3485 **/
3486STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3487{
3488	s32 i;
3489	bool bit = 0;
3490
3491	DEBUGFUNC("e1000_clock_in_i2c_byte");
3492
3493	*data = 0;
3494	for (i = 7; i >= 0; i--) {
3495		e1000_clock_in_i2c_bit(hw, &bit);
3496		*data |= bit << i;
3497	}
3498
3499	return E1000_SUCCESS;
3500}
3501
3502/**
3503 *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3504 *  @hw: pointer to hardware structure
3505 *  @data: data byte clocked out
3506 *
3507 *  Clocks out one byte data via I2C data/clock
3508 **/
3509STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3510{
3511	s32 status = E1000_SUCCESS;
3512	s32 i;
3513	u32 i2cctl;
3514	bool bit = 0;
3515
3516	DEBUGFUNC("e1000_clock_out_i2c_byte");
3517
3518	for (i = 7; i >= 0; i--) {
3519		bit = (data >> i) & 0x1;
3520		status = e1000_clock_out_i2c_bit(hw, bit);
3521
3522		if (status != E1000_SUCCESS)
3523			break;
3524	}
3525
3526	/* Release SDA line (set high) */
3527	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3528
3529	i2cctl |= E1000_I2C_DATA_OE_N;
3530	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3531	E1000_WRITE_FLUSH(hw);
3532
3533	return status;
3534}
3535
3536/**
3537 *  e1000_get_i2c_ack - Polls for I2C ACK
3538 *  @hw: pointer to hardware structure
3539 *
3540 *  Clocks in/out one bit via I2C data/clock
3541 **/
3542STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3543{
3544	s32 status = E1000_SUCCESS;
3545	u32 i = 0;
3546	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3547	u32 timeout = 10;
3548	bool ack = true;
3549
3550	DEBUGFUNC("e1000_get_i2c_ack");
3551
3552	e1000_raise_i2c_clk(hw, &i2cctl);
3553
3554	/* Minimum high period of clock is 4us */
3555	usec_delay(E1000_I2C_T_HIGH);
3556
3557	/* Wait until SCL returns high */
3558	for (i = 0; i < timeout; i++) {
3559		usec_delay(1);
3560		i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3561		if (i2cctl & E1000_I2C_CLK_IN)
3562			break;
3563	}
3564	if (!(i2cctl & E1000_I2C_CLK_IN))
3565		return E1000_ERR_I2C;
3566
3567	ack = e1000_get_i2c_data(&i2cctl);
3568	if (ack) {
3569		DEBUGOUT("I2C ack was not received.\n");
3570		status = E1000_ERR_I2C;
3571	}
3572
3573	e1000_lower_i2c_clk(hw, &i2cctl);
3574
3575	/* Minimum low period of clock is 4.7 us */
3576	usec_delay(E1000_I2C_T_LOW);
3577
3578	return status;
3579}
3580
3581/**
3582 *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3583 *  @hw: pointer to hardware structure
3584 *  @data: read data value
3585 *
3586 *  Clocks in one bit via I2C data/clock
3587 **/
3588STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3589{
3590	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3591
3592	DEBUGFUNC("e1000_clock_in_i2c_bit");
3593
3594	e1000_raise_i2c_clk(hw, &i2cctl);
3595
3596	/* Minimum high period of clock is 4us */
3597	usec_delay(E1000_I2C_T_HIGH);
3598
3599	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3600	*data = e1000_get_i2c_data(&i2cctl);
3601
3602	e1000_lower_i2c_clk(hw, &i2cctl);
3603
3604	/* Minimum low period of clock is 4.7 us */
3605	usec_delay(E1000_I2C_T_LOW);
3606
3607	return E1000_SUCCESS;
3608}
3609
3610/**
3611 *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3612 *  @hw: pointer to hardware structure
3613 *  @data: data value to write
3614 *
3615 *  Clocks out one bit via I2C data/clock
3616 **/
3617STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3618{
3619	s32 status;
3620	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3621
3622	DEBUGFUNC("e1000_clock_out_i2c_bit");
3623
3624	status = e1000_set_i2c_data(hw, &i2cctl, data);
3625	if (status == E1000_SUCCESS) {
3626		e1000_raise_i2c_clk(hw, &i2cctl);
3627
3628		/* Minimum high period of clock is 4us */
3629		usec_delay(E1000_I2C_T_HIGH);
3630
3631		e1000_lower_i2c_clk(hw, &i2cctl);
3632
3633		/* Minimum low period of clock is 4.7 us.
3634		 * This also takes care of the data hold time.
3635		 */
3636		usec_delay(E1000_I2C_T_LOW);
3637	} else {
3638		status = E1000_ERR_I2C;
3639		DEBUGOUT1("I2C data was not set to %X\n", data);
3640	}
3641
3642	return status;
3643}
3644/**
3645 *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3646 *  @hw: pointer to hardware structure
3647 *  @i2cctl: Current value of I2CCTL register
3648 *
3649 *  Raises the I2C clock line '0'->'1'
3650 **/
3651STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3652{
3653	DEBUGFUNC("e1000_raise_i2c_clk");
3654
3655	*i2cctl |= E1000_I2C_CLK_OUT;
3656	*i2cctl &= ~E1000_I2C_CLK_OE_N;
3657	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3658	E1000_WRITE_FLUSH(hw);
3659
3660	/* SCL rise time (1000ns) */
3661	usec_delay(E1000_I2C_T_RISE);
3662}
3663
3664/**
3665 *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3666 *  @hw: pointer to hardware structure
3667 *  @i2cctl: Current value of I2CCTL register
3668 *
3669 *  Lowers the I2C clock line '1'->'0'
3670 **/
3671STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3672{
3673
3674	DEBUGFUNC("e1000_lower_i2c_clk");
3675
3676	*i2cctl &= ~E1000_I2C_CLK_OUT;
3677	*i2cctl &= ~E1000_I2C_CLK_OE_N;
3678	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3679	E1000_WRITE_FLUSH(hw);
3680
3681	/* SCL fall time (300ns) */
3682	usec_delay(E1000_I2C_T_FALL);
3683}
3684
3685/**
3686 *  e1000_set_i2c_data - Sets the I2C data bit
3687 *  @hw: pointer to hardware structure
3688 *  @i2cctl: Current value of I2CCTL register
3689 *  @data: I2C data value (0 or 1) to set
3690 *
3691 *  Sets the I2C data bit
3692 **/
3693STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3694{
3695	s32 status = E1000_SUCCESS;
3696
3697	DEBUGFUNC("e1000_set_i2c_data");
3698
3699	if (data)
3700		*i2cctl |= E1000_I2C_DATA_OUT;
3701	else
3702		*i2cctl &= ~E1000_I2C_DATA_OUT;
3703
3704	*i2cctl &= ~E1000_I2C_DATA_OE_N;
3705	*i2cctl |= E1000_I2C_CLK_OE_N;
3706	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3707	E1000_WRITE_FLUSH(hw);
3708
3709	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3710	usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3711
3712	*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3713	if (data != e1000_get_i2c_data(i2cctl)) {
3714		status = E1000_ERR_I2C;
3715		DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3716	}
3717
3718	return status;
3719}
3720
3721/**
3722 *  e1000_get_i2c_data - Reads the I2C SDA data bit
3723 *  @hw: pointer to hardware structure
3724 *  @i2cctl: Current value of I2CCTL register
3725 *
3726 *  Returns the I2C data bit value
3727 **/
3728STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3729{
3730	bool data;
3731
3732	DEBUGFUNC("e1000_get_i2c_data");
3733
3734	if (*i2cctl & E1000_I2C_DATA_IN)
3735		data = 1;
3736	else
3737		data = 0;
3738
3739	return data;
3740}
3741
3742/**
3743 *  e1000_i2c_bus_clear - Clears the I2C bus
3744 *  @hw: pointer to hardware structure
3745 *
3746 *  Clears the I2C bus by sending nine clock pulses.
3747 *  Used when data line is stuck low.
3748 **/
3749void e1000_i2c_bus_clear(struct e1000_hw *hw)
3750{
3751	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3752	u32 i;
3753
3754	DEBUGFUNC("e1000_i2c_bus_clear");
3755
3756	e1000_i2c_start(hw);
3757
3758	e1000_set_i2c_data(hw, &i2cctl, 1);
3759
3760	for (i = 0; i < 9; i++) {
3761		e1000_raise_i2c_clk(hw, &i2cctl);
3762
3763		/* Min high period of clock is 4us */
3764		usec_delay(E1000_I2C_T_HIGH);
3765
3766		e1000_lower_i2c_clk(hw, &i2cctl);
3767
3768		/* Min low period of clock is 4.7us*/
3769		usec_delay(E1000_I2C_T_LOW);
3770	}
3771
3772	e1000_i2c_start(hw);
3773
3774	/* Put the i2c bus back to default state */
3775	e1000_i2c_stop(hw);
3776}
3777
3778