1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/*
35a551c94aSIdo Barnea * 82575EB Gigabit Network Connection
36a551c94aSIdo Barnea * 82575EB Gigabit Backplane Connection
37a551c94aSIdo Barnea * 82575GB Gigabit Network Connection
38a551c94aSIdo Barnea * 82576 Gigabit Network Connection
39a551c94aSIdo Barnea * 82576 Quad Port Gigabit Mezzanine Adapter
40a551c94aSIdo Barnea * 82580 Gigabit Network Connection
41a551c94aSIdo Barnea * I350 Gigabit Network Connection
42a551c94aSIdo Barnea */
43a551c94aSIdo Barnea
44a551c94aSIdo Barnea#include "e1000_api.h"
45a551c94aSIdo Barnea#include "e1000_i210.h"
46a551c94aSIdo Barnea
47a551c94aSIdo BarneaSTATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
48a551c94aSIdo BarneaSTATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
49a551c94aSIdo BarneaSTATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
50a551c94aSIdo BarneaSTATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51a551c94aSIdo BarneaSTATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
52a551c94aSIdo BarneaSTATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53a551c94aSIdo BarneaSTATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
54a551c94aSIdo BarneaSTATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
55a551c94aSIdo BarneaSTATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
56a551c94aSIdo BarneaSTATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57a551c94aSIdo Barnea					 u16 *duplex);
58a551c94aSIdo BarneaSTATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59a551c94aSIdo BarneaSTATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60a551c94aSIdo Barnea					   u16 *data);
61a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
62a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
63a551c94aSIdo BarneaSTATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
64a551c94aSIdo Barnea				     u32 offset, u16 *data);
65a551c94aSIdo BarneaSTATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
66a551c94aSIdo Barnea				      u32 offset, u16 data);
67a551c94aSIdo BarneaSTATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
68a551c94aSIdo Barnea					  bool active);
69a551c94aSIdo BarneaSTATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
70a551c94aSIdo Barnea					  bool active);
71a551c94aSIdo BarneaSTATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
72a551c94aSIdo Barnea					  bool active);
73a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
74a551c94aSIdo BarneaSTATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75a551c94aSIdo BarneaSTATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
76a551c94aSIdo BarneaSTATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77a551c94aSIdo BarneaSTATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78a551c94aSIdo BarneaSTATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79a551c94aSIdo Barnea					    u32 offset, u16 data);
80a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81a551c94aSIdo BarneaSTATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82a551c94aSIdo BarneaSTATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83a551c94aSIdo Barnea						 u16 *speed, u16 *duplex);
84a551c94aSIdo BarneaSTATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
85a551c94aSIdo BarneaSTATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86a551c94aSIdo BarneaSTATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87a551c94aSIdo BarneaSTATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
88a551c94aSIdo BarneaSTATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
89a551c94aSIdo BarneaSTATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91a551c94aSIdo BarneaSTATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92a551c94aSIdo BarneaSTATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93a551c94aSIdo BarneaSTATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94a551c94aSIdo BarneaSTATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95a551c94aSIdo BarneaSTATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96a551c94aSIdo BarneaSTATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97a551c94aSIdo BarneaSTATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
98a551c94aSIdo Barnea						 u16 offset);
99a551c94aSIdo BarneaSTATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
100a551c94aSIdo Barnea						   u16 offset);
101a551c94aSIdo BarneaSTATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102a551c94aSIdo BarneaSTATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103a551c94aSIdo BarneaSTATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
104a551c94aSIdo Barnea
105a551c94aSIdo BarneaSTATIC void e1000_i2c_start(struct e1000_hw *hw);
106a551c94aSIdo BarneaSTATIC void e1000_i2c_stop(struct e1000_hw *hw);
107a551c94aSIdo BarneaSTATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
108a551c94aSIdo BarneaSTATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
109a551c94aSIdo BarneaSTATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
110a551c94aSIdo BarneaSTATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
111a551c94aSIdo BarneaSTATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
112a551c94aSIdo BarneaSTATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
113a551c94aSIdo BarneaSTATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114a551c94aSIdo BarneaSTATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
115a551c94aSIdo BarneaSTATIC bool e1000_get_i2c_data(u32 *i2cctl);
116a551c94aSIdo Barnea
117a551c94aSIdo BarneaSTATIC const u16 e1000_82580_rxpbs_table[] = {
118a551c94aSIdo Barnea	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
119a551c94aSIdo Barnea#define E1000_82580_RXPBS_TABLE_SIZE \
120a551c94aSIdo Barnea	(sizeof(e1000_82580_rxpbs_table) / \
121a551c94aSIdo Barnea	 sizeof(e1000_82580_rxpbs_table[0]))
122a551c94aSIdo Barnea
123a551c94aSIdo Barnea
124a551c94aSIdo Barnea/**
125a551c94aSIdo Barnea *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
126a551c94aSIdo Barnea *  @hw: pointer to the HW structure
127a551c94aSIdo Barnea *
128a551c94aSIdo Barnea *  Called to determine if the I2C pins are being used for I2C or as an
129a551c94aSIdo Barnea *  external MDIO interface since the two options are mutually exclusive.
130a551c94aSIdo Barnea **/
131a551c94aSIdo BarneaSTATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
132a551c94aSIdo Barnea{
133a551c94aSIdo Barnea	u32 reg = 0;
134a551c94aSIdo Barnea	bool ext_mdio = false;
135a551c94aSIdo Barnea
136a551c94aSIdo Barnea	DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
137a551c94aSIdo Barnea
138a551c94aSIdo Barnea	switch (hw->mac.type) {
139a551c94aSIdo Barnea	case e1000_82575:
140a551c94aSIdo Barnea	case e1000_82576:
141a551c94aSIdo Barnea		reg = E1000_READ_REG(hw, E1000_MDIC);
142a551c94aSIdo Barnea		ext_mdio = !!(reg & E1000_MDIC_DEST);
143a551c94aSIdo Barnea		break;
144a551c94aSIdo Barnea	case e1000_82580:
145a551c94aSIdo Barnea	case e1000_i350:
146a551c94aSIdo Barnea	case e1000_i354:
147a551c94aSIdo Barnea	case e1000_i210:
148a551c94aSIdo Barnea	case e1000_i211:
149a551c94aSIdo Barnea		reg = E1000_READ_REG(hw, E1000_MDICNFG);
150a551c94aSIdo Barnea		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
151a551c94aSIdo Barnea		break;
152a551c94aSIdo Barnea	default:
153a551c94aSIdo Barnea		break;
154a551c94aSIdo Barnea	}
155a551c94aSIdo Barnea	return ext_mdio;
156a551c94aSIdo Barnea}
157a551c94aSIdo Barnea
158a551c94aSIdo Barnea/**
159a551c94aSIdo Barnea *  e1000_init_phy_params_82575 - Init PHY func ptrs.
160a551c94aSIdo Barnea *  @hw: pointer to the HW structure
161a551c94aSIdo Barnea **/
162a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
163a551c94aSIdo Barnea{
164a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
165a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
166a551c94aSIdo Barnea	u32 ctrl_ext;
167a551c94aSIdo Barnea
168a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_82575");
169a551c94aSIdo Barnea
170a551c94aSIdo Barnea	phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171a551c94aSIdo Barnea	phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
172a551c94aSIdo Barnea
173a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper) {
174a551c94aSIdo Barnea		phy->type = e1000_phy_none;
175a551c94aSIdo Barnea		goto out;
176a551c94aSIdo Barnea	}
177a551c94aSIdo Barnea
178a551c94aSIdo Barnea	phy->ops.power_up   = e1000_power_up_phy_copper;
179a551c94aSIdo Barnea	phy->ops.power_down = e1000_power_down_phy_copper_82575;
180a551c94aSIdo Barnea
181a551c94aSIdo Barnea	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
182a551c94aSIdo Barnea	phy->reset_delay_us	= 100;
183a551c94aSIdo Barnea
184a551c94aSIdo Barnea	phy->ops.acquire	= e1000_acquire_phy_82575;
185a551c94aSIdo Barnea	phy->ops.check_reset_block = e1000_check_reset_block_generic;
186a551c94aSIdo Barnea	phy->ops.commit		= e1000_phy_sw_reset_generic;
187a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_82575;
188a551c94aSIdo Barnea	phy->ops.release	= e1000_release_phy_82575;
189a551c94aSIdo Barnea
190a551c94aSIdo Barnea	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
191a551c94aSIdo Barnea
192a551c94aSIdo Barnea	if (e1000_sgmii_active_82575(hw)) {
193a551c94aSIdo Barnea		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194a551c94aSIdo Barnea		ctrl_ext |= E1000_CTRL_I2C_ENA;
195a551c94aSIdo Barnea	} else {
196a551c94aSIdo Barnea		phy->ops.reset = e1000_phy_hw_reset_generic;
197a551c94aSIdo Barnea		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
198a551c94aSIdo Barnea	}
199a551c94aSIdo Barnea
200a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201a551c94aSIdo Barnea	e1000_reset_mdicnfg_82580(hw);
202a551c94aSIdo Barnea
203a551c94aSIdo Barnea	if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204a551c94aSIdo Barnea		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205a551c94aSIdo Barnea		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
206a551c94aSIdo Barnea	} else {
207a551c94aSIdo Barnea		switch (hw->mac.type) {
208a551c94aSIdo Barnea		case e1000_82580:
209a551c94aSIdo Barnea		case e1000_i350:
210a551c94aSIdo Barnea		case e1000_i354:
211a551c94aSIdo Barnea			phy->ops.read_reg = e1000_read_phy_reg_82580;
212a551c94aSIdo Barnea			phy->ops.write_reg = e1000_write_phy_reg_82580;
213a551c94aSIdo Barnea			break;
214a551c94aSIdo Barnea		case e1000_i210:
215a551c94aSIdo Barnea		case e1000_i211:
216a551c94aSIdo Barnea			phy->ops.read_reg = e1000_read_phy_reg_gs40g;
217a551c94aSIdo Barnea			phy->ops.write_reg = e1000_write_phy_reg_gs40g;
218a551c94aSIdo Barnea			break;
219a551c94aSIdo Barnea		default:
220a551c94aSIdo Barnea			phy->ops.read_reg = e1000_read_phy_reg_igp;
221a551c94aSIdo Barnea			phy->ops.write_reg = e1000_write_phy_reg_igp;
222a551c94aSIdo Barnea		}
223a551c94aSIdo Barnea	}
224a551c94aSIdo Barnea
225a551c94aSIdo Barnea	/* Set phy->phy_addr and phy->id. */
226a551c94aSIdo Barnea	ret_val = e1000_get_phy_id_82575(hw);
227a551c94aSIdo Barnea
228a551c94aSIdo Barnea	/* Verify phy id and set remaining function pointers */
229a551c94aSIdo Barnea	switch (phy->id) {
230a551c94aSIdo Barnea	case M88E1543_E_PHY_ID:
231a551c94aSIdo Barnea	case M88E1512_E_PHY_ID:
232a551c94aSIdo Barnea	case I347AT4_E_PHY_ID:
233a551c94aSIdo Barnea	case M88E1112_E_PHY_ID:
234a551c94aSIdo Barnea	case M88E1340M_E_PHY_ID:
235a551c94aSIdo Barnea	case M88E1111_I_PHY_ID:
236a551c94aSIdo Barnea		phy->type		= e1000_phy_m88;
237a551c94aSIdo Barnea		phy->ops.check_polarity	= e1000_check_polarity_m88;
238a551c94aSIdo Barnea		phy->ops.get_info	= e1000_get_phy_info_m88;
239a551c94aSIdo Barnea		if (phy->id == I347AT4_E_PHY_ID ||
240a551c94aSIdo Barnea		    phy->id == M88E1112_E_PHY_ID ||
241a551c94aSIdo Barnea		    phy->id == M88E1340M_E_PHY_ID)
242a551c94aSIdo Barnea			phy->ops.get_cable_length =
243a551c94aSIdo Barnea					 e1000_get_cable_length_m88_gen2;
244a551c94aSIdo Barnea		else if (phy->id == M88E1543_E_PHY_ID ||
245a551c94aSIdo Barnea			 phy->id == M88E1512_E_PHY_ID)
246a551c94aSIdo Barnea			phy->ops.get_cable_length =
247a551c94aSIdo Barnea					 e1000_get_cable_length_m88_gen2;
248a551c94aSIdo Barnea		else
249a551c94aSIdo Barnea			phy->ops.get_cable_length = e1000_get_cable_length_m88;
250a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
251a551c94aSIdo Barnea		/* Check if this PHY is confgured for media swap. */
252a551c94aSIdo Barnea		if (phy->id == M88E1112_E_PHY_ID) {
253a551c94aSIdo Barnea			u16 data;
254a551c94aSIdo Barnea
255a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw,
256a551c94aSIdo Barnea						     E1000_M88E1112_PAGE_ADDR,
257a551c94aSIdo Barnea						     2);
258a551c94aSIdo Barnea			if (ret_val)
259a551c94aSIdo Barnea				goto out;
260a551c94aSIdo Barnea
261a551c94aSIdo Barnea			ret_val = phy->ops.read_reg(hw,
262a551c94aSIdo Barnea						    E1000_M88E1112_MAC_CTRL_1,
263a551c94aSIdo Barnea						    &data);
264a551c94aSIdo Barnea			if (ret_val)
265a551c94aSIdo Barnea				goto out;
266a551c94aSIdo Barnea
267a551c94aSIdo Barnea			data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
268a551c94aSIdo Barnea			       E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
269a551c94aSIdo Barnea			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
270a551c94aSIdo Barnea			    data == E1000_M88E1112_AUTO_COPPER_BASEX)
271a551c94aSIdo Barnea				hw->mac.ops.check_for_link =
272a551c94aSIdo Barnea						e1000_check_for_link_media_swap;
273a551c94aSIdo Barnea		}
274a551c94aSIdo Barnea		if (phy->id == M88E1512_E_PHY_ID) {
275a551c94aSIdo Barnea			ret_val = e1000_initialize_M88E1512_phy(hw);
276a551c94aSIdo Barnea			if (ret_val)
277a551c94aSIdo Barnea				goto out;
278a551c94aSIdo Barnea		}
279a551c94aSIdo Barnea		if (phy->id == M88E1543_E_PHY_ID) {
280a551c94aSIdo Barnea			ret_val = e1000_initialize_M88E1543_phy(hw);
281a551c94aSIdo Barnea			if (ret_val)
282a551c94aSIdo Barnea				goto out;
283a551c94aSIdo Barnea		}
284a551c94aSIdo Barnea		break;
285a551c94aSIdo Barnea	case IGP03E1000_E_PHY_ID:
286a551c94aSIdo Barnea	case IGP04E1000_E_PHY_ID:
287a551c94aSIdo Barnea		phy->type = e1000_phy_igp_3;
288a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_igp;
289a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_igp;
290a551c94aSIdo Barnea		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
291a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
292a551c94aSIdo Barnea		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
293a551c94aSIdo Barnea		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
294a551c94aSIdo Barnea		break;
295a551c94aSIdo Barnea	case I82580_I_PHY_ID:
296a551c94aSIdo Barnea	case I350_I_PHY_ID:
297a551c94aSIdo Barnea		phy->type = e1000_phy_82580;
298a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_82577;
299a551c94aSIdo Barnea		phy->ops.force_speed_duplex =
300a551c94aSIdo Barnea					 e1000_phy_force_speed_duplex_82577;
301a551c94aSIdo Barnea		phy->ops.get_cable_length = e1000_get_cable_length_82577;
302a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_82577;
303a551c94aSIdo Barnea		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304a551c94aSIdo Barnea		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
305a551c94aSIdo Barnea		break;
306a551c94aSIdo Barnea	case I210_I_PHY_ID:
307a551c94aSIdo Barnea		phy->type		= e1000_phy_i210;
308a551c94aSIdo Barnea		phy->ops.check_polarity	= e1000_check_polarity_m88;
309a551c94aSIdo Barnea		phy->ops.get_info	= e1000_get_phy_info_m88;
310a551c94aSIdo Barnea		phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
311a551c94aSIdo Barnea		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
312a551c94aSIdo Barnea		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
313a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
314a551c94aSIdo Barnea		break;
315a551c94aSIdo Barnea	default:
316a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
317a551c94aSIdo Barnea		goto out;
318a551c94aSIdo Barnea	}
319a551c94aSIdo Barnea
320a551c94aSIdo Barneaout:
321a551c94aSIdo Barnea	return ret_val;
322a551c94aSIdo Barnea}
323a551c94aSIdo Barnea
324a551c94aSIdo Barnea/**
325a551c94aSIdo Barnea *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
326a551c94aSIdo Barnea *  @hw: pointer to the HW structure
327a551c94aSIdo Barnea **/
328a551c94aSIdo Barneas32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
329a551c94aSIdo Barnea{
330a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
331a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
332a551c94aSIdo Barnea	u16 size;
333a551c94aSIdo Barnea
334a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_82575");
335a551c94aSIdo Barnea
336a551c94aSIdo Barnea	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
337a551c94aSIdo Barnea		     E1000_EECD_SIZE_EX_SHIFT);
338a551c94aSIdo Barnea	/*
339a551c94aSIdo Barnea	 * Added to a constant, "size" becomes the left-shift value
340a551c94aSIdo Barnea	 * for setting word_size.
341a551c94aSIdo Barnea	 */
342a551c94aSIdo Barnea	size += NVM_WORD_SIZE_BASE_SHIFT;
343a551c94aSIdo Barnea
344a551c94aSIdo Barnea	/* Just in case size is out of range, cap it to the largest
345a551c94aSIdo Barnea	 * EEPROM size supported
346a551c94aSIdo Barnea	 */
347a551c94aSIdo Barnea	if (size > 15)
348a551c94aSIdo Barnea		size = 15;
349a551c94aSIdo Barnea
350a551c94aSIdo Barnea	nvm->word_size = 1 << size;
351a551c94aSIdo Barnea	if (hw->mac.type < e1000_i210) {
352a551c94aSIdo Barnea		nvm->opcode_bits = 8;
353a551c94aSIdo Barnea		nvm->delay_usec = 1;
354a551c94aSIdo Barnea
355a551c94aSIdo Barnea		switch (nvm->override) {
356a551c94aSIdo Barnea		case e1000_nvm_override_spi_large:
357a551c94aSIdo Barnea			nvm->page_size = 32;
358a551c94aSIdo Barnea			nvm->address_bits = 16;
359a551c94aSIdo Barnea			break;
360a551c94aSIdo Barnea		case e1000_nvm_override_spi_small:
361a551c94aSIdo Barnea			nvm->page_size = 8;
362a551c94aSIdo Barnea			nvm->address_bits = 8;
363a551c94aSIdo Barnea			break;
364a551c94aSIdo Barnea		default:
365a551c94aSIdo Barnea			nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
366a551c94aSIdo Barnea			nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
367a551c94aSIdo Barnea					    16 : 8;
368a551c94aSIdo Barnea			break;
369a551c94aSIdo Barnea		}
370a551c94aSIdo Barnea		if (nvm->word_size == (1 << 15))
371a551c94aSIdo Barnea			nvm->page_size = 128;
372a551c94aSIdo Barnea
373a551c94aSIdo Barnea		nvm->type = e1000_nvm_eeprom_spi;
374a551c94aSIdo Barnea	} else {
375a551c94aSIdo Barnea		nvm->type = e1000_nvm_flash_hw;
376a551c94aSIdo Barnea	}
377a551c94aSIdo Barnea
378a551c94aSIdo Barnea	/* Function Pointers */
379a551c94aSIdo Barnea	nvm->ops.acquire = e1000_acquire_nvm_82575;
380a551c94aSIdo Barnea	nvm->ops.release = e1000_release_nvm_82575;
381a551c94aSIdo Barnea	if (nvm->word_size < (1 << 15))
382a551c94aSIdo Barnea		nvm->ops.read = e1000_read_nvm_eerd;
383a551c94aSIdo Barnea	else
384a551c94aSIdo Barnea		nvm->ops.read = e1000_read_nvm_spi;
385a551c94aSIdo Barnea
386a551c94aSIdo Barnea	nvm->ops.write = e1000_write_nvm_spi;
387a551c94aSIdo Barnea	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
388a551c94aSIdo Barnea	nvm->ops.update = e1000_update_nvm_checksum_generic;
389a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
390a551c94aSIdo Barnea
391a551c94aSIdo Barnea	/* override generic family function pointers for specific descendants */
392a551c94aSIdo Barnea	switch (hw->mac.type) {
393a551c94aSIdo Barnea	case e1000_82580:
394a551c94aSIdo Barnea		nvm->ops.validate = e1000_validate_nvm_checksum_82580;
395a551c94aSIdo Barnea		nvm->ops.update = e1000_update_nvm_checksum_82580;
396a551c94aSIdo Barnea		break;
397a551c94aSIdo Barnea	case e1000_i350:
398a551c94aSIdo Barnea	case e1000_i354:
399a551c94aSIdo Barnea		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
400a551c94aSIdo Barnea		nvm->ops.update = e1000_update_nvm_checksum_i350;
401a551c94aSIdo Barnea		break;
402a551c94aSIdo Barnea	default:
403a551c94aSIdo Barnea		break;
404a551c94aSIdo Barnea	}
405a551c94aSIdo Barnea
406a551c94aSIdo Barnea	return E1000_SUCCESS;
407a551c94aSIdo Barnea}
408a551c94aSIdo Barnea
409a551c94aSIdo Barnea/**
410a551c94aSIdo Barnea *  e1000_init_mac_params_82575 - Init MAC func ptrs.
411a551c94aSIdo Barnea *  @hw: pointer to the HW structure
412a551c94aSIdo Barnea **/
413a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
414a551c94aSIdo Barnea{
415a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
416a551c94aSIdo Barnea	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
417a551c94aSIdo Barnea
418a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_82575");
419a551c94aSIdo Barnea
420a551c94aSIdo Barnea	/* Derives media type */
421a551c94aSIdo Barnea	e1000_get_media_type_82575(hw);
422a551c94aSIdo Barnea	/* Set mta register count */
423a551c94aSIdo Barnea	mac->mta_reg_count = 128;
424a551c94aSIdo Barnea	/* Set uta register count */
425a551c94aSIdo Barnea	mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
426a551c94aSIdo Barnea	/* Set rar entry count */
427a551c94aSIdo Barnea	mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
428a551c94aSIdo Barnea	if (mac->type == e1000_82576)
429a551c94aSIdo Barnea		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
430a551c94aSIdo Barnea	if (mac->type == e1000_82580)
431a551c94aSIdo Barnea		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
432a551c94aSIdo Barnea	if (mac->type == e1000_i350 || mac->type == e1000_i354)
433a551c94aSIdo Barnea		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
434a551c94aSIdo Barnea
435a551c94aSIdo Barnea	/* Enable EEE default settings for EEE supported devices */
436a551c94aSIdo Barnea	if (mac->type >= e1000_i350)
437a551c94aSIdo Barnea		dev_spec->eee_disable = false;
438a551c94aSIdo Barnea
439a551c94aSIdo Barnea	/* Allow a single clear of the SW semaphore on I210 and newer */
440a551c94aSIdo Barnea	if (mac->type >= e1000_i210)
441a551c94aSIdo Barnea		dev_spec->clear_semaphore_once = true;
442a551c94aSIdo Barnea
443a551c94aSIdo Barnea	/* Set if part includes ASF firmware */
444a551c94aSIdo Barnea	mac->asf_firmware_present = true;
445a551c94aSIdo Barnea	/* FWSM register */
446a551c94aSIdo Barnea	mac->has_fwsm = true;
447a551c94aSIdo Barnea	/* ARC supported; valid only if manageability features are enabled. */
448a551c94aSIdo Barnea	mac->arc_subsystem_valid =
449a551c94aSIdo Barnea		!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
450a551c94aSIdo Barnea
451a551c94aSIdo Barnea	/* Function pointers */
452a551c94aSIdo Barnea
453a551c94aSIdo Barnea	/* bus type/speed/width */
454a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
455a551c94aSIdo Barnea	/* reset */
456a551c94aSIdo Barnea	if (mac->type >= e1000_82580)
457a551c94aSIdo Barnea		mac->ops.reset_hw = e1000_reset_hw_82580;
458a551c94aSIdo Barnea	else
459a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_82575;
460a551c94aSIdo Barnea	/* hw initialization */
461a551c94aSIdo Barnea	if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
462a551c94aSIdo Barnea		mac->ops.init_hw = e1000_init_hw_i210;
463a551c94aSIdo Barnea	else
464a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_82575;
465a551c94aSIdo Barnea	/* link setup */
466a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_generic;
467a551c94aSIdo Barnea	/* physical interface link setup */
468a551c94aSIdo Barnea	mac->ops.setup_physical_interface =
469a551c94aSIdo Barnea		(hw->phy.media_type == e1000_media_type_copper)
470a551c94aSIdo Barnea		? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
471a551c94aSIdo Barnea	/* physical interface shutdown */
472a551c94aSIdo Barnea	mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
473a551c94aSIdo Barnea	/* physical interface power up */
474a551c94aSIdo Barnea	mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
475a551c94aSIdo Barnea	/* check for link */
476a551c94aSIdo Barnea	mac->ops.check_for_link = e1000_check_for_link_82575;
477a551c94aSIdo Barnea	/* read mac address */
478a551c94aSIdo Barnea	mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
479a551c94aSIdo Barnea	/* configure collision distance */
480a551c94aSIdo Barnea	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
481a551c94aSIdo Barnea	/* multicast address update */
482a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
483a551c94aSIdo Barnea	if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
484a551c94aSIdo Barnea		/* writing VFTA */
485a551c94aSIdo Barnea		mac->ops.write_vfta = e1000_write_vfta_i350;
486a551c94aSIdo Barnea		/* clearing VFTA */
487a551c94aSIdo Barnea		mac->ops.clear_vfta = e1000_clear_vfta_i350;
488a551c94aSIdo Barnea	} else {
489a551c94aSIdo Barnea		/* writing VFTA */
490a551c94aSIdo Barnea		mac->ops.write_vfta = e1000_write_vfta_generic;
491a551c94aSIdo Barnea		/* clearing VFTA */
492a551c94aSIdo Barnea		mac->ops.clear_vfta = e1000_clear_vfta_generic;
493a551c94aSIdo Barnea	}
494a551c94aSIdo Barnea	if (hw->mac.type >= e1000_82580)
495a551c94aSIdo Barnea		mac->ops.validate_mdi_setting =
496a551c94aSIdo Barnea				e1000_validate_mdi_setting_crossover_generic;
497a551c94aSIdo Barnea	/* ID LED init */
498a551c94aSIdo Barnea	mac->ops.id_led_init = e1000_id_led_init_generic;
499a551c94aSIdo Barnea	/* blink LED */
500a551c94aSIdo Barnea	mac->ops.blink_led = e1000_blink_led_generic;
501a551c94aSIdo Barnea	/* setup LED */
502a551c94aSIdo Barnea	mac->ops.setup_led = e1000_setup_led_generic;
503a551c94aSIdo Barnea	/* cleanup LED */
504a551c94aSIdo Barnea	mac->ops.cleanup_led = e1000_cleanup_led_generic;
505a551c94aSIdo Barnea	/* turn on/off LED */
506a551c94aSIdo Barnea	mac->ops.led_on = e1000_led_on_generic;
507a551c94aSIdo Barnea	mac->ops.led_off = e1000_led_off_generic;
508a551c94aSIdo Barnea	/* clear hardware counters */
509a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
510a551c94aSIdo Barnea	/* link info */
511a551c94aSIdo Barnea	mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
512a551c94aSIdo Barnea	/* acquire SW_FW sync */
513a551c94aSIdo Barnea	mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
514a551c94aSIdo Barnea	mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
515a551c94aSIdo Barnea	if (mac->type >= e1000_i210) {
516a551c94aSIdo Barnea		mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
517a551c94aSIdo Barnea		mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
518a551c94aSIdo Barnea	}
519a551c94aSIdo Barnea
520a551c94aSIdo Barnea	/* set lan id for port to determine which phy lock to use */
521a551c94aSIdo Barnea	hw->mac.ops.set_lan_id(hw);
522a551c94aSIdo Barnea
523a551c94aSIdo Barnea	return E1000_SUCCESS;
524a551c94aSIdo Barnea}
525a551c94aSIdo Barnea
526a551c94aSIdo Barnea/**
527a551c94aSIdo Barnea *  e1000_init_function_pointers_82575 - Init func ptrs.
528a551c94aSIdo Barnea *  @hw: pointer to the HW structure
529a551c94aSIdo Barnea *
530a551c94aSIdo Barnea *  Called to initialize all function pointers and parameters.
531a551c94aSIdo Barnea **/
532a551c94aSIdo Barneavoid e1000_init_function_pointers_82575(struct e1000_hw *hw)
533a551c94aSIdo Barnea{
534a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_function_pointers_82575");
535a551c94aSIdo Barnea
536a551c94aSIdo Barnea	hw->mac.ops.init_params = e1000_init_mac_params_82575;
537a551c94aSIdo Barnea	hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
538a551c94aSIdo Barnea	hw->phy.ops.init_params = e1000_init_phy_params_82575;
539a551c94aSIdo Barnea	hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
540a551c94aSIdo Barnea}
541a551c94aSIdo Barnea
542a551c94aSIdo Barnea/**
543a551c94aSIdo Barnea *  e1000_acquire_phy_82575 - Acquire rights to access PHY
544a551c94aSIdo Barnea *  @hw: pointer to the HW structure
545a551c94aSIdo Barnea *
546a551c94aSIdo Barnea *  Acquire access rights to the correct PHY.
547a551c94aSIdo Barnea **/
548a551c94aSIdo BarneaSTATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
549a551c94aSIdo Barnea{
550a551c94aSIdo Barnea	u16 mask = E1000_SWFW_PHY0_SM;
551a551c94aSIdo Barnea
552a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_phy_82575");
553a551c94aSIdo Barnea
554a551c94aSIdo Barnea	if (hw->bus.func == E1000_FUNC_1)
555a551c94aSIdo Barnea		mask = E1000_SWFW_PHY1_SM;
556a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_2)
557a551c94aSIdo Barnea		mask = E1000_SWFW_PHY2_SM;
558a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_3)
559a551c94aSIdo Barnea		mask = E1000_SWFW_PHY3_SM;
560a551c94aSIdo Barnea
561a551c94aSIdo Barnea	return hw->mac.ops.acquire_swfw_sync(hw, mask);
562a551c94aSIdo Barnea}
563a551c94aSIdo Barnea
564a551c94aSIdo Barnea/**
565a551c94aSIdo Barnea *  e1000_release_phy_82575 - Release rights to access PHY
566a551c94aSIdo Barnea *  @hw: pointer to the HW structure
567a551c94aSIdo Barnea *
568a551c94aSIdo Barnea *  A wrapper to release access rights to the correct PHY.
569a551c94aSIdo Barnea **/
570a551c94aSIdo BarneaSTATIC void e1000_release_phy_82575(struct e1000_hw *hw)
571a551c94aSIdo Barnea{
572a551c94aSIdo Barnea	u16 mask = E1000_SWFW_PHY0_SM;
573a551c94aSIdo Barnea
574a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_phy_82575");
575a551c94aSIdo Barnea
576a551c94aSIdo Barnea	if (hw->bus.func == E1000_FUNC_1)
577a551c94aSIdo Barnea		mask = E1000_SWFW_PHY1_SM;
578a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_2)
579a551c94aSIdo Barnea		mask = E1000_SWFW_PHY2_SM;
580a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_3)
581a551c94aSIdo Barnea		mask = E1000_SWFW_PHY3_SM;
582a551c94aSIdo Barnea
583a551c94aSIdo Barnea	hw->mac.ops.release_swfw_sync(hw, mask);
584a551c94aSIdo Barnea}
585a551c94aSIdo Barnea
586a551c94aSIdo Barnea/**
587a551c94aSIdo Barnea *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
588a551c94aSIdo Barnea *  @hw: pointer to the HW structure
589a551c94aSIdo Barnea *  @offset: register offset to be read
590a551c94aSIdo Barnea *  @data: pointer to the read data
591a551c94aSIdo Barnea *
592a551c94aSIdo Barnea *  Reads the PHY register at offset using the serial gigabit media independent
593a551c94aSIdo Barnea *  interface and stores the retrieved information in data.
594a551c94aSIdo Barnea **/
595a551c94aSIdo BarneaSTATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
596a551c94aSIdo Barnea					  u16 *data)
597a551c94aSIdo Barnea{
598a551c94aSIdo Barnea	s32 ret_val = -E1000_ERR_PARAM;
599a551c94aSIdo Barnea
600a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
601a551c94aSIdo Barnea
602a551c94aSIdo Barnea	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
603a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %u is out of range\n", offset);
604a551c94aSIdo Barnea		goto out;
605a551c94aSIdo Barnea	}
606a551c94aSIdo Barnea
607a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
608a551c94aSIdo Barnea	if (ret_val)
609a551c94aSIdo Barnea		goto out;
610a551c94aSIdo Barnea
611a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
612a551c94aSIdo Barnea
613a551c94aSIdo Barnea	hw->phy.ops.release(hw);
614a551c94aSIdo Barnea
615a551c94aSIdo Barneaout:
616a551c94aSIdo Barnea	return ret_val;
617a551c94aSIdo Barnea}
618a551c94aSIdo Barnea
619a551c94aSIdo Barnea/**
620a551c94aSIdo Barnea *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
621a551c94aSIdo Barnea *  @hw: pointer to the HW structure
622a551c94aSIdo Barnea *  @offset: register offset to write to
623a551c94aSIdo Barnea *  @data: data to write at register offset
624a551c94aSIdo Barnea *
625a551c94aSIdo Barnea *  Writes the data to PHY register at the offset using the serial gigabit
626a551c94aSIdo Barnea *  media independent interface.
627a551c94aSIdo Barnea **/
628a551c94aSIdo BarneaSTATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
629a551c94aSIdo Barnea					   u16 data)
630a551c94aSIdo Barnea{
631a551c94aSIdo Barnea	s32 ret_val = -E1000_ERR_PARAM;
632a551c94aSIdo Barnea
633a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
634a551c94aSIdo Barnea
635a551c94aSIdo Barnea	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
636a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %d is out of range\n", offset);
637a551c94aSIdo Barnea		goto out;
638a551c94aSIdo Barnea	}
639a551c94aSIdo Barnea
640a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
641a551c94aSIdo Barnea	if (ret_val)
642a551c94aSIdo Barnea		goto out;
643a551c94aSIdo Barnea
644a551c94aSIdo Barnea	ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
645a551c94aSIdo Barnea
646a551c94aSIdo Barnea	hw->phy.ops.release(hw);
647a551c94aSIdo Barnea
648a551c94aSIdo Barneaout:
649a551c94aSIdo Barnea	return ret_val;
650a551c94aSIdo Barnea}
651a551c94aSIdo Barnea
652a551c94aSIdo Barnea/**
653a551c94aSIdo Barnea *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
654a551c94aSIdo Barnea *  @hw: pointer to the HW structure
655a551c94aSIdo Barnea *
656a551c94aSIdo Barnea *  Retrieves the PHY address and ID for both PHY's which do and do not use
657a551c94aSIdo Barnea *  sgmi interface.
658a551c94aSIdo Barnea **/
659a551c94aSIdo BarneaSTATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
660a551c94aSIdo Barnea{
661a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
662a551c94aSIdo Barnea	s32  ret_val = E1000_SUCCESS;
663a551c94aSIdo Barnea	u16 phy_id;
664a551c94aSIdo Barnea	u32 ctrl_ext;
665a551c94aSIdo Barnea	u32 mdic;
666a551c94aSIdo Barnea
667a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_phy_id_82575");
668a551c94aSIdo Barnea
669a551c94aSIdo Barnea	/* some i354 devices need an extra read for phy id */
670a551c94aSIdo Barnea	if (hw->mac.type == e1000_i354)
671a551c94aSIdo Barnea		e1000_get_phy_id(hw);
672a551c94aSIdo Barnea
673a551c94aSIdo Barnea	/*
674a551c94aSIdo Barnea	 * For SGMII PHYs, we try the list of possible addresses until
675a551c94aSIdo Barnea	 * we find one that works.  For non-SGMII PHYs
676a551c94aSIdo Barnea	 * (e.g. integrated copper PHYs), an address of 1 should
677a551c94aSIdo Barnea	 * work.  The result of this function should mean phy->phy_addr
678a551c94aSIdo Barnea	 * and phy->id are set correctly.
679a551c94aSIdo Barnea	 */
680a551c94aSIdo Barnea	if (!e1000_sgmii_active_82575(hw)) {
681a551c94aSIdo Barnea		phy->addr = 1;
682a551c94aSIdo Barnea		ret_val = e1000_get_phy_id(hw);
683a551c94aSIdo Barnea		goto out;
684a551c94aSIdo Barnea	}
685a551c94aSIdo Barnea
686a551c94aSIdo Barnea	if (e1000_sgmii_uses_mdio_82575(hw)) {
687a551c94aSIdo Barnea		switch (hw->mac.type) {
688a551c94aSIdo Barnea		case e1000_82575:
689a551c94aSIdo Barnea		case e1000_82576:
690a551c94aSIdo Barnea			mdic = E1000_READ_REG(hw, E1000_MDIC);
691a551c94aSIdo Barnea			mdic &= E1000_MDIC_PHY_MASK;
692a551c94aSIdo Barnea			phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
693a551c94aSIdo Barnea			break;
694a551c94aSIdo Barnea		case e1000_82580:
695a551c94aSIdo Barnea		case e1000_i350:
696a551c94aSIdo Barnea		case e1000_i354:
697a551c94aSIdo Barnea		case e1000_i210:
698a551c94aSIdo Barnea		case e1000_i211:
699a551c94aSIdo Barnea			mdic = E1000_READ_REG(hw, E1000_MDICNFG);
700a551c94aSIdo Barnea			mdic &= E1000_MDICNFG_PHY_MASK;
701a551c94aSIdo Barnea			phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
702a551c94aSIdo Barnea			break;
703a551c94aSIdo Barnea		default:
704a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
705a551c94aSIdo Barnea			goto out;
706a551c94aSIdo Barnea			break;
707a551c94aSIdo Barnea		}
708a551c94aSIdo Barnea		ret_val = e1000_get_phy_id(hw);
709a551c94aSIdo Barnea		goto out;
710a551c94aSIdo Barnea	}
711a551c94aSIdo Barnea
712a551c94aSIdo Barnea	/* Power on sgmii phy if it is disabled */
713a551c94aSIdo Barnea	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
714a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT,
715a551c94aSIdo Barnea			ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
716a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
717a551c94aSIdo Barnea	msec_delay(300);
718a551c94aSIdo Barnea
719a551c94aSIdo Barnea	/*
720a551c94aSIdo Barnea	 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
721a551c94aSIdo Barnea	 * Therefore, we need to test 1-7
722a551c94aSIdo Barnea	 */
723a551c94aSIdo Barnea	for (phy->addr = 1; phy->addr < 8; phy->addr++) {
724a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
725a551c94aSIdo Barnea		if (ret_val == E1000_SUCCESS) {
726a551c94aSIdo Barnea			DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
727a551c94aSIdo Barnea				  phy_id, phy->addr);
728a551c94aSIdo Barnea			/*
729a551c94aSIdo Barnea			 * At the time of this writing, The M88 part is
730a551c94aSIdo Barnea			 * the only supported SGMII PHY product.
731a551c94aSIdo Barnea			 */
732a551c94aSIdo Barnea			if (phy_id == M88_VENDOR)
733a551c94aSIdo Barnea				break;
734a551c94aSIdo Barnea		} else {
735a551c94aSIdo Barnea			DEBUGOUT1("PHY address %u was unreadable\n",
736a551c94aSIdo Barnea				  phy->addr);
737a551c94aSIdo Barnea		}
738a551c94aSIdo Barnea	}
739a551c94aSIdo Barnea
740a551c94aSIdo Barnea	/* A valid PHY type couldn't be found. */
741a551c94aSIdo Barnea	if (phy->addr == 8) {
742a551c94aSIdo Barnea		phy->addr = 0;
743a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
744a551c94aSIdo Barnea	} else {
745a551c94aSIdo Barnea		ret_val = e1000_get_phy_id(hw);
746a551c94aSIdo Barnea	}
747a551c94aSIdo Barnea
748a551c94aSIdo Barnea	/* restore previous sfp cage power state */
749a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
750a551c94aSIdo Barnea
751a551c94aSIdo Barneaout:
752a551c94aSIdo Barnea	return ret_val;
753a551c94aSIdo Barnea}
754a551c94aSIdo Barnea
755a551c94aSIdo Barnea/**
756a551c94aSIdo Barnea *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
757a551c94aSIdo Barnea *  @hw: pointer to the HW structure
758a551c94aSIdo Barnea *
759a551c94aSIdo Barnea *  Resets the PHY using the serial gigabit media independent interface.
760a551c94aSIdo Barnea **/
761a551c94aSIdo BarneaSTATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
762a551c94aSIdo Barnea{
763a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
764a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
765a551c94aSIdo Barnea
766a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
767a551c94aSIdo Barnea
768a551c94aSIdo Barnea	/*
769a551c94aSIdo Barnea	 * This isn't a true "hard" reset, but is the only reset
770a551c94aSIdo Barnea	 * available to us at this time.
771a551c94aSIdo Barnea	 */
772a551c94aSIdo Barnea
773a551c94aSIdo Barnea	DEBUGOUT("Soft resetting SGMII attached PHY...\n");
774a551c94aSIdo Barnea
775a551c94aSIdo Barnea	if (!(hw->phy.ops.write_reg))
776a551c94aSIdo Barnea		goto out;
777a551c94aSIdo Barnea
778a551c94aSIdo Barnea	/*
779a551c94aSIdo Barnea	 * SFP documentation requires the following to configure the SPF module
780a551c94aSIdo Barnea	 * to work on SGMII.  No further documentation is given.
781a551c94aSIdo Barnea	 */
782a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
783a551c94aSIdo Barnea	if (ret_val)
784a551c94aSIdo Barnea		goto out;
785a551c94aSIdo Barnea
786a551c94aSIdo Barnea	ret_val = hw->phy.ops.commit(hw);
787a551c94aSIdo Barnea	if (ret_val)
788a551c94aSIdo Barnea		goto out;
789a551c94aSIdo Barnea
790a551c94aSIdo Barnea	if (phy->id == M88E1512_E_PHY_ID)
791a551c94aSIdo Barnea		ret_val = e1000_initialize_M88E1512_phy(hw);
792a551c94aSIdo Barneaout:
793a551c94aSIdo Barnea	return ret_val;
794a551c94aSIdo Barnea}
795a551c94aSIdo Barnea
796a551c94aSIdo Barnea/**
797a551c94aSIdo Barnea *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
798a551c94aSIdo Barnea *  @hw: pointer to the HW structure
799a551c94aSIdo Barnea *  @active: true to enable LPLU, false to disable
800a551c94aSIdo Barnea *
801a551c94aSIdo Barnea *  Sets the LPLU D0 state according to the active flag.  When
802a551c94aSIdo Barnea *  activating LPLU this function also disables smart speed
803a551c94aSIdo Barnea *  and vice versa.  LPLU will not be activated unless the
804a551c94aSIdo Barnea *  device autonegotiation advertisement meets standards of
805a551c94aSIdo Barnea *  either 10 or 10/100 or 10/100/1000 at all duplexes.
806a551c94aSIdo Barnea *  This is a function pointer entry point only called by
807a551c94aSIdo Barnea *  PHY setup routines.
808a551c94aSIdo Barnea **/
809a551c94aSIdo BarneaSTATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
810a551c94aSIdo Barnea{
811a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
812a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
813a551c94aSIdo Barnea	u16 data;
814a551c94aSIdo Barnea
815a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_d0_lplu_state_82575");
816a551c94aSIdo Barnea
817a551c94aSIdo Barnea	if (!(hw->phy.ops.read_reg))
818a551c94aSIdo Barnea		goto out;
819a551c94aSIdo Barnea
820a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
821a551c94aSIdo Barnea	if (ret_val)
822a551c94aSIdo Barnea		goto out;
823a551c94aSIdo Barnea
824a551c94aSIdo Barnea	if (active) {
825a551c94aSIdo Barnea		data |= IGP02E1000_PM_D0_LPLU;
826a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827a551c94aSIdo Barnea					     data);
828a551c94aSIdo Barnea		if (ret_val)
829a551c94aSIdo Barnea			goto out;
830a551c94aSIdo Barnea
831a551c94aSIdo Barnea		/* When LPLU is enabled, we should disable SmartSpeed */
832a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
833a551c94aSIdo Barnea					    &data);
834a551c94aSIdo Barnea		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
835a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836a551c94aSIdo Barnea					     data);
837a551c94aSIdo Barnea		if (ret_val)
838a551c94aSIdo Barnea			goto out;
839a551c94aSIdo Barnea	} else {
840a551c94aSIdo Barnea		data &= ~IGP02E1000_PM_D0_LPLU;
841a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
842a551c94aSIdo Barnea					     data);
843a551c94aSIdo Barnea		/*
844a551c94aSIdo Barnea		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
845a551c94aSIdo Barnea		 * during Dx states where the power conservation is most
846a551c94aSIdo Barnea		 * important.  During driver activity we should enable
847a551c94aSIdo Barnea		 * SmartSpeed, so performance is maintained.
848a551c94aSIdo Barnea		 */
849a551c94aSIdo Barnea		if (phy->smart_speed == e1000_smart_speed_on) {
850a551c94aSIdo Barnea			ret_val = phy->ops.read_reg(hw,
851a551c94aSIdo Barnea						    IGP01E1000_PHY_PORT_CONFIG,
852a551c94aSIdo Barnea						    &data);
853a551c94aSIdo Barnea			if (ret_val)
854a551c94aSIdo Barnea				goto out;
855a551c94aSIdo Barnea
856a551c94aSIdo Barnea			data |= IGP01E1000_PSCFR_SMART_SPEED;
857a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw,
858a551c94aSIdo Barnea						     IGP01E1000_PHY_PORT_CONFIG,
859a551c94aSIdo Barnea						     data);
860a551c94aSIdo Barnea			if (ret_val)
861a551c94aSIdo Barnea				goto out;
862a551c94aSIdo Barnea		} else if (phy->smart_speed == e1000_smart_speed_off) {
863a551c94aSIdo Barnea			ret_val = phy->ops.read_reg(hw,
864a551c94aSIdo Barnea						    IGP01E1000_PHY_PORT_CONFIG,
865a551c94aSIdo Barnea						    &data);
866a551c94aSIdo Barnea			if (ret_val)
867a551c94aSIdo Barnea				goto out;
868a551c94aSIdo Barnea
869a551c94aSIdo Barnea			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
870a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw,
871a551c94aSIdo Barnea						     IGP01E1000_PHY_PORT_CONFIG,
872a551c94aSIdo Barnea						     data);
873a551c94aSIdo Barnea			if (ret_val)
874a551c94aSIdo Barnea				goto out;
875a551c94aSIdo Barnea		}
876a551c94aSIdo Barnea	}
877a551c94aSIdo Barnea
878a551c94aSIdo Barneaout:
879a551c94aSIdo Barnea	return ret_val;
880a551c94aSIdo Barnea}
881a551c94aSIdo Barnea
882a551c94aSIdo Barnea/**
883a551c94aSIdo Barnea *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
884a551c94aSIdo Barnea *  @hw: pointer to the HW structure
885a551c94aSIdo Barnea *  @active: true to enable LPLU, false to disable
886a551c94aSIdo Barnea *
887a551c94aSIdo Barnea *  Sets the LPLU D0 state according to the active flag.  When
888a551c94aSIdo Barnea *  activating LPLU this function also disables smart speed
889a551c94aSIdo Barnea *  and vice versa.  LPLU will not be activated unless the
890a551c94aSIdo Barnea *  device autonegotiation advertisement meets standards of
891a551c94aSIdo Barnea *  either 10 or 10/100 or 10/100/1000 at all duplexes.
892a551c94aSIdo Barnea *  This is a function pointer entry point only called by
893a551c94aSIdo Barnea *  PHY setup routines.
894a551c94aSIdo Barnea **/
895a551c94aSIdo BarneaSTATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
896a551c94aSIdo Barnea{
897a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
898a551c94aSIdo Barnea	u32 data;
899a551c94aSIdo Barnea
900a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_d0_lplu_state_82580");
901a551c94aSIdo Barnea
902a551c94aSIdo Barnea	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
903a551c94aSIdo Barnea
904a551c94aSIdo Barnea	if (active) {
905a551c94aSIdo Barnea		data |= E1000_82580_PM_D0_LPLU;
906a551c94aSIdo Barnea
907a551c94aSIdo Barnea		/* When LPLU is enabled, we should disable SmartSpeed */
908a551c94aSIdo Barnea		data &= ~E1000_82580_PM_SPD;
909a551c94aSIdo Barnea	} else {
910a551c94aSIdo Barnea		data &= ~E1000_82580_PM_D0_LPLU;
911a551c94aSIdo Barnea
912a551c94aSIdo Barnea		/*
913a551c94aSIdo Barnea		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
914a551c94aSIdo Barnea		 * during Dx states where the power conservation is most
915a551c94aSIdo Barnea		 * important.  During driver activity we should enable
916a551c94aSIdo Barnea		 * SmartSpeed, so performance is maintained.
917a551c94aSIdo Barnea		 */
918a551c94aSIdo Barnea		if (phy->smart_speed == e1000_smart_speed_on)
919a551c94aSIdo Barnea			data |= E1000_82580_PM_SPD;
920a551c94aSIdo Barnea		else if (phy->smart_speed == e1000_smart_speed_off)
921a551c94aSIdo Barnea			data &= ~E1000_82580_PM_SPD;
922a551c94aSIdo Barnea	}
923a551c94aSIdo Barnea
924a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
925a551c94aSIdo Barnea	return E1000_SUCCESS;
926a551c94aSIdo Barnea}
927a551c94aSIdo Barnea
928a551c94aSIdo Barnea/**
929a551c94aSIdo Barnea *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
930a551c94aSIdo Barnea *  @hw: pointer to the HW structure
931a551c94aSIdo Barnea *  @active: boolean used to enable/disable lplu
932a551c94aSIdo Barnea *
933a551c94aSIdo Barnea *  Success returns 0, Failure returns 1
934a551c94aSIdo Barnea *
935a551c94aSIdo Barnea *  The low power link up (lplu) state is set to the power management level D3
936a551c94aSIdo Barnea *  and SmartSpeed is disabled when active is true, else clear lplu for D3
937a551c94aSIdo Barnea *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
938a551c94aSIdo Barnea *  is used during Dx states where the power conservation is most important.
939a551c94aSIdo Barnea *  During driver activity, SmartSpeed should be enabled so performance is
940a551c94aSIdo Barnea *  maintained.
941a551c94aSIdo Barnea **/
942a551c94aSIdo Barneas32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
943a551c94aSIdo Barnea{
944a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
945a551c94aSIdo Barnea	u32 data;
946a551c94aSIdo Barnea
947a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_d3_lplu_state_82580");
948a551c94aSIdo Barnea
949a551c94aSIdo Barnea	data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
950a551c94aSIdo Barnea
951a551c94aSIdo Barnea	if (!active) {
952a551c94aSIdo Barnea		data &= ~E1000_82580_PM_D3_LPLU;
953a551c94aSIdo Barnea		/*
954a551c94aSIdo Barnea		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
955a551c94aSIdo Barnea		 * during Dx states where the power conservation is most
956a551c94aSIdo Barnea		 * important.  During driver activity we should enable
957a551c94aSIdo Barnea		 * SmartSpeed, so performance is maintained.
958a551c94aSIdo Barnea		 */
959a551c94aSIdo Barnea		if (phy->smart_speed == e1000_smart_speed_on)
960a551c94aSIdo Barnea			data |= E1000_82580_PM_SPD;
961a551c94aSIdo Barnea		else if (phy->smart_speed == e1000_smart_speed_off)
962a551c94aSIdo Barnea			data &= ~E1000_82580_PM_SPD;
963a551c94aSIdo Barnea	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
964a551c94aSIdo Barnea		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
965a551c94aSIdo Barnea		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
966a551c94aSIdo Barnea		data |= E1000_82580_PM_D3_LPLU;
967a551c94aSIdo Barnea		/* When LPLU is enabled, we should disable SmartSpeed */
968a551c94aSIdo Barnea		data &= ~E1000_82580_PM_SPD;
969a551c94aSIdo Barnea	}
970a551c94aSIdo Barnea
971a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
972a551c94aSIdo Barnea	return E1000_SUCCESS;
973a551c94aSIdo Barnea}
974a551c94aSIdo Barnea
975a551c94aSIdo Barnea/**
976a551c94aSIdo Barnea *  e1000_acquire_nvm_82575 - Request for access to EEPROM
977a551c94aSIdo Barnea *  @hw: pointer to the HW structure
978a551c94aSIdo Barnea *
979a551c94aSIdo Barnea *  Acquire the necessary semaphores for exclusive access to the EEPROM.
980a551c94aSIdo Barnea *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
981a551c94aSIdo Barnea *  Return successful if access grant bit set, else clear the request for
982a551c94aSIdo Barnea *  EEPROM access and return -E1000_ERR_NVM (-1).
983a551c94aSIdo Barnea **/
984a551c94aSIdo BarneaSTATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
985a551c94aSIdo Barnea{
986a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
987a551c94aSIdo Barnea
988a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_nvm_82575");
989a551c94aSIdo Barnea
990a551c94aSIdo Barnea	ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
991a551c94aSIdo Barnea	if (ret_val)
992a551c94aSIdo Barnea		goto out;
993a551c94aSIdo Barnea
994a551c94aSIdo Barnea	/*
995a551c94aSIdo Barnea	 * Check if there is some access
996a551c94aSIdo Barnea	 * error this access may hook on
997a551c94aSIdo Barnea	 */
998a551c94aSIdo Barnea	if (hw->mac.type == e1000_i350) {
999a551c94aSIdo Barnea		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1000a551c94aSIdo Barnea		if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
1001a551c94aSIdo Barnea		    E1000_EECD_TIMEOUT)) {
1002a551c94aSIdo Barnea			/* Clear all access error flags */
1003a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_EECD, eecd |
1004a551c94aSIdo Barnea					E1000_EECD_ERROR_CLR);
1005a551c94aSIdo Barnea			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1006a551c94aSIdo Barnea		}
1007a551c94aSIdo Barnea	}
1008a551c94aSIdo Barnea
1009a551c94aSIdo Barnea	if (hw->mac.type == e1000_82580) {
1010a551c94aSIdo Barnea		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1011a551c94aSIdo Barnea		if (eecd & E1000_EECD_BLOCKED) {
1012a551c94aSIdo Barnea			/* Clear access error flag */
1013a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_EECD, eecd |
1014a551c94aSIdo Barnea					E1000_EECD_BLOCKED);
1015a551c94aSIdo Barnea			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1016a551c94aSIdo Barnea		}
1017a551c94aSIdo Barnea	}
1018a551c94aSIdo Barnea
1019a551c94aSIdo Barnea	ret_val = e1000_acquire_nvm_generic(hw);
1020a551c94aSIdo Barnea	if (ret_val)
1021a551c94aSIdo Barnea		e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1022a551c94aSIdo Barnea
1023a551c94aSIdo Barneaout:
1024a551c94aSIdo Barnea	return ret_val;
1025a551c94aSIdo Barnea}
1026a551c94aSIdo Barnea
1027a551c94aSIdo Barnea/**
1028a551c94aSIdo Barnea *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1029a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1030a551c94aSIdo Barnea *
1031a551c94aSIdo Barnea *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1032a551c94aSIdo Barnea *  then release the semaphores acquired.
1033a551c94aSIdo Barnea **/
1034a551c94aSIdo BarneaSTATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1035a551c94aSIdo Barnea{
1036a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_nvm_82575");
1037a551c94aSIdo Barnea
1038a551c94aSIdo Barnea	e1000_release_nvm_generic(hw);
1039a551c94aSIdo Barnea
1040a551c94aSIdo Barnea	e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1041a551c94aSIdo Barnea}
1042a551c94aSIdo Barnea
1043a551c94aSIdo Barnea/**
1044a551c94aSIdo Barnea *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1045a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1046a551c94aSIdo Barnea *  @mask: specifies which semaphore to acquire
1047a551c94aSIdo Barnea *
1048a551c94aSIdo Barnea *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1049a551c94aSIdo Barnea *  will also specify which port we're acquiring the lock for.
1050a551c94aSIdo Barnea **/
1051a551c94aSIdo BarneaSTATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1052a551c94aSIdo Barnea{
1053a551c94aSIdo Barnea	u32 swfw_sync;
1054a551c94aSIdo Barnea	u32 swmask = mask;
1055a551c94aSIdo Barnea	u32 fwmask = mask << 16;
1056a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1057a551c94aSIdo Barnea	s32 i = 0, timeout = 200;
1058a551c94aSIdo Barnea
1059a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1060a551c94aSIdo Barnea
1061a551c94aSIdo Barnea	while (i < timeout) {
1062a551c94aSIdo Barnea		if (e1000_get_hw_semaphore_generic(hw)) {
1063a551c94aSIdo Barnea			ret_val = -E1000_ERR_SWFW_SYNC;
1064a551c94aSIdo Barnea			goto out;
1065a551c94aSIdo Barnea		}
1066a551c94aSIdo Barnea
1067a551c94aSIdo Barnea		swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1068a551c94aSIdo Barnea		if (!(swfw_sync & (fwmask | swmask)))
1069a551c94aSIdo Barnea			break;
1070a551c94aSIdo Barnea
1071a551c94aSIdo Barnea		/*
1072a551c94aSIdo Barnea		 * Firmware currently using resource (fwmask)
1073a551c94aSIdo Barnea		 * or other software thread using resource (swmask)
1074a551c94aSIdo Barnea		 */
1075a551c94aSIdo Barnea		e1000_put_hw_semaphore_generic(hw);
1076a551c94aSIdo Barnea		msec_delay_irq(5);
1077a551c94aSIdo Barnea		i++;
1078a551c94aSIdo Barnea	}
1079a551c94aSIdo Barnea
1080a551c94aSIdo Barnea	if (i == timeout) {
1081a551c94aSIdo Barnea		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1082a551c94aSIdo Barnea		ret_val = -E1000_ERR_SWFW_SYNC;
1083a551c94aSIdo Barnea		goto out;
1084a551c94aSIdo Barnea	}
1085a551c94aSIdo Barnea
1086a551c94aSIdo Barnea	swfw_sync |= swmask;
1087a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1088a551c94aSIdo Barnea
1089a551c94aSIdo Barnea	e1000_put_hw_semaphore_generic(hw);
1090a551c94aSIdo Barnea
1091a551c94aSIdo Barneaout:
1092a551c94aSIdo Barnea	return ret_val;
1093a551c94aSIdo Barnea}
1094a551c94aSIdo Barnea
1095a551c94aSIdo Barnea/**
1096a551c94aSIdo Barnea *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1097a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1098a551c94aSIdo Barnea *  @mask: specifies which semaphore to acquire
1099a551c94aSIdo Barnea *
1100a551c94aSIdo Barnea *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1101a551c94aSIdo Barnea *  will also specify which port we're releasing the lock for.
1102a551c94aSIdo Barnea **/
1103a551c94aSIdo BarneaSTATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1104a551c94aSIdo Barnea{
1105a551c94aSIdo Barnea	u32 swfw_sync;
1106a551c94aSIdo Barnea
1107a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_swfw_sync_82575");
1108a551c94aSIdo Barnea
1109a551c94aSIdo Barnea	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1110a551c94aSIdo Barnea		; /* Empty */
1111a551c94aSIdo Barnea
1112a551c94aSIdo Barnea	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1113a551c94aSIdo Barnea	swfw_sync &= ~mask;
1114a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1115a551c94aSIdo Barnea
1116a551c94aSIdo Barnea	e1000_put_hw_semaphore_generic(hw);
1117a551c94aSIdo Barnea}
1118a551c94aSIdo Barnea
1119a551c94aSIdo Barnea/**
1120a551c94aSIdo Barnea *  e1000_get_cfg_done_82575 - Read config done bit
1121a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1122a551c94aSIdo Barnea *
1123a551c94aSIdo Barnea *  Read the management control register for the config done bit for
1124a551c94aSIdo Barnea *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1125a551c94aSIdo Barnea *  to read the config done bit, so an error is *ONLY* logged and returns
1126a551c94aSIdo Barnea *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1127a551c94aSIdo Barnea *  would not be able to be reset or change link.
1128a551c94aSIdo Barnea **/
1129a551c94aSIdo BarneaSTATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1130a551c94aSIdo Barnea{
1131a551c94aSIdo Barnea	s32 timeout = PHY_CFG_TIMEOUT;
1132a551c94aSIdo Barnea	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1133a551c94aSIdo Barnea
1134a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_cfg_done_82575");
1135a551c94aSIdo Barnea
1136a551c94aSIdo Barnea	if (hw->bus.func == E1000_FUNC_1)
1137a551c94aSIdo Barnea		mask = E1000_NVM_CFG_DONE_PORT_1;
1138a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_2)
1139a551c94aSIdo Barnea		mask = E1000_NVM_CFG_DONE_PORT_2;
1140a551c94aSIdo Barnea	else if (hw->bus.func == E1000_FUNC_3)
1141a551c94aSIdo Barnea		mask = E1000_NVM_CFG_DONE_PORT_3;
1142a551c94aSIdo Barnea	while (timeout) {
1143a551c94aSIdo Barnea		if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1144a551c94aSIdo Barnea			break;
1145a551c94aSIdo Barnea		msec_delay(1);
1146a551c94aSIdo Barnea		timeout--;
1147a551c94aSIdo Barnea	}
1148a551c94aSIdo Barnea	if (!timeout)
1149a551c94aSIdo Barnea		DEBUGOUT("MNG configuration cycle has not completed.\n");
1150a551c94aSIdo Barnea
1151a551c94aSIdo Barnea	/* If EEPROM is not marked present, init the PHY manually */
1152a551c94aSIdo Barnea	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1153a551c94aSIdo Barnea	    (hw->phy.type == e1000_phy_igp_3))
1154a551c94aSIdo Barnea		e1000_phy_init_script_igp3(hw);
1155a551c94aSIdo Barnea
1156a551c94aSIdo Barnea	return E1000_SUCCESS;
1157a551c94aSIdo Barnea}
1158a551c94aSIdo Barnea
1159a551c94aSIdo Barnea/**
1160a551c94aSIdo Barnea *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1161a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1162a551c94aSIdo Barnea *  @speed: stores the current speed
1163a551c94aSIdo Barnea *  @duplex: stores the current duplex
1164a551c94aSIdo Barnea *
1165a551c94aSIdo Barnea *  This is a wrapper function, if using the serial gigabit media independent
1166a551c94aSIdo Barnea *  interface, use PCS to retrieve the link speed and duplex information.
1167a551c94aSIdo Barnea *  Otherwise, use the generic function to get the link speed and duplex info.
1168a551c94aSIdo Barnea **/
1169a551c94aSIdo BarneaSTATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1170a551c94aSIdo Barnea					u16 *duplex)
1171a551c94aSIdo Barnea{
1172a551c94aSIdo Barnea	s32 ret_val;
1173a551c94aSIdo Barnea
1174a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_link_up_info_82575");
1175a551c94aSIdo Barnea
1176a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper)
1177a551c94aSIdo Barnea		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1178a551c94aSIdo Barnea							       duplex);
1179a551c94aSIdo Barnea	else
1180a551c94aSIdo Barnea		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1181a551c94aSIdo Barnea								    duplex);
1182a551c94aSIdo Barnea
1183a551c94aSIdo Barnea	return ret_val;
1184a551c94aSIdo Barnea}
1185a551c94aSIdo Barnea
1186a551c94aSIdo Barnea/**
1187a551c94aSIdo Barnea *  e1000_check_for_link_82575 - Check for link
1188a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1189a551c94aSIdo Barnea *
1190a551c94aSIdo Barnea *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1191a551c94aSIdo Barnea *  use the generic interface for determining link.
1192a551c94aSIdo Barnea **/
1193a551c94aSIdo BarneaSTATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1194a551c94aSIdo Barnea{
1195a551c94aSIdo Barnea	s32 ret_val;
1196a551c94aSIdo Barnea	u16 speed, duplex;
1197a551c94aSIdo Barnea
1198a551c94aSIdo Barnea	DEBUGFUNC("e1000_check_for_link_82575");
1199a551c94aSIdo Barnea
1200a551c94aSIdo Barnea	if (hw->phy.media_type != e1000_media_type_copper) {
1201a551c94aSIdo Barnea		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1202a551c94aSIdo Barnea							       &duplex);
1203a551c94aSIdo Barnea		/*
1204a551c94aSIdo Barnea		 * Use this flag to determine if link needs to be checked or
1205a551c94aSIdo Barnea		 * not.  If we have link clear the flag so that we do not
1206a551c94aSIdo Barnea		 * continue to check for link.
1207a551c94aSIdo Barnea		 */
1208a551c94aSIdo Barnea		hw->mac.get_link_status = !hw->mac.serdes_has_link;
1209a551c94aSIdo Barnea
1210a551c94aSIdo Barnea		/*
1211a551c94aSIdo Barnea		 * Configure Flow Control now that Auto-Neg has completed.
1212a551c94aSIdo Barnea		 * First, we need to restore the desired flow control
1213a551c94aSIdo Barnea		 * settings because we may have had to re-autoneg with a
1214a551c94aSIdo Barnea		 * different link partner.
1215a551c94aSIdo Barnea		 */
1216a551c94aSIdo Barnea		ret_val = e1000_config_fc_after_link_up_generic(hw);
1217a551c94aSIdo Barnea		if (ret_val)
1218a551c94aSIdo Barnea			DEBUGOUT("Error configuring flow control\n");
1219a551c94aSIdo Barnea	} else {
1220a551c94aSIdo Barnea		ret_val = e1000_check_for_copper_link_generic(hw);
1221a551c94aSIdo Barnea	}
1222a551c94aSIdo Barnea
1223a551c94aSIdo Barnea	return ret_val;
1224a551c94aSIdo Barnea}
1225a551c94aSIdo Barnea
1226a551c94aSIdo Barnea/**
1227a551c94aSIdo Barnea *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1228a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1229a551c94aSIdo Barnea *
1230a551c94aSIdo Barnea *  Poll the M88E1112 interfaces to see which interface achieved link.
1231a551c94aSIdo Barnea */
1232a551c94aSIdo BarneaSTATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1233a551c94aSIdo Barnea{
1234a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1235a551c94aSIdo Barnea	s32 ret_val;
1236a551c94aSIdo Barnea	u16 data;
1237a551c94aSIdo Barnea	u8 port = 0;
1238a551c94aSIdo Barnea
1239a551c94aSIdo Barnea	DEBUGFUNC("e1000_check_for_link_media_swap");
1240a551c94aSIdo Barnea
1241a551c94aSIdo Barnea	/* Check for copper. */
1242a551c94aSIdo Barnea	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1243a551c94aSIdo Barnea	if (ret_val)
1244a551c94aSIdo Barnea		return ret_val;
1245a551c94aSIdo Barnea
1246a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1247a551c94aSIdo Barnea	if (ret_val)
1248a551c94aSIdo Barnea		return ret_val;
1249a551c94aSIdo Barnea
1250a551c94aSIdo Barnea	if (data & E1000_M88E1112_STATUS_LINK)
1251a551c94aSIdo Barnea		port = E1000_MEDIA_PORT_COPPER;
1252a551c94aSIdo Barnea
1253a551c94aSIdo Barnea	/* Check for other. */
1254a551c94aSIdo Barnea	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1255a551c94aSIdo Barnea	if (ret_val)
1256a551c94aSIdo Barnea		return ret_val;
1257a551c94aSIdo Barnea
1258a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1259a551c94aSIdo Barnea	if (ret_val)
1260a551c94aSIdo Barnea		return ret_val;
1261a551c94aSIdo Barnea
1262a551c94aSIdo Barnea	if (data & E1000_M88E1112_STATUS_LINK)
1263a551c94aSIdo Barnea		port = E1000_MEDIA_PORT_OTHER;
1264a551c94aSIdo Barnea
1265a551c94aSIdo Barnea	/* Determine if a swap needs to happen. */
1266a551c94aSIdo Barnea	if (port && (hw->dev_spec._82575.media_port != port)) {
1267a551c94aSIdo Barnea		hw->dev_spec._82575.media_port = port;
1268a551c94aSIdo Barnea		hw->dev_spec._82575.media_changed = true;
1269a551c94aSIdo Barnea	}
1270a551c94aSIdo Barnea
1271a551c94aSIdo Barnea	if (port == E1000_MEDIA_PORT_COPPER) {
1272a551c94aSIdo Barnea		/* reset page to 0 */
1273a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1274a551c94aSIdo Barnea		if (ret_val)
1275a551c94aSIdo Barnea			return ret_val;
1276a551c94aSIdo Barnea		e1000_check_for_link_82575(hw);
1277a551c94aSIdo Barnea	} else {
1278a551c94aSIdo Barnea		e1000_check_for_link_82575(hw);
1279a551c94aSIdo Barnea		/* reset page to 0 */
1280a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1281a551c94aSIdo Barnea		if (ret_val)
1282a551c94aSIdo Barnea			return ret_val;
1283a551c94aSIdo Barnea	}
1284a551c94aSIdo Barnea
1285a551c94aSIdo Barnea	return E1000_SUCCESS;
1286a551c94aSIdo Barnea}
1287a551c94aSIdo Barnea
1288a551c94aSIdo Barnea/**
1289a551c94aSIdo Barnea *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1290a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1291a551c94aSIdo Barnea **/
1292a551c94aSIdo BarneaSTATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1293a551c94aSIdo Barnea{
1294a551c94aSIdo Barnea	u32 reg;
1295a551c94aSIdo Barnea
1296a551c94aSIdo Barnea	DEBUGFUNC("e1000_power_up_serdes_link_82575");
1297a551c94aSIdo Barnea
1298a551c94aSIdo Barnea	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1299a551c94aSIdo Barnea	    !e1000_sgmii_active_82575(hw))
1300a551c94aSIdo Barnea		return;
1301a551c94aSIdo Barnea
1302a551c94aSIdo Barnea	/* Enable PCS to turn on link */
1303a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1304a551c94aSIdo Barnea	reg |= E1000_PCS_CFG_PCS_EN;
1305a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1306a551c94aSIdo Barnea
1307a551c94aSIdo Barnea	/* Power up the laser */
1308a551c94aSIdo Barnea	reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1309a551c94aSIdo Barnea	reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1310a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1311a551c94aSIdo Barnea
1312a551c94aSIdo Barnea	/* flush the write to verify completion */
1313a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1314a551c94aSIdo Barnea	msec_delay(1);
1315a551c94aSIdo Barnea}
1316a551c94aSIdo Barnea
1317a551c94aSIdo Barnea/**
1318a551c94aSIdo Barnea *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1319a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1320a551c94aSIdo Barnea *  @speed: stores the current speed
1321a551c94aSIdo Barnea *  @duplex: stores the current duplex
1322a551c94aSIdo Barnea *
1323a551c94aSIdo Barnea *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1324a551c94aSIdo Barnea *  duplex, then store the values in the pointers provided.
1325a551c94aSIdo Barnea **/
1326a551c94aSIdo BarneaSTATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1327a551c94aSIdo Barnea						u16 *speed, u16 *duplex)
1328a551c94aSIdo Barnea{
1329a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
1330a551c94aSIdo Barnea	u32 pcs;
1331a551c94aSIdo Barnea	u32 status;
1332a551c94aSIdo Barnea
1333a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1334a551c94aSIdo Barnea
1335a551c94aSIdo Barnea	/*
1336a551c94aSIdo Barnea	 * Read the PCS Status register for link state. For non-copper mode,
1337a551c94aSIdo Barnea	 * the status register is not accurate. The PCS status register is
1338a551c94aSIdo Barnea	 * used instead.
1339a551c94aSIdo Barnea	 */
1340a551c94aSIdo Barnea	pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1341a551c94aSIdo Barnea
1342a551c94aSIdo Barnea	/*
1343a551c94aSIdo Barnea	 * The link up bit determines when link is up on autoneg.
1344a551c94aSIdo Barnea	 */
1345a551c94aSIdo Barnea	if (pcs & E1000_PCS_LSTS_LINK_OK) {
1346a551c94aSIdo Barnea		mac->serdes_has_link = true;
1347a551c94aSIdo Barnea
1348a551c94aSIdo Barnea		/* Detect and store PCS speed */
1349a551c94aSIdo Barnea		if (pcs & E1000_PCS_LSTS_SPEED_1000)
1350a551c94aSIdo Barnea			*speed = SPEED_1000;
1351a551c94aSIdo Barnea		else if (pcs & E1000_PCS_LSTS_SPEED_100)
1352a551c94aSIdo Barnea			*speed = SPEED_100;
1353a551c94aSIdo Barnea		else
1354a551c94aSIdo Barnea			*speed = SPEED_10;
1355a551c94aSIdo Barnea
1356a551c94aSIdo Barnea		/* Detect and store PCS duplex */
1357a551c94aSIdo Barnea		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1358a551c94aSIdo Barnea			*duplex = FULL_DUPLEX;
1359a551c94aSIdo Barnea		else
1360a551c94aSIdo Barnea			*duplex = HALF_DUPLEX;
1361a551c94aSIdo Barnea
1362a551c94aSIdo Barnea		/* Check if it is an I354 2.5Gb backplane connection. */
1363a551c94aSIdo Barnea		if (mac->type == e1000_i354) {
1364a551c94aSIdo Barnea			status = E1000_READ_REG(hw, E1000_STATUS);
1365a551c94aSIdo Barnea			if ((status & E1000_STATUS_2P5_SKU) &&
1366a551c94aSIdo Barnea			    !(status & E1000_STATUS_2P5_SKU_OVER)) {
1367a551c94aSIdo Barnea				*speed = SPEED_2500;
1368a551c94aSIdo Barnea				*duplex = FULL_DUPLEX;
1369a551c94aSIdo Barnea				DEBUGOUT("2500 Mbs, ");
1370a551c94aSIdo Barnea				DEBUGOUT("Full Duplex\n");
1371a551c94aSIdo Barnea			}
1372a551c94aSIdo Barnea		}
1373a551c94aSIdo Barnea
1374a551c94aSIdo Barnea	} else {
1375a551c94aSIdo Barnea		mac->serdes_has_link = false;
1376a551c94aSIdo Barnea		*speed = 0;
1377a551c94aSIdo Barnea		*duplex = 0;
1378a551c94aSIdo Barnea	}
1379a551c94aSIdo Barnea
1380a551c94aSIdo Barnea	return E1000_SUCCESS;
1381a551c94aSIdo Barnea}
1382a551c94aSIdo Barnea
1383a551c94aSIdo Barnea/**
1384a551c94aSIdo Barnea *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1385a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1386a551c94aSIdo Barnea *
1387a551c94aSIdo Barnea *  In the case of serdes shut down sfp and PCS on driver unload
1388a551c94aSIdo Barnea *  when management pass thru is not enabled.
1389a551c94aSIdo Barnea **/
1390a551c94aSIdo Barneavoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1391a551c94aSIdo Barnea{
1392a551c94aSIdo Barnea	u32 reg;
1393a551c94aSIdo Barnea
1394a551c94aSIdo Barnea	DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1395a551c94aSIdo Barnea
1396a551c94aSIdo Barnea	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1397a551c94aSIdo Barnea	    !e1000_sgmii_active_82575(hw))
1398a551c94aSIdo Barnea		return;
1399a551c94aSIdo Barnea
1400a551c94aSIdo Barnea	if (!e1000_enable_mng_pass_thru(hw)) {
1401a551c94aSIdo Barnea		/* Disable PCS to turn off link */
1402a551c94aSIdo Barnea		reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1403a551c94aSIdo Barnea		reg &= ~E1000_PCS_CFG_PCS_EN;
1404a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1405a551c94aSIdo Barnea
1406a551c94aSIdo Barnea		/* shutdown the laser */
1407a551c94aSIdo Barnea		reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1408a551c94aSIdo Barnea		reg |= E1000_CTRL_EXT_SDP3_DATA;
1409a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1410a551c94aSIdo Barnea
1411a551c94aSIdo Barnea		/* flush the write to verify completion */
1412a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
1413a551c94aSIdo Barnea		msec_delay(1);
1414a551c94aSIdo Barnea	}
1415a551c94aSIdo Barnea
1416a551c94aSIdo Barnea	return;
1417a551c94aSIdo Barnea}
1418a551c94aSIdo Barnea
1419a551c94aSIdo Barnea/**
1420a551c94aSIdo Barnea *  e1000_reset_hw_82575 - Reset hardware
1421a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1422a551c94aSIdo Barnea *
1423a551c94aSIdo Barnea *  This resets the hardware into a known state.
1424a551c94aSIdo Barnea **/
1425a551c94aSIdo BarneaSTATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1426a551c94aSIdo Barnea{
1427a551c94aSIdo Barnea	u32 ctrl;
1428a551c94aSIdo Barnea	s32 ret_val;
1429a551c94aSIdo Barnea
1430a551c94aSIdo Barnea	DEBUGFUNC("e1000_reset_hw_82575");
1431a551c94aSIdo Barnea
1432a551c94aSIdo Barnea	/*
1433a551c94aSIdo Barnea	 * Prevent the PCI-E bus from sticking if there is no TLP connection
1434a551c94aSIdo Barnea	 * on the last TLP read/write transaction when MAC is reset.
1435a551c94aSIdo Barnea	 */
1436a551c94aSIdo Barnea	ret_val = e1000_disable_pcie_master_generic(hw);
1437a551c94aSIdo Barnea	if (ret_val)
1438a551c94aSIdo Barnea		DEBUGOUT("PCI-E Master disable polling has failed.\n");
1439a551c94aSIdo Barnea
1440a551c94aSIdo Barnea	/* set the completion timeout for interface */
1441a551c94aSIdo Barnea	ret_val = e1000_set_pcie_completion_timeout(hw);
1442a551c94aSIdo Barnea	if (ret_val)
1443a551c94aSIdo Barnea		DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1444a551c94aSIdo Barnea
1445a551c94aSIdo Barnea	DEBUGOUT("Masking off all interrupts\n");
1446a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1447a551c94aSIdo Barnea
1448a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_RCTL, 0);
1449a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1450a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1451a551c94aSIdo Barnea
1452a551c94aSIdo Barnea	msec_delay(10);
1453a551c94aSIdo Barnea
1454a551c94aSIdo Barnea	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1455a551c94aSIdo Barnea
1456a551c94aSIdo Barnea	DEBUGOUT("Issuing a global reset to MAC\n");
1457a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1458a551c94aSIdo Barnea
1459a551c94aSIdo Barnea	ret_val = e1000_get_auto_rd_done_generic(hw);
1460a551c94aSIdo Barnea	if (ret_val) {
1461a551c94aSIdo Barnea		/*
1462a551c94aSIdo Barnea		 * When auto config read does not complete, do not
1463a551c94aSIdo Barnea		 * return with an error. This can happen in situations
1464a551c94aSIdo Barnea		 * where there is no eeprom and prevents getting link.
1465a551c94aSIdo Barnea		 */
1466a551c94aSIdo Barnea		DEBUGOUT("Auto Read Done did not complete\n");
1467a551c94aSIdo Barnea	}
1468a551c94aSIdo Barnea
1469a551c94aSIdo Barnea	/* If EEPROM is not present, run manual init scripts */
1470a551c94aSIdo Barnea	if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1471a551c94aSIdo Barnea		e1000_reset_init_script_82575(hw);
1472a551c94aSIdo Barnea
1473a551c94aSIdo Barnea	/* Clear any pending interrupt events. */
1474a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1475a551c94aSIdo Barnea	E1000_READ_REG(hw, E1000_ICR);
1476a551c94aSIdo Barnea
1477a551c94aSIdo Barnea	/* Install any alternate MAC address into RAR0 */
1478a551c94aSIdo Barnea	ret_val = e1000_check_alt_mac_addr_generic(hw);
1479a551c94aSIdo Barnea
1480a551c94aSIdo Barnea	return ret_val;
1481a551c94aSIdo Barnea}
1482a551c94aSIdo Barnea