1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_HW_H_
35a551c94aSIdo Barnea#define _E1000_HW_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barnea#include "e1000_osdep.h"
38a551c94aSIdo Barnea#include "e1000_regs.h"
39a551c94aSIdo Barnea#include "e1000_defines.h"
40a551c94aSIdo Barnea
41a551c94aSIdo Barneastruct e1000_hw;
42a551c94aSIdo Barnea
43a551c94aSIdo Barnea#define E1000_DEV_ID_82542			0x1000
44a551c94aSIdo Barnea#define E1000_DEV_ID_82543GC_FIBER		0x1001
45a551c94aSIdo Barnea#define E1000_DEV_ID_82543GC_COPPER		0x1004
46a551c94aSIdo Barnea#define E1000_DEV_ID_82544EI_COPPER		0x1008
47a551c94aSIdo Barnea#define E1000_DEV_ID_82544EI_FIBER		0x1009
48a551c94aSIdo Barnea#define E1000_DEV_ID_82544GC_COPPER		0x100C
49a551c94aSIdo Barnea#define E1000_DEV_ID_82544GC_LOM		0x100D
50a551c94aSIdo Barnea#define E1000_DEV_ID_82540EM			0x100E
51a551c94aSIdo Barnea#define E1000_DEV_ID_82540EM_LOM		0x1015
52a551c94aSIdo Barnea#define E1000_DEV_ID_82540EP_LOM		0x1016
53a551c94aSIdo Barnea#define E1000_DEV_ID_82540EP			0x1017
54a551c94aSIdo Barnea#define E1000_DEV_ID_82540EP_LP			0x101E
55a551c94aSIdo Barnea#define E1000_DEV_ID_82545EM_COPPER		0x100F
56a551c94aSIdo Barnea#define E1000_DEV_ID_82545EM_FIBER		0x1011
57a551c94aSIdo Barnea#define E1000_DEV_ID_82545GM_COPPER		0x1026
58a551c94aSIdo Barnea#define E1000_DEV_ID_82545GM_FIBER		0x1027
59a551c94aSIdo Barnea#define E1000_DEV_ID_82545GM_SERDES		0x1028
60a551c94aSIdo Barnea#define E1000_DEV_ID_82546EB_COPPER		0x1010
61a551c94aSIdo Barnea#define E1000_DEV_ID_82546EB_FIBER		0x1012
62a551c94aSIdo Barnea#define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
63a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_COPPER		0x1079
64a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_FIBER		0x107A
65a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_SERDES		0x107B
66a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_PCIE		0x108A
67a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
68a551c94aSIdo Barnea#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
69a551c94aSIdo Barnea#define E1000_DEV_ID_82541EI			0x1013
70a551c94aSIdo Barnea#define E1000_DEV_ID_82541EI_MOBILE		0x1018
71a551c94aSIdo Barnea#define E1000_DEV_ID_82541ER_LOM		0x1014
72a551c94aSIdo Barnea#define E1000_DEV_ID_82541ER			0x1078
73a551c94aSIdo Barnea#define E1000_DEV_ID_82541GI			0x1076
74a551c94aSIdo Barnea#define E1000_DEV_ID_82541GI_LF			0x107C
75a551c94aSIdo Barnea#define E1000_DEV_ID_82541GI_MOBILE		0x1077
76a551c94aSIdo Barnea#define E1000_DEV_ID_82547EI			0x1019
77a551c94aSIdo Barnea#define E1000_DEV_ID_82547EI_MOBILE		0x101A
78a551c94aSIdo Barnea#define E1000_DEV_ID_82547GI			0x1075
79a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_COPPER		0x105E
80a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_FIBER		0x105F
81a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_SERDES		0x1060
82a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
83a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
84a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
85a551c94aSIdo Barnea#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
86a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
87a551c94aSIdo Barnea#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
88a551c94aSIdo Barnea#define E1000_DEV_ID_82572EI_COPPER		0x107D
89a551c94aSIdo Barnea#define E1000_DEV_ID_82572EI_FIBER		0x107E
90a551c94aSIdo Barnea#define E1000_DEV_ID_82572EI_SERDES		0x107F
91a551c94aSIdo Barnea#define E1000_DEV_ID_82572EI			0x10B9
92a551c94aSIdo Barnea#define E1000_DEV_ID_82573E			0x108B
93a551c94aSIdo Barnea#define E1000_DEV_ID_82573E_IAMT		0x108C
94a551c94aSIdo Barnea#define E1000_DEV_ID_82573L			0x109A
95a551c94aSIdo Barnea#define E1000_DEV_ID_82574L			0x10D3
96a551c94aSIdo Barnea#define E1000_DEV_ID_82574LA			0x10F6
97a551c94aSIdo Barnea#define E1000_DEV_ID_82583V			0x150C
98a551c94aSIdo Barnea#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
99a551c94aSIdo Barnea#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
100a551c94aSIdo Barnea#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
101a551c94aSIdo Barnea#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
102a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_82567V_3		0x1501
103a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
104a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
105a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IGP_C			0x104B
106a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IFE			0x104C
107a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
108a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
109a551c94aSIdo Barnea#define E1000_DEV_ID_ICH8_IGP_M			0x104D
110a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
111a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
112a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
113a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
114a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_BM			0x10E5
115a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IGP_C			0x294C
116a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IFE			0x10C0
117a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
118a551c94aSIdo Barnea#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
119a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
120a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
121a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
122a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
123a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
124a551c94aSIdo Barnea#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
125a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
126a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
127a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
128a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
129a551c94aSIdo Barnea#define E1000_DEV_ID_PCH2_LV_LM			0x1502
130a551c94aSIdo Barnea#define E1000_DEV_ID_PCH2_LV_V			0x1503
131a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
132a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
133a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
134a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
135a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_I218_LM2		0x15A0
136a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_I218_V2		0x15A1
137a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
138a551c94aSIdo Barnea#define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
1399ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F /* Sunrise Point PCH */
1409ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_V		0x1570 /* Sunrise Point PCH */
1419ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7 /* Sunrise Point-H PCH */
1429ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8 /* Sunrise Point-H PCH */
1439ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_LBG_I219_LM3		0x15B9 /* LEWISBURG PCH */
1449ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_LM4		0x15D7
1459ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_V4		0x15D8
1469ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_LM5		0x15E3
1479ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_SPT_I219_V5		0x15D6
1489ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_CNP_I219_LM6		0x15BD
1499ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_CNP_I219_V6		0x15BE
1509ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_CNP_I219_LM7		0x15BB
1519ca4a157SIdo Barnea#define E1000_DEV_ID_PCH_CNP_I219_V7		0x15BC
152a551c94aSIdo Barnea#define E1000_DEV_ID_82576			0x10C9
153a551c94aSIdo Barnea#define E1000_DEV_ID_82576_FIBER		0x10E6
154a551c94aSIdo Barnea#define E1000_DEV_ID_82576_SERDES		0x10E7
155a551c94aSIdo Barnea#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
156a551c94aSIdo Barnea#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
157a551c94aSIdo Barnea#define E1000_DEV_ID_82576_NS			0x150A
158a551c94aSIdo Barnea#define E1000_DEV_ID_82576_NS_SERDES		0x1518
159a551c94aSIdo Barnea#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
160a551c94aSIdo Barnea#define E1000_DEV_ID_82576_VF			0x10CA
161a551c94aSIdo Barnea#define E1000_DEV_ID_82576_VF_HV		0x152D
162a551c94aSIdo Barnea#define E1000_DEV_ID_I350_VF			0x1520
163a551c94aSIdo Barnea#define E1000_DEV_ID_I350_VF_HV			0x152F
164a551c94aSIdo Barnea#define E1000_DEV_ID_82575EB_COPPER		0x10A7
165a551c94aSIdo Barnea#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
166a551c94aSIdo Barnea#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
167a551c94aSIdo Barnea#define E1000_DEV_ID_82580_COPPER		0x150E
168a551c94aSIdo Barnea#define E1000_DEV_ID_82580_FIBER		0x150F
169a551c94aSIdo Barnea#define E1000_DEV_ID_82580_SERDES		0x1510
170a551c94aSIdo Barnea#define E1000_DEV_ID_82580_SGMII		0x1511
171a551c94aSIdo Barnea#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
172a551c94aSIdo Barnea#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
173a551c94aSIdo Barnea#define E1000_DEV_ID_I350_COPPER		0x1521
174a551c94aSIdo Barnea#define E1000_DEV_ID_I350_FIBER			0x1522
175a551c94aSIdo Barnea#define E1000_DEV_ID_I350_SERDES		0x1523
176a551c94aSIdo Barnea#define E1000_DEV_ID_I350_SGMII			0x1524
177a551c94aSIdo Barnea#define E1000_DEV_ID_I350_DA4			0x1546
178a551c94aSIdo Barnea#define E1000_DEV_ID_I210_COPPER		0x1533
179a551c94aSIdo Barnea#define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
180a551c94aSIdo Barnea#define E1000_DEV_ID_I210_COPPER_IT		0x1535
181a551c94aSIdo Barnea#define E1000_DEV_ID_I210_FIBER			0x1536
182a551c94aSIdo Barnea#define E1000_DEV_ID_I210_SERDES		0x1537
183a551c94aSIdo Barnea#define E1000_DEV_ID_I210_SGMII			0x1538
184a551c94aSIdo Barnea#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
185a551c94aSIdo Barnea#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
186a551c94aSIdo Barnea#define E1000_DEV_ID_I211_COPPER		0x1539
187a551c94aSIdo Barnea#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
188a551c94aSIdo Barnea#define E1000_DEV_ID_I354_SGMII			0x1F41
189a551c94aSIdo Barnea#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
190a551c94aSIdo Barnea#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
191a551c94aSIdo Barnea#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
192a551c94aSIdo Barnea#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
193a551c94aSIdo Barnea#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
194a551c94aSIdo Barnea
195a551c94aSIdo Barnea#define E1000_REVISION_0	0
196a551c94aSIdo Barnea#define E1000_REVISION_1	1
197a551c94aSIdo Barnea#define E1000_REVISION_2	2
198a551c94aSIdo Barnea#define E1000_REVISION_3	3
199a551c94aSIdo Barnea#define E1000_REVISION_4	4
200a551c94aSIdo Barnea
201a551c94aSIdo Barnea#define E1000_FUNC_0		0
202a551c94aSIdo Barnea#define E1000_FUNC_1		1
203a551c94aSIdo Barnea#define E1000_FUNC_2		2
204a551c94aSIdo Barnea#define E1000_FUNC_3		3
205a551c94aSIdo Barnea
206a551c94aSIdo Barnea#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
207a551c94aSIdo Barnea#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
208a551c94aSIdo Barnea#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
209a551c94aSIdo Barnea#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
210a551c94aSIdo Barnea
211a551c94aSIdo Barneaenum e1000_mac_type {
212a551c94aSIdo Barnea	e1000_undefined = 0,
213a551c94aSIdo Barnea	e1000_82542,
214a551c94aSIdo Barnea	e1000_82543,
215a551c94aSIdo Barnea	e1000_82544,
216a551c94aSIdo Barnea	e1000_82540,
217a551c94aSIdo Barnea	e1000_82545,
218a551c94aSIdo Barnea	e1000_82545_rev_3,
219a551c94aSIdo Barnea	e1000_82546,
220a551c94aSIdo Barnea	e1000_82546_rev_3,
221a551c94aSIdo Barnea	e1000_82541,
222a551c94aSIdo Barnea	e1000_82541_rev_2,
223a551c94aSIdo Barnea	e1000_82547,
224a551c94aSIdo Barnea	e1000_82547_rev_2,
225a551c94aSIdo Barnea	e1000_82571,
226a551c94aSIdo Barnea	e1000_82572,
227a551c94aSIdo Barnea	e1000_82573,
228a551c94aSIdo Barnea	e1000_82574,
229a551c94aSIdo Barnea	e1000_82583,
230a551c94aSIdo Barnea	e1000_80003es2lan,
231a551c94aSIdo Barnea	e1000_ich8lan,
232a551c94aSIdo Barnea	e1000_ich9lan,
233a551c94aSIdo Barnea	e1000_ich10lan,
234a551c94aSIdo Barnea	e1000_pchlan,
235a551c94aSIdo Barnea	e1000_pch2lan,
236a551c94aSIdo Barnea	e1000_pch_lpt,
2379ca4a157SIdo Barnea	e1000_pch_spt,
2389ca4a157SIdo Barnea	e1000_pch_cnp,
239a551c94aSIdo Barnea	e1000_82575,
240a551c94aSIdo Barnea	e1000_82576,
241a551c94aSIdo Barnea	e1000_82580,
242a551c94aSIdo Barnea	e1000_i350,
243a551c94aSIdo Barnea	e1000_i354,
244a551c94aSIdo Barnea	e1000_i210,
245a551c94aSIdo Barnea	e1000_i211,
246a551c94aSIdo Barnea	e1000_vfadapt,
247a551c94aSIdo Barnea	e1000_vfadapt_i350,
248a551c94aSIdo Barnea	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
249a551c94aSIdo Barnea};
250a551c94aSIdo Barnea
251a551c94aSIdo Barneaenum e1000_media_type {
252a551c94aSIdo Barnea	e1000_media_type_unknown = 0,
253a551c94aSIdo Barnea	e1000_media_type_copper = 1,
254a551c94aSIdo Barnea	e1000_media_type_fiber = 2,
255a551c94aSIdo Barnea	e1000_media_type_internal_serdes = 3,
256a551c94aSIdo Barnea	e1000_num_media_types
257a551c94aSIdo Barnea};
258a551c94aSIdo Barnea
259a551c94aSIdo Barneaenum e1000_nvm_type {
260a551c94aSIdo Barnea	e1000_nvm_unknown = 0,
261a551c94aSIdo Barnea	e1000_nvm_none,
262a551c94aSIdo Barnea	e1000_nvm_eeprom_spi,
263a551c94aSIdo Barnea	e1000_nvm_eeprom_microwire,
264a551c94aSIdo Barnea	e1000_nvm_flash_hw,
265a551c94aSIdo Barnea	e1000_nvm_invm,
266a551c94aSIdo Barnea	e1000_nvm_flash_sw
267a551c94aSIdo Barnea};
268a551c94aSIdo Barnea
269a551c94aSIdo Barneaenum e1000_nvm_override {
270a551c94aSIdo Barnea	e1000_nvm_override_none = 0,
271a551c94aSIdo Barnea	e1000_nvm_override_spi_small,
272a551c94aSIdo Barnea	e1000_nvm_override_spi_large,
273a551c94aSIdo Barnea	e1000_nvm_override_microwire_small,
274a551c94aSIdo Barnea	e1000_nvm_override_microwire_large
275a551c94aSIdo Barnea};
276a551c94aSIdo Barnea
277a551c94aSIdo Barneaenum e1000_phy_type {
278a551c94aSIdo Barnea	e1000_phy_unknown = 0,
279a551c94aSIdo Barnea	e1000_phy_none,
280a551c94aSIdo Barnea	e1000_phy_m88,
281a551c94aSIdo Barnea	e1000_phy_igp,
282a551c94aSIdo Barnea	e1000_phy_igp_2,
283a551c94aSIdo Barnea	e1000_phy_gg82563,
284a551c94aSIdo Barnea	e1000_phy_igp_3,
285a551c94aSIdo Barnea	e1000_phy_ife,
286a551c94aSIdo Barnea	e1000_phy_bm,
287a551c94aSIdo Barnea	e1000_phy_82578,
288a551c94aSIdo Barnea	e1000_phy_82577,
289a551c94aSIdo Barnea	e1000_phy_82579,
290a551c94aSIdo Barnea	e1000_phy_i217,
291a551c94aSIdo Barnea	e1000_phy_82580,
292a551c94aSIdo Barnea	e1000_phy_vf,
293a551c94aSIdo Barnea	e1000_phy_i210,
294a551c94aSIdo Barnea};
295a551c94aSIdo Barnea
296a551c94aSIdo Barneaenum e1000_bus_type {
297a551c94aSIdo Barnea	e1000_bus_type_unknown = 0,
298a551c94aSIdo Barnea	e1000_bus_type_pci,
299a551c94aSIdo Barnea	e1000_bus_type_pcix,
300a551c94aSIdo Barnea	e1000_bus_type_pci_express,
301a551c94aSIdo Barnea	e1000_bus_type_reserved
302a551c94aSIdo Barnea};
303a551c94aSIdo Barnea
304a551c94aSIdo Barneaenum e1000_bus_speed {
305a551c94aSIdo Barnea	e1000_bus_speed_unknown = 0,
306a551c94aSIdo Barnea	e1000_bus_speed_33,
307a551c94aSIdo Barnea	e1000_bus_speed_66,
308a551c94aSIdo Barnea	e1000_bus_speed_100,
309a551c94aSIdo Barnea	e1000_bus_speed_120,
310a551c94aSIdo Barnea	e1000_bus_speed_133,
311a551c94aSIdo Barnea	e1000_bus_speed_2500,
312a551c94aSIdo Barnea	e1000_bus_speed_5000,
313a551c94aSIdo Barnea	e1000_bus_speed_reserved
314a551c94aSIdo Barnea};
315a551c94aSIdo Barnea
316a551c94aSIdo Barneaenum e1000_bus_width {
317a551c94aSIdo Barnea	e1000_bus_width_unknown = 0,
318a551c94aSIdo Barnea	e1000_bus_width_pcie_x1,
319a551c94aSIdo Barnea	e1000_bus_width_pcie_x2,
320a551c94aSIdo Barnea	e1000_bus_width_pcie_x4 = 4,
321a551c94aSIdo Barnea	e1000_bus_width_pcie_x8 = 8,
322a551c94aSIdo Barnea	e1000_bus_width_32,
323a551c94aSIdo Barnea	e1000_bus_width_64,
324a551c94aSIdo Barnea	e1000_bus_width_reserved
325a551c94aSIdo Barnea};
326a551c94aSIdo Barnea
327a551c94aSIdo Barneaenum e1000_1000t_rx_status {
328a551c94aSIdo Barnea	e1000_1000t_rx_status_not_ok = 0,
329a551c94aSIdo Barnea	e1000_1000t_rx_status_ok,
330a551c94aSIdo Barnea	e1000_1000t_rx_status_undefined = 0xFF
331a551c94aSIdo Barnea};
332a551c94aSIdo Barnea
333a551c94aSIdo Barneaenum e1000_rev_polarity {
334a551c94aSIdo Barnea	e1000_rev_polarity_normal = 0,
335a551c94aSIdo Barnea	e1000_rev_polarity_reversed,
336a551c94aSIdo Barnea	e1000_rev_polarity_undefined = 0xFF
337a551c94aSIdo Barnea};
338a551c94aSIdo Barnea
339a551c94aSIdo Barneaenum e1000_fc_mode {
340a551c94aSIdo Barnea	e1000_fc_none = 0,
341a551c94aSIdo Barnea	e1000_fc_rx_pause,
342a551c94aSIdo Barnea	e1000_fc_tx_pause,
343a551c94aSIdo Barnea	e1000_fc_full,
344a551c94aSIdo Barnea	e1000_fc_default = 0xFF
345a551c94aSIdo Barnea};
346a551c94aSIdo Barnea
347a551c94aSIdo Barneaenum e1000_ffe_config {
348a551c94aSIdo Barnea	e1000_ffe_config_enabled = 0,
349a551c94aSIdo Barnea	e1000_ffe_config_active,
350a551c94aSIdo Barnea	e1000_ffe_config_blocked
351a551c94aSIdo Barnea};
352a551c94aSIdo Barnea
353a551c94aSIdo Barneaenum e1000_dsp_config {
354a551c94aSIdo Barnea	e1000_dsp_config_disabled = 0,
355a551c94aSIdo Barnea	e1000_dsp_config_enabled,
356a551c94aSIdo Barnea	e1000_dsp_config_activated,
357a551c94aSIdo Barnea	e1000_dsp_config_undefined = 0xFF
358a551c94aSIdo Barnea};
359a551c94aSIdo Barnea
360a551c94aSIdo Barneaenum e1000_ms_type {
361a551c94aSIdo Barnea	e1000_ms_hw_default = 0,
362a551c94aSIdo Barnea	e1000_ms_force_master,
363a551c94aSIdo Barnea	e1000_ms_force_slave,
364a551c94aSIdo Barnea	e1000_ms_auto
365a551c94aSIdo Barnea};
366a551c94aSIdo Barnea
367a551c94aSIdo Barneaenum e1000_smart_speed {
368a551c94aSIdo Barnea	e1000_smart_speed_default = 0,
369a551c94aSIdo Barnea	e1000_smart_speed_on,
370a551c94aSIdo Barnea	e1000_smart_speed_off
371a551c94aSIdo Barnea};
372a551c94aSIdo Barnea
373a551c94aSIdo Barneaenum e1000_serdes_link_state {
374a551c94aSIdo Barnea	e1000_serdes_link_down = 0,
375a551c94aSIdo Barnea	e1000_serdes_link_autoneg_progress,
376a551c94aSIdo Barnea	e1000_serdes_link_autoneg_complete,
377a551c94aSIdo Barnea	e1000_serdes_link_forced_up
378a551c94aSIdo Barnea};
379a551c94aSIdo Barnea
380a551c94aSIdo Barnea#define __le16 u16
381a551c94aSIdo Barnea#define __le32 u32
382a551c94aSIdo Barnea#define __le64 u64
383a551c94aSIdo Barnea/* Receive Descriptor */
384a551c94aSIdo Barneastruct e1000_rx_desc {
385a551c94aSIdo Barnea	__le64 buffer_addr; /* Address of the descriptor's data buffer */
386a551c94aSIdo Barnea	__le16 length;      /* Length of data DMAed into data buffer */
387a551c94aSIdo Barnea	__le16 csum; /* Packet checksum */
388a551c94aSIdo Barnea	u8  status;  /* Descriptor status */
389a551c94aSIdo Barnea	u8  errors;  /* Descriptor Errors */
390a551c94aSIdo Barnea	__le16 special;
391a551c94aSIdo Barnea};
392a551c94aSIdo Barnea
393a551c94aSIdo Barnea/* Receive Descriptor - Extended */
394a551c94aSIdo Barneaunion e1000_rx_desc_extended {
395a551c94aSIdo Barnea	struct {
396a551c94aSIdo Barnea		__le64 buffer_addr;
397a551c94aSIdo Barnea		__le64 reserved;
398a551c94aSIdo Barnea	} read;
399a551c94aSIdo Barnea	struct {
400a551c94aSIdo Barnea		struct {
401a551c94aSIdo Barnea			__le32 mrq; /* Multiple Rx Queues */
402a551c94aSIdo Barnea			union {
403a551c94aSIdo Barnea				__le32 rss; /* RSS Hash */
404a551c94aSIdo Barnea				struct {
405a551c94aSIdo Barnea					__le16 ip_id;  /* IP id */
406a551c94aSIdo Barnea					__le16 csum;   /* Packet Checksum */
407a551c94aSIdo Barnea				} csum_ip;
408a551c94aSIdo Barnea			} hi_dword;
409a551c94aSIdo Barnea		} lower;
410a551c94aSIdo Barnea		struct {
411a551c94aSIdo Barnea			__le32 status_error;  /* ext status/error */
412a551c94aSIdo Barnea			__le16 length;
413a551c94aSIdo Barnea			__le16 vlan; /* VLAN tag */
414a551c94aSIdo Barnea		} upper;
415a551c94aSIdo Barnea	} wb;  /* writeback */
416a551c94aSIdo Barnea};
417a551c94aSIdo Barnea
418a551c94aSIdo Barnea#define MAX_PS_BUFFERS 4
419a551c94aSIdo Barnea
420a551c94aSIdo Barnea/* Number of packet split data buffers (not including the header buffer) */
421a551c94aSIdo Barnea#define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
422a551c94aSIdo Barnea
423a551c94aSIdo Barnea/* Receive Descriptor - Packet Split */
424a551c94aSIdo Barneaunion e1000_rx_desc_packet_split {
425a551c94aSIdo Barnea	struct {
426a551c94aSIdo Barnea		/* one buffer for protocol header(s), three data buffers */
427a551c94aSIdo Barnea		__le64 buffer_addr[MAX_PS_BUFFERS];
428a551c94aSIdo Barnea	} read;
429a551c94aSIdo Barnea	struct {
430a551c94aSIdo Barnea		struct {
431a551c94aSIdo Barnea			__le32 mrq;  /* Multiple Rx Queues */
432a551c94aSIdo Barnea			union {
433a551c94aSIdo Barnea				__le32 rss; /* RSS Hash */
434a551c94aSIdo Barnea				struct {
435a551c94aSIdo Barnea					__le16 ip_id;    /* IP id */
436a551c94aSIdo Barnea					__le16 csum;     /* Packet Checksum */
437a551c94aSIdo Barnea				} csum_ip;
438a551c94aSIdo Barnea			} hi_dword;
439a551c94aSIdo Barnea		} lower;
440a551c94aSIdo Barnea		struct {
441a551c94aSIdo Barnea			__le32 status_error;  /* ext status/error */
442a551c94aSIdo Barnea			__le16 length0;  /* length of buffer 0 */
443a551c94aSIdo Barnea			__le16 vlan;  /* VLAN tag */
444a551c94aSIdo Barnea		} middle;
445a551c94aSIdo Barnea		struct {
446a551c94aSIdo Barnea			__le16 header_status;
447a551c94aSIdo Barnea			/* length of buffers 1-3 */
448a551c94aSIdo Barnea			__le16 length[PS_PAGE_BUFFERS];
449a551c94aSIdo Barnea		} upper;
450a551c94aSIdo Barnea		__le64 reserved;
451a551c94aSIdo Barnea	} wb; /* writeback */
452a551c94aSIdo Barnea};
453a551c94aSIdo Barnea
454a551c94aSIdo Barnea/* Transmit Descriptor */
455a551c94aSIdo Barneastruct e1000_tx_desc {
456a551c94aSIdo Barnea	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
457a551c94aSIdo Barnea	union {
458a551c94aSIdo Barnea		__le32 data;
459a551c94aSIdo Barnea		struct {
460a551c94aSIdo Barnea			__le16 length;  /* Data buffer length */
461a551c94aSIdo Barnea			u8 cso;  /* Checksum offset */
462a551c94aSIdo Barnea			u8 cmd;  /* Descriptor control */
463a551c94aSIdo Barnea		} flags;
464a551c94aSIdo Barnea	} lower;
465a551c94aSIdo Barnea	union {
466a551c94aSIdo Barnea		__le32 data;
467a551c94aSIdo Barnea		struct {
468a551c94aSIdo Barnea			u8 status; /* Descriptor status */
469a551c94aSIdo Barnea			u8 css;  /* Checksum start */
470a551c94aSIdo Barnea			__le16 special;
471a551c94aSIdo Barnea		} fields;
472a551c94aSIdo Barnea	} upper;
473a551c94aSIdo Barnea};
474a551c94aSIdo Barnea
475a551c94aSIdo Barnea/* Offload Context Descriptor */
476a551c94aSIdo Barneastruct e1000_context_desc {
477a551c94aSIdo Barnea	union {
478a551c94aSIdo Barnea		__le32 ip_config;
479a551c94aSIdo Barnea		struct {
480a551c94aSIdo Barnea			u8 ipcss;  /* IP checksum start */
481a551c94aSIdo Barnea			u8 ipcso;  /* IP checksum offset */
482a551c94aSIdo Barnea			__le16 ipcse;  /* IP checksum end */
483a551c94aSIdo Barnea		} ip_fields;
484a551c94aSIdo Barnea	} lower_setup;
485a551c94aSIdo Barnea	union {
486a551c94aSIdo Barnea		__le32 tcp_config;
487a551c94aSIdo Barnea		struct {
488a551c94aSIdo Barnea			u8 tucss;  /* TCP checksum start */
489a551c94aSIdo Barnea			u8 tucso;  /* TCP checksum offset */
490a551c94aSIdo Barnea			__le16 tucse;  /* TCP checksum end */
491a551c94aSIdo Barnea		} tcp_fields;
492a551c94aSIdo Barnea	} upper_setup;
493a551c94aSIdo Barnea	__le32 cmd_and_length;
494a551c94aSIdo Barnea	union {
495a551c94aSIdo Barnea		__le32 data;
496a551c94aSIdo Barnea		struct {
497a551c94aSIdo Barnea			u8 status;  /* Descriptor status */
498a551c94aSIdo Barnea			u8 hdr_len;  /* Header length */
499a551c94aSIdo Barnea			__le16 mss;  /* Maximum segment size */
500a551c94aSIdo Barnea		} fields;
501a551c94aSIdo Barnea	} tcp_seg_setup;
502a551c94aSIdo Barnea};
503a551c94aSIdo Barnea
504a551c94aSIdo Barnea/* Offload data descriptor */
505a551c94aSIdo Barneastruct e1000_data_desc {
506a551c94aSIdo Barnea	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
507a551c94aSIdo Barnea	union {
508a551c94aSIdo Barnea		__le32 data;
509a551c94aSIdo Barnea		struct {
510a551c94aSIdo Barnea			__le16 length;  /* Data buffer length */
511a551c94aSIdo Barnea			u8 typ_len_ext;
512a551c94aSIdo Barnea			u8 cmd;
513a551c94aSIdo Barnea		} flags;
514a551c94aSIdo Barnea	} lower;
515a551c94aSIdo Barnea	union {
516a551c94aSIdo Barnea		__le32 data;
517a551c94aSIdo Barnea		struct {
518a551c94aSIdo Barnea			u8 status;  /* Descriptor status */
519a551c94aSIdo Barnea			u8 popts;  /* Packet Options */
520a551c94aSIdo Barnea			__le16 special;
521a551c94aSIdo Barnea		} fields;
522a551c94aSIdo Barnea	} upper;
523a551c94aSIdo Barnea};
524a551c94aSIdo Barnea
525a551c94aSIdo Barnea/* Statistics counters collected by the MAC */
526a551c94aSIdo Barneastruct e1000_hw_stats {
527a551c94aSIdo Barnea	u64 crcerrs;
528a551c94aSIdo Barnea	u64 algnerrc;
529a551c94aSIdo Barnea	u64 symerrs;
530a551c94aSIdo Barnea	u64 rxerrc;
531a551c94aSIdo Barnea	u64 mpc;
532a551c94aSIdo Barnea	u64 scc;
533a551c94aSIdo Barnea	u64 ecol;
534a551c94aSIdo Barnea	u64 mcc;
535a551c94aSIdo Barnea	u64 latecol;
536a551c94aSIdo Barnea	u64 colc;
537a551c94aSIdo Barnea	u64 dc;
538a551c94aSIdo Barnea	u64 tncrs;
539a551c94aSIdo Barnea	u64 sec;
540a551c94aSIdo Barnea	u64 cexterr;
541a551c94aSIdo Barnea	u64 rlec;
542a551c94aSIdo Barnea	u64 xonrxc;
543a551c94aSIdo Barnea	u64 xontxc;
544a551c94aSIdo Barnea	u64 xoffrxc;
545a551c94aSIdo Barnea	u64 xofftxc;
546a551c94aSIdo Barnea	u64 fcruc;
547a551c94aSIdo Barnea	u64 prc64;
548a551c94aSIdo Barnea	u64 prc127;
549a551c94aSIdo Barnea	u64 prc255;
550a551c94aSIdo Barnea	u64 prc511;
551a551c94aSIdo Barnea	u64 prc1023;
552a551c94aSIdo Barnea	u64 prc1522;
553a551c94aSIdo Barnea	u64 gprc;
554a551c94aSIdo Barnea	u64 bprc;
555a551c94aSIdo Barnea	u64 mprc;
556a551c94aSIdo Barnea	u64 gptc;
557a551c94aSIdo Barnea	u64 gorc;
558a551c94aSIdo Barnea	u64 gotc;
559a551c94aSIdo Barnea	u64 rnbc;
560a551c94aSIdo Barnea	u64 ruc;
561a551c94aSIdo Barnea	u64 rfc;
562a551c94aSIdo Barnea	u64 roc;
563a551c94aSIdo Barnea	u64 rjc;
564a551c94aSIdo Barnea	u64 mgprc;
565a551c94aSIdo Barnea	u64 mgpdc;
566a551c94aSIdo Barnea	u64 mgptc;
567a551c94aSIdo Barnea	u64 tor;
568a551c94aSIdo Barnea	u64 tot;
569a551c94aSIdo Barnea	u64 tpr;
570a551c94aSIdo Barnea	u64 tpt;
571a551c94aSIdo Barnea	u64 ptc64;
572a551c94aSIdo Barnea	u64 ptc127;
573a551c94aSIdo Barnea	u64 ptc255;
574a551c94aSIdo Barnea	u64 ptc511;
575a551c94aSIdo Barnea	u64 ptc1023;
576a551c94aSIdo Barnea	u64 ptc1522;
577a551c94aSIdo Barnea	u64 mptc;
578a551c94aSIdo Barnea	u64 bptc;
579a551c94aSIdo Barnea	u64 tsctc;
580a551c94aSIdo Barnea	u64 tsctfc;
581a551c94aSIdo Barnea	u64 iac;
582a551c94aSIdo Barnea	u64 icrxptc;
583a551c94aSIdo Barnea	u64 icrxatc;
584a551c94aSIdo Barnea	u64 ictxptc;
585a551c94aSIdo Barnea	u64 ictxatc;
586a551c94aSIdo Barnea	u64 ictxqec;
587a551c94aSIdo Barnea	u64 ictxqmtc;
588a551c94aSIdo Barnea	u64 icrxdmtc;
589a551c94aSIdo Barnea	u64 icrxoc;
590a551c94aSIdo Barnea	u64 cbtmpc;
591a551c94aSIdo Barnea	u64 htdpmc;
592a551c94aSIdo Barnea	u64 cbrdpc;
593a551c94aSIdo Barnea	u64 cbrmpc;
594a551c94aSIdo Barnea	u64 rpthc;
595a551c94aSIdo Barnea	u64 hgptc;
596a551c94aSIdo Barnea	u64 htcbdpc;
597a551c94aSIdo Barnea	u64 hgorc;
598a551c94aSIdo Barnea	u64 hgotc;
599a551c94aSIdo Barnea	u64 lenerrs;
600a551c94aSIdo Barnea	u64 scvpc;
601a551c94aSIdo Barnea	u64 hrmpc;
602a551c94aSIdo Barnea	u64 doosync;
603a551c94aSIdo Barnea	u64 o2bgptc;
604a551c94aSIdo Barnea	u64 o2bspc;
605a551c94aSIdo Barnea	u64 b2ospc;
606a551c94aSIdo Barnea	u64 b2ogprc;
607a551c94aSIdo Barnea};
608a551c94aSIdo Barnea
609a551c94aSIdo Barneastruct e1000_vf_stats {
610a551c94aSIdo Barnea	u64 base_gprc;
611a551c94aSIdo Barnea	u64 base_gptc;
612a551c94aSIdo Barnea	u64 base_gorc;
613a551c94aSIdo Barnea	u64 base_gotc;
614a551c94aSIdo Barnea	u64 base_mprc;
615a551c94aSIdo Barnea	u64 base_gotlbc;
616a551c94aSIdo Barnea	u64 base_gptlbc;
617a551c94aSIdo Barnea	u64 base_gorlbc;
618a551c94aSIdo Barnea	u64 base_gprlbc;
619a551c94aSIdo Barnea
620a551c94aSIdo Barnea	u32 last_gprc;
621a551c94aSIdo Barnea	u32 last_gptc;
622a551c94aSIdo Barnea	u32 last_gorc;
623a551c94aSIdo Barnea	u32 last_gotc;
624a551c94aSIdo Barnea	u32 last_mprc;
625a551c94aSIdo Barnea	u32 last_gotlbc;
626a551c94aSIdo Barnea	u32 last_gptlbc;
627a551c94aSIdo Barnea	u32 last_gorlbc;
628a551c94aSIdo Barnea	u32 last_gprlbc;
629a551c94aSIdo Barnea
630a551c94aSIdo Barnea	u64 gprc;
631a551c94aSIdo Barnea	u64 gptc;
632a551c94aSIdo Barnea	u64 gorc;
633a551c94aSIdo Barnea	u64 gotc;
634a551c94aSIdo Barnea	u64 mprc;
635a551c94aSIdo Barnea	u64 gotlbc;
636a551c94aSIdo Barnea	u64 gptlbc;
637a551c94aSIdo Barnea	u64 gorlbc;
638a551c94aSIdo Barnea	u64 gprlbc;
639a551c94aSIdo Barnea};
640a551c94aSIdo Barnea
641a551c94aSIdo Barneastruct e1000_phy_stats {
642a551c94aSIdo Barnea	u32 idle_errors;
643a551c94aSIdo Barnea	u32 receive_errors;
644a551c94aSIdo Barnea};
645a551c94aSIdo Barnea
646a551c94aSIdo Barneastruct e1000_host_mng_dhcp_cookie {
647a551c94aSIdo Barnea	u32 signature;
648a551c94aSIdo Barnea	u8  status;
649a551c94aSIdo Barnea	u8  reserved0;
650a551c94aSIdo Barnea	u16 vlan_id;
651a551c94aSIdo Barnea	u32 reserved1;
652a551c94aSIdo Barnea	u16 reserved2;
653a551c94aSIdo Barnea	u8  reserved3;
654a551c94aSIdo Barnea	u8  checksum;
655a551c94aSIdo Barnea};
656a551c94aSIdo Barnea
657a551c94aSIdo Barnea/* Host Interface "Rev 1" */
658a551c94aSIdo Barneastruct e1000_host_command_header {
659a551c94aSIdo Barnea	u8 command_id;
660a551c94aSIdo Barnea	u8 command_length;
661a551c94aSIdo Barnea	u8 command_options;
662a551c94aSIdo Barnea	u8 checksum;
663a551c94aSIdo Barnea};
664a551c94aSIdo Barnea
665a551c94aSIdo Barnea#define E1000_HI_MAX_DATA_LENGTH	252
666a551c94aSIdo Barneastruct e1000_host_command_info {
667a551c94aSIdo Barnea	struct e1000_host_command_header command_header;
668a551c94aSIdo Barnea	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
669a551c94aSIdo Barnea};
670a551c94aSIdo Barnea
671a551c94aSIdo Barnea/* Host Interface "Rev 2" */
672a551c94aSIdo Barneastruct e1000_host_mng_command_header {
673a551c94aSIdo Barnea	u8  command_id;
674a551c94aSIdo Barnea	u8  checksum;
675a551c94aSIdo Barnea	u16 reserved1;
676a551c94aSIdo Barnea	u16 reserved2;
677a551c94aSIdo Barnea	u16 command_length;
678a551c94aSIdo Barnea};
679a551c94aSIdo Barnea
680a551c94aSIdo Barnea#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
681a551c94aSIdo Barneastruct e1000_host_mng_command_info {
682a551c94aSIdo Barnea	struct e1000_host_mng_command_header command_header;
683a551c94aSIdo Barnea	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
684a551c94aSIdo Barnea};
685a551c94aSIdo Barnea
686a551c94aSIdo Barnea#include "e1000_mac.h"
687a551c94aSIdo Barnea#include "e1000_phy.h"
688a551c94aSIdo Barnea#include "e1000_nvm.h"
689a551c94aSIdo Barnea#include "e1000_manage.h"
690a551c94aSIdo Barnea#include "e1000_mbx.h"
691a551c94aSIdo Barnea
692a551c94aSIdo Barnea/* Function pointers for the MAC. */
693a551c94aSIdo Barneastruct e1000_mac_operations {
694a551c94aSIdo Barnea	s32  (*init_params)(struct e1000_hw *);
695a551c94aSIdo Barnea	s32  (*id_led_init)(struct e1000_hw *);
696a551c94aSIdo Barnea	s32  (*blink_led)(struct e1000_hw *);
697a551c94aSIdo Barnea	bool (*check_mng_mode)(struct e1000_hw *);
698a551c94aSIdo Barnea	s32  (*check_for_link)(struct e1000_hw *);
699a551c94aSIdo Barnea	s32  (*cleanup_led)(struct e1000_hw *);
700a551c94aSIdo Barnea	void (*clear_hw_cntrs)(struct e1000_hw *);
701a551c94aSIdo Barnea	void (*clear_vfta)(struct e1000_hw *);
702a551c94aSIdo Barnea	s32  (*get_bus_info)(struct e1000_hw *);
703a551c94aSIdo Barnea	void (*set_lan_id)(struct e1000_hw *);
704a551c94aSIdo Barnea	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
705a551c94aSIdo Barnea	s32  (*led_on)(struct e1000_hw *);
706a551c94aSIdo Barnea	s32  (*led_off)(struct e1000_hw *);
707a551c94aSIdo Barnea	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
708a551c94aSIdo Barnea	s32  (*reset_hw)(struct e1000_hw *);
709a551c94aSIdo Barnea	s32  (*init_hw)(struct e1000_hw *);
710a551c94aSIdo Barnea	void (*shutdown_serdes)(struct e1000_hw *);
711a551c94aSIdo Barnea	void (*power_up_serdes)(struct e1000_hw *);
712a551c94aSIdo Barnea	s32  (*setup_link)(struct e1000_hw *);
713a551c94aSIdo Barnea	s32  (*setup_physical_interface)(struct e1000_hw *);
714a551c94aSIdo Barnea	s32  (*setup_led)(struct e1000_hw *);
715a551c94aSIdo Barnea	void (*write_vfta)(struct e1000_hw *, u32, u32);
716a551c94aSIdo Barnea	void (*config_collision_dist)(struct e1000_hw *);
717a551c94aSIdo Barnea	int  (*rar_set)(struct e1000_hw *, u8*, u32);
718a551c94aSIdo Barnea	s32  (*read_mac_addr)(struct e1000_hw *);
719a551c94aSIdo Barnea	s32  (*validate_mdi_setting)(struct e1000_hw *);
720a551c94aSIdo Barnea	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
721a551c94aSIdo Barnea	void (*release_swfw_sync)(struct e1000_hw *, u16);
722a551c94aSIdo Barnea};
723a551c94aSIdo Barnea
724a551c94aSIdo Barnea/* When to use various PHY register access functions:
725a551c94aSIdo Barnea *
726a551c94aSIdo Barnea *                 Func   Caller
727a551c94aSIdo Barnea *   Function      Does   Does    When to use
728a551c94aSIdo Barnea *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
729a551c94aSIdo Barnea *   X_reg         L,P,A  n/a     for simple PHY reg accesses
730a551c94aSIdo Barnea *   X_reg_locked  P,A    L       for multiple accesses of different regs
731a551c94aSIdo Barnea *                                on different pages
732a551c94aSIdo Barnea *   X_reg_page    A      L,P     for multiple accesses of different regs
733a551c94aSIdo Barnea *                                on the same page
734a551c94aSIdo Barnea *
735a551c94aSIdo Barnea * Where X=[read|write], L=locking, P=sets page, A=register access
736a551c94aSIdo Barnea *
737a551c94aSIdo Barnea */
738a551c94aSIdo Barneastruct e1000_phy_operations {
739a551c94aSIdo Barnea	s32  (*init_params)(struct e1000_hw *);
740a551c94aSIdo Barnea	s32  (*acquire)(struct e1000_hw *);
741a551c94aSIdo Barnea	s32  (*cfg_on_link_up)(struct e1000_hw *);
742a551c94aSIdo Barnea	s32  (*check_polarity)(struct e1000_hw *);
743a551c94aSIdo Barnea	s32  (*check_reset_block)(struct e1000_hw *);
744a551c94aSIdo Barnea	s32  (*commit)(struct e1000_hw *);
745a551c94aSIdo Barnea	s32  (*force_speed_duplex)(struct e1000_hw *);
746a551c94aSIdo Barnea	s32  (*get_cfg_done)(struct e1000_hw *hw);
747a551c94aSIdo Barnea	s32  (*get_cable_length)(struct e1000_hw *);
748a551c94aSIdo Barnea	s32  (*get_info)(struct e1000_hw *);
749a551c94aSIdo Barnea	s32  (*set_page)(struct e1000_hw *, u16);
750a551c94aSIdo Barnea	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
751a551c94aSIdo Barnea	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
752a551c94aSIdo Barnea	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
753a551c94aSIdo Barnea	void (*release)(struct e1000_hw *);
754a551c94aSIdo Barnea	s32  (*reset)(struct e1000_hw *);
755a551c94aSIdo Barnea	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
756a551c94aSIdo Barnea	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
757a551c94aSIdo Barnea	s32  (*write_reg)(struct e1000_hw *, u32, u16);
758a551c94aSIdo Barnea	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
759a551c94aSIdo Barnea	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
760a551c94aSIdo Barnea	void (*power_up)(struct e1000_hw *);
761a551c94aSIdo Barnea	void (*power_down)(struct e1000_hw *);
762a551c94aSIdo Barnea	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
763a551c94aSIdo Barnea	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
764a551c94aSIdo Barnea};
765a551c94aSIdo Barnea
766a551c94aSIdo Barnea/* Function pointers for the NVM. */
767a551c94aSIdo Barneastruct e1000_nvm_operations {
768a551c94aSIdo Barnea	s32  (*init_params)(struct e1000_hw *);
769a551c94aSIdo Barnea	s32  (*acquire)(struct e1000_hw *);
770a551c94aSIdo Barnea	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
771a551c94aSIdo Barnea	void (*release)(struct e1000_hw *);
772a551c94aSIdo Barnea	void (*reload)(struct e1000_hw *);
773a551c94aSIdo Barnea	s32  (*update)(struct e1000_hw *);
774a551c94aSIdo Barnea	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
775a551c94aSIdo Barnea	s32  (*validate)(struct e1000_hw *);
776a551c94aSIdo Barnea	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
777a551c94aSIdo Barnea};
778a551c94aSIdo Barnea
779a551c94aSIdo Barneastruct e1000_mac_info {
780a551c94aSIdo Barnea	struct e1000_mac_operations ops;
781a551c94aSIdo Barnea	u8 addr[ETH_ADDR_LEN];
782a551c94aSIdo Barnea	u8 perm_addr[ETH_ADDR_LEN];
783a551c94aSIdo Barnea
784a551c94aSIdo Barnea	enum e1000_mac_type type;
785a551c94aSIdo Barnea
786a551c94aSIdo Barnea	u32 collision_delta;
787a551c94aSIdo Barnea	u32 ledctl_default;
788a551c94aSIdo Barnea	u32 ledctl_mode1;
789a551c94aSIdo Barnea	u32 ledctl_mode2;
790a551c94aSIdo Barnea	u32 mc_filter_type;
791a551c94aSIdo Barnea	u32 tx_packet_delta;
792a551c94aSIdo Barnea	u32 txcw;
793a551c94aSIdo Barnea
794a551c94aSIdo Barnea	u16 current_ifs_val;
795a551c94aSIdo Barnea	u16 ifs_max_val;
796a551c94aSIdo Barnea	u16 ifs_min_val;
797a551c94aSIdo Barnea	u16 ifs_ratio;
798a551c94aSIdo Barnea	u16 ifs_step_size;
799a551c94aSIdo Barnea	u16 mta_reg_count;
800a551c94aSIdo Barnea	u16 uta_reg_count;
801a551c94aSIdo Barnea
802a551c94aSIdo Barnea	/* Maximum size of the MTA register table in all supported adapters */
803a551c94aSIdo Barnea#define MAX_MTA_REG 128
804a551c94aSIdo Barnea	u32 mta_shadow[MAX_MTA_REG];
805a551c94aSIdo Barnea	u16 rar_entry_count;
806a551c94aSIdo Barnea
807a551c94aSIdo Barnea	u8  forced_speed_duplex;
808a551c94aSIdo Barnea
809a551c94aSIdo Barnea	bool adaptive_ifs;
810a551c94aSIdo Barnea	bool has_fwsm;
811a551c94aSIdo Barnea	bool arc_subsystem_valid;
812a551c94aSIdo Barnea	bool asf_firmware_present;
813a551c94aSIdo Barnea	bool autoneg;
814a551c94aSIdo Barnea	bool autoneg_failed;
815a551c94aSIdo Barnea	bool get_link_status;
816a551c94aSIdo Barnea	bool in_ifs_mode;
817a551c94aSIdo Barnea	bool report_tx_early;
818a551c94aSIdo Barnea	enum e1000_serdes_link_state serdes_link_state;
819a551c94aSIdo Barnea	bool serdes_has_link;
820a551c94aSIdo Barnea	bool tx_pkt_filtering;
821a551c94aSIdo Barnea};
822a551c94aSIdo Barnea
823a551c94aSIdo Barneastruct e1000_phy_info {
824a551c94aSIdo Barnea	struct e1000_phy_operations ops;
825a551c94aSIdo Barnea	enum e1000_phy_type type;
826a551c94aSIdo Barnea
827a551c94aSIdo Barnea	enum e1000_1000t_rx_status local_rx;
828a551c94aSIdo Barnea	enum e1000_1000t_rx_status remote_rx;
829a551c94aSIdo Barnea	enum e1000_ms_type ms_type;
830a551c94aSIdo Barnea	enum e1000_ms_type original_ms_type;
831a551c94aSIdo Barnea	enum e1000_rev_polarity cable_polarity;
832a551c94aSIdo Barnea	enum e1000_smart_speed smart_speed;
833a551c94aSIdo Barnea
834a551c94aSIdo Barnea	u32 addr;
835a551c94aSIdo Barnea	u32 id;
836a551c94aSIdo Barnea	u32 reset_delay_us; /* in usec */
837a551c94aSIdo Barnea	u32 revision;
838a551c94aSIdo Barnea
839a551c94aSIdo Barnea	enum e1000_media_type media_type;
840a551c94aSIdo Barnea
841a551c94aSIdo Barnea	u16 autoneg_advertised;
842a551c94aSIdo Barnea	u16 autoneg_mask;
843a551c94aSIdo Barnea	u16 cable_length;
844a551c94aSIdo Barnea	u16 max_cable_length;
845a551c94aSIdo Barnea	u16 min_cable_length;
846a551c94aSIdo Barnea
847a551c94aSIdo Barnea	u8 mdix;
848a551c94aSIdo Barnea
849a551c94aSIdo Barnea	bool disable_polarity_correction;
850a551c94aSIdo Barnea	bool is_mdix;
851a551c94aSIdo Barnea	bool polarity_correction;
852a551c94aSIdo Barnea	bool speed_downgraded;
853a551c94aSIdo Barnea	bool autoneg_wait_to_complete;
854a551c94aSIdo Barnea};
855a551c94aSIdo Barnea
856a551c94aSIdo Barneastruct e1000_nvm_info {
857a551c94aSIdo Barnea	struct e1000_nvm_operations ops;
858a551c94aSIdo Barnea	enum e1000_nvm_type type;
859a551c94aSIdo Barnea	enum e1000_nvm_override override;
860a551c94aSIdo Barnea
861a551c94aSIdo Barnea	u32 flash_bank_size;
862a551c94aSIdo Barnea	u32 flash_base_addr;
863a551c94aSIdo Barnea
864a551c94aSIdo Barnea	u16 word_size;
865a551c94aSIdo Barnea	u16 delay_usec;
866a551c94aSIdo Barnea	u16 address_bits;
867a551c94aSIdo Barnea	u16 opcode_bits;
868a551c94aSIdo Barnea	u16 page_size;
869a551c94aSIdo Barnea};
870a551c94aSIdo Barnea
871a551c94aSIdo Barneastruct e1000_bus_info {
872a551c94aSIdo Barnea	enum e1000_bus_type type;
873a551c94aSIdo Barnea	enum e1000_bus_speed speed;
874a551c94aSIdo Barnea	enum e1000_bus_width width;
875a551c94aSIdo Barnea
876a551c94aSIdo Barnea	u16 func;
877a551c94aSIdo Barnea	u16 pci_cmd_word;
878a551c94aSIdo Barnea};
879a551c94aSIdo Barnea
880a551c94aSIdo Barneastruct e1000_fc_info {
881a551c94aSIdo Barnea	u32 high_water;  /* Flow control high-water mark */
882a551c94aSIdo Barnea	u32 low_water;  /* Flow control low-water mark */
883a551c94aSIdo Barnea	u16 pause_time;  /* Flow control pause timer */
884a551c94aSIdo Barnea	u16 refresh_time;  /* Flow control refresh timer */
885a551c94aSIdo Barnea	bool send_xon;  /* Flow control send XON */
886a551c94aSIdo Barnea	bool strict_ieee;  /* Strict IEEE mode */
887a551c94aSIdo Barnea	enum e1000_fc_mode current_mode;  /* FC mode in effect */
888a551c94aSIdo Barnea	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
889a551c94aSIdo Barnea};
890a551c94aSIdo Barnea
891a551c94aSIdo Barneastruct e1000_mbx_operations {
892a551c94aSIdo Barnea	s32 (*init_params)(struct e1000_hw *hw);
893a551c94aSIdo Barnea	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
894a551c94aSIdo Barnea	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
895a551c94aSIdo Barnea	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
896a551c94aSIdo Barnea	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
897a551c94aSIdo Barnea	s32 (*check_for_msg)(struct e1000_hw *, u16);
898a551c94aSIdo Barnea	s32 (*check_for_ack)(struct e1000_hw *, u16);
899a551c94aSIdo Barnea	s32 (*check_for_rst)(struct e1000_hw *, u16);
900a551c94aSIdo Barnea};
901a551c94aSIdo Barnea
902a551c94aSIdo Barneastruct e1000_mbx_stats {
903a551c94aSIdo Barnea	u32 msgs_tx;
904a551c94aSIdo Barnea	u32 msgs_rx;
905a551c94aSIdo Barnea
906a551c94aSIdo Barnea	u32 acks;
907a551c94aSIdo Barnea	u32 reqs;
908a551c94aSIdo Barnea	u32 rsts;
909a551c94aSIdo Barnea};
910a551c94aSIdo Barnea
911a551c94aSIdo Barneastruct e1000_mbx_info {
912a551c94aSIdo Barnea	struct e1000_mbx_operations ops;
913a551c94aSIdo Barnea	struct e1000_mbx_stats stats;
914a551c94aSIdo Barnea	u32 timeout;
915a551c94aSIdo Barnea	u32 usec_delay;
916a551c94aSIdo Barnea	u16 size;
917a551c94aSIdo Barnea};
918a551c94aSIdo Barnea
919a551c94aSIdo Barneastruct e1000_dev_spec_82541 {
920a551c94aSIdo Barnea	enum e1000_dsp_config dsp_config;
921a551c94aSIdo Barnea	enum e1000_ffe_config ffe_config;
922a551c94aSIdo Barnea	u16 spd_default;
923a551c94aSIdo Barnea	bool phy_init_script;
924a551c94aSIdo Barnea};
925a551c94aSIdo Barnea
926a551c94aSIdo Barneastruct e1000_dev_spec_82542 {
927a551c94aSIdo Barnea	bool dma_fairness;
928a551c94aSIdo Barnea};
929a551c94aSIdo Barnea
930a551c94aSIdo Barneastruct e1000_dev_spec_82543 {
931a551c94aSIdo Barnea	u32  tbi_compatibility;
932a551c94aSIdo Barnea	bool dma_fairness;
933a551c94aSIdo Barnea	bool init_phy_disabled;
934a551c94aSIdo Barnea};
935a551c94aSIdo Barnea
936a551c94aSIdo Barneastruct e1000_dev_spec_82571 {
937a551c94aSIdo Barnea	bool laa_is_present;
938a551c94aSIdo Barnea	u32 smb_counter;
939a551c94aSIdo Barnea	E1000_MUTEX swflag_mutex;
940a551c94aSIdo Barnea};
941a551c94aSIdo Barnea
942a551c94aSIdo Barneastruct e1000_dev_spec_80003es2lan {
943a551c94aSIdo Barnea	bool  mdic_wa_enable;
944a551c94aSIdo Barnea};
945a551c94aSIdo Barnea
946a551c94aSIdo Barneastruct e1000_shadow_ram {
947a551c94aSIdo Barnea	u16  value;
948a551c94aSIdo Barnea	bool modified;
949a551c94aSIdo Barnea};
950a551c94aSIdo Barnea
951a551c94aSIdo Barnea#define E1000_SHADOW_RAM_WORDS		2048
952a551c94aSIdo Barnea
953a551c94aSIdo Barnea#ifdef ULP_SUPPORT
954a551c94aSIdo Barnea/* I218 PHY Ultra Low Power (ULP) states */
955a551c94aSIdo Barneaenum e1000_ulp_state {
956a551c94aSIdo Barnea	e1000_ulp_state_unknown,
957a551c94aSIdo Barnea	e1000_ulp_state_off,
958a551c94aSIdo Barnea	e1000_ulp_state_on,
959a551c94aSIdo Barnea};
960a551c94aSIdo Barnea
961a551c94aSIdo Barnea#endif /* ULP_SUPPORT */
962a551c94aSIdo Barneastruct e1000_dev_spec_ich8lan {
963a551c94aSIdo Barnea	bool kmrn_lock_loss_workaround_enabled;
964a551c94aSIdo Barnea	struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
965a551c94aSIdo Barnea	E1000_MUTEX nvm_mutex;
966a551c94aSIdo Barnea	E1000_MUTEX swflag_mutex;
967a551c94aSIdo Barnea	bool nvm_k1_enabled;
9689ca4a157SIdo Barnea	bool disable_k1_off;
969a551c94aSIdo Barnea	bool eee_disable;
970a551c94aSIdo Barnea	u16 eee_lp_ability;
971a551c94aSIdo Barnea#ifdef ULP_SUPPORT
972a551c94aSIdo Barnea	enum e1000_ulp_state ulp_state;
9739ca4a157SIdo Barnea	bool ulp_capability_disabled;
9749ca4a157SIdo Barnea	bool during_suspend_flow;
9759ca4a157SIdo Barnea	bool during_dpg_exit;
9769ca4a157SIdo Barnea#endif /* ULP_SUPPORT */
977a551c94aSIdo Barnea	u16 lat_enc;
978a551c94aSIdo Barnea	u16 max_ltr_enc;
979a551c94aSIdo Barnea	bool smbus_disable;
980a551c94aSIdo Barnea};
981a551c94aSIdo Barnea
982a551c94aSIdo Barneastruct e1000_dev_spec_82575 {
983a551c94aSIdo Barnea	bool sgmii_active;
984a551c94aSIdo Barnea	bool global_device_reset;
985a551c94aSIdo Barnea	bool eee_disable;
986a551c94aSIdo Barnea	bool module_plugged;
987a551c94aSIdo Barnea	bool clear_semaphore_once;
988a551c94aSIdo Barnea	u32 mtu;
989a551c94aSIdo Barnea	struct sfp_e1000_flags eth_flags;
990a551c94aSIdo Barnea	u8 media_port;
991a551c94aSIdo Barnea	bool media_changed;
992a551c94aSIdo Barnea};
993a551c94aSIdo Barnea
994a551c94aSIdo Barneastruct e1000_dev_spec_vf {
995a551c94aSIdo Barnea	u32 vf_number;
996a551c94aSIdo Barnea	u32 v2p_mailbox;
997a551c94aSIdo Barnea};
998a551c94aSIdo Barnea
999a551c94aSIdo Barneastruct e1000_hw {
1000a551c94aSIdo Barnea	void *back;
1001a551c94aSIdo Barnea
1002a551c94aSIdo Barnea	u8 *hw_addr;
1003a551c94aSIdo Barnea	u8 *flash_address;
1004a551c94aSIdo Barnea	unsigned long io_base;
1005a551c94aSIdo Barnea
1006a551c94aSIdo Barnea	struct e1000_mac_info  mac;
1007a551c94aSIdo Barnea	struct e1000_fc_info   fc;
1008a551c94aSIdo Barnea	struct e1000_phy_info  phy;
1009a551c94aSIdo Barnea	struct e1000_nvm_info  nvm;
1010a551c94aSIdo Barnea	struct e1000_bus_info  bus;
1011a551c94aSIdo Barnea	struct e1000_mbx_info mbx;
1012a551c94aSIdo Barnea	struct e1000_host_mng_dhcp_cookie mng_cookie;
1013a551c94aSIdo Barnea
1014a551c94aSIdo Barnea	union {
1015a551c94aSIdo Barnea		struct e1000_dev_spec_82541 _82541;
1016a551c94aSIdo Barnea		struct e1000_dev_spec_82542 _82542;
1017a551c94aSIdo Barnea		struct e1000_dev_spec_82543 _82543;
1018a551c94aSIdo Barnea		struct e1000_dev_spec_82571 _82571;
1019a551c94aSIdo Barnea		struct e1000_dev_spec_80003es2lan _80003es2lan;
1020a551c94aSIdo Barnea		struct e1000_dev_spec_ich8lan ich8lan;
1021a551c94aSIdo Barnea		struct e1000_dev_spec_82575 _82575;
1022a551c94aSIdo Barnea		struct e1000_dev_spec_vf vf;
1023a551c94aSIdo Barnea	} dev_spec;
1024a551c94aSIdo Barnea
1025a551c94aSIdo Barnea	u16 device_id;
1026a551c94aSIdo Barnea	u16 subsystem_vendor_id;
1027a551c94aSIdo Barnea	u16 subsystem_device_id;
1028a551c94aSIdo Barnea	u16 vendor_id;
1029a551c94aSIdo Barnea
1030a551c94aSIdo Barnea	u8  revision_id;
1031a551c94aSIdo Barnea};
1032a551c94aSIdo Barnea
1033a551c94aSIdo Barnea#include "e1000_82541.h"
1034a551c94aSIdo Barnea#include "e1000_82543.h"
1035a551c94aSIdo Barnea#include "e1000_82571.h"
1036a551c94aSIdo Barnea#include "e1000_80003es2lan.h"
1037a551c94aSIdo Barnea#include "e1000_ich8lan.h"
1038a551c94aSIdo Barnea#include "e1000_82575.h"
1039a551c94aSIdo Barnea#include "e1000_i210.h"
1040a551c94aSIdo Barnea
1041a551c94aSIdo Barnea/* These functions must be implemented by drivers */
1042a551c94aSIdo Barneavoid e1000_pci_clear_mwi(struct e1000_hw *hw);
1043a551c94aSIdo Barneavoid e1000_pci_set_mwi(struct e1000_hw *hw);
1044a551c94aSIdo Barneas32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1045a551c94aSIdo Barneas32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1046a551c94aSIdo Barneavoid e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1047a551c94aSIdo Barneavoid e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1048a551c94aSIdo Barnea
1049a551c94aSIdo Barnea#endif