1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
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6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
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16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
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20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_I210_H_
35a551c94aSIdo Barnea#define _E1000_I210_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barneabool e1000_get_flash_presence_i210(struct e1000_hw *hw);
38a551c94aSIdo Barneas32 e1000_update_flash_i210(struct e1000_hw *hw);
39a551c94aSIdo Barneas32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);
40a551c94aSIdo Barneas32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);
41a551c94aSIdo Barneas32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
42a551c94aSIdo Barnea			      u16 words, u16 *data);
43a551c94aSIdo Barneas32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
44a551c94aSIdo Barnea			     u16 words, u16 *data);
45a551c94aSIdo Barneas32 e1000_read_invm_version(struct e1000_hw *hw,
46a551c94aSIdo Barnea			    struct e1000_fw_version *invm_ver);
47a551c94aSIdo Barneas32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
48a551c94aSIdo Barneavoid e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
49a551c94aSIdo Barneas32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
50a551c94aSIdo Barnea			 u16 *data);
51a551c94aSIdo Barneas32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
52a551c94aSIdo Barnea			  u16 data);
53a551c94aSIdo Barneas32 e1000_init_hw_i210(struct e1000_hw *hw);
54a551c94aSIdo Barnea
55a551c94aSIdo Barnea#define E1000_STM_OPCODE		0xDB00
56a551c94aSIdo Barnea#define E1000_EEPROM_FLASH_SIZE_WORD	0x11
57a551c94aSIdo Barnea
58a551c94aSIdo Barnea#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
59a551c94aSIdo Barnea	(u8)((invm_dword) & 0x7)
60a551c94aSIdo Barnea#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
61a551c94aSIdo Barnea	(u8)(((invm_dword) & 0x0000FE00) >> 9)
62a551c94aSIdo Barnea#define INVM_DWORD_TO_WORD_DATA(invm_dword) \
63a551c94aSIdo Barnea	(u16)(((invm_dword) & 0xFFFF0000) >> 16)
64a551c94aSIdo Barnea
65a551c94aSIdo Barneaenum E1000_INVM_STRUCTURE_TYPE {
66a551c94aSIdo Barnea	E1000_INVM_UNINITIALIZED_STRUCTURE		= 0x00,
67a551c94aSIdo Barnea	E1000_INVM_WORD_AUTOLOAD_STRUCTURE		= 0x01,
68a551c94aSIdo Barnea	E1000_INVM_CSR_AUTOLOAD_STRUCTURE		= 0x02,
69a551c94aSIdo Barnea	E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE	= 0x03,
70a551c94aSIdo Barnea	E1000_INVM_RSA_KEY_SHA256_STRUCTURE		= 0x04,
71a551c94aSIdo Barnea	E1000_INVM_INVALIDATED_STRUCTURE		= 0x0F,
72a551c94aSIdo Barnea};
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS	8
75a551c94aSIdo Barnea#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS	1
76a551c94aSIdo Barnea#define E1000_INVM_ULT_BYTES_SIZE	8
77a551c94aSIdo Barnea#define E1000_INVM_RECORD_SIZE_IN_BYTES	4
78a551c94aSIdo Barnea#define E1000_INVM_VER_FIELD_ONE	0x1FF8
79a551c94aSIdo Barnea#define E1000_INVM_VER_FIELD_TWO	0x7FE000
80a551c94aSIdo Barnea#define E1000_INVM_IMGTYPE_FIELD	0x1F800000
81a551c94aSIdo Barnea
82a551c94aSIdo Barnea#define E1000_INVM_MAJOR_MASK	0x3F0
83a551c94aSIdo Barnea#define E1000_INVM_MINOR_MASK	0xF
84a551c94aSIdo Barnea#define E1000_INVM_MAJOR_SHIFT	4
85a551c94aSIdo Barnea
86a551c94aSIdo Barnea#define ID_LED_DEFAULT_I210		((ID_LED_OFF1_ON2  << 8) | \
87a551c94aSIdo Barnea					 (ID_LED_DEF1_DEF2 <<  4) | \
88a551c94aSIdo Barnea					 (ID_LED_OFF1_OFF2))
89a551c94aSIdo Barnea#define ID_LED_DEFAULT_I210_SERDES	((ID_LED_DEF1_DEF2 << 8) | \
90a551c94aSIdo Barnea					 (ID_LED_DEF1_DEF2 <<  4) | \
91a551c94aSIdo Barnea					 (ID_LED_OFF1_ON2))
92a551c94aSIdo Barnea
93a551c94aSIdo Barnea/* NVM offset defaults for I211 devices */
94a551c94aSIdo Barnea#define NVM_INIT_CTRL_2_DEFAULT_I211	0X7243
95a551c94aSIdo Barnea#define NVM_INIT_CTRL_4_DEFAULT_I211	0x00C1
96a551c94aSIdo Barnea#define NVM_LED_1_CFG_DEFAULT_I211	0x0184
97a551c94aSIdo Barnea#define NVM_LED_0_2_CFG_DEFAULT_I211	0x200C
98a551c94aSIdo Barnea
99a551c94aSIdo Barnea/* PLL Defines */
100a551c94aSIdo Barnea#define E1000_PCI_PMCSR			0x44
101a551c94aSIdo Barnea#define E1000_PCI_PMCSR_D3		0x03
102a551c94aSIdo Barnea#define E1000_MAX_PLL_TRIES		5
103a551c94aSIdo Barnea#define E1000_PHY_PLL_UNCONF		0xFF
104a551c94aSIdo Barnea#define E1000_PHY_PLL_FREQ_PAGE		0xFC0000
105a551c94aSIdo Barnea#define E1000_PHY_PLL_FREQ_REG		0x000E
106a551c94aSIdo Barnea#define E1000_INVM_DEFAULT_AL		0x202F
107a551c94aSIdo Barnea#define E1000_INVM_AUTOLOAD		0x0A
108a551c94aSIdo Barnea#define E1000_INVM_PLL_WO_VAL		0x0010
109a551c94aSIdo Barnea
110a551c94aSIdo Barnea#endif
111