1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea/* 82562G 10/100 Network Connection
35a551c94aSIdo Barnea * 82562G-2 10/100 Network Connection
36a551c94aSIdo Barnea * 82562GT 10/100 Network Connection
37a551c94aSIdo Barnea * 82562GT-2 10/100 Network Connection
38a551c94aSIdo Barnea * 82562V 10/100 Network Connection
39a551c94aSIdo Barnea * 82562V-2 10/100 Network Connection
40a551c94aSIdo Barnea * 82566DC-2 Gigabit Network Connection
41a551c94aSIdo Barnea * 82566DC Gigabit Network Connection
42a551c94aSIdo Barnea * 82566DM-2 Gigabit Network Connection
43a551c94aSIdo Barnea * 82566DM Gigabit Network Connection
44a551c94aSIdo Barnea * 82566MC Gigabit Network Connection
45a551c94aSIdo Barnea * 82566MM Gigabit Network Connection
46a551c94aSIdo Barnea * 82567LM Gigabit Network Connection
47a551c94aSIdo Barnea * 82567LF Gigabit Network Connection
48a551c94aSIdo Barnea * 82567V Gigabit Network Connection
49a551c94aSIdo Barnea * 82567LM-2 Gigabit Network Connection
50a551c94aSIdo Barnea * 82567LF-2 Gigabit Network Connection
51a551c94aSIdo Barnea * 82567V-2 Gigabit Network Connection
52a551c94aSIdo Barnea * 82567LF-3 Gigabit Network Connection
53a551c94aSIdo Barnea * 82567LM-3 Gigabit Network Connection
54a551c94aSIdo Barnea * 82567LM-4 Gigabit Network Connection
55a551c94aSIdo Barnea * 82577LM Gigabit Network Connection
56a551c94aSIdo Barnea * 82577LC Gigabit Network Connection
57a551c94aSIdo Barnea * 82578DM Gigabit Network Connection
58a551c94aSIdo Barnea * 82578DC Gigabit Network Connection
59a551c94aSIdo Barnea * 82579LM Gigabit Network Connection
60a551c94aSIdo Barnea * 82579V Gigabit Network Connection
61a551c94aSIdo Barnea * Ethernet Connection I217-LM
62a551c94aSIdo Barnea * Ethernet Connection I217-V
63a551c94aSIdo Barnea * Ethernet Connection I218-V
64a551c94aSIdo Barnea * Ethernet Connection I218-LM
65a551c94aSIdo Barnea * Ethernet Connection (2) I218-LM
66a551c94aSIdo Barnea * Ethernet Connection (2) I218-V
67a551c94aSIdo Barnea * Ethernet Connection (3) I218-LM
68a551c94aSIdo Barnea * Ethernet Connection (3) I218-V
69a551c94aSIdo Barnea */
70a551c94aSIdo Barnea
71a551c94aSIdo Barnea#include "e1000_api.h"
72a551c94aSIdo Barnea
73a551c94aSIdo BarneaSTATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74a551c94aSIdo BarneaSTATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75a551c94aSIdo BarneaSTATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76a551c94aSIdo BarneaSTATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77a551c94aSIdo BarneaSTATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78a551c94aSIdo BarneaSTATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79a551c94aSIdo BarneaSTATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80a551c94aSIdo BarneaSTATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81a551c94aSIdo BarneaSTATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82a551c94aSIdo BarneaSTATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83a551c94aSIdo Barnea#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84a551c94aSIdo BarneaSTATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
85a551c94aSIdo Barnea					      u8 *mc_addr_list,
86a551c94aSIdo Barnea					      u32 mc_addr_count);
87a551c94aSIdo Barnea#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88a551c94aSIdo BarneaSTATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89a551c94aSIdo BarneaSTATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90a551c94aSIdo BarneaSTATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91a551c94aSIdo BarneaSTATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
92a551c94aSIdo Barnea					    bool active);
93a551c94aSIdo BarneaSTATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
94a551c94aSIdo Barnea					    bool active);
95a551c94aSIdo BarneaSTATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96a551c94aSIdo Barnea				   u16 words, u16 *data);
979ca4a157SIdo BarneaSTATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
989ca4a157SIdo Barnea			       u16 *data);
99a551c94aSIdo BarneaSTATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
100a551c94aSIdo Barnea				    u16 words, u16 *data);
101a551c94aSIdo BarneaSTATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
102a551c94aSIdo BarneaSTATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
1039ca4a157SIdo BarneaSTATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
104a551c94aSIdo BarneaSTATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
105a551c94aSIdo Barnea					    u16 *data);
106a551c94aSIdo BarneaSTATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
107a551c94aSIdo BarneaSTATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
108a551c94aSIdo BarneaSTATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
109a551c94aSIdo BarneaSTATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
110a551c94aSIdo BarneaSTATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
111a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
112a551c94aSIdo BarneaSTATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
113a551c94aSIdo BarneaSTATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
114a551c94aSIdo Barnea					   u16 *speed, u16 *duplex);
115a551c94aSIdo BarneaSTATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
116a551c94aSIdo BarneaSTATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
117a551c94aSIdo BarneaSTATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
118a551c94aSIdo BarneaSTATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
119a551c94aSIdo BarneaSTATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
120a551c94aSIdo BarneaSTATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
121a551c94aSIdo BarneaSTATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
122a551c94aSIdo BarneaSTATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
123a551c94aSIdo BarneaSTATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
124a551c94aSIdo BarneaSTATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
125a551c94aSIdo BarneaSTATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
126a551c94aSIdo BarneaSTATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
127a551c94aSIdo BarneaSTATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
128a551c94aSIdo Barnea					  u32 offset, u8 *data);
129a551c94aSIdo BarneaSTATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
130a551c94aSIdo Barnea					  u8 size, u16 *data);
1319ca4a157SIdo BarneaSTATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
1329ca4a157SIdo Barnea					    u32 *data);
1339ca4a157SIdo BarneaSTATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
1349ca4a157SIdo Barnea					   u32 offset, u32 *data);
1359ca4a157SIdo BarneaSTATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
1369ca4a157SIdo Barnea					     u32 offset, u32 data);
1379ca4a157SIdo BarneaSTATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
1389ca4a157SIdo Barnea						  u32 offset, u32 dword);
139a551c94aSIdo BarneaSTATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
140a551c94aSIdo Barnea					  u32 offset, u16 *data);
141a551c94aSIdo BarneaSTATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
142a551c94aSIdo Barnea						 u32 offset, u8 byte);
143a551c94aSIdo BarneaSTATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
144a551c94aSIdo BarneaSTATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145a551c94aSIdo BarneaSTATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
146a551c94aSIdo BarneaSTATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
147a551c94aSIdo BarneaSTATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
148a551c94aSIdo BarneaSTATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
149a551c94aSIdo Barnea
150a551c94aSIdo Barnea/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151a551c94aSIdo Barnea/* Offset 04h HSFSTS */
152a551c94aSIdo Barneaunion ich8_hws_flash_status {
153a551c94aSIdo Barnea	struct ich8_hsfsts {
154a551c94aSIdo Barnea		u16 flcdone:1; /* bit 0 Flash Cycle Done */
155a551c94aSIdo Barnea		u16 flcerr:1; /* bit 1 Flash Cycle Error */
156a551c94aSIdo Barnea		u16 dael:1; /* bit 2 Direct Access error Log */
157a551c94aSIdo Barnea		u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158a551c94aSIdo Barnea		u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159a551c94aSIdo Barnea		u16 reserved1:2; /* bit 13:6 Reserved */
160a551c94aSIdo Barnea		u16 reserved2:6; /* bit 13:6 Reserved */
161a551c94aSIdo Barnea		u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162a551c94aSIdo Barnea		u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
163a551c94aSIdo Barnea	} hsf_status;
164a551c94aSIdo Barnea	u16 regval;
165a551c94aSIdo Barnea};
166a551c94aSIdo Barnea
167a551c94aSIdo Barnea/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168a551c94aSIdo Barnea/* Offset 06h FLCTL */
169a551c94aSIdo Barneaunion ich8_hws_flash_ctrl {
170a551c94aSIdo Barnea	struct ich8_hsflctl {
171a551c94aSIdo Barnea		u16 flcgo:1;   /* 0 Flash Cycle Go */
172a551c94aSIdo Barnea		u16 flcycle:2;   /* 2:1 Flash Cycle */
173a551c94aSIdo Barnea		u16 reserved:5;   /* 7:3 Reserved  */
174a551c94aSIdo Barnea		u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
175a551c94aSIdo Barnea		u16 flockdn:6;   /* 15:10 Reserved */
176a551c94aSIdo Barnea	} hsf_ctrl;
177a551c94aSIdo Barnea	u16 regval;
178a551c94aSIdo Barnea};
179a551c94aSIdo Barnea
180a551c94aSIdo Barnea/* ICH Flash Region Access Permissions */
181a551c94aSIdo Barneaunion ich8_hws_flash_regacc {
182a551c94aSIdo Barnea	struct ich8_flracc {
183a551c94aSIdo Barnea		u32 grra:8; /* 0:7 GbE region Read Access */
184a551c94aSIdo Barnea		u32 grwa:8; /* 8:15 GbE region Write Access */
185a551c94aSIdo Barnea		u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186a551c94aSIdo Barnea		u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
187a551c94aSIdo Barnea	} hsf_flregacc;
188a551c94aSIdo Barnea	u16 regval;
189a551c94aSIdo Barnea};
190a551c94aSIdo Barnea
191a551c94aSIdo Barnea/**
192a551c94aSIdo Barnea *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
193a551c94aSIdo Barnea *  @hw: pointer to the HW structure
194a551c94aSIdo Barnea *
195a551c94aSIdo Barnea *  Test access to the PHY registers by reading the PHY ID registers.  If
196a551c94aSIdo Barnea *  the PHY ID is already known (e.g. resume path) compare it with known ID,
197a551c94aSIdo Barnea *  otherwise assume the read PHY ID is correct if it is valid.
198a551c94aSIdo Barnea *
199a551c94aSIdo Barnea *  Assumes the sw/fw/hw semaphore is already acquired.
200a551c94aSIdo Barnea **/
201a551c94aSIdo BarneaSTATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
202a551c94aSIdo Barnea{
203a551c94aSIdo Barnea	u16 phy_reg = 0;
204a551c94aSIdo Barnea	u32 phy_id = 0;
205a551c94aSIdo Barnea	s32 ret_val = 0;
206a551c94aSIdo Barnea	u16 retry_count;
207a551c94aSIdo Barnea	u32 mac_reg = 0;
208a551c94aSIdo Barnea
209a551c94aSIdo Barnea	for (retry_count = 0; retry_count < 2; retry_count++) {
210a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211a551c94aSIdo Barnea		if (ret_val || (phy_reg == 0xFFFF))
212a551c94aSIdo Barnea			continue;
213a551c94aSIdo Barnea		phy_id = (u32)(phy_reg << 16);
214a551c94aSIdo Barnea
215a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216a551c94aSIdo Barnea		if (ret_val || (phy_reg == 0xFFFF)) {
217a551c94aSIdo Barnea			phy_id = 0;
218a551c94aSIdo Barnea			continue;
219a551c94aSIdo Barnea		}
220a551c94aSIdo Barnea		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
221a551c94aSIdo Barnea		break;
222a551c94aSIdo Barnea	}
223a551c94aSIdo Barnea
224a551c94aSIdo Barnea	if (hw->phy.id) {
225a551c94aSIdo Barnea		if  (hw->phy.id == phy_id)
226a551c94aSIdo Barnea			goto out;
227a551c94aSIdo Barnea	} else if (phy_id) {
228a551c94aSIdo Barnea		hw->phy.id = phy_id;
229a551c94aSIdo Barnea		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
230a551c94aSIdo Barnea		goto out;
231a551c94aSIdo Barnea	}
232a551c94aSIdo Barnea
233a551c94aSIdo Barnea	/* In case the PHY needs to be in mdio slow mode,
234a551c94aSIdo Barnea	 * set slow mode and try to get the PHY id again.
235a551c94aSIdo Barnea	 */
236a551c94aSIdo Barnea	if (hw->mac.type < e1000_pch_lpt) {
237a551c94aSIdo Barnea		hw->phy.ops.release(hw);
238a551c94aSIdo Barnea		ret_val = e1000_set_mdio_slow_mode_hv(hw);
239a551c94aSIdo Barnea		if (!ret_val)
240a551c94aSIdo Barnea			ret_val = e1000_get_phy_id(hw);
241a551c94aSIdo Barnea		hw->phy.ops.acquire(hw);
242a551c94aSIdo Barnea	}
243a551c94aSIdo Barnea
244a551c94aSIdo Barnea	if (ret_val)
245a551c94aSIdo Barnea		return false;
246a551c94aSIdo Barneaout:
2479ca4a157SIdo Barnea	if (hw->mac.type >= e1000_pch_lpt) {
248a551c94aSIdo Barnea		/* Only unforce SMBus if ME is not active */
249a551c94aSIdo Barnea		if (!(E1000_READ_REG(hw, E1000_FWSM) &
250a551c94aSIdo Barnea		    E1000_ICH_FWSM_FW_VALID)) {
251a551c94aSIdo Barnea			/* Unforce SMBus mode in PHY */
252a551c94aSIdo Barnea			hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253a551c94aSIdo Barnea			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254a551c94aSIdo Barnea			hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
255a551c94aSIdo Barnea
256a551c94aSIdo Barnea			/* Unforce SMBus mode in MAC */
257a551c94aSIdo Barnea			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258a551c94aSIdo Barnea			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
260a551c94aSIdo Barnea		}
261a551c94aSIdo Barnea	}
262a551c94aSIdo Barnea
263a551c94aSIdo Barnea	return true;
264a551c94aSIdo Barnea}
265a551c94aSIdo Barnea
266a551c94aSIdo Barnea/**
267a551c94aSIdo Barnea *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268a551c94aSIdo Barnea *  @hw: pointer to the HW structure
269a551c94aSIdo Barnea *
270a551c94aSIdo Barnea *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
271a551c94aSIdo Barnea *  used to reset the PHY to a quiescent state when necessary.
272a551c94aSIdo Barnea **/
273a551c94aSIdo BarneaSTATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
274a551c94aSIdo Barnea{
275a551c94aSIdo Barnea	u32 mac_reg;
276a551c94aSIdo Barnea
277a551c94aSIdo Barnea	DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
278a551c94aSIdo Barnea
279a551c94aSIdo Barnea	/* Set Phy Config Counter to 50msec */
280a551c94aSIdo Barnea	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281a551c94aSIdo Barnea	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282a551c94aSIdo Barnea	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
284a551c94aSIdo Barnea
285a551c94aSIdo Barnea	/* Toggle LANPHYPC Value bit */
286a551c94aSIdo Barnea	mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287a551c94aSIdo Barnea	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288a551c94aSIdo Barnea	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
2919ca4a157SIdo Barnea	msec_delay(1);
292a551c94aSIdo Barnea	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
295a551c94aSIdo Barnea
296a551c94aSIdo Barnea	if (hw->mac.type < e1000_pch_lpt) {
297a551c94aSIdo Barnea		msec_delay(50);
298a551c94aSIdo Barnea	} else {
299a551c94aSIdo Barnea		u16 count = 20;
300a551c94aSIdo Barnea
301a551c94aSIdo Barnea		do {
302a551c94aSIdo Barnea			msec_delay(5);
303a551c94aSIdo Barnea		} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304a551c94aSIdo Barnea			   E1000_CTRL_EXT_LPCD) && count--);
305a551c94aSIdo Barnea
306a551c94aSIdo Barnea		msec_delay(30);
307a551c94aSIdo Barnea	}
308a551c94aSIdo Barnea}
309a551c94aSIdo Barnea
310a551c94aSIdo Barnea/**
311a551c94aSIdo Barnea *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
312a551c94aSIdo Barnea *  @hw: pointer to the HW structure
313a551c94aSIdo Barnea *
314a551c94aSIdo Barnea *  Workarounds/flow necessary for PHY initialization during driver load
315a551c94aSIdo Barnea *  and resume paths.
316a551c94aSIdo Barnea **/
317a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
318a551c94aSIdo Barnea{
319a551c94aSIdo Barnea	u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
320a551c94aSIdo Barnea	s32 ret_val;
321a551c94aSIdo Barnea
322a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
323a551c94aSIdo Barnea
324a551c94aSIdo Barnea	/* Gate automatic PHY configuration by hardware on managed and
325a551c94aSIdo Barnea	 * non-managed 82579 and newer adapters.
326a551c94aSIdo Barnea	 */
327a551c94aSIdo Barnea	e1000_gate_hw_phy_config_ich8lan(hw, true);
328a551c94aSIdo Barnea
329a551c94aSIdo Barnea#ifdef ULP_SUPPORT
330a551c94aSIdo Barnea	/* It is not possible to be certain of the current state of ULP
331a551c94aSIdo Barnea	 * so forcibly disable it.
332a551c94aSIdo Barnea	 */
333a551c94aSIdo Barnea	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
334a551c94aSIdo Barnea
335a551c94aSIdo Barnea#endif /* ULP_SUPPORT */
336a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
337a551c94aSIdo Barnea	if (ret_val) {
338a551c94aSIdo Barnea		DEBUGOUT("Failed to initialize PHY flow\n");
339a551c94aSIdo Barnea		goto out;
340a551c94aSIdo Barnea	}
341a551c94aSIdo Barnea
342a551c94aSIdo Barnea	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
343a551c94aSIdo Barnea	 * inaccessible and resetting the PHY is not blocked, toggle the
344a551c94aSIdo Barnea	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
345a551c94aSIdo Barnea	 */
346a551c94aSIdo Barnea	switch (hw->mac.type) {
347a551c94aSIdo Barnea	case e1000_pch_lpt:
3489ca4a157SIdo Barnea	case e1000_pch_spt:
3499ca4a157SIdo Barnea	case e1000_pch_cnp:
350a551c94aSIdo Barnea		if (e1000_phy_is_accessible_pchlan(hw))
351a551c94aSIdo Barnea			break;
352a551c94aSIdo Barnea
353a551c94aSIdo Barnea		/* Before toggling LANPHYPC, see if PHY is accessible by
354a551c94aSIdo Barnea		 * forcing MAC to SMBus mode first.
355a551c94aSIdo Barnea		 */
356a551c94aSIdo Barnea		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
357a551c94aSIdo Barnea		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
358a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
359a551c94aSIdo Barnea
360a551c94aSIdo Barnea		/* Wait 50 milliseconds for MAC to finish any retries
361a551c94aSIdo Barnea		 * that it might be trying to perform from previous
362a551c94aSIdo Barnea		 * attempts to acknowledge any phy read requests.
363a551c94aSIdo Barnea		 */
364a551c94aSIdo Barnea		 msec_delay(50);
365a551c94aSIdo Barnea
366a551c94aSIdo Barnea		/* fall-through */
367a551c94aSIdo Barnea	case e1000_pch2lan:
368a551c94aSIdo Barnea		if (e1000_phy_is_accessible_pchlan(hw))
369a551c94aSIdo Barnea			break;
370a551c94aSIdo Barnea
371a551c94aSIdo Barnea		/* fall-through */
372a551c94aSIdo Barnea	case e1000_pchlan:
373a551c94aSIdo Barnea		if ((hw->mac.type == e1000_pchlan) &&
374a551c94aSIdo Barnea		    (fwsm & E1000_ICH_FWSM_FW_VALID))
375a551c94aSIdo Barnea			break;
376a551c94aSIdo Barnea
377a551c94aSIdo Barnea		if (hw->phy.ops.check_reset_block(hw)) {
378a551c94aSIdo Barnea			DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
379a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
380a551c94aSIdo Barnea			break;
381a551c94aSIdo Barnea		}
382a551c94aSIdo Barnea
383a551c94aSIdo Barnea		/* Toggle LANPHYPC Value bit */
384a551c94aSIdo Barnea		e1000_toggle_lanphypc_pch_lpt(hw);
385a551c94aSIdo Barnea		if (hw->mac.type >= e1000_pch_lpt) {
386a551c94aSIdo Barnea			if (e1000_phy_is_accessible_pchlan(hw))
387a551c94aSIdo Barnea				break;
388a551c94aSIdo Barnea
389a551c94aSIdo Barnea			/* Toggling LANPHYPC brings the PHY out of SMBus mode
390a551c94aSIdo Barnea			 * so ensure that the MAC is also out of SMBus mode
391a551c94aSIdo Barnea			 */
392a551c94aSIdo Barnea			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
393a551c94aSIdo Barnea			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
394a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
395a551c94aSIdo Barnea
396a551c94aSIdo Barnea			if (e1000_phy_is_accessible_pchlan(hw))
397a551c94aSIdo Barnea				break;
398a551c94aSIdo Barnea
399a551c94aSIdo Barnea			ret_val = -E1000_ERR_PHY;
400a551c94aSIdo Barnea		}
401a551c94aSIdo Barnea		break;
402a551c94aSIdo Barnea	default:
403a551c94aSIdo Barnea		break;
404a551c94aSIdo Barnea	}
405a551c94aSIdo Barnea
406a551c94aSIdo Barnea	hw->phy.ops.release(hw);
407a551c94aSIdo Barnea	if (!ret_val) {
408a551c94aSIdo Barnea
409a551c94aSIdo Barnea		/* Check to see if able to reset PHY.  Print error if not */
410a551c94aSIdo Barnea		if (hw->phy.ops.check_reset_block(hw)) {
411a551c94aSIdo Barnea			ERROR_REPORT("Reset blocked by ME\n");
412a551c94aSIdo Barnea			goto out;
413a551c94aSIdo Barnea		}
414a551c94aSIdo Barnea
415a551c94aSIdo Barnea		/* Reset the PHY before any access to it.  Doing so, ensures
416a551c94aSIdo Barnea		 * that the PHY is in a known good state before we read/write
417a551c94aSIdo Barnea		 * PHY registers.  The generic reset is sufficient here,
418a551c94aSIdo Barnea		 * because we haven't determined the PHY type yet.
419a551c94aSIdo Barnea		 */
420a551c94aSIdo Barnea		ret_val = e1000_phy_hw_reset_generic(hw);
421a551c94aSIdo Barnea		if (ret_val)
422a551c94aSIdo Barnea			goto out;
423a551c94aSIdo Barnea
424a551c94aSIdo Barnea		/* On a successful reset, possibly need to wait for the PHY
425a551c94aSIdo Barnea		 * to quiesce to an accessible state before returning control
426a551c94aSIdo Barnea		 * to the calling function.  If the PHY does not quiesce, then
427a551c94aSIdo Barnea		 * return E1000E_BLK_PHY_RESET, as this is the condition that
428a551c94aSIdo Barnea		 *  the PHY is in.
429a551c94aSIdo Barnea		 */
430a551c94aSIdo Barnea		ret_val = hw->phy.ops.check_reset_block(hw);
431a551c94aSIdo Barnea		if (ret_val)
432a551c94aSIdo Barnea			ERROR_REPORT("ME blocked access to PHY after reset\n");
433a551c94aSIdo Barnea	}
434a551c94aSIdo Barnea
435a551c94aSIdo Barneaout:
436a551c94aSIdo Barnea	/* Ungate automatic PHY configuration on non-managed 82579 */
437a551c94aSIdo Barnea	if ((hw->mac.type == e1000_pch2lan) &&
438a551c94aSIdo Barnea	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
439a551c94aSIdo Barnea		msec_delay(10);
440a551c94aSIdo Barnea		e1000_gate_hw_phy_config_ich8lan(hw, false);
441a551c94aSIdo Barnea	}
442a551c94aSIdo Barnea
443a551c94aSIdo Barnea	return ret_val;
444a551c94aSIdo Barnea}
445a551c94aSIdo Barnea
446a551c94aSIdo Barnea/**
447a551c94aSIdo Barnea *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
448a551c94aSIdo Barnea *  @hw: pointer to the HW structure
449a551c94aSIdo Barnea *
450a551c94aSIdo Barnea *  Initialize family-specific PHY parameters and function pointers.
451a551c94aSIdo Barnea **/
452a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
453a551c94aSIdo Barnea{
454a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
455a551c94aSIdo Barnea	s32 ret_val;
456a551c94aSIdo Barnea
457a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_pchlan");
458a551c94aSIdo Barnea
459a551c94aSIdo Barnea	phy->addr		= 1;
460a551c94aSIdo Barnea	phy->reset_delay_us	= 100;
461a551c94aSIdo Barnea
462a551c94aSIdo Barnea	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
463a551c94aSIdo Barnea	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
464a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
465a551c94aSIdo Barnea	phy->ops.set_page	= e1000_set_page_igp;
466a551c94aSIdo Barnea	phy->ops.read_reg	= e1000_read_phy_reg_hv;
467a551c94aSIdo Barnea	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
468a551c94aSIdo Barnea	phy->ops.read_reg_page	= e1000_read_phy_reg_page_hv;
469a551c94aSIdo Barnea	phy->ops.release	= e1000_release_swflag_ich8lan;
470a551c94aSIdo Barnea	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
471a551c94aSIdo Barnea	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
472a551c94aSIdo Barnea	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
473a551c94aSIdo Barnea	phy->ops.write_reg	= e1000_write_phy_reg_hv;
474a551c94aSIdo Barnea	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
475a551c94aSIdo Barnea	phy->ops.write_reg_page	= e1000_write_phy_reg_page_hv;
476a551c94aSIdo Barnea	phy->ops.power_up	= e1000_power_up_phy_copper;
477a551c94aSIdo Barnea	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
478a551c94aSIdo Barnea	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
479a551c94aSIdo Barnea
480a551c94aSIdo Barnea	phy->id = e1000_phy_unknown;
481a551c94aSIdo Barnea
482a551c94aSIdo Barnea	ret_val = e1000_init_phy_workarounds_pchlan(hw);
483a551c94aSIdo Barnea	if (ret_val)
484a551c94aSIdo Barnea		return ret_val;
485a551c94aSIdo Barnea
486a551c94aSIdo Barnea	if (phy->id == e1000_phy_unknown)
487a551c94aSIdo Barnea		switch (hw->mac.type) {
488a551c94aSIdo Barnea		default:
489a551c94aSIdo Barnea			ret_val = e1000_get_phy_id(hw);
490a551c94aSIdo Barnea			if (ret_val)
491a551c94aSIdo Barnea				return ret_val;
492a551c94aSIdo Barnea			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
493a551c94aSIdo Barnea				break;
494a551c94aSIdo Barnea			/* fall-through */
495a551c94aSIdo Barnea		case e1000_pch2lan:
496a551c94aSIdo Barnea		case e1000_pch_lpt:
4979ca4a157SIdo Barnea		case e1000_pch_spt:
4989ca4a157SIdo Barnea		case e1000_pch_cnp:
499a551c94aSIdo Barnea			/* In case the PHY needs to be in mdio slow mode,
500a551c94aSIdo Barnea			 * set slow mode and try to get the PHY id again.
501a551c94aSIdo Barnea			 */
502a551c94aSIdo Barnea			ret_val = e1000_set_mdio_slow_mode_hv(hw);
503a551c94aSIdo Barnea			if (ret_val)
504a551c94aSIdo Barnea				return ret_val;
505a551c94aSIdo Barnea			ret_val = e1000_get_phy_id(hw);
506a551c94aSIdo Barnea			if (ret_val)
507a551c94aSIdo Barnea				return ret_val;
508a551c94aSIdo Barnea			break;
509a551c94aSIdo Barnea		}
510a551c94aSIdo Barnea	phy->type = e1000_get_phy_type_from_id(phy->id);
511a551c94aSIdo Barnea
512a551c94aSIdo Barnea	switch (phy->type) {
513a551c94aSIdo Barnea	case e1000_phy_82577:
514a551c94aSIdo Barnea	case e1000_phy_82579:
515a551c94aSIdo Barnea	case e1000_phy_i217:
516a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_82577;
517a551c94aSIdo Barnea		phy->ops.force_speed_duplex =
518a551c94aSIdo Barnea			e1000_phy_force_speed_duplex_82577;
519a551c94aSIdo Barnea		phy->ops.get_cable_length = e1000_get_cable_length_82577;
520a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_82577;
521a551c94aSIdo Barnea		phy->ops.commit = e1000_phy_sw_reset_generic;
522a551c94aSIdo Barnea		break;
523a551c94aSIdo Barnea	case e1000_phy_82578:
524a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_m88;
525a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
526a551c94aSIdo Barnea		phy->ops.get_cable_length = e1000_get_cable_length_m88;
527a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_m88;
528a551c94aSIdo Barnea		break;
529a551c94aSIdo Barnea	default:
530a551c94aSIdo Barnea		ret_val = -E1000_ERR_PHY;
531a551c94aSIdo Barnea		break;
532a551c94aSIdo Barnea	}
533a551c94aSIdo Barnea
534a551c94aSIdo Barnea	return ret_val;
535a551c94aSIdo Barnea}
536a551c94aSIdo Barnea
537a551c94aSIdo Barnea/**
538a551c94aSIdo Barnea *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
539a551c94aSIdo Barnea *  @hw: pointer to the HW structure
540a551c94aSIdo Barnea *
541a551c94aSIdo Barnea *  Initialize family-specific PHY parameters and function pointers.
542a551c94aSIdo Barnea **/
543a551c94aSIdo BarneaSTATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
544a551c94aSIdo Barnea{
545a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
546a551c94aSIdo Barnea	s32 ret_val;
547a551c94aSIdo Barnea	u16 i = 0;
548a551c94aSIdo Barnea
549a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_params_ich8lan");
550a551c94aSIdo Barnea
551a551c94aSIdo Barnea	phy->addr		= 1;
552a551c94aSIdo Barnea	phy->reset_delay_us	= 100;
553a551c94aSIdo Barnea
554a551c94aSIdo Barnea	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
555a551c94aSIdo Barnea	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
556a551c94aSIdo Barnea	phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
557a551c94aSIdo Barnea	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
558a551c94aSIdo Barnea	phy->ops.read_reg	= e1000_read_phy_reg_igp;
559a551c94aSIdo Barnea	phy->ops.release	= e1000_release_swflag_ich8lan;
560a551c94aSIdo Barnea	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
561a551c94aSIdo Barnea	phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
562a551c94aSIdo Barnea	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
563a551c94aSIdo Barnea	phy->ops.write_reg	= e1000_write_phy_reg_igp;
564a551c94aSIdo Barnea	phy->ops.power_up	= e1000_power_up_phy_copper;
565a551c94aSIdo Barnea	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
566a551c94aSIdo Barnea
567a551c94aSIdo Barnea	/* We may need to do this twice - once for IGP and if that fails,
568a551c94aSIdo Barnea	 * we'll set BM func pointers and try again
569a551c94aSIdo Barnea	 */
570a551c94aSIdo Barnea	ret_val = e1000_determine_phy_address(hw);
571a551c94aSIdo Barnea	if (ret_val) {
572a551c94aSIdo Barnea		phy->ops.write_reg = e1000_write_phy_reg_bm;
573a551c94aSIdo Barnea		phy->ops.read_reg  = e1000_read_phy_reg_bm;
574a551c94aSIdo Barnea		ret_val = e1000_determine_phy_address(hw);
575a551c94aSIdo Barnea		if (ret_val) {
576a551c94aSIdo Barnea			DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
577a551c94aSIdo Barnea			return ret_val;
578a551c94aSIdo Barnea		}
579a551c94aSIdo Barnea	}
580a551c94aSIdo Barnea
581a551c94aSIdo Barnea	phy->id = 0;
582a551c94aSIdo Barnea	while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
583a551c94aSIdo Barnea	       (i++ < 100)) {
584a551c94aSIdo Barnea		msec_delay(1);
585a551c94aSIdo Barnea		ret_val = e1000_get_phy_id(hw);
586a551c94aSIdo Barnea		if (ret_val)
587a551c94aSIdo Barnea			return ret_val;
588a551c94aSIdo Barnea	}
589a551c94aSIdo Barnea
590a551c94aSIdo Barnea	/* Verify phy id */
591a551c94aSIdo Barnea	switch (phy->id) {
592a551c94aSIdo Barnea	case IGP03E1000_E_PHY_ID:
593a551c94aSIdo Barnea		phy->type = e1000_phy_igp_3;
594a551c94aSIdo Barnea		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
595a551c94aSIdo Barnea		phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
596a551c94aSIdo Barnea		phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
597a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_igp;
598a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_igp;
599a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
600a551c94aSIdo Barnea		break;
601a551c94aSIdo Barnea	case IFE_E_PHY_ID:
602a551c94aSIdo Barnea	case IFE_PLUS_E_PHY_ID:
603a551c94aSIdo Barnea	case IFE_C_E_PHY_ID:
604a551c94aSIdo Barnea		phy->type = e1000_phy_ife;
605a551c94aSIdo Barnea		phy->autoneg_mask = E1000_ALL_NOT_GIG;
606a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_ife;
607a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_ife;
608a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
609a551c94aSIdo Barnea		break;
610a551c94aSIdo Barnea	case BME1000_E_PHY_ID:
611a551c94aSIdo Barnea		phy->type = e1000_phy_bm;
612a551c94aSIdo Barnea		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
613a551c94aSIdo Barnea		phy->ops.read_reg = e1000_read_phy_reg_bm;
614a551c94aSIdo Barnea		phy->ops.write_reg = e1000_write_phy_reg_bm;
615a551c94aSIdo Barnea		phy->ops.commit = e1000_phy_sw_reset_generic;
616a551c94aSIdo Barnea		phy->ops.get_info = e1000_get_phy_info_m88;
617a551c94aSIdo Barnea		phy->ops.check_polarity = e1000_check_polarity_m88;
618a551c94aSIdo Barnea		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
619a551c94aSIdo Barnea		break;
620a551c94aSIdo Barnea	default:
621a551c94aSIdo Barnea		return -E1000_ERR_PHY;
622a551c94aSIdo Barnea		break;
623a551c94aSIdo Barnea	}
624a551c94aSIdo Barnea
625a551c94aSIdo Barnea	return E1000_SUCCESS;
626a551c94aSIdo Barnea}
627a551c94aSIdo Barnea
628a551c94aSIdo Barnea/**
629a551c94aSIdo Barnea *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
630a551c94aSIdo Barnea *  @hw: pointer to the HW structure
631a551c94aSIdo Barnea *
632a551c94aSIdo Barnea *  Initialize family-specific NVM parameters and function
633a551c94aSIdo Barnea *  pointers.
634a551c94aSIdo Barnea **/
635a551c94aSIdo BarneaSTATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
636a551c94aSIdo Barnea{
637a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
638a551c94aSIdo Barnea	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
639a551c94aSIdo Barnea	u32 gfpreg, sector_base_addr, sector_end_addr;
640a551c94aSIdo Barnea	u16 i;
6419ca4a157SIdo Barnea	u32 nvm_size;
642a551c94aSIdo Barnea
643a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_params_ich8lan");
644a551c94aSIdo Barnea
645a551c94aSIdo Barnea	nvm->type = e1000_nvm_flash_sw;
646a551c94aSIdo Barnea
6479ca4a157SIdo Barnea	if (hw->mac.type >= e1000_pch_spt) {
6489ca4a157SIdo Barnea		/* in SPT, gfpreg doesn't exist. NVM size is taken from the
6499ca4a157SIdo Barnea		 * STRAP register. This is because in SPT the GbE Flash region
6509ca4a157SIdo Barnea		 * is no longer accessed through the flash registers. Instead,
6519ca4a157SIdo Barnea		 * the mechanism has changed, and the Flash region access
6529ca4a157SIdo Barnea		 * registers are now implemented in GbE memory space.
6539ca4a157SIdo Barnea		 */
6549ca4a157SIdo Barnea		nvm->flash_base_addr = 0;
6559ca4a157SIdo Barnea		nvm_size =
6569ca4a157SIdo Barnea		    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
6579ca4a157SIdo Barnea		    * NVM_SIZE_MULTIPLIER;
6589ca4a157SIdo Barnea		nvm->flash_bank_size = nvm_size / 2;
6599ca4a157SIdo Barnea		/* Adjust to word count */
6609ca4a157SIdo Barnea		nvm->flash_bank_size /= sizeof(u16);
6619ca4a157SIdo Barnea		/* Set the base address for flash register access */
6629ca4a157SIdo Barnea		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
6639ca4a157SIdo Barnea	} else {
6649ca4a157SIdo Barnea		/* Can't read flash registers if register set isn't mapped. */
6659ca4a157SIdo Barnea		if (!hw->flash_address) {
6669ca4a157SIdo Barnea			DEBUGOUT("ERROR: Flash registers not mapped\n");
6679ca4a157SIdo Barnea			return -E1000_ERR_CONFIG;
6689ca4a157SIdo Barnea		}
669a551c94aSIdo Barnea
6709ca4a157SIdo Barnea		gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
671a551c94aSIdo Barnea
6729ca4a157SIdo Barnea		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
6739ca4a157SIdo Barnea		 * Add 1 to sector_end_addr since this sector is included in
6749ca4a157SIdo Barnea		 * the overall size.
6759ca4a157SIdo Barnea		 */
6769ca4a157SIdo Barnea		sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
6779ca4a157SIdo Barnea		sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
678a551c94aSIdo Barnea
6799ca4a157SIdo Barnea		/* flash_base_addr is byte-aligned */
6809ca4a157SIdo Barnea		nvm->flash_base_addr = sector_base_addr
6819ca4a157SIdo Barnea				       << FLASH_SECTOR_ADDR_SHIFT;
6829ca4a157SIdo Barnea
6839ca4a157SIdo Barnea		/* find total size of the NVM, then cut in half since the total
6849ca4a157SIdo Barnea		 * size represents two separate NVM banks.
6859ca4a157SIdo Barnea		 */
6869ca4a157SIdo Barnea		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
6879ca4a157SIdo Barnea					<< FLASH_SECTOR_ADDR_SHIFT);
6889ca4a157SIdo Barnea		nvm->flash_bank_size /= 2;
6899ca4a157SIdo Barnea		/* Adjust to word count */
6909ca4a157SIdo Barnea		nvm->flash_bank_size /= sizeof(u16);
6919ca4a157SIdo Barnea	}
692a551c94aSIdo Barnea
693a551c94aSIdo Barnea	nvm->word_size = E1000_SHADOW_RAM_WORDS;
694a551c94aSIdo Barnea
695a551c94aSIdo Barnea	/* Clear shadow ram */
696a551c94aSIdo Barnea	for (i = 0; i < nvm->word_size; i++) {
697a551c94aSIdo Barnea		dev_spec->shadow_ram[i].modified = false;
698a551c94aSIdo Barnea		dev_spec->shadow_ram[i].value    = 0xFFFF;
699a551c94aSIdo Barnea	}
700a551c94aSIdo Barnea
701a551c94aSIdo Barnea	E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
702a551c94aSIdo Barnea	E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
703a551c94aSIdo Barnea
704a551c94aSIdo Barnea	/* Function Pointers */
705a551c94aSIdo Barnea	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
706a551c94aSIdo Barnea	nvm->ops.release	= e1000_release_nvm_ich8lan;
7079ca4a157SIdo Barnea	if (hw->mac.type >= e1000_pch_spt) {
7089ca4a157SIdo Barnea		nvm->ops.read	= e1000_read_nvm_spt;
7099ca4a157SIdo Barnea		nvm->ops.update	= e1000_update_nvm_checksum_spt;
7109ca4a157SIdo Barnea	} else {
7119ca4a157SIdo Barnea		nvm->ops.read	= e1000_read_nvm_ich8lan;
7129ca4a157SIdo Barnea		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
7139ca4a157SIdo Barnea	}
714a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
715a551c94aSIdo Barnea	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
716a551c94aSIdo Barnea	nvm->ops.write		= e1000_write_nvm_ich8lan;
717a551c94aSIdo Barnea
718a551c94aSIdo Barnea	return E1000_SUCCESS;
719a551c94aSIdo Barnea}
720a551c94aSIdo Barnea
721a551c94aSIdo Barnea/**
722a551c94aSIdo Barnea *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
723a551c94aSIdo Barnea *  @hw: pointer to the HW structure
724a551c94aSIdo Barnea *
725a551c94aSIdo Barnea *  Initialize family-specific MAC parameters and function
726a551c94aSIdo Barnea *  pointers.
727a551c94aSIdo Barnea **/
728a551c94aSIdo BarneaSTATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
729a551c94aSIdo Barnea{
730a551c94aSIdo Barnea	struct e1000_mac_info *mac = &hw->mac;
731a551c94aSIdo Barnea#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
732a551c94aSIdo Barnea	u16 pci_cfg;
733a551c94aSIdo Barnea#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
734a551c94aSIdo Barnea
735a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_mac_params_ich8lan");
736a551c94aSIdo Barnea
737a551c94aSIdo Barnea	/* Set media type function pointer */
738a551c94aSIdo Barnea	hw->phy.media_type = e1000_media_type_copper;
739a551c94aSIdo Barnea
740a551c94aSIdo Barnea	/* Set mta register count */
741a551c94aSIdo Barnea	mac->mta_reg_count = 32;
742a551c94aSIdo Barnea	/* Set rar entry count */
743a551c94aSIdo Barnea	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
744a551c94aSIdo Barnea	if (mac->type == e1000_ich8lan)
745a551c94aSIdo Barnea		mac->rar_entry_count--;
746a551c94aSIdo Barnea	/* Set if part includes ASF firmware */
747a551c94aSIdo Barnea	mac->asf_firmware_present = true;
748a551c94aSIdo Barnea	/* FWSM register */
749a551c94aSIdo Barnea	mac->has_fwsm = true;
750a551c94aSIdo Barnea	/* ARC subsystem not supported */
751a551c94aSIdo Barnea	mac->arc_subsystem_valid = false;
752a551c94aSIdo Barnea	/* Adaptive IFS supported */
753a551c94aSIdo Barnea	mac->adaptive_ifs = true;
754a551c94aSIdo Barnea
755a551c94aSIdo Barnea	/* Function pointers */
756a551c94aSIdo Barnea
757a551c94aSIdo Barnea	/* bus type/speed/width */
758a551c94aSIdo Barnea	mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
759a551c94aSIdo Barnea	/* function id */
760a551c94aSIdo Barnea	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
761a551c94aSIdo Barnea	/* reset */
762a551c94aSIdo Barnea	mac->ops.reset_hw = e1000_reset_hw_ich8lan;
763a551c94aSIdo Barnea	/* hw initialization */
764a551c94aSIdo Barnea	mac->ops.init_hw = e1000_init_hw_ich8lan;
765a551c94aSIdo Barnea	/* link setup */
766a551c94aSIdo Barnea	mac->ops.setup_link = e1000_setup_link_ich8lan;
767a551c94aSIdo Barnea	/* physical interface setup */
768a551c94aSIdo Barnea	mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
769a551c94aSIdo Barnea	/* check for link */
770a551c94aSIdo Barnea	mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
771a551c94aSIdo Barnea	/* link info */
772a551c94aSIdo Barnea	mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
773a551c94aSIdo Barnea	/* multicast address update */
774a551c94aSIdo Barnea	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
775a551c94aSIdo Barnea	/* clear hardware counters */
776a551c94aSIdo Barnea	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
777a551c94aSIdo Barnea
778a551c94aSIdo Barnea	/* LED and other operations */
779a551c94aSIdo Barnea	switch (mac->type) {
780a551c94aSIdo Barnea	case e1000_ich8lan:
781a551c94aSIdo Barnea	case e1000_ich9lan:
782a551c94aSIdo Barnea	case e1000_ich10lan:
783a551c94aSIdo Barnea		/* check management mode */
784a551c94aSIdo Barnea		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
785a551c94aSIdo Barnea		/* ID LED init */
786a551c94aSIdo Barnea		mac->ops.id_led_init = e1000_id_led_init_generic;
787a551c94aSIdo Barnea		/* blink LED */
788a551c94aSIdo Barnea		mac->ops.blink_led = e1000_blink_led_generic;
789a551c94aSIdo Barnea		/* setup LED */
790a551c94aSIdo Barnea		mac->ops.setup_led = e1000_setup_led_generic;
791a551c94aSIdo Barnea		/* cleanup LED */
792a551c94aSIdo Barnea		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
793a551c94aSIdo Barnea		/* turn on/off LED */
794a551c94aSIdo Barnea		mac->ops.led_on = e1000_led_on_ich8lan;
795a551c94aSIdo Barnea		mac->ops.led_off = e1000_led_off_ich8lan;
796a551c94aSIdo Barnea		break;
797a551c94aSIdo Barnea	case e1000_pch2lan:
798a551c94aSIdo Barnea		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
799a551c94aSIdo Barnea		mac->ops.rar_set = e1000_rar_set_pch2lan;
800a551c94aSIdo Barnea		/* fall-through */
801a551c94aSIdo Barnea	case e1000_pch_lpt:
8029ca4a157SIdo Barnea	case e1000_pch_spt:
8039ca4a157SIdo Barnea	case e1000_pch_cnp:
804a551c94aSIdo Barnea#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
805a551c94aSIdo Barnea		/* multicast address update for pch2 */
806a551c94aSIdo Barnea		mac->ops.update_mc_addr_list =
807a551c94aSIdo Barnea			e1000_update_mc_addr_list_pch2lan;
808a551c94aSIdo Barnea		/* fall-through */
809a551c94aSIdo Barnea#endif
810a551c94aSIdo Barnea	case e1000_pchlan:
811a551c94aSIdo Barnea#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
812a551c94aSIdo Barnea		/* save PCH revision_id */
813a551c94aSIdo Barnea		e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
8149ca4a157SIdo Barnea		/* SPT uses full byte for revision ID,
8159ca4a157SIdo Barnea		 * as opposed to previous generations
8169ca4a157SIdo Barnea		 */
8179ca4a157SIdo Barnea		if (hw->mac.type >= e1000_pch_spt)
8189ca4a157SIdo Barnea			hw->revision_id = (u8)(pci_cfg &= 0x00FF);
8199ca4a157SIdo Barnea		else
8209ca4a157SIdo Barnea			hw->revision_id = (u8)(pci_cfg &= 0x000F);
821a551c94aSIdo Barnea#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
822a551c94aSIdo Barnea		/* check management mode */
823a551c94aSIdo Barnea		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
824a551c94aSIdo Barnea		/* ID LED init */
825a551c94aSIdo Barnea		mac->ops.id_led_init = e1000_id_led_init_pchlan;
826a551c94aSIdo Barnea		/* setup LED */
827a551c94aSIdo Barnea		mac->ops.setup_led = e1000_setup_led_pchlan;
828a551c94aSIdo Barnea		/* cleanup LED */
829a551c94aSIdo Barnea		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
830a551c94aSIdo Barnea		/* turn on/off LED */
831a551c94aSIdo Barnea		mac->ops.led_on = e1000_led_on_pchlan;
832a551c94aSIdo Barnea		mac->ops.led_off = e1000_led_off_pchlan;
833a551c94aSIdo Barnea		break;
834a551c94aSIdo Barnea	default:
835a551c94aSIdo Barnea		break;
836a551c94aSIdo Barnea	}
837a551c94aSIdo Barnea
8389ca4a157SIdo Barnea	if (mac->type >= e1000_pch_lpt) {
839a551c94aSIdo Barnea		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
840a551c94aSIdo Barnea		mac->ops.rar_set = e1000_rar_set_pch_lpt;
841a551c94aSIdo Barnea		mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
842a551c94aSIdo Barnea	}
843a551c94aSIdo Barnea
844a551c94aSIdo Barnea	/* Enable PCS Lock-loss workaround for ICH8 */
845a551c94aSIdo Barnea	if (mac->type == e1000_ich8lan)
846a551c94aSIdo Barnea		e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
847a551c94aSIdo Barnea
848a551c94aSIdo Barnea	return E1000_SUCCESS;
849a551c94aSIdo Barnea}
850a551c94aSIdo Barnea
851a551c94aSIdo Barnea/**
852a551c94aSIdo Barnea *  __e1000_access_emi_reg_locked - Read/write EMI register
853a551c94aSIdo Barnea *  @hw: pointer to the HW structure
854a551c94aSIdo Barnea *  @addr: EMI address to program
855a551c94aSIdo Barnea *  @data: pointer to value to read/write from/to the EMI address
856a551c94aSIdo Barnea *  @read: boolean flag to indicate read or write
857a551c94aSIdo Barnea *
858a551c94aSIdo Barnea *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
859a551c94aSIdo Barnea **/
860a551c94aSIdo BarneaSTATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
861a551c94aSIdo Barnea					 u16 *data, bool read)
862a551c94aSIdo Barnea{
863a551c94aSIdo Barnea	s32 ret_val;
864a551c94aSIdo Barnea
865a551c94aSIdo Barnea	DEBUGFUNC("__e1000_access_emi_reg_locked");
866a551c94aSIdo Barnea
867a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
868a551c94aSIdo Barnea	if (ret_val)
869a551c94aSIdo Barnea		return ret_val;
870a551c94aSIdo Barnea
871a551c94aSIdo Barnea	if (read)
872a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
873a551c94aSIdo Barnea						      data);
874a551c94aSIdo Barnea	else
875a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
876a551c94aSIdo Barnea						       *data);
877a551c94aSIdo Barnea
878a551c94aSIdo Barnea	return ret_val;
879a551c94aSIdo Barnea}
880a551c94aSIdo Barnea
881a551c94aSIdo Barnea/**
882a551c94aSIdo Barnea *  e1000_read_emi_reg_locked - Read Extended Management Interface register
883a551c94aSIdo Barnea *  @hw: pointer to the HW structure
884a551c94aSIdo Barnea *  @addr: EMI address to program
885a551c94aSIdo Barnea *  @data: value to be read from the EMI address
886a551c94aSIdo Barnea *
887a551c94aSIdo Barnea *  Assumes the SW/FW/HW Semaphore is already acquired.
888a551c94aSIdo Barnea **/
889a551c94aSIdo Barneas32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
890a551c94aSIdo Barnea{
891a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_emi_reg_locked");
892a551c94aSIdo Barnea
893a551c94aSIdo Barnea	return __e1000_access_emi_reg_locked(hw, addr, data, true);
894a551c94aSIdo Barnea}
895a551c94aSIdo Barnea
896a551c94aSIdo Barnea/**
897a551c94aSIdo Barnea *  e1000_write_emi_reg_locked - Write Extended Management Interface register
898a551c94aSIdo Barnea *  @hw: pointer to the HW structure
899a551c94aSIdo Barnea *  @addr: EMI address to program
900a551c94aSIdo Barnea *  @data: value to be written to the EMI address
901a551c94aSIdo Barnea *
902a551c94aSIdo Barnea *  Assumes the SW/FW/HW Semaphore is already acquired.
903a551c94aSIdo Barnea **/
904a551c94aSIdo Barneas32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
905a551c94aSIdo Barnea{
906a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_emi_reg_locked");
907a551c94aSIdo Barnea
908a551c94aSIdo Barnea	return __e1000_access_emi_reg_locked(hw, addr, &data, false);
909a551c94aSIdo Barnea}
910a551c94aSIdo Barnea
911a551c94aSIdo Barnea/**
912a551c94aSIdo Barnea *  e1000_set_eee_pchlan - Enable/disable EEE support
913a551c94aSIdo Barnea *  @hw: pointer to the HW structure
914a551c94aSIdo Barnea *
915a551c94aSIdo Barnea *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
916a551c94aSIdo Barnea *  the link and the EEE capabilities of the link partner.  The LPI Control
917a551c94aSIdo Barnea *  register bits will remain set only if/when link is up.
918a551c94aSIdo Barnea *
919a551c94aSIdo Barnea *  EEE LPI must not be asserted earlier than one second after link is up.
920a551c94aSIdo Barnea *  On 82579, EEE LPI should not be enabled until such time otherwise there
921a551c94aSIdo Barnea *  can be link issues with some switches.  Other devices can have EEE LPI
922a551c94aSIdo Barnea *  enabled immediately upon link up since they have a timer in hardware which
923a551c94aSIdo Barnea *  prevents LPI from being asserted too early.
924a551c94aSIdo Barnea **/
925a551c94aSIdo Barneas32 e1000_set_eee_pchlan(struct e1000_hw *hw)
926a551c94aSIdo Barnea{
927a551c94aSIdo Barnea	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
928a551c94aSIdo Barnea	s32 ret_val;
929a551c94aSIdo Barnea	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
930a551c94aSIdo Barnea
931a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_eee_pchlan");
932a551c94aSIdo Barnea
933a551c94aSIdo Barnea	switch (hw->phy.type) {
934a551c94aSIdo Barnea	case e1000_phy_82579:
935a551c94aSIdo Barnea		lpa = I82579_EEE_LP_ABILITY;
936a551c94aSIdo Barnea		pcs_status = I82579_EEE_PCS_STATUS;
937a551c94aSIdo Barnea		adv_addr = I82579_EEE_ADVERTISEMENT;
938a551c94aSIdo Barnea		break;
939a551c94aSIdo Barnea	case e1000_phy_i217:
940a551c94aSIdo Barnea		lpa = I217_EEE_LP_ABILITY;
941a551c94aSIdo Barnea		pcs_status = I217_EEE_PCS_STATUS;
942a551c94aSIdo Barnea		adv_addr = I217_EEE_ADVERTISEMENT;
943a551c94aSIdo Barnea		break;
944a551c94aSIdo Barnea	default:
945a551c94aSIdo Barnea		return E1000_SUCCESS;
946a551c94aSIdo Barnea	}
947a551c94aSIdo Barnea
948a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
949a551c94aSIdo Barnea	if (ret_val)
950a551c94aSIdo Barnea		return ret_val;
951a551c94aSIdo Barnea
952a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
953a551c94aSIdo Barnea	if (ret_val)
954a551c94aSIdo Barnea		goto release;
955a551c94aSIdo Barnea
956a551c94aSIdo Barnea	/* Clear bits that enable EEE in various speeds */
957a551c94aSIdo Barnea	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
958a551c94aSIdo Barnea
959a551c94aSIdo Barnea	/* Enable EEE if not disabled by user */
960a551c94aSIdo Barnea	if (!dev_spec->eee_disable) {
961a551c94aSIdo Barnea		/* Save off link partner's EEE ability */
962a551c94aSIdo Barnea		ret_val = e1000_read_emi_reg_locked(hw, lpa,
963a551c94aSIdo Barnea						    &dev_spec->eee_lp_ability);
964a551c94aSIdo Barnea		if (ret_val)
965a551c94aSIdo Barnea			goto release;
966a551c94aSIdo Barnea
967a551c94aSIdo Barnea		/* Read EEE advertisement */
968a551c94aSIdo Barnea		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
969a551c94aSIdo Barnea		if (ret_val)
970a551c94aSIdo Barnea			goto release;
971a551c94aSIdo Barnea
972a551c94aSIdo Barnea		/* Enable EEE only for speeds in which the link partner is
973a551c94aSIdo Barnea		 * EEE capable and for which we advertise EEE.
974a551c94aSIdo Barnea		 */
975a551c94aSIdo Barnea		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
976a551c94aSIdo Barnea			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
977a551c94aSIdo Barnea
978a551c94aSIdo Barnea		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
979a551c94aSIdo Barnea			hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
980a551c94aSIdo Barnea			if (data & NWAY_LPAR_100TX_FD_CAPS)
981a551c94aSIdo Barnea				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
982a551c94aSIdo Barnea			else
983a551c94aSIdo Barnea				/* EEE is not supported in 100Half, so ignore
984a551c94aSIdo Barnea				 * partner's EEE in 100 ability if full-duplex
985a551c94aSIdo Barnea				 * is not advertised.
986a551c94aSIdo Barnea				 */
987a551c94aSIdo Barnea				dev_spec->eee_lp_ability &=
988a551c94aSIdo Barnea				    ~I82579_EEE_100_SUPPORTED;
989a551c94aSIdo Barnea		}
990a551c94aSIdo Barnea	}
991a551c94aSIdo Barnea
992a551c94aSIdo Barnea	if (hw->phy.type == e1000_phy_82579) {
993a551c94aSIdo Barnea		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
994a551c94aSIdo Barnea						    &data);
995a551c94aSIdo Barnea		if (ret_val)
996a551c94aSIdo Barnea			goto release;
997a551c94aSIdo Barnea
998a551c94aSIdo Barnea		data &= ~I82579_LPI_100_PLL_SHUT;
999a551c94aSIdo Barnea		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
1000a551c94aSIdo Barnea						     data);
1001a551c94aSIdo Barnea	}
1002a551c94aSIdo Barnea
1003a551c94aSIdo Barnea	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
1004a551c94aSIdo Barnea	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
1005a551c94aSIdo Barnea	if (ret_val)
1006a551c94aSIdo Barnea		goto release;
1007a551c94aSIdo Barnea
1008a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
1009a551c94aSIdo Barnearelease:
1010a551c94aSIdo Barnea	hw->phy.ops.release(hw);
1011a551c94aSIdo Barnea
1012a551c94aSIdo Barnea	return ret_val;
1013a551c94aSIdo Barnea}
1014a551c94aSIdo Barnea
1015a551c94aSIdo Barnea/**
1016a551c94aSIdo Barnea *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
1017a551c94aSIdo Barnea *  @hw:   pointer to the HW structure
1018a551c94aSIdo Barnea *  @link: link up bool flag
1019a551c94aSIdo Barnea *
1020a551c94aSIdo Barnea *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1021a551c94aSIdo Barnea *  preventing further DMA write requests.  Workaround the issue by disabling
1022a551c94aSIdo Barnea *  the de-assertion of the clock request when in 1Gpbs mode.
1023a551c94aSIdo Barnea *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1024a551c94aSIdo Barnea *  speeds in order to avoid Tx hangs.
1025a551c94aSIdo Barnea **/
1026a551c94aSIdo BarneaSTATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1027a551c94aSIdo Barnea{
1028a551c94aSIdo Barnea	u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1029a551c94aSIdo Barnea	u32 status = E1000_READ_REG(hw, E1000_STATUS);
1030a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1031a551c94aSIdo Barnea	u16 reg;
1032a551c94aSIdo Barnea
1033a551c94aSIdo Barnea	if (link && (status & E1000_STATUS_SPEED_1000)) {
1034a551c94aSIdo Barnea		ret_val = hw->phy.ops.acquire(hw);
1035a551c94aSIdo Barnea		if (ret_val)
1036a551c94aSIdo Barnea			return ret_val;
1037a551c94aSIdo Barnea
1038a551c94aSIdo Barnea		ret_val =
1039a551c94aSIdo Barnea		    e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1040a551c94aSIdo Barnea					       &reg);
1041a551c94aSIdo Barnea		if (ret_val)
1042a551c94aSIdo Barnea			goto release;
1043a551c94aSIdo Barnea
1044a551c94aSIdo Barnea		ret_val =
1045a551c94aSIdo Barnea		    e1000_write_kmrn_reg_locked(hw,
1046a551c94aSIdo Barnea						E1000_KMRNCTRLSTA_K1_CONFIG,
1047a551c94aSIdo Barnea						reg &
1048a551c94aSIdo Barnea						~E1000_KMRNCTRLSTA_K1_ENABLE);
1049a551c94aSIdo Barnea		if (ret_val)
1050a551c94aSIdo Barnea			goto release;
1051a551c94aSIdo Barnea
1052a551c94aSIdo Barnea		usec_delay(10);
1053a551c94aSIdo Barnea
1054a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1055a551c94aSIdo Barnea				fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1056a551c94aSIdo Barnea
1057a551c94aSIdo Barnea		ret_val =
1058a551c94aSIdo Barnea		    e1000_write_kmrn_reg_locked(hw,
1059a551c94aSIdo Barnea						E1000_KMRNCTRLSTA_K1_CONFIG,
1060a551c94aSIdo Barnea						reg);
1061a551c94aSIdo Barnearelease:
1062a551c94aSIdo Barnea		hw->phy.ops.release(hw);
1063a551c94aSIdo Barnea	} else {
1064a551c94aSIdo Barnea		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
1065a551c94aSIdo Barnea		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1066a551c94aSIdo Barnea
10679ca4a157SIdo Barnea		if ((hw->phy.revision > 5) || !link ||
10689ca4a157SIdo Barnea		    ((status & E1000_STATUS_SPEED_100) &&
10699ca4a157SIdo Barnea		     (status & E1000_STATUS_FD)))
1070a551c94aSIdo Barnea			goto update_fextnvm6;
1071a551c94aSIdo Barnea
1072a551c94aSIdo Barnea		ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1073a551c94aSIdo Barnea		if (ret_val)
1074a551c94aSIdo Barnea			return ret_val;
1075a551c94aSIdo Barnea
1076a551c94aSIdo Barnea		/* Clear link status transmit timeout */
1077a551c94aSIdo Barnea		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1078a551c94aSIdo Barnea
1079a551c94aSIdo Barnea		if (status & E1000_STATUS_SPEED_100) {
1080a551c94aSIdo Barnea			/* Set inband Tx timeout to 5x10us for 100Half */
1081a551c94aSIdo Barnea			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1082a551c94aSIdo Barnea
1083a551c94aSIdo Barnea			/* Do not extend the K1 entry latency for 100Half */
1084a551c94aSIdo Barnea			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1085a551c94aSIdo Barnea		} else {
1086a551c94aSIdo Barnea			/* Set inband Tx timeout to 50x10us for 10Full/Half */
1087a551c94aSIdo Barnea			reg |= 50 <<
1088a551c94aSIdo Barnea			       I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1089a551c94aSIdo Barnea
1090a551c94aSIdo Barnea			/* Extend the K1 entry latency for 10 Mbps */
1091a551c94aSIdo Barnea			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1092a551c94aSIdo Barnea		}
1093a551c94aSIdo Barnea
1094a551c94aSIdo Barnea		ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1095a551c94aSIdo Barnea		if (ret_val)
1096a551c94aSIdo Barnea			return ret_val;
1097a551c94aSIdo Barnea
1098a551c94aSIdo Barneaupdate_fextnvm6:
1099a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1100a551c94aSIdo Barnea	}
1101a551c94aSIdo Barnea
1102a551c94aSIdo Barnea	return ret_val;
1103a551c94aSIdo Barnea}
1104a551c94aSIdo Barnea
1105a551c94aSIdo Barnea#ifdef ULP_SUPPORT
1106a551c94aSIdo Barnea/**
1107a551c94aSIdo Barnea *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1108a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1109a551c94aSIdo Barnea *  @to_sx: boolean indicating a system power state transition to Sx
1110a551c94aSIdo Barnea *
1111a551c94aSIdo Barnea *  When link is down, configure ULP mode to significantly reduce the power
1112a551c94aSIdo Barnea *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1113a551c94aSIdo Barnea *  ME firmware to start the ULP configuration.  If not on an ME enabled
1114a551c94aSIdo Barnea *  system, configure the ULP mode by software.
1115a551c94aSIdo Barnea */
1116a551c94aSIdo Barneas32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1117a551c94aSIdo Barnea{
1118a551c94aSIdo Barnea	u32 mac_reg;
1119a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1120a551c94aSIdo Barnea	u16 phy_reg;
11219ca4a157SIdo Barnea	u16 oem_reg = 0;
1122a551c94aSIdo Barnea
1123a551c94aSIdo Barnea	if ((hw->mac.type < e1000_pch_lpt) ||
1124a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1125a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1126a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1127a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1128a551c94aSIdo Barnea	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1129a551c94aSIdo Barnea		return 0;
1130a551c94aSIdo Barnea
1131a551c94aSIdo Barnea	if (!to_sx) {
1132a551c94aSIdo Barnea		int i = 0;
1133a551c94aSIdo Barnea		/* Poll up to 5 seconds for Cable Disconnected indication */
1134a551c94aSIdo Barnea		while (!(E1000_READ_REG(hw, E1000_FEXT) &
1135a551c94aSIdo Barnea			 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1136a551c94aSIdo Barnea			/* Bail if link is re-acquired */
1137a551c94aSIdo Barnea			if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1138a551c94aSIdo Barnea				return -E1000_ERR_PHY;
1139a551c94aSIdo Barnea			if (i++ == 100)
1140a551c94aSIdo Barnea				break;
1141a551c94aSIdo Barnea
1142a551c94aSIdo Barnea			msec_delay(50);
1143a551c94aSIdo Barnea		}
1144a551c94aSIdo Barnea		DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1145a551c94aSIdo Barnea			  (E1000_READ_REG(hw, E1000_FEXT) &
1146a551c94aSIdo Barnea			   E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1147a551c94aSIdo Barnea			  i * 50);
1148a551c94aSIdo Barnea		if (!(E1000_READ_REG(hw, E1000_FEXT) &
1149a551c94aSIdo Barnea		    E1000_FEXT_PHY_CABLE_DISCONNECTED))
1150a551c94aSIdo Barnea			return 0;
1151a551c94aSIdo Barnea	}
1152a551c94aSIdo Barnea
1153a551c94aSIdo Barnea	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1154a551c94aSIdo Barnea		/* Request ME configure ULP mode in the PHY */
1155a551c94aSIdo Barnea		mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1156a551c94aSIdo Barnea		mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1157a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1158a551c94aSIdo Barnea
1159a551c94aSIdo Barnea		goto out;
1160a551c94aSIdo Barnea	}
1161a551c94aSIdo Barnea
1162a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
1163a551c94aSIdo Barnea	if (ret_val)
1164a551c94aSIdo Barnea		goto out;
1165a551c94aSIdo Barnea
1166a551c94aSIdo Barnea	/* During S0 Idle keep the phy in PCI-E mode */
1167a551c94aSIdo Barnea	if (hw->dev_spec.ich8lan.smbus_disable)
1168a551c94aSIdo Barnea		goto skip_smbus;
1169a551c94aSIdo Barnea
1170a551c94aSIdo Barnea	/* Force SMBus mode in PHY */
1171a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1172a551c94aSIdo Barnea	if (ret_val)
1173a551c94aSIdo Barnea		goto release;
1174a551c94aSIdo Barnea	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1175a551c94aSIdo Barnea	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1176a551c94aSIdo Barnea
1177a551c94aSIdo Barnea	/* Force SMBus mode in MAC */
1178a551c94aSIdo Barnea	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1179a551c94aSIdo Barnea	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1180a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1181a551c94aSIdo Barnea
11829ca4a157SIdo Barnea	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
11839ca4a157SIdo Barnea	 * LPLU and disable Gig speed when entering ULP
11849ca4a157SIdo Barnea	 */
11859ca4a157SIdo Barnea	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
11869ca4a157SIdo Barnea		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
11879ca4a157SIdo Barnea						       &oem_reg);
11889ca4a157SIdo Barnea		if (ret_val)
11899ca4a157SIdo Barnea			goto release;
11909ca4a157SIdo Barnea
11919ca4a157SIdo Barnea		phy_reg = oem_reg;
11929ca4a157SIdo Barnea		phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
11939ca4a157SIdo Barnea
11949ca4a157SIdo Barnea		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
11959ca4a157SIdo Barnea							phy_reg);
11969ca4a157SIdo Barnea
11979ca4a157SIdo Barnea		if (ret_val)
11989ca4a157SIdo Barnea			goto release;
11999ca4a157SIdo Barnea	}
12009ca4a157SIdo Barnea
1201a551c94aSIdo Barneaskip_smbus:
1202a551c94aSIdo Barnea	if (!to_sx) {
1203a551c94aSIdo Barnea		/* Change the 'Link Status Change' interrupt to trigger
1204a551c94aSIdo Barnea		 * on 'Cable Status Change'
1205a551c94aSIdo Barnea		 */
1206a551c94aSIdo Barnea		ret_val = e1000_read_kmrn_reg_locked(hw,
1207a551c94aSIdo Barnea						     E1000_KMRNCTRLSTA_OP_MODES,
1208a551c94aSIdo Barnea						     &phy_reg);
1209a551c94aSIdo Barnea		if (ret_val)
1210a551c94aSIdo Barnea			goto release;
1211a551c94aSIdo Barnea		phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1212a551c94aSIdo Barnea		e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1213a551c94aSIdo Barnea					    phy_reg);
1214a551c94aSIdo Barnea	}
1215a551c94aSIdo Barnea
1216a551c94aSIdo Barnea	/* Set Inband ULP Exit, Reset to SMBus mode and
1217a551c94aSIdo Barnea	 * Disable SMBus Release on PERST# in PHY
1218a551c94aSIdo Barnea	 */
1219a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1220a551c94aSIdo Barnea	if (ret_val)
1221a551c94aSIdo Barnea		goto release;
1222a551c94aSIdo Barnea	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1223a551c94aSIdo Barnea		    I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1224a551c94aSIdo Barnea	if (to_sx) {
1225a551c94aSIdo Barnea		if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1226a551c94aSIdo Barnea			phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1227a551c94aSIdo Barnea		else
1228a551c94aSIdo Barnea			phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1229a551c94aSIdo Barnea
1230a551c94aSIdo Barnea		phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1231a551c94aSIdo Barnea		phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1232a551c94aSIdo Barnea	} else {
1233a551c94aSIdo Barnea		phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1234a551c94aSIdo Barnea		phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1235a551c94aSIdo Barnea		phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1236a551c94aSIdo Barnea	}
1237a551c94aSIdo Barnea	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1238a551c94aSIdo Barnea
1239a551c94aSIdo Barnea	/* Set Disable SMBus Release on PERST# in MAC */
1240a551c94aSIdo Barnea	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1241a551c94aSIdo Barnea	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1242a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1243a551c94aSIdo Barnea
1244a551c94aSIdo Barnea	/* Commit ULP changes in PHY by starting auto ULP configuration */
1245a551c94aSIdo Barnea	phy_reg |= I218_ULP_CONFIG1_START;
1246a551c94aSIdo Barnea	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1247a551c94aSIdo Barnea
1248a551c94aSIdo Barnea	if (!to_sx) {
1249a551c94aSIdo Barnea		/* Disable Tx so that the MAC doesn't send any (buffered)
1250a551c94aSIdo Barnea		 * packets to the PHY.
1251a551c94aSIdo Barnea		 */
1252a551c94aSIdo Barnea		mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1253a551c94aSIdo Barnea		mac_reg &= ~E1000_TCTL_EN;
1254a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1255a551c94aSIdo Barnea	}
1256a551c94aSIdo Barnea
12579ca4a157SIdo Barnea	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
12589ca4a157SIdo Barnea	    to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
12599ca4a157SIdo Barnea		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
12609ca4a157SIdo Barnea							oem_reg);
12619ca4a157SIdo Barnea		if (ret_val)
12629ca4a157SIdo Barnea			goto release;
12639ca4a157SIdo Barnea	}
12649ca4a157SIdo Barnea
1265a551c94aSIdo Barnearelease:
1266a551c94aSIdo Barnea	hw->phy.ops.release(hw);
1267a551c94aSIdo Barneaout:
1268a551c94aSIdo Barnea	if (ret_val)
1269a551c94aSIdo Barnea		DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1270a551c94aSIdo Barnea	else
1271a551c94aSIdo Barnea		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1272a551c94aSIdo Barnea
1273a551c94aSIdo Barnea	return ret_val;
1274a551c94aSIdo Barnea}
1275a551c94aSIdo Barnea
1276a551c94aSIdo Barnea/**
1277a551c94aSIdo Barnea *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1278a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1279a551c94aSIdo Barnea *  @force: boolean indicating whether or not to force disabling ULP
1280a551c94aSIdo Barnea *
1281a551c94aSIdo Barnea *  Un-configure ULP mode when link is up, the system is transitioned from
1282a551c94aSIdo Barnea *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1283a551c94aSIdo Barnea *  system, poll for an indication from ME that ULP has been un-configured.
1284a551c94aSIdo Barnea *  If not on an ME enabled system, un-configure the ULP mode by software.
1285a551c94aSIdo Barnea *
1286a551c94aSIdo Barnea *  During nominal operation, this function is called when link is acquired
1287a551c94aSIdo Barnea *  to disable ULP mode (force=false); otherwise, for example when unloading
1288a551c94aSIdo Barnea *  the driver or during Sx->S0 transitions, this is called with force=true
1289a551c94aSIdo Barnea *  to forcibly disable ULP.
1290a551c94aSIdo Barnea
1291a551c94aSIdo Barnea *  When the cable is plugged in while the device is in D0, a Cable Status
1292a551c94aSIdo Barnea *  Change interrupt is generated which causes this function to be called
1293a551c94aSIdo Barnea *  to partially disable ULP mode and restart autonegotiation.  This function
1294a551c94aSIdo Barnea *  is then called again due to the resulting Link Status Change interrupt
1295a551c94aSIdo Barnea *  to finish cleaning up after the ULP flow.
1296a551c94aSIdo Barnea */
1297a551c94aSIdo Barneas32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1298a551c94aSIdo Barnea{
1299a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
1300a551c94aSIdo Barnea	u32 mac_reg;
1301a551c94aSIdo Barnea	u16 phy_reg;
1302a551c94aSIdo Barnea	int i = 0;
1303a551c94aSIdo Barnea
1304a551c94aSIdo Barnea	if ((hw->mac.type < e1000_pch_lpt) ||
1305a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1306a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1307a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1308a551c94aSIdo Barnea	    (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1309a551c94aSIdo Barnea	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1310a551c94aSIdo Barnea		return 0;
1311a551c94aSIdo Barnea
1312a551c94aSIdo Barnea	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1313a551c94aSIdo Barnea		if (force) {
1314a551c94aSIdo Barnea			/* Request ME un-configure ULP mode in the PHY */
1315a551c94aSIdo Barnea			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1316a551c94aSIdo Barnea			mac_reg &= ~E1000_H2ME_ULP;
1317a551c94aSIdo Barnea			mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1318a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1319a551c94aSIdo Barnea		}
1320a551c94aSIdo Barnea
13219ca4a157SIdo Barnea		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1322a551c94aSIdo Barnea		while (E1000_READ_REG(hw, E1000_FWSM) &
1323a551c94aSIdo Barnea		       E1000_FWSM_ULP_CFG_DONE) {
13249ca4a157SIdo Barnea			if (i++ == 30) {
1325a551c94aSIdo Barnea				ret_val = -E1000_ERR_PHY;
1326a551c94aSIdo Barnea				goto out;
1327a551c94aSIdo Barnea			}
1328a551c94aSIdo Barnea
1329a551c94aSIdo Barnea			msec_delay(10);
1330a551c94aSIdo Barnea		}
1331a551c94aSIdo Barnea		DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1332a551c94aSIdo Barnea
1333a551c94aSIdo Barnea		if (force) {
1334a551c94aSIdo Barnea			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1335a551c94aSIdo Barnea			mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1336a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1337a551c94aSIdo Barnea		} else {
1338a551c94aSIdo Barnea			/* Clear H2ME.ULP after ME ULP configuration */
1339a551c94aSIdo Barnea			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1340a551c94aSIdo Barnea			mac_reg &= ~E1000_H2ME_ULP;
1341a551c94aSIdo Barnea			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1342a551c94aSIdo Barnea
1343a551c94aSIdo Barnea			/* Restore link speed advertisements and restart
1344a551c94aSIdo Barnea			 * Auto-negotiation
1345a551c94aSIdo Barnea			 */
1346a551c94aSIdo Barnea			if (hw->mac.autoneg) {
1347a551c94aSIdo Barnea				ret_val = e1000_phy_setup_autoneg(hw);
1348a551c94aSIdo Barnea				if (ret_val)
1349a551c94aSIdo Barnea					goto out;
1350a551c94aSIdo Barnea			} else {
1351a551c94aSIdo Barnea				ret_val = e1000_setup_copper_link_generic(hw);
1352a551c94aSIdo Barnea				if (ret_val)
1353a551c94aSIdo Barnea					goto out;
1354a551c94aSIdo Barnea			}
1355a551c94aSIdo Barnea			ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1356a551c94aSIdo Barnea		}
1357a551c94aSIdo Barnea
1358a551c94aSIdo Barnea		goto out;
1359a551c94aSIdo Barnea	}
1360a551c94aSIdo Barnea
1361a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
1362a551c94aSIdo Barnea	if (ret_val)
1363a551c94aSIdo Barnea		goto out;
1364a551c94aSIdo Barnea
1365a551c94aSIdo Barnea	/* Revert the change to the 'Link Status Change'
1366a551c94aSIdo Barnea	 * interrupt to trigger on 'Cable Status Change'
1367a551c94aSIdo Barnea	 */
1368a551c94aSIdo Barnea	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1369a551c94aSIdo Barnea					     &phy_reg);
1370a551c94aSIdo Barnea	if (ret_val)
1371a551c94aSIdo Barnea		goto release;
1372a551c94aSIdo Barnea	phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1373a551c94aSIdo Barnea	e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1374a551c94aSIdo Barnea
1375a551c94aSIdo Barnea	if (force)
1376a551c94aSIdo Barnea		/* Toggle LANPHYPC Value bit */
1377a551c94aSIdo Barnea		e1000_toggle_lanphypc_pch_lpt(hw);
1378a551c94aSIdo Barnea
1379a551c94aSIdo Barnea	/* Unforce SMBus mode in PHY */
1380a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1381a551c94aSIdo Barnea	if (ret_val) {
1382a551c94aSIdo Barnea		/* The MAC might be in PCIe mode, so temporarily force to
1383a551c94aSIdo Barnea		 * SMBus mode in order to access the PHY.
1384a551c94aSIdo Barnea		 */
1385a551c94aSIdo Barnea		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1386a551c94aSIdo Barnea		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1387a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1388a551c94aSIdo Barnea
1389a551c94aSIdo Barnea		msec_delay(50);
1390a551c94aSIdo Barnea
1391a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1392a551c94aSIdo Barnea						       &phy_reg);
1393a551c94aSIdo Barnea		if (ret_val)
1394a551c94aSIdo Barnea			goto release;
1395a551c94aSIdo Barnea	}
1396a551c94aSIdo Barnea	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1397a551c94aSIdo Barnea	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1398a551c94aSIdo Barnea
1399a551c94aSIdo Barnea	/* Unforce SMBus mode in MAC */
1400a551c94aSIdo Barnea	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1401a551c94aSIdo Barnea	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1402a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1403a551c94aSIdo Barnea
1404a551c94aSIdo Barnea	/* When ULP mode was previously entered, K1 was disabled by the
1405a551c94aSIdo Barnea	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1406a551c94aSIdo Barnea	 */
1407a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1408a551c94aSIdo Barnea	if (ret_val)
1409a551c94aSIdo Barnea		goto release;
1410a551c94aSIdo Barnea	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1411a551c94aSIdo Barnea	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1412a551c94aSIdo Barnea
1413a551c94aSIdo Barnea	/* Clear ULP enabled configuration */
1414a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1415a551c94aSIdo Barnea	if (ret_val)
1416a551c94aSIdo Barnea		goto release;
1417a551c94aSIdo Barnea	/* CSC interrupt received due to ULP Indication */
1418a551c94aSIdo Barnea	if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1419a551c94aSIdo Barnea		phy_reg &= ~(I218_ULP_CONFIG1_IND |
1420a551c94aSIdo Barnea			     I218_ULP_CONFIG1_STICKY_ULP |
1421a551c94aSIdo Barnea			     I218_ULP_CONFIG1_RESET_TO_SMBUS |
1422a551c94aSIdo Barnea			     I218_ULP_CONFIG1_WOL_HOST |
1423a551c94aSIdo Barnea			     I218_ULP_CONFIG1_INBAND_EXIT |
14249ca4a157SIdo Barnea			     I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
14259ca4a157SIdo Barnea			     I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1426a551c94aSIdo Barnea			     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1427a551c94aSIdo Barnea		e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1428a551c94aSIdo Barnea
1429a551c94aSIdo Barnea		/* Commit ULP changes by starting auto ULP configuration */
1430