1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_ICH8LAN_H_
35a551c94aSIdo Barnea#define _E1000_ICH8LAN_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barnea#define ICH_FLASH_GFPREG		0x0000
38a551c94aSIdo Barnea#define ICH_FLASH_HSFSTS		0x0004
39a551c94aSIdo Barnea#define ICH_FLASH_HSFCTL		0x0006
40a551c94aSIdo Barnea#define ICH_FLASH_FADDR			0x0008
41a551c94aSIdo Barnea#define ICH_FLASH_FDATA0		0x0010
42a551c94aSIdo Barnea
43a551c94aSIdo Barnea/* Requires up to 10 seconds when MNG might be accessing part. */
44a551c94aSIdo Barnea#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
45a551c94aSIdo Barnea#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
46a551c94aSIdo Barnea#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
47a551c94aSIdo Barnea#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
48a551c94aSIdo Barnea#define ICH_FLASH_CYCLE_REPEAT_COUNT	10
49a551c94aSIdo Barnea
50a551c94aSIdo Barnea#define ICH_CYCLE_READ			0
51a551c94aSIdo Barnea#define ICH_CYCLE_WRITE			2
52a551c94aSIdo Barnea#define ICH_CYCLE_ERASE			3
53a551c94aSIdo Barnea
54a551c94aSIdo Barnea#define FLASH_GFPREG_BASE_MASK		0x1FFF
55a551c94aSIdo Barnea#define FLASH_SECTOR_ADDR_SHIFT		12
56a551c94aSIdo Barnea
57a551c94aSIdo Barnea#define ICH_FLASH_SEG_SIZE_256		256
58a551c94aSIdo Barnea#define ICH_FLASH_SEG_SIZE_4K		4096
59a551c94aSIdo Barnea#define ICH_FLASH_SEG_SIZE_8K		8192
60a551c94aSIdo Barnea#define ICH_FLASH_SEG_SIZE_64K		65536
61a551c94aSIdo Barnea
62a551c94aSIdo Barnea#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */
63a551c94aSIdo Barnea/* FW established a valid mode */
64a551c94aSIdo Barnea#define E1000_ICH_FWSM_FW_VALID	0x00008000
65a551c94aSIdo Barnea#define E1000_ICH_FWSM_PCIM2PCI	0x01000000 /* ME PCIm-to-PCI active */
66a551c94aSIdo Barnea#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000
67a551c94aSIdo Barnea
68a551c94aSIdo Barnea#define E1000_ICH_MNG_IAMT_MODE		0x2
69a551c94aSIdo Barnea
70a551c94aSIdo Barnea#define E1000_FWSM_WLOCK_MAC_MASK	0x0380
71a551c94aSIdo Barnea#define E1000_FWSM_WLOCK_MAC_SHIFT	7
72a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
73a551c94aSIdo Barnea#define E1000_FWSM_ULP_CFG_DONE		0x00000400  /* Low power cfg done */
74a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
75a551c94aSIdo Barnea
76a551c94aSIdo Barnea/* Shared Receive Address Registers */
77a551c94aSIdo Barnea#define E1000_SHRAL_PCH_LPT(_i)		(0x05408 + ((_i) * 8))
78a551c94aSIdo Barnea#define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))
79a551c94aSIdo Barnea
80a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
81a551c94aSIdo Barnea#define E1000_H2ME		0x05B50    /* Host to ME */
82a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
83a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
84a551c94aSIdo Barnea#define E1000_H2ME_ULP		0x00000800 /* ULP Indication Bit */
85a551c94aSIdo Barnea#define E1000_H2ME_ENFORCE_SETTINGS	0x00001000 /* Enforce Settings */
86a551c94aSIdo Barnea
87a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
88a551c94aSIdo Barnea#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
89a551c94aSIdo Barnea				 (ID_LED_OFF1_OFF2 <<  8) | \
90a551c94aSIdo Barnea				 (ID_LED_OFF1_ON2  <<  4) | \
91a551c94aSIdo Barnea				 (ID_LED_DEF1_DEF2))
92a551c94aSIdo Barnea
93a551c94aSIdo Barnea#define E1000_ICH_NVM_SIG_WORD		0x13
94a551c94aSIdo Barnea#define E1000_ICH_NVM_SIG_MASK		0xC000
95a551c94aSIdo Barnea#define E1000_ICH_NVM_VALID_SIG_MASK	0xC0
96a551c94aSIdo Barnea#define E1000_ICH_NVM_SIG_VALUE		0x80
97a551c94aSIdo Barnea
98a551c94aSIdo Barnea#define E1000_ICH8_LAN_INIT_TIMEOUT	1500
99a551c94aSIdo Barnea
100a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
101a551c94aSIdo Barnea/* FEXT register bit definition */
102a551c94aSIdo Barnea#define E1000_FEXT_PHY_CABLE_DISCONNECTED	0x00000004
103a551c94aSIdo Barnea
104a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
105a551c94aSIdo Barnea#define E1000_FEXTNVM_SW_CONFIG		1
106a551c94aSIdo Barnea#define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27) /* different on ICH8M */
107a551c94aSIdo Barnea
108a551c94aSIdo Barnea#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK	0x0C000000
109a551c94aSIdo Barnea#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC	0x08000000
110a551c94aSIdo Barnea
111a551c94aSIdo Barnea#define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7
112a551c94aSIdo Barnea#define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7
113a551c94aSIdo Barnea#define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3
114a551c94aSIdo Barnea
115a551c94aSIdo Barnea#define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100
116a551c94aSIdo Barnea#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
117a551c94aSIdo Barnea#define E1000_FEXTNVM6_K1_OFF_ENABLE	0x80000000
118a551c94aSIdo Barnea/* bit for disabling packet buffer read */
119a551c94aSIdo Barnea#define E1000_FEXTNVM7_DISABLE_PB_READ	0x00040000
120a551c94aSIdo Barnea#define E1000_FEXTNVM7_SIDE_CLK_UNGATE	0x00000004
121a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
122a551c94aSIdo Barnea#define E1000_FEXTNVM7_DISABLE_SMB_PERST	0x00000020
123a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
1249ca4a157SIdo Barnea#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS	0x00000800
1259ca4a157SIdo Barnea#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS	0x00001000
1269ca4a157SIdo Barnea#define E1000_FEXTNVM11_DISABLE_PB_READ		0x00000200
1279ca4a157SIdo Barnea#define E1000_FEXTNVM11_DISABLE_MULR_FIX	0x00002000
1289ca4a157SIdo Barnea
1299ca4a157SIdo Barnea/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
1309ca4a157SIdo Barnea#define E1000_RXDCTL_THRESH_UNIT_DESC	0x01000000
1319ca4a157SIdo Barnea
1329ca4a157SIdo Barnea#define NVM_SIZE_MULTIPLIER 4096  /*multiplier for NVMS field*/
1339ca4a157SIdo Barnea#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
1349ca4a157SIdo Barnea#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
1359ca4a157SIdo Barnea#define E1000_TARC0_CB_MULTIQ_3_REQ	(1 << 28 | 1 << 29)
136a551c94aSIdo Barnea#define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
137a551c94aSIdo Barnea
138a551c94aSIdo Barnea#define E1000_ICH_RAR_ENTRIES	7
139a551c94aSIdo Barnea#define E1000_PCH2_RAR_ENTRIES	5 /* RAR[0], SHRA[0-3] */
140a551c94aSIdo Barnea#define E1000_PCH_LPT_RAR_ENTRIES	12 /* RAR[0], SHRA[0-10] */
141a551c94aSIdo Barnea
142a551c94aSIdo Barnea#define PHY_PAGE_SHIFT		5
143a551c94aSIdo Barnea#define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \
144a551c94aSIdo Barnea				 ((reg) & MAX_PHY_REG_ADDRESS))
145a551c94aSIdo Barnea#define IGP3_KMRN_DIAG	PHY_REG(770, 19) /* KMRN Diagnostic */
146a551c94aSIdo Barnea#define IGP3_VR_CTRL	PHY_REG(776, 18) /* Voltage Regulator Control */
147a551c94aSIdo Barnea
148a551c94aSIdo Barnea#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002
149a551c94aSIdo Barnea#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300
150a551c94aSIdo Barnea#define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200
151a551c94aSIdo Barnea
152a551c94aSIdo Barnea/* PHY Wakeup Registers and defines */
153a551c94aSIdo Barnea#define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)
154a551c94aSIdo Barnea#define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)
155a551c94aSIdo Barnea#define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)
156a551c94aSIdo Barnea#define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)
157a551c94aSIdo Barnea#define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)
158a551c94aSIdo Barnea#define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
159a551c94aSIdo Barnea#define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
160a551c94aSIdo Barnea#define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
161a551c94aSIdo Barnea#define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
162a551c94aSIdo Barnea#define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
163a551c94aSIdo Barnea
164a551c94aSIdo Barnea#define BM_RCTL_UPE		0x0001 /* Unicast Promiscuous Mode */
165a551c94aSIdo Barnea#define BM_RCTL_MPE		0x0002 /* Multicast Promiscuous Mode */
166a551c94aSIdo Barnea#define BM_RCTL_MO_SHIFT	3      /* Multicast Offset Shift */
167a551c94aSIdo Barnea#define BM_RCTL_MO_MASK		(3 << 3) /* Multicast Offset Mask */
168a551c94aSIdo Barnea#define BM_RCTL_BAM		0x0020 /* Broadcast Accept Mode */
169a551c94aSIdo Barnea#define BM_RCTL_PMCF		0x0040 /* Pass MAC Control Frames */
170a551c94aSIdo Barnea#define BM_RCTL_RFCE		0x0080 /* Rx Flow Control Enable */
171a551c94aSIdo Barnea
172a551c94aSIdo Barnea#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
173a551c94aSIdo Barnea#define HV_MUX_DATA_CTRL	PHY_REG(776, 16)
174a551c94aSIdo Barnea#define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400
175a551c94aSIdo Barnea#define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004
176a551c94aSIdo Barnea#define HV_STATS_PAGE	778
177a551c94aSIdo Barnea/* Half-duplex collision counts */
178a551c94aSIdo Barnea#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
179a551c94aSIdo Barnea#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
180a551c94aSIdo Barnea#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
181a551c94aSIdo Barnea#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
182a551c94aSIdo Barnea#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
183a551c94aSIdo Barnea#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
184a551c94aSIdo Barnea#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
185a551c94aSIdo Barnea#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
186a551c94aSIdo Barnea#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision */
187a551c94aSIdo Barnea#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
188a551c94aSIdo Barnea#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
189a551c94aSIdo Barnea#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
190a551c94aSIdo Barnea#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
191a551c94aSIdo Barnea#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
192a551c94aSIdo Barnea
193a551c94aSIdo Barnea#define E1000_FCRTV_PCH	0x05F40 /* PCH Flow Control Refresh Timer Value */
194a551c94aSIdo Barnea
195a551c94aSIdo Barnea#define E1000_NVM_K1_CONFIG	0x1B /* NVM K1 Config Word */
196a551c94aSIdo Barnea#define E1000_NVM_K1_ENABLE	0x1  /* NVM Enable K1 bit */
197a551c94aSIdo Barnea#define K1_ENTRY_LATENCY	0
198a551c94aSIdo Barnea#define K1_MIN_TIME		1
199a551c94aSIdo Barnea
200a551c94aSIdo Barnea/* SMBus Control Phy Register */
201a551c94aSIdo Barnea#define CV_SMB_CTRL		PHY_REG(769, 23)
202a551c94aSIdo Barnea#define CV_SMB_CTRL_FORCE_SMBUS	0x0001
203a551c94aSIdo Barnea
204a551c94aSIdo Barnea#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
205a551c94aSIdo Barnea/* I218 Ultra Low Power Configuration 1 Register */
206a551c94aSIdo Barnea#define I218_ULP_CONFIG1		PHY_REG(779, 16)
207a551c94aSIdo Barnea#define I218_ULP_CONFIG1_START		0x0001 /* Start auto ULP config */
208a551c94aSIdo Barnea#define I218_ULP_CONFIG1_IND		0x0004 /* Pwr up from ULP indication */
209a551c94aSIdo Barnea#define I218_ULP_CONFIG1_STICKY_ULP	0x0010 /* Set sticky ULP mode */
210a551c94aSIdo Barnea#define I218_ULP_CONFIG1_INBAND_EXIT	0x0020 /* Inband on ULP exit */
211a551c94aSIdo Barnea#define I218_ULP_CONFIG1_WOL_HOST	0x0040 /* WoL Host on ULP exit */
212a551c94aSIdo Barnea#define I218_ULP_CONFIG1_RESET_TO_SMBUS	0x0100 /* Reset to SMBus mode */
2139ca4a157SIdo Barnea/* enable ULP even if when phy powered down via lanphypc */
2149ca4a157SIdo Barnea#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC	0x0400
2159ca4a157SIdo Barnea/* disable clear of sticky ULP on PERST */
2169ca4a157SIdo Barnea#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST	0x0800
217a551c94aSIdo Barnea#define I218_ULP_CONFIG1_DISABLE_SMB_PERST	0x1000 /* Disable on PERST# */
218a551c94aSIdo Barnea
219a551c94aSIdo Barnea#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
220a551c94aSIdo Barnea/* SMBus Address Phy Register */
221a551c94aSIdo Barnea#define HV_SMB_ADDR		PHY_REG(768, 26)
222a551c94aSIdo Barnea#define HV_SMB_ADDR_MASK	0x007F
223a551c94aSIdo Barnea#define HV_SMB_ADDR_PEC_EN	0x0200
224a551c94aSIdo Barnea#define HV_SMB_ADDR_VALID	0x0080
225a551c94aSIdo Barnea#define HV_SMB_ADDR_FREQ_MASK		0x1100
226a551c94aSIdo Barnea#define HV_SMB_ADDR_FREQ_LOW_SHIFT	8
227a551c94aSIdo Barnea#define HV_SMB_ADDR_FREQ_HIGH_SHIFT	12
228a551c94aSIdo Barnea
229a551c94aSIdo Barnea/* Strapping Option Register - RO */
230a551c94aSIdo Barnea#define E1000_STRAP			0x0000C
231a551c94aSIdo Barnea#define E1000_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000
232a551c94aSIdo Barnea#define E1000_STRAP_SMBUS_ADDRESS_SHIFT	17
233a551c94aSIdo Barnea#define E1000_STRAP_SMT_FREQ_MASK	0x00003000
234a551c94aSIdo Barnea#define E1000_STRAP_SMT_FREQ_SHIFT	12
235a551c94aSIdo Barnea
236a551c94aSIdo Barnea/* OEM Bits Phy Register */
237a551c94aSIdo Barnea#define HV_OEM_BITS		PHY_REG(768, 25)
238a551c94aSIdo Barnea#define HV_OEM_BITS_LPLU	0x0004 /* Low Power Link Up */
239a551c94aSIdo Barnea#define HV_OEM_BITS_GBE_DIS	0x0040 /* Gigabit Disable */
240a551c94aSIdo Barnea#define HV_OEM_BITS_RESTART_AN	0x0400 /* Restart Auto-negotiation */
241a551c94aSIdo Barnea
242a551c94aSIdo Barnea/* KMRN Mode Control */
243a551c94aSIdo Barnea#define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)
244a551c94aSIdo Barnea#define HV_KMRN_MDIO_SLOW	0x0400
245a551c94aSIdo Barnea
246a551c94aSIdo Barnea/* KMRN FIFO Control and Status */
247a551c94aSIdo Barnea#define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)
248a551c94aSIdo Barnea#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000
249a551c94aSIdo Barnea#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12
250a551c94aSIdo Barnea
251a551c94aSIdo Barnea/* PHY Power Management Control */
252a551c94aSIdo Barnea#define HV_PM_CTRL		PHY_REG(770, 17)
2539ca4a157SIdo Barnea#define HV_PM_CTRL_K1_CLK_REQ		0x200
254a551c94aSIdo Barnea#define HV_PM_CTRL_K1_ENABLE		0x4000
255a551c94aSIdo Barnea
2569ca4a157SIdo Barnea#define I217_PLL_CLOCK_GATE_REG	PHY_REG(772, 28)
2579ca4a157SIdo Barnea#define I217_PLL_CLOCK_GATE_MASK	0x07FF
2589ca4a157SIdo Barnea
259a551c94aSIdo Barnea#define SW_FLAG_TIMEOUT		1000 /* SW Semaphore flag timeout in ms */
260a551c94aSIdo Barnea
261a551c94aSIdo Barnea/* Inband Control */
262a551c94aSIdo Barnea#define I217_INBAND_CTRL				PHY_REG(770, 18)
263a551c94aSIdo Barnea#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00
264a551c94aSIdo Barnea#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8
265a551c94aSIdo Barnea
266a551c94aSIdo Barnea/* Low Power Idle GPIO Control */
267a551c94aSIdo Barnea#define I217_LPI_GPIO_CTRL			PHY_REG(772, 18)
268a551c94aSIdo Barnea#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI		0x0800
269a551c94aSIdo Barnea
270a551c94aSIdo Barnea/* PHY Low Power Idle Control */
271a551c94aSIdo Barnea#define I82579_LPI_CTRL				PHY_REG(772, 20)
272a551c94aSIdo Barnea#define I82579_LPI_CTRL_100_ENABLE		0x2000
273a551c94aSIdo Barnea#define I82579_LPI_CTRL_1000_ENABLE		0x4000
274a551c94aSIdo Barnea#define I82579_LPI_CTRL_ENABLE_MASK		0x6000
275a551c94aSIdo Barnea
276a551c94aSIdo Barnea/* 82579 DFT Control */
277a551c94aSIdo Barnea#define I82579_DFT_CTRL			PHY_REG(769, 20)
278a551c94aSIdo Barnea#define I82579_DFT_CTRL_GATE_PHY_RESET	0x0040 /* Gate PHY Reset on MAC Reset */
279a551c94aSIdo Barnea
280a551c94aSIdo Barnea/* Extended Management Interface (EMI) Registers */
281a551c94aSIdo Barnea#define I82579_EMI_ADDR		0x10
282a551c94aSIdo Barnea#define I82579_EMI_DATA		0x11
283a551c94aSIdo Barnea#define I82579_LPI_UPDATE_TIMER	0x4805 /* in 40ns units + 40 ns base value */
284a551c94aSIdo Barnea#define I82579_MSE_THRESHOLD	0x084F /* 82579 Mean Square Error Threshold */
285a551c94aSIdo Barnea#define I82577_MSE_THRESHOLD	0x0887 /* 82577 Mean Square Error Threshold */
286a551c94aSIdo Barnea#define I82579_MSE_LINK_DOWN	0x2411 /* MSE count before dropping link */
287a551c94aSIdo Barnea#define I82579_RX_CONFIG		0x3412 /* Receive configuration */
288a551c94aSIdo Barnea#define I82579_LPI_PLL_SHUT		0x4412 /* LPI PLL Shut Enable */
289a551c94aSIdo Barnea#define I82579_EEE_PCS_STATUS		0x182E	/* IEEE MMD Register 3.1 >> 8 */
290a551c94aSIdo Barnea#define I82579_EEE_CAPABILITY		0x0410 /* IEEE MMD Register 3.20 */
291a551c94aSIdo Barnea#define I82579_EEE_ADVERTISEMENT	0x040E /* IEEE MMD Register 7.60 */
292a551c94aSIdo Barnea#define I82579_EEE_LP_ABILITY		0x040F /* IEEE MMD Register 7.61 */
293a551c94aSIdo Barnea#define I82579_EEE_100_SUPPORTED	(1 << 1) /* 100BaseTx EEE */
294a551c94aSIdo Barnea#define I82579_EEE_1000_SUPPORTED	(1 << 2) /* 1000BaseTx EEE */
295a551c94aSIdo Barnea#define I82579_LPI_100_PLL_SHUT	(1 << 2) /* 100M LPI PLL Shut Enabled */
296a551c94aSIdo Barnea#define I217_EEE_PCS_STATUS	0x9401   /* IEEE MMD Register 3.1 */
297a551c94aSIdo Barnea#define I217_EEE_CAPABILITY	0x8000   /* IEEE MMD Register 3.20 */
298a551c94aSIdo Barnea#define I217_EEE_ADVERTISEMENT	0x8001   /* IEEE MMD Register 7.60 */
299a551c94aSIdo Barnea#define I217_EEE_LP_ABILITY	0x8002   /* IEEE MMD Register 7.61 */
300a551c94aSIdo Barnea#define I217_RX_CONFIG		0xB20C /* Receive configuration */
301a551c94aSIdo Barnea
302a551c94aSIdo Barnea#define E1000_EEE_RX_LPI_RCVD	0x0400	/* Tx LP idle received */
303a551c94aSIdo Barnea#define E1000_EEE_TX_LPI_RCVD	0x0800	/* Rx LP idle received */
304a551c94aSIdo Barnea
305a551c94aSIdo Barnea/* Intel Rapid Start Technology Support */
306a551c94aSIdo Barnea#define I217_PROXY_CTRL		BM_PHY_REG(BM_WUC_PAGE, 70)
307a551c94aSIdo Barnea#define I217_PROXY_CTRL_AUTO_DISABLE	0x0080
308a551c94aSIdo Barnea#define I217_SxCTRL			PHY_REG(BM_PORT_CTRL_PAGE, 28)
309a551c94aSIdo Barnea#define I217_SxCTRL_ENABLE_LPI_RESET	0x1000
310a551c94aSIdo Barnea#define I217_CGFREG			PHY_REG(772, 29)
311a551c94aSIdo Barnea#define I217_CGFREG_ENABLE_MTA_RESET	0x0002
312a551c94aSIdo Barnea#define I217_MEMPWR			PHY_REG(772, 26)
313a551c94aSIdo Barnea#define I217_MEMPWR_DISABLE_SMB_RELEASE	0x0010
314a551c94aSIdo Barnea
315a551c94aSIdo Barnea/* Receive Address Initial CRC Calculation */
316a551c94aSIdo Barnea#define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
317a551c94aSIdo Barnea
318a551c94aSIdo Barnea#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
319a551c94aSIdo Barnea#define E1000_PCI_REVISION_ID_REG	0x08
320a551c94aSIdo Barnea#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */
321a551c94aSIdo Barneavoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
322a551c94aSIdo Barnea						 bool state);
323a551c94aSIdo Barneavoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
324a551c94aSIdo Barneavoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
325a551c94aSIdo Barneavoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
326a551c94aSIdo Barneau32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
327a551c94aSIdo Barneas32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
328a551c94aSIdo Barneas32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
329a551c94aSIdo Barneavoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
330a551c94aSIdo Barneas32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
331a551c94aSIdo Barneas32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
332a551c94aSIdo Barneas32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
333a551c94aSIdo Barneas32 e1000_set_eee_pchlan(struct e1000_hw *hw);
334a551c94aSIdo Barnea#ifdef ULP_SUPPORT
335a551c94aSIdo Barneas32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
336a551c94aSIdo Barneas32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
337a551c94aSIdo Barnea#endif /* ULP_SUPPORT */
338a551c94aSIdo Barnea#endif /* _E1000_ICH8LAN_H_ */
339a551c94aSIdo Barneavoid e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link);
340