1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34#ifndef _E1000_MANAGE_H_
35#define _E1000_MANAGE_H_
36
37bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
38bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
39s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
40s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
41				     u16 length, u16 offset, u8 *sum);
42s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
43				     struct e1000_host_mng_command_header *hdr);
44s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
45				       u8 *buffer, u16 length);
46bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
47u8 e1000_calculate_checksum(u8 *buffer, u32 length);
48s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
49s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
50
51enum e1000_mng_mode {
52	e1000_mng_mode_none = 0,
53	e1000_mng_mode_asf,
54	e1000_mng_mode_pt,
55	e1000_mng_mode_ipmi,
56	e1000_mng_mode_host_if_only
57};
58
59#define E1000_FACTPS_MNGCG			0x20000000
60
61#define E1000_FWSM_MODE_MASK			0xE
62#define E1000_FWSM_MODE_SHIFT			1
63#define E1000_FWSM_FW_VALID			0x00008000
64#define E1000_FWSM_HI_EN_ONLY_MODE		0x4
65
66#define E1000_MNG_IAMT_MODE			0x3
67#define E1000_MNG_DHCP_COOKIE_LENGTH		0x10
68#define E1000_MNG_DHCP_COOKIE_OFFSET		0x6F0
69#define E1000_MNG_DHCP_COMMAND_TIMEOUT		10
70#define E1000_MNG_DHCP_TX_PAYLOAD_CMD		64
71#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
72#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
73
74#define E1000_VFTA_ENTRY_SHIFT			5
75#define E1000_VFTA_ENTRY_MASK			0x7F
76#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK		0x1F
77
78#define E1000_HI_MAX_BLOCK_BYTE_LENGTH		1792 /* Num of bytes in range */
79#define E1000_HI_MAX_BLOCK_DWORD_LENGTH		448 /* Num of dwords in range */
80#define E1000_HI_COMMAND_TIMEOUT		500 /* Process HI cmd limit */
81#define E1000_HI_FW_BASE_ADDRESS		0x10000
82#define E1000_HI_FW_MAX_LENGTH			(64 * 1024) /* Num of bytes */
83#define E1000_HI_FW_BLOCK_DWORD_LENGTH		256 /* Num of DWORDs per page */
84#define E1000_HICR_MEMORY_BASE_EN		0x200 /* MB Enable bit - RO */
85#define E1000_HICR_EN			0x01  /* Enable bit - RO */
86/* Driver sets this bit when done to put command in RAM */
87#define E1000_HICR_C			0x02
88#define E1000_HICR_SV			0x04  /* Status Validity */
89#define E1000_HICR_FW_RESET_ENABLE	0x40
90#define E1000_HICR_FW_RESET		0x80
91
92/* Intel(R) Active Management Technology signature */
93#define E1000_IAMT_SIGNATURE		0x544D4149
94
95#endif
96