1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
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15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
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20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef _E1000_MANAGE_H_
35a551c94aSIdo Barnea#define _E1000_MANAGE_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barneabool e1000_check_mng_mode_generic(struct e1000_hw *hw);
38a551c94aSIdo Barneabool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
39a551c94aSIdo Barneas32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
40a551c94aSIdo Barneas32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
41a551c94aSIdo Barnea				     u16 length, u16 offset, u8 *sum);
42a551c94aSIdo Barneas32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
43a551c94aSIdo Barnea				     struct e1000_host_mng_command_header *hdr);
44a551c94aSIdo Barneas32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
45a551c94aSIdo Barnea				       u8 *buffer, u16 length);
46a551c94aSIdo Barneabool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
47a551c94aSIdo Barneau8 e1000_calculate_checksum(u8 *buffer, u32 length);
48a551c94aSIdo Barneas32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
49a551c94aSIdo Barneas32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
50a551c94aSIdo Barnea
51a551c94aSIdo Barneaenum e1000_mng_mode {
52a551c94aSIdo Barnea	e1000_mng_mode_none = 0,
53a551c94aSIdo Barnea	e1000_mng_mode_asf,
54a551c94aSIdo Barnea	e1000_mng_mode_pt,
55a551c94aSIdo Barnea	e1000_mng_mode_ipmi,
56a551c94aSIdo Barnea	e1000_mng_mode_host_if_only
57a551c94aSIdo Barnea};
58a551c94aSIdo Barnea
59a551c94aSIdo Barnea#define E1000_FACTPS_MNGCG			0x20000000
60a551c94aSIdo Barnea
61a551c94aSIdo Barnea#define E1000_FWSM_MODE_MASK			0xE
62a551c94aSIdo Barnea#define E1000_FWSM_MODE_SHIFT			1
63a551c94aSIdo Barnea#define E1000_FWSM_FW_VALID			0x00008000
64a551c94aSIdo Barnea#define E1000_FWSM_HI_EN_ONLY_MODE		0x4
65a551c94aSIdo Barnea
66a551c94aSIdo Barnea#define E1000_MNG_IAMT_MODE			0x3
67a551c94aSIdo Barnea#define E1000_MNG_DHCP_COOKIE_LENGTH		0x10
68a551c94aSIdo Barnea#define E1000_MNG_DHCP_COOKIE_OFFSET		0x6F0
69a551c94aSIdo Barnea#define E1000_MNG_DHCP_COMMAND_TIMEOUT		10
70a551c94aSIdo Barnea#define E1000_MNG_DHCP_TX_PAYLOAD_CMD		64
71a551c94aSIdo Barnea#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
72a551c94aSIdo Barnea#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea#define E1000_VFTA_ENTRY_SHIFT			5
75a551c94aSIdo Barnea#define E1000_VFTA_ENTRY_MASK			0x7F
76a551c94aSIdo Barnea#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK		0x1F
77a551c94aSIdo Barnea
78a551c94aSIdo Barnea#define E1000_HI_MAX_BLOCK_BYTE_LENGTH		1792 /* Num of bytes in range */
79a551c94aSIdo Barnea#define E1000_HI_MAX_BLOCK_DWORD_LENGTH		448 /* Num of dwords in range */
80a551c94aSIdo Barnea#define E1000_HI_COMMAND_TIMEOUT		500 /* Process HI cmd limit */
81a551c94aSIdo Barnea#define E1000_HI_FW_BASE_ADDRESS		0x10000
82a551c94aSIdo Barnea#define E1000_HI_FW_MAX_LENGTH			(64 * 1024) /* Num of bytes */
83a551c94aSIdo Barnea#define E1000_HI_FW_BLOCK_DWORD_LENGTH		256 /* Num of DWORDs per page */
84a551c94aSIdo Barnea#define E1000_HICR_MEMORY_BASE_EN		0x200 /* MB Enable bit - RO */
85a551c94aSIdo Barnea#define E1000_HICR_EN			0x01  /* Enable bit - RO */
86a551c94aSIdo Barnea/* Driver sets this bit when done to put command in RAM */
87a551c94aSIdo Barnea#define E1000_HICR_C			0x02
88a551c94aSIdo Barnea#define E1000_HICR_SV			0x04  /* Status Validity */
89a551c94aSIdo Barnea#define E1000_HICR_FW_RESET_ENABLE	0x40
90a551c94aSIdo Barnea#define E1000_HICR_FW_RESET		0x80
91a551c94aSIdo Barnea
92a551c94aSIdo Barnea/* Intel(R) Active Management Technology signature */
93a551c94aSIdo Barnea#define E1000_IAMT_SIGNATURE		0x544D4149
94a551c94aSIdo Barnea
95a551c94aSIdo Barnea#endif
96