1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#include "e1000_api.h"
35a551c94aSIdo Barnea
36a551c94aSIdo BarneaSTATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
37a551c94aSIdo Barnea
38a551c94aSIdo Barnea/**
39a551c94aSIdo Barnea *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
40a551c94aSIdo Barnea *  @hw: pointer to the HW structure
41a551c94aSIdo Barnea *
42a551c94aSIdo Barnea *  Setups up the function pointers to no-op functions
43a551c94aSIdo Barnea **/
44a551c94aSIdo Barneavoid e1000_init_nvm_ops_generic(struct e1000_hw *hw)
45a551c94aSIdo Barnea{
46a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
47a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_nvm_ops_generic");
48a551c94aSIdo Barnea
49a551c94aSIdo Barnea	/* Initialize function pointers */
50a551c94aSIdo Barnea	nvm->ops.init_params = e1000_null_ops_generic;
51a551c94aSIdo Barnea	nvm->ops.acquire = e1000_null_ops_generic;
52a551c94aSIdo Barnea	nvm->ops.read = e1000_null_read_nvm;
53a551c94aSIdo Barnea	nvm->ops.release = e1000_null_nvm_generic;
54a551c94aSIdo Barnea	nvm->ops.reload = e1000_reload_nvm_generic;
55a551c94aSIdo Barnea	nvm->ops.update = e1000_null_ops_generic;
56a551c94aSIdo Barnea	nvm->ops.valid_led_default = e1000_null_led_default;
57a551c94aSIdo Barnea	nvm->ops.validate = e1000_null_ops_generic;
58a551c94aSIdo Barnea	nvm->ops.write = e1000_null_write_nvm;
59a551c94aSIdo Barnea}
60a551c94aSIdo Barnea
61a551c94aSIdo Barnea/**
62a551c94aSIdo Barnea *  e1000_null_nvm_read - No-op function, return 0
63a551c94aSIdo Barnea *  @hw: pointer to the HW structure
64a551c94aSIdo Barnea **/
65a551c94aSIdo Barneas32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
66a551c94aSIdo Barnea			u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
67a551c94aSIdo Barnea			u16 E1000_UNUSEDARG *c)
68a551c94aSIdo Barnea{
69a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_read_nvm");
70a551c94aSIdo Barnea	UNREFERENCED_4PARAMETER(hw, a, b, c);
71a551c94aSIdo Barnea	return E1000_SUCCESS;
72a551c94aSIdo Barnea}
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea/**
75a551c94aSIdo Barnea *  e1000_null_nvm_generic - No-op function, return void
76a551c94aSIdo Barnea *  @hw: pointer to the HW structure
77a551c94aSIdo Barnea **/
78a551c94aSIdo Barneavoid e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
79a551c94aSIdo Barnea{
80a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_nvm_generic");
81a551c94aSIdo Barnea	UNREFERENCED_1PARAMETER(hw);
82a551c94aSIdo Barnea	return;
83a551c94aSIdo Barnea}
84a551c94aSIdo Barnea
85a551c94aSIdo Barnea/**
86a551c94aSIdo Barnea *  e1000_null_led_default - No-op function, return 0
87a551c94aSIdo Barnea *  @hw: pointer to the HW structure
88a551c94aSIdo Barnea **/
89a551c94aSIdo Barneas32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
90a551c94aSIdo Barnea			   u16 E1000_UNUSEDARG *data)
91a551c94aSIdo Barnea{
92a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_led_default");
93a551c94aSIdo Barnea	UNREFERENCED_2PARAMETER(hw, data);
94a551c94aSIdo Barnea	return E1000_SUCCESS;
95a551c94aSIdo Barnea}
96a551c94aSIdo Barnea
97a551c94aSIdo Barnea/**
98a551c94aSIdo Barnea *  e1000_null_write_nvm - No-op function, return 0
99a551c94aSIdo Barnea *  @hw: pointer to the HW structure
100a551c94aSIdo Barnea **/
101a551c94aSIdo Barneas32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
102a551c94aSIdo Barnea			 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
103a551c94aSIdo Barnea			 u16 E1000_UNUSEDARG *c)
104a551c94aSIdo Barnea{
105a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_write_nvm");
106a551c94aSIdo Barnea	UNREFERENCED_4PARAMETER(hw, a, b, c);
107a551c94aSIdo Barnea	return E1000_SUCCESS;
108a551c94aSIdo Barnea}
109a551c94aSIdo Barnea
110a551c94aSIdo Barnea/**
111a551c94aSIdo Barnea *  e1000_raise_eec_clk - Raise EEPROM clock
112a551c94aSIdo Barnea *  @hw: pointer to the HW structure
113a551c94aSIdo Barnea *  @eecd: pointer to the EEPROM
114a551c94aSIdo Barnea *
115a551c94aSIdo Barnea *  Enable/Raise the EEPROM clock bit.
116a551c94aSIdo Barnea **/
117a551c94aSIdo BarneaSTATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
118a551c94aSIdo Barnea{
119a551c94aSIdo Barnea	*eecd = *eecd | E1000_EECD_SK;
120a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
121a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
122a551c94aSIdo Barnea	usec_delay(hw->nvm.delay_usec);
123a551c94aSIdo Barnea}
124a551c94aSIdo Barnea
125a551c94aSIdo Barnea/**
126a551c94aSIdo Barnea *  e1000_lower_eec_clk - Lower EEPROM clock
127a551c94aSIdo Barnea *  @hw: pointer to the HW structure
128a551c94aSIdo Barnea *  @eecd: pointer to the EEPROM
129a551c94aSIdo Barnea *
130a551c94aSIdo Barnea *  Clear/Lower the EEPROM clock bit.
131a551c94aSIdo Barnea **/
132a551c94aSIdo BarneaSTATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
133a551c94aSIdo Barnea{
134a551c94aSIdo Barnea	*eecd = *eecd & ~E1000_EECD_SK;
135a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
136a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
137a551c94aSIdo Barnea	usec_delay(hw->nvm.delay_usec);
138a551c94aSIdo Barnea}
139a551c94aSIdo Barnea
140a551c94aSIdo Barnea/**
141a551c94aSIdo Barnea *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
142a551c94aSIdo Barnea *  @hw: pointer to the HW structure
143a551c94aSIdo Barnea *  @data: data to send to the EEPROM
144a551c94aSIdo Barnea *  @count: number of bits to shift out
145a551c94aSIdo Barnea *
146a551c94aSIdo Barnea *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
147a551c94aSIdo Barnea *  "data" parameter will be shifted out to the EEPROM one bit at a time.
148a551c94aSIdo Barnea *  In order to do this, "data" must be broken down into bits.
149a551c94aSIdo Barnea **/
150a551c94aSIdo BarneaSTATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
151a551c94aSIdo Barnea{
152a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
153a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
154a551c94aSIdo Barnea	u32 mask;
155a551c94aSIdo Barnea
156a551c94aSIdo Barnea	DEBUGFUNC("e1000_shift_out_eec_bits");
157a551c94aSIdo Barnea
158a551c94aSIdo Barnea	mask = 0x01 << (count - 1);
159a551c94aSIdo Barnea	if (nvm->type == e1000_nvm_eeprom_microwire)
160a551c94aSIdo Barnea		eecd &= ~E1000_EECD_DO;
161a551c94aSIdo Barnea	else
162a551c94aSIdo Barnea	if (nvm->type == e1000_nvm_eeprom_spi)
163a551c94aSIdo Barnea		eecd |= E1000_EECD_DO;
164a551c94aSIdo Barnea
165a551c94aSIdo Barnea	do {
166a551c94aSIdo Barnea		eecd &= ~E1000_EECD_DI;
167a551c94aSIdo Barnea
168a551c94aSIdo Barnea		if (data & mask)
169a551c94aSIdo Barnea			eecd |= E1000_EECD_DI;
170a551c94aSIdo Barnea
171a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
172a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
173a551c94aSIdo Barnea
174a551c94aSIdo Barnea		usec_delay(nvm->delay_usec);
175a551c94aSIdo Barnea
176a551c94aSIdo Barnea		e1000_raise_eec_clk(hw, &eecd);
177a551c94aSIdo Barnea		e1000_lower_eec_clk(hw, &eecd);
178a551c94aSIdo Barnea
179a551c94aSIdo Barnea		mask >>= 1;
180a551c94aSIdo Barnea	} while (mask);
181a551c94aSIdo Barnea
182a551c94aSIdo Barnea	eecd &= ~E1000_EECD_DI;
183a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_EECD, eecd);
184a551c94aSIdo Barnea}
185a551c94aSIdo Barnea
186a551c94aSIdo Barnea/**
187a551c94aSIdo Barnea *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
188a551c94aSIdo Barnea *  @hw: pointer to the HW structure
189a551c94aSIdo Barnea *  @count: number of bits to shift in
190a551c94aSIdo Barnea *
191a551c94aSIdo Barnea *  In order to read a register from the EEPROM, we need to shift 'count' bits
192a551c94aSIdo Barnea *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
193a551c94aSIdo Barnea *  the EEPROM (setting the SK bit), and then reading the value of the data out
194a551c94aSIdo Barnea *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
195a551c94aSIdo Barnea *  always be clear.
196a551c94aSIdo Barnea **/
197a551c94aSIdo BarneaSTATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
198a551c94aSIdo Barnea{
199a551c94aSIdo Barnea	u32 eecd;
200a551c94aSIdo Barnea	u32 i;
201a551c94aSIdo Barnea	u16 data;
202a551c94aSIdo Barnea
203a551c94aSIdo Barnea	DEBUGFUNC("e1000_shift_in_eec_bits");
204a551c94aSIdo Barnea
205a551c94aSIdo Barnea	eecd = E1000_READ_REG(hw, E1000_EECD);
206a551c94aSIdo Barnea
207a551c94aSIdo Barnea	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
208a551c94aSIdo Barnea	data = 0;
209a551c94aSIdo Barnea
210a551c94aSIdo Barnea	for (i = 0; i < count; i++) {
211a551c94aSIdo Barnea		data <<= 1;
212a551c94aSIdo Barnea		e1000_raise_eec_clk(hw, &eecd);
213a551c94aSIdo Barnea
214a551c94aSIdo Barnea		eecd = E1000_READ_REG(hw, E1000_EECD);
215a551c94aSIdo Barnea
216a551c94aSIdo Barnea		eecd &= ~E1000_EECD_DI;
217a551c94aSIdo Barnea		if (eecd & E1000_EECD_DO)
218a551c94aSIdo Barnea			data |= 1;
219a551c94aSIdo Barnea
220a551c94aSIdo Barnea		e1000_lower_eec_clk(hw, &eecd);
221a551c94aSIdo Barnea	}
222a551c94aSIdo Barnea
223a551c94aSIdo Barnea	return data;
224a551c94aSIdo Barnea}
225a551c94aSIdo Barnea
226a551c94aSIdo Barnea/**
227a551c94aSIdo Barnea *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
228a551c94aSIdo Barnea *  @hw: pointer to the HW structure
229a551c94aSIdo Barnea *  @ee_reg: EEPROM flag for polling
230a551c94aSIdo Barnea *
231a551c94aSIdo Barnea *  Polls the EEPROM status bit for either read or write completion based
232a551c94aSIdo Barnea *  upon the value of 'ee_reg'.
233a551c94aSIdo Barnea **/
234a551c94aSIdo Barneas32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
235a551c94aSIdo Barnea{
236a551c94aSIdo Barnea	u32 attempts = 100000;
237a551c94aSIdo Barnea	u32 i, reg = 0;
238a551c94aSIdo Barnea
239a551c94aSIdo Barnea	DEBUGFUNC("e1000_poll_eerd_eewr_done");
240a551c94aSIdo Barnea
241a551c94aSIdo Barnea	for (i = 0; i < attempts; i++) {
242a551c94aSIdo Barnea		if (ee_reg == E1000_NVM_POLL_READ)
243a551c94aSIdo Barnea			reg = E1000_READ_REG(hw, E1000_EERD);
244a551c94aSIdo Barnea		else
245a551c94aSIdo Barnea			reg = E1000_READ_REG(hw, E1000_EEWR);
246a551c94aSIdo Barnea
247a551c94aSIdo Barnea		if (reg & E1000_NVM_RW_REG_DONE)
248a551c94aSIdo Barnea			return E1000_SUCCESS;
249a551c94aSIdo Barnea
250a551c94aSIdo Barnea		usec_delay(5);
251a551c94aSIdo Barnea	}
252a551c94aSIdo Barnea
253a551c94aSIdo Barnea	return -E1000_ERR_NVM;
254a551c94aSIdo Barnea}
255a551c94aSIdo Barnea
256a551c94aSIdo Barnea/**
257a551c94aSIdo Barnea *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
258a551c94aSIdo Barnea *  @hw: pointer to the HW structure
259a551c94aSIdo Barnea *
260a551c94aSIdo Barnea *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
261a551c94aSIdo Barnea *  Return successful if access grant bit set, else clear the request for
262a551c94aSIdo Barnea *  EEPROM access and return -E1000_ERR_NVM (-1).
263a551c94aSIdo Barnea **/
264a551c94aSIdo Barneas32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
265a551c94aSIdo Barnea{
266a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
267a551c94aSIdo Barnea	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
268a551c94aSIdo Barnea
269a551c94aSIdo Barnea	DEBUGFUNC("e1000_acquire_nvm_generic");
270a551c94aSIdo Barnea
271a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
272a551c94aSIdo Barnea	eecd = E1000_READ_REG(hw, E1000_EECD);
273a551c94aSIdo Barnea
274a551c94aSIdo Barnea	while (timeout) {
275a551c94aSIdo Barnea		if (eecd & E1000_EECD_GNT)
276a551c94aSIdo Barnea			break;
277a551c94aSIdo Barnea		usec_delay(5);
278a551c94aSIdo Barnea		eecd = E1000_READ_REG(hw, E1000_EECD);
279a551c94aSIdo Barnea		timeout--;
280a551c94aSIdo Barnea	}
281a551c94aSIdo Barnea
282a551c94aSIdo Barnea	if (!timeout) {
283a551c94aSIdo Barnea		eecd &= ~E1000_EECD_REQ;
284a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
285a551c94aSIdo Barnea		DEBUGOUT("Could not acquire NVM grant\n");
286a551c94aSIdo Barnea		return -E1000_ERR_NVM;
287a551c94aSIdo Barnea	}
288a551c94aSIdo Barnea
289a551c94aSIdo Barnea	return E1000_SUCCESS;
290a551c94aSIdo Barnea}
291a551c94aSIdo Barnea
292a551c94aSIdo Barnea/**
293a551c94aSIdo Barnea *  e1000_standby_nvm - Return EEPROM to standby state
294a551c94aSIdo Barnea *  @hw: pointer to the HW structure
295a551c94aSIdo Barnea *
296a551c94aSIdo Barnea *  Return the EEPROM to a standby state.
297a551c94aSIdo Barnea **/
298a551c94aSIdo BarneaSTATIC void e1000_standby_nvm(struct e1000_hw *hw)
299a551c94aSIdo Barnea{
300a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
301a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
302a551c94aSIdo Barnea
303a551c94aSIdo Barnea	DEBUGFUNC("e1000_standby_nvm");
304a551c94aSIdo Barnea
305a551c94aSIdo Barnea	if (nvm->type == e1000_nvm_eeprom_microwire) {
306a551c94aSIdo Barnea		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
307a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
308a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
309a551c94aSIdo Barnea		usec_delay(nvm->delay_usec);
310a551c94aSIdo Barnea
311a551c94aSIdo Barnea		e1000_raise_eec_clk(hw, &eecd);
312a551c94aSIdo Barnea
313a551c94aSIdo Barnea		/* Select EEPROM */
314a551c94aSIdo Barnea		eecd |= E1000_EECD_CS;
315a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
316a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
317a551c94aSIdo Barnea		usec_delay(nvm->delay_usec);
318a551c94aSIdo Barnea
319a551c94aSIdo Barnea		e1000_lower_eec_clk(hw, &eecd);
320a551c94aSIdo Barnea	} else if (nvm->type == e1000_nvm_eeprom_spi) {
321a551c94aSIdo Barnea		/* Toggle CS to flush commands */
322a551c94aSIdo Barnea		eecd |= E1000_EECD_CS;
323a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
324a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
325a551c94aSIdo Barnea		usec_delay(nvm->delay_usec);
326a551c94aSIdo Barnea		eecd &= ~E1000_EECD_CS;
327a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
328a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
329a551c94aSIdo Barnea		usec_delay(nvm->delay_usec);
330a551c94aSIdo Barnea	}
331a551c94aSIdo Barnea}
332a551c94aSIdo Barnea
333a551c94aSIdo Barnea/**
334a551c94aSIdo Barnea *  e1000_stop_nvm - Terminate EEPROM command
335a551c94aSIdo Barnea *  @hw: pointer to the HW structure
336a551c94aSIdo Barnea *
337a551c94aSIdo Barnea *  Terminates the current command by inverting the EEPROM's chip select pin.
338a551c94aSIdo Barnea **/
339a551c94aSIdo Barneavoid e1000_stop_nvm(struct e1000_hw *hw)
340a551c94aSIdo Barnea{
341a551c94aSIdo Barnea	u32 eecd;
342a551c94aSIdo Barnea
343a551c94aSIdo Barnea	DEBUGFUNC("e1000_stop_nvm");
344a551c94aSIdo Barnea
345a551c94aSIdo Barnea	eecd = E1000_READ_REG(hw, E1000_EECD);
346a551c94aSIdo Barnea	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
347a551c94aSIdo Barnea		/* Pull CS high */
348a551c94aSIdo Barnea		eecd |= E1000_EECD_CS;
349a551c94aSIdo Barnea		e1000_lower_eec_clk(hw, &eecd);
350a551c94aSIdo Barnea	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
351a551c94aSIdo Barnea		/* CS on Microwire is active-high */
352a551c94aSIdo Barnea		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
353a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
354a551c94aSIdo Barnea		e1000_raise_eec_clk(hw, &eecd);
355a551c94aSIdo Barnea		e1000_lower_eec_clk(hw, &eecd);
356a551c94aSIdo Barnea	}
357a551c94aSIdo Barnea}
358a551c94aSIdo Barnea
359a551c94aSIdo Barnea/**
360a551c94aSIdo Barnea *  e1000_release_nvm_generic - Release exclusive access to EEPROM
361a551c94aSIdo Barnea *  @hw: pointer to the HW structure
362a551c94aSIdo Barnea *
363a551c94aSIdo Barnea *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
364a551c94aSIdo Barnea **/
365a551c94aSIdo Barneavoid e1000_release_nvm_generic(struct e1000_hw *hw)
366a551c94aSIdo Barnea{
367a551c94aSIdo Barnea	u32 eecd;
368a551c94aSIdo Barnea
369a551c94aSIdo Barnea	DEBUGFUNC("e1000_release_nvm_generic");
370a551c94aSIdo Barnea
371a551c94aSIdo Barnea	e1000_stop_nvm(hw);
372a551c94aSIdo Barnea
373a551c94aSIdo Barnea	eecd = E1000_READ_REG(hw, E1000_EECD);
374a551c94aSIdo Barnea	eecd &= ~E1000_EECD_REQ;
375a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_EECD, eecd);
376a551c94aSIdo Barnea}
377a551c94aSIdo Barnea
378a551c94aSIdo Barnea/**
379a551c94aSIdo Barnea *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
380a551c94aSIdo Barnea *  @hw: pointer to the HW structure
381a551c94aSIdo Barnea *
382a551c94aSIdo Barnea *  Setups the EEPROM for reading and writing.
383a551c94aSIdo Barnea **/
384a551c94aSIdo BarneaSTATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
385a551c94aSIdo Barnea{
386a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
387a551c94aSIdo Barnea	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
388a551c94aSIdo Barnea	u8 spi_stat_reg;
389a551c94aSIdo Barnea
390a551c94aSIdo Barnea	DEBUGFUNC("e1000_ready_nvm_eeprom");
391a551c94aSIdo Barnea
392a551c94aSIdo Barnea	if (nvm->type == e1000_nvm_eeprom_microwire) {
393a551c94aSIdo Barnea		/* Clear SK and DI */
394a551c94aSIdo Barnea		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
395a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
396a551c94aSIdo Barnea		/* Set CS */
397a551c94aSIdo Barnea		eecd |= E1000_EECD_CS;
398a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
399a551c94aSIdo Barnea	} else if (nvm->type == e1000_nvm_eeprom_spi) {
400a551c94aSIdo Barnea		u16 timeout = NVM_MAX_RETRY_SPI;
401a551c94aSIdo Barnea
402a551c94aSIdo Barnea		/* Clear SK and CS */
403a551c94aSIdo Barnea		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EECD, eecd);
405a551c94aSIdo Barnea		E1000_WRITE_FLUSH(hw);
406a551c94aSIdo Barnea		usec_delay(1);
407a551c94aSIdo Barnea
408a551c94aSIdo Barnea		/* Read "Status Register" repeatedly until the LSB is cleared.
409a551c94aSIdo Barnea		 * The EEPROM will signal that the command has been completed
410a551c94aSIdo Barnea		 * by clearing bit 0 of the internal status register.  If it's
411a551c94aSIdo Barnea		 * not cleared within 'timeout', then error out.
412a551c94aSIdo Barnea		 */
413a551c94aSIdo Barnea		while (timeout) {
414a551c94aSIdo Barnea			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
415a551c94aSIdo Barnea						 hw->nvm.opcode_bits);
416a551c94aSIdo Barnea			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
417a551c94aSIdo Barnea			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
418a551c94aSIdo Barnea				break;
419a551c94aSIdo Barnea
420a551c94aSIdo Barnea			usec_delay(5);
421a551c94aSIdo Barnea			e1000_standby_nvm(hw);
422a551c94aSIdo Barnea			timeout--;
423a551c94aSIdo Barnea		}
424a551c94aSIdo Barnea
425a551c94aSIdo Barnea		if (!timeout) {
426a551c94aSIdo Barnea			DEBUGOUT("SPI NVM Status error\n");
427a551c94aSIdo Barnea			return -E1000_ERR_NVM;
428a551c94aSIdo Barnea		}
429a551c94aSIdo Barnea	}
430a551c94aSIdo Barnea
431a551c94aSIdo Barnea	return E1000_SUCCESS;
432a551c94aSIdo Barnea}
433a551c94aSIdo Barnea
434a551c94aSIdo Barnea/**
435a551c94aSIdo Barnea *  e1000_read_nvm_spi - Read EEPROM's using SPI
436a551c94aSIdo Barnea *  @hw: pointer to the HW structure
437a551c94aSIdo Barnea *  @offset: offset of word in the EEPROM to read
438a551c94aSIdo Barnea *  @words: number of words to read
439a551c94aSIdo Barnea *  @data: word read from the EEPROM
440a551c94aSIdo Barnea *
441a551c94aSIdo Barnea *  Reads a 16 bit word from the EEPROM.
442a551c94aSIdo Barnea **/
443a551c94aSIdo Barneas32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
444a551c94aSIdo Barnea{
445a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
446a551c94aSIdo Barnea	u32 i = 0;
447a551c94aSIdo Barnea	s32 ret_val;
448a551c94aSIdo Barnea	u16 word_in;
449a551c94aSIdo Barnea	u8 read_opcode = NVM_READ_OPCODE_SPI;
450a551c94aSIdo Barnea
451a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_nvm_spi");
452a551c94aSIdo Barnea
453a551c94aSIdo Barnea	/* A check for invalid values:  offset too large, too many words,
454a551c94aSIdo Barnea	 * and not enough words.
455a551c94aSIdo Barnea	 */
456a551c94aSIdo Barnea	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
457a551c94aSIdo Barnea	    (words == 0)) {
458a551c94aSIdo Barnea		DEBUGOUT("nvm parameter(s) out of bounds\n");
459a551c94aSIdo Barnea		return -E1000_ERR_NVM;
460a551c94aSIdo Barnea	}
461a551c94aSIdo Barnea
462a551c94aSIdo Barnea	ret_val = nvm->ops.acquire(hw);
463a551c94aSIdo Barnea	if (ret_val)
464a551c94aSIdo Barnea		return ret_val;
465a551c94aSIdo Barnea
466a551c94aSIdo Barnea	ret_val = e1000_ready_nvm_eeprom(hw);
467a551c94aSIdo Barnea	if (ret_val)
468a551c94aSIdo Barnea		goto release;
469a551c94aSIdo Barnea
470a551c94aSIdo Barnea	e1000_standby_nvm(hw);
471a551c94aSIdo Barnea
472a551c94aSIdo Barnea	if ((nvm->address_bits == 8) && (offset >= 128))
473a551c94aSIdo Barnea		read_opcode |= NVM_A8_OPCODE_SPI;
474a551c94aSIdo Barnea
475a551c94aSIdo Barnea	/* Send the READ command (opcode + addr) */
476a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
477a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
478a551c94aSIdo Barnea
479a551c94aSIdo Barnea	/* Read the data.  SPI NVMs increment the address with each byte
480a551c94aSIdo Barnea	 * read and will roll over if reading beyond the end.  This allows
481a551c94aSIdo Barnea	 * us to read the whole NVM from any offset
482a551c94aSIdo Barnea	 */
483a551c94aSIdo Barnea	for (i = 0; i < words; i++) {
484a551c94aSIdo Barnea		word_in = e1000_shift_in_eec_bits(hw, 16);
485a551c94aSIdo Barnea		data[i] = (word_in >> 8) | (word_in << 8);
486a551c94aSIdo Barnea	}
487a551c94aSIdo Barnea
488a551c94aSIdo Barnearelease:
489a551c94aSIdo Barnea	nvm->ops.release(hw);
490a551c94aSIdo Barnea
491a551c94aSIdo Barnea	return ret_val;
492a551c94aSIdo Barnea}
493a551c94aSIdo Barnea
494a551c94aSIdo Barnea/**
495a551c94aSIdo Barnea *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
496a551c94aSIdo Barnea *  @hw: pointer to the HW structure
497a551c94aSIdo Barnea *  @offset: offset of word in the EEPROM to read
498a551c94aSIdo Barnea *  @words: number of words to read
499a551c94aSIdo Barnea *  @data: word read from the EEPROM
500a551c94aSIdo Barnea *
501a551c94aSIdo Barnea *  Reads a 16 bit word from the EEPROM.
502a551c94aSIdo Barnea **/
503a551c94aSIdo Barneas32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
504a551c94aSIdo Barnea			     u16 *data)
505a551c94aSIdo Barnea{
506a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
507a551c94aSIdo Barnea	u32 i = 0;
508a551c94aSIdo Barnea	s32 ret_val;
509a551c94aSIdo Barnea	u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
510a551c94aSIdo Barnea
511a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_nvm_microwire");
512a551c94aSIdo Barnea
513a551c94aSIdo Barnea	/* A check for invalid values:  offset too large, too many words,
514a551c94aSIdo Barnea	 * and not enough words.
515a551c94aSIdo Barnea	 */
516a551c94aSIdo Barnea	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
517a551c94aSIdo Barnea	    (words == 0)) {
518a551c94aSIdo Barnea		DEBUGOUT("nvm parameter(s) out of bounds\n");
519a551c94aSIdo Barnea		return -E1000_ERR_NVM;
520a551c94aSIdo Barnea	}
521a551c94aSIdo Barnea
522a551c94aSIdo Barnea	ret_val = nvm->ops.acquire(hw);
523a551c94aSIdo Barnea	if (ret_val)
524a551c94aSIdo Barnea		return ret_val;
525a551c94aSIdo Barnea
526a551c94aSIdo Barnea	ret_val = e1000_ready_nvm_eeprom(hw);
527a551c94aSIdo Barnea	if (ret_val)
528a551c94aSIdo Barnea		goto release;
529a551c94aSIdo Barnea
530a551c94aSIdo Barnea	for (i = 0; i < words; i++) {
531a551c94aSIdo Barnea		/* Send the READ command (opcode + addr) */
532a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
533a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, (u16)(offset + i),
534a551c94aSIdo Barnea					nvm->address_bits);
535a551c94aSIdo Barnea
536a551c94aSIdo Barnea		/* Read the data.  For microwire, each word requires the
537a551c94aSIdo Barnea		 * overhead of setup and tear-down.
538a551c94aSIdo Barnea		 */
539a551c94aSIdo Barnea		data[i] = e1000_shift_in_eec_bits(hw, 16);
540a551c94aSIdo Barnea		e1000_standby_nvm(hw);
541a551c94aSIdo Barnea	}
542a551c94aSIdo Barnea
543a551c94aSIdo Barnearelease:
544a551c94aSIdo Barnea	nvm->ops.release(hw);
545a551c94aSIdo Barnea
546a551c94aSIdo Barnea	return ret_val;
547a551c94aSIdo Barnea}
548a551c94aSIdo Barnea
549a551c94aSIdo Barnea/**
550a551c94aSIdo Barnea *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
551a551c94aSIdo Barnea *  @hw: pointer to the HW structure
552a551c94aSIdo Barnea *  @offset: offset of word in the EEPROM to read
553a551c94aSIdo Barnea *  @words: number of words to read
554a551c94aSIdo Barnea *  @data: word read from the EEPROM
555a551c94aSIdo Barnea *
556a551c94aSIdo Barnea *  Reads a 16 bit word from the EEPROM using the EERD register.
557a551c94aSIdo Barnea **/
558a551c94aSIdo Barneas32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
559a551c94aSIdo Barnea{
560a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
561a551c94aSIdo Barnea	u32 i, eerd = 0;
562a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
563a551c94aSIdo Barnea
564a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_nvm_eerd");
565a551c94aSIdo Barnea
566a551c94aSIdo Barnea	/* A check for invalid values:  offset too large, too many words,
567a551c94aSIdo Barnea	 * too many words for the offset, and not enough words.
568a551c94aSIdo Barnea	 */
569a551c94aSIdo Barnea	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
570a551c94aSIdo Barnea	    (words == 0)) {
571a551c94aSIdo Barnea		DEBUGOUT("nvm parameter(s) out of bounds\n");
572a551c94aSIdo Barnea		return -E1000_ERR_NVM;
573a551c94aSIdo Barnea	}
574a551c94aSIdo Barnea
575a551c94aSIdo Barnea	for (i = 0; i < words; i++) {
576a551c94aSIdo Barnea		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
577a551c94aSIdo Barnea		       E1000_NVM_RW_REG_START;
578a551c94aSIdo Barnea
579a551c94aSIdo Barnea		E1000_WRITE_REG(hw, E1000_EERD, eerd);
580a551c94aSIdo Barnea		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
581a551c94aSIdo Barnea		if (ret_val)
582a551c94aSIdo Barnea			break;
583a551c94aSIdo Barnea
584a551c94aSIdo Barnea		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
585a551c94aSIdo Barnea			   E1000_NVM_RW_REG_DATA);
586a551c94aSIdo Barnea	}
587a551c94aSIdo Barnea
588a551c94aSIdo Barnea	if (ret_val)
589a551c94aSIdo Barnea		DEBUGOUT1("NVM read error: %d\n", ret_val);
590a551c94aSIdo Barnea
591a551c94aSIdo Barnea	return ret_val;
592a551c94aSIdo Barnea}
593a551c94aSIdo Barnea
594a551c94aSIdo Barnea/**
595a551c94aSIdo Barnea *  e1000_write_nvm_spi - Write to EEPROM using SPI
596a551c94aSIdo Barnea *  @hw: pointer to the HW structure
597a551c94aSIdo Barnea *  @offset: offset within the EEPROM to be written to
598a551c94aSIdo Barnea *  @words: number of words to write
599a551c94aSIdo Barnea *  @data: 16 bit word(s) to be written to the EEPROM
600a551c94aSIdo Barnea *
601a551c94aSIdo Barnea *  Writes data to EEPROM at offset using SPI interface.
602a551c94aSIdo Barnea *
603a551c94aSIdo Barnea *  If e1000_update_nvm_checksum is not called after this function , the
604a551c94aSIdo Barnea *  EEPROM will most likely contain an invalid checksum.
605a551c94aSIdo Barnea **/
606a551c94aSIdo Barneas32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
607a551c94aSIdo Barnea{
608a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
609a551c94aSIdo Barnea	s32 ret_val = -E1000_ERR_NVM;
610a551c94aSIdo Barnea	u16 widx = 0;
611a551c94aSIdo Barnea
612a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_nvm_spi");
613a551c94aSIdo Barnea
614a551c94aSIdo Barnea	/* A check for invalid values:  offset too large, too many words,
615a551c94aSIdo Barnea	 * and not enough words.
616a551c94aSIdo Barnea	 */
617a551c94aSIdo Barnea	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
618a551c94aSIdo Barnea	    (words == 0)) {
619a551c94aSIdo Barnea		DEBUGOUT("nvm parameter(s) out of bounds\n");
620a551c94aSIdo Barnea		return -E1000_ERR_NVM;
621a551c94aSIdo Barnea	}
622a551c94aSIdo Barnea
623a551c94aSIdo Barnea	while (widx < words) {
624a551c94aSIdo Barnea		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
625a551c94aSIdo Barnea
626a551c94aSIdo Barnea		ret_val = nvm->ops.acquire(hw);
627a551c94aSIdo Barnea		if (ret_val)
628a551c94aSIdo Barnea			return ret_val;
629a551c94aSIdo Barnea
630a551c94aSIdo Barnea		ret_val = e1000_ready_nvm_eeprom(hw);
631a551c94aSIdo Barnea		if (ret_val) {
632a551c94aSIdo Barnea			nvm->ops.release(hw);
633a551c94aSIdo Barnea			return ret_val;
634a551c94aSIdo Barnea		}
635a551c94aSIdo Barnea
636a551c94aSIdo Barnea		e1000_standby_nvm(hw);
637a551c94aSIdo Barnea
638a551c94aSIdo Barnea		/* Send the WRITE ENABLE command (8 bit opcode) */
639a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
640a551c94aSIdo Barnea					 nvm->opcode_bits);
641a551c94aSIdo Barnea
642a551c94aSIdo Barnea		e1000_standby_nvm(hw);
643a551c94aSIdo Barnea
644a551c94aSIdo Barnea		/* Some SPI eeproms use the 8th address bit embedded in the
645a551c94aSIdo Barnea		 * opcode
646a551c94aSIdo Barnea		 */
647a551c94aSIdo Barnea		if ((nvm->address_bits == 8) && (offset >= 128))
648a551c94aSIdo Barnea			write_opcode |= NVM_A8_OPCODE_SPI;
649a551c94aSIdo Barnea
650a551c94aSIdo Barnea		/* Send the Write command (8-bit opcode + addr) */
651a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
652a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
653a551c94aSIdo Barnea					 nvm->address_bits);
654a551c94aSIdo Barnea
655a551c94aSIdo Barnea		/* Loop to allow for up to whole page write of eeprom */
656a551c94aSIdo Barnea		while (widx < words) {
657a551c94aSIdo Barnea			u16 word_out = data[widx];
658a551c94aSIdo Barnea			word_out = (word_out >> 8) | (word_out << 8);
659a551c94aSIdo Barnea			e1000_shift_out_eec_bits(hw, word_out, 16);
660a551c94aSIdo Barnea			widx++;
661a551c94aSIdo Barnea
662a551c94aSIdo Barnea			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
663a551c94aSIdo Barnea				e1000_standby_nvm(hw);
664a551c94aSIdo Barnea				break;
665a551c94aSIdo Barnea			}
666a551c94aSIdo Barnea		}
667a551c94aSIdo Barnea		msec_delay(10);
668a551c94aSIdo Barnea		nvm->ops.release(hw);
669a551c94aSIdo Barnea	}
670a551c94aSIdo Barnea
671a551c94aSIdo Barnea	return ret_val;
672a551c94aSIdo Barnea}
673a551c94aSIdo Barnea
674a551c94aSIdo Barnea/**
675a551c94aSIdo Barnea *  e1000_write_nvm_microwire - Writes EEPROM using microwire
676a551c94aSIdo Barnea *  @hw: pointer to the HW structure
677a551c94aSIdo Barnea *  @offset: offset within the EEPROM to be written to
678a551c94aSIdo Barnea *  @words: number of words to write
679a551c94aSIdo Barnea *  @data: 16 bit word(s) to be written to the EEPROM
680a551c94aSIdo Barnea *
681a551c94aSIdo Barnea *  Writes data to EEPROM at offset using microwire interface.
682a551c94aSIdo Barnea *
683a551c94aSIdo Barnea *  If e1000_update_nvm_checksum is not called after this function , the
684a551c94aSIdo Barnea *  EEPROM will most likely contain an invalid checksum.
685a551c94aSIdo Barnea **/
686a551c94aSIdo Barneas32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
687a551c94aSIdo Barnea			      u16 *data)
688a551c94aSIdo Barnea{
689a551c94aSIdo Barnea	struct e1000_nvm_info *nvm = &hw->nvm;
690a551c94aSIdo Barnea	s32  ret_val;
691a551c94aSIdo Barnea	u32 eecd;
692a551c94aSIdo Barnea	u16 words_written = 0;
693a551c94aSIdo Barnea	u16 widx = 0;
694a551c94aSIdo Barnea
695a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_nvm_microwire");
696a551c94aSIdo Barnea
697a551c94aSIdo Barnea	/* A check for invalid values:  offset too large, too many words,
698a551c94aSIdo Barnea	 * and not enough words.
699a551c94aSIdo Barnea	 */
700a551c94aSIdo Barnea	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
701a551c94aSIdo Barnea	    (words == 0)) {
702a551c94aSIdo Barnea		DEBUGOUT("nvm parameter(s) out of bounds\n");
703a551c94aSIdo Barnea		return -E1000_ERR_NVM;
704a551c94aSIdo Barnea	}
705a551c94aSIdo Barnea
706a551c94aSIdo Barnea	ret_val = nvm->ops.acquire(hw);
707a551c94aSIdo Barnea	if (ret_val)
708a551c94aSIdo Barnea		return ret_val;
709a551c94aSIdo Barnea
710a551c94aSIdo Barnea	ret_val = e1000_ready_nvm_eeprom(hw);
711a551c94aSIdo Barnea	if (ret_val)
712a551c94aSIdo Barnea		goto release;
713a551c94aSIdo Barnea
714a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
715a551c94aSIdo Barnea				 (u16)(nvm->opcode_bits + 2));
716a551c94aSIdo Barnea
717a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
718a551c94aSIdo Barnea
719a551c94aSIdo Barnea	e1000_standby_nvm(hw);
720a551c94aSIdo Barnea
721a551c94aSIdo Barnea	while (words_written < words) {
722a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
723a551c94aSIdo Barnea					 nvm->opcode_bits);
724a551c94aSIdo Barnea
725a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
726a551c94aSIdo Barnea					 nvm->address_bits);
727a551c94aSIdo Barnea
728a551c94aSIdo Barnea		e1000_shift_out_eec_bits(hw, data[words_written], 16);
729a551c94aSIdo Barnea
730a551c94aSIdo Barnea		e1000_standby_nvm(hw);
731a551c94aSIdo Barnea
732a551c94aSIdo Barnea		for (widx = 0; widx < 200; widx++) {
733a551c94aSIdo Barnea			eecd = E1000_READ_REG(hw, E1000_EECD);
734a551c94aSIdo Barnea			if (eecd & E1000_EECD_DO)
735a551c94aSIdo Barnea				break;
736a551c94aSIdo Barnea			usec_delay(50);
737a551c94aSIdo Barnea		}
738a551c94aSIdo Barnea
739a551c94aSIdo Barnea		if (widx == 200) {
740a551c94aSIdo Barnea			DEBUGOUT("NVM Write did not complete\n");
741a551c94aSIdo Barnea			ret_val = -E1000_ERR_NVM;
742a551c94aSIdo Barnea			goto release;
743a551c94aSIdo Barnea		}
744a551c94aSIdo Barnea
745a551c94aSIdo Barnea		e1000_standby_nvm(hw);
746a551c94aSIdo Barnea
747a551c94aSIdo Barnea		words_written++;
748a551c94aSIdo Barnea	}
749a551c94aSIdo Barnea
750a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
751a551c94aSIdo Barnea				 (u16)(nvm->opcode_bits + 2));
752a551c94aSIdo Barnea
753a551c94aSIdo Barnea	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
754a551c94aSIdo Barnea
755a551c94aSIdo Barnearelease:
756a551c94aSIdo Barnea	nvm->ops.release(hw);
757a551c94aSIdo Barnea
758a551c94aSIdo Barnea	return ret_val;
759a551c94aSIdo Barnea}
760a551c94aSIdo Barnea
761a551c94aSIdo Barnea/**
762a551c94aSIdo Barnea *  e1000_read_pba_string_generic - Read device part number
763a551c94aSIdo Barnea *  @hw: pointer to the HW structure
764a551c94aSIdo Barnea *  @pba_num: pointer to device part number
765a551c94aSIdo Barnea *  @pba_num_size: size of part number buffer
766a551c94aSIdo Barnea *
767a551c94aSIdo Barnea *  Reads the product board assembly (PBA) number from the EEPROM and stores
768a551c94aSIdo Barnea *  the value in pba_num.
769a551c94aSIdo Barnea **/
770a551c94aSIdo Barneas32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
771a551c94aSIdo Barnea				  u32 pba_num_size)
772a551c94aSIdo Barnea{
773a551c94aSIdo Barnea	s32 ret_val;
774a551c94aSIdo Barnea	u16 nvm_data;
775a551c94aSIdo Barnea	u16 pba_ptr;
776a551c94aSIdo Barnea	u16 offset;
777a551c94aSIdo Barnea	u16 length;
778a551c94aSIdo Barnea
779a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_pba_string_generic");
780a551c94aSIdo Barnea
781a551c94aSIdo Barnea	if ((hw->mac.type >= e1000_i210) &&
782a551c94aSIdo Barnea	    !e1000_get_flash_presence_i210(hw)) {
783a551c94aSIdo Barnea		DEBUGOUT("Flashless no PBA string\n");
784a551c94aSIdo Barnea		return -E1000_ERR_NVM_PBA_SECTION;
785a551c94aSIdo Barnea	}
786a551c94aSIdo Barnea
787a551c94aSIdo Barnea	if (pba_num == NULL) {
788a551c94aSIdo Barnea		DEBUGOUT("PBA string buffer was null\n");
789a551c94aSIdo Barnea		return -E1000_ERR_INVALID_ARGUMENT;
790a551c94aSIdo Barnea	}
791a551c94aSIdo Barnea
792a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
793a551c94aSIdo Barnea	if (ret_val) {
794a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
795a551c94aSIdo Barnea		return ret_val;
796a551c94aSIdo Barnea	}
797a551c94aSIdo Barnea
798a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
799a551c94aSIdo Barnea	if (ret_val) {
800a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
801a551c94aSIdo Barnea		return ret_val;
802a551c94aSIdo Barnea	}
803a551c94aSIdo Barnea
804a551c94aSIdo Barnea	/* if nvm_data is not ptr guard the PBA must be in legacy format which
805a551c94aSIdo Barnea	 * means pba_ptr is actually our second data word for the PBA number
806a551c94aSIdo Barnea	 * and we can decode it into an ascii string
807a551c94aSIdo Barnea	 */
808a551c94aSIdo Barnea	if (nvm_data != NVM_PBA_PTR_GUARD) {
809a551c94aSIdo Barnea		DEBUGOUT("NVM PBA number is not stored as string\n");
810a551c94aSIdo Barnea
811a551c94aSIdo Barnea		/* make sure callers buffer is big enough to store the PBA */
812a551c94aSIdo Barnea		if (pba_num_size < E1000_PBANUM_LENGTH) {
813a551c94aSIdo Barnea			DEBUGOUT("PBA string buffer too small\n");
814a551c94aSIdo Barnea			return E1000_ERR_NO_SPACE;
815a551c94aSIdo Barnea		}
816a551c94aSIdo Barnea
817a551c94aSIdo Barnea		/* extract hex string from data and pba_ptr */
818a551c94aSIdo Barnea		pba_num[0] = (nvm_data >> 12) & 0xF;
819a551c94aSIdo Barnea		pba_num[1] = (nvm_data >> 8) & 0xF;
820a551c94aSIdo Barnea		pba_num[2] = (nvm_data >> 4) & 0xF;
821a551c94aSIdo Barnea		pba_num[3] = nvm_data & 0xF;
822a551c94aSIdo Barnea		pba_num[4] = (pba_ptr >> 12) & 0xF;
823a551c94aSIdo Barnea		pba_num[5] = (pba_ptr >> 8) & 0xF;
824a551c94aSIdo Barnea		pba_num[6] = '-';
825a551c94aSIdo Barnea		pba_num[7] = 0;
826a551c94aSIdo Barnea		pba_num[8] = (pba_ptr >> 4) & 0xF;
827a551c94aSIdo Barnea		pba_num[9] = pba_ptr & 0xF;
828a551c94aSIdo Barnea
829a551c94aSIdo Barnea		/* put a null character on the end of our string */
830a551c94aSIdo Barnea		pba_num[10] = '\0';
831a551c94aSIdo Barnea
832a551c94aSIdo Barnea		/* switch all the data but the '-' to hex char */
833a551c94aSIdo Barnea		for (offset = 0; offset < 10; offset++) {
834a551c94aSIdo Barnea			if (pba_num[offset] < 0xA)
835a551c94aSIdo Barnea				pba_num[offset] += '0';
836a551c94aSIdo Barnea			else if (pba_num[offset] < 0x10)
837a551c94aSIdo Barnea				pba_num[offset] += 'A' - 0xA;
838a551c94aSIdo Barnea		}
839a551c94aSIdo Barnea
840a551c94aSIdo Barnea		return E1000_SUCCESS;
841a551c94aSIdo Barnea	}
842a551c94aSIdo Barnea
843a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
844a551c94aSIdo Barnea	if (ret_val) {
845a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
846a551c94aSIdo Barnea		return ret_val;
847a551c94aSIdo Barnea	}
848a551c94aSIdo Barnea
849a551c94aSIdo Barnea	if (length == 0xFFFF || length == 0) {
850a551c94aSIdo Barnea		DEBUGOUT("NVM PBA number section invalid length\n");
851a551c94aSIdo Barnea		return -E1000_ERR_NVM_PBA_SECTION;
852a551c94aSIdo Barnea	}
853a551c94aSIdo Barnea	/* check if pba_num buffer is big enough */
854a551c94aSIdo Barnea	if (pba_num_size < (((u32)length * 2) - 1)) {
855a551c94aSIdo Barnea		DEBUGOUT("PBA string buffer too small\n");
856a551c94aSIdo Barnea		return -E1000_ERR_NO_SPACE;
857a551c94aSIdo Barnea	}
858a551c94aSIdo Barnea
859a551c94aSIdo Barnea	/* trim pba length from start of string */
860a551c94aSIdo Barnea	pba_ptr++;
861a551c94aSIdo Barnea	length--;
862a551c94aSIdo Barnea
863a551c94aSIdo Barnea	for (offset = 0; offset < length; offset++) {
864a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
865a551c94aSIdo Barnea		if (ret_val) {
866a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error\n");
867a551c94aSIdo Barnea			return ret_val;
868a551c94aSIdo Barnea		}
869a551c94aSIdo Barnea		pba_num[offset * 2] = (u8)(nvm_data >> 8);
870a551c94aSIdo Barnea		pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
871a551c94aSIdo Barnea	}
872a551c94aSIdo Barnea	pba_num[offset * 2] = '\0';
873a551c94aSIdo Barnea
874a551c94aSIdo Barnea	return E1000_SUCCESS;
875a551c94aSIdo Barnea}
876a551c94aSIdo Barnea
877a551c94aSIdo Barnea/**
878a551c94aSIdo Barnea *  e1000_read_pba_length_generic - Read device part number length
879a551c94aSIdo Barnea *  @hw: pointer to the HW structure
880a551c94aSIdo Barnea *  @pba_num_size: size of part number buffer
881a551c94aSIdo Barnea *
882a551c94aSIdo Barnea *  Reads the product board assembly (PBA) number length from the EEPROM and
883a551c94aSIdo Barnea *  stores the value in pba_num_size.
884a551c94aSIdo Barnea **/
885a551c94aSIdo Barneas32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
886a551c94aSIdo Barnea{
887a551c94aSIdo Barnea	s32 ret_val;
888a551c94aSIdo Barnea	u16 nvm_data;
889a551c94aSIdo Barnea	u16 pba_ptr;
890a551c94aSIdo Barnea	u16 length;
891a551c94aSIdo Barnea
892a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_pba_length_generic");
893a551c94aSIdo Barnea
894a551c94aSIdo Barnea	if (pba_num_size == NULL) {
895a551c94aSIdo Barnea		DEBUGOUT("PBA buffer size was null\n");
896a551c94aSIdo Barnea		return -E1000_ERR_INVALID_ARGUMENT;
897a551c94aSIdo Barnea	}
898a551c94aSIdo Barnea
899a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
900a551c94aSIdo Barnea	if (ret_val) {
901a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
902a551c94aSIdo Barnea		return ret_val;
903a551c94aSIdo Barnea	}
904a551c94aSIdo Barnea
905a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
906a551c94aSIdo Barnea	if (ret_val) {
907a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
908a551c94aSIdo Barnea		return ret_val;
909a551c94aSIdo Barnea	}
910a551c94aSIdo Barnea
911a551c94aSIdo Barnea	 /* if data is not ptr guard the PBA must be in legacy format */
912a551c94aSIdo Barnea	if (nvm_data != NVM_PBA_PTR_GUARD) {
913a551c94aSIdo Barnea		*pba_num_size = E1000_PBANUM_LENGTH;
914a551c94aSIdo Barnea		return E1000_SUCCESS;
915a551c94aSIdo Barnea	}
916a551c94aSIdo Barnea
917a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
918a551c94aSIdo Barnea	if (ret_val) {
919a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
920a551c94aSIdo Barnea		return ret_val;
921a551c94aSIdo Barnea	}
922a551c94aSIdo Barnea
923a551c94aSIdo Barnea	if (length == 0xFFFF || length == 0) {
924a551c94aSIdo Barnea		DEBUGOUT("NVM PBA number section invalid length\n");
925a551c94aSIdo Barnea		return -E1000_ERR_NVM_PBA_SECTION;
926a551c94aSIdo Barnea	}
927a551c94aSIdo Barnea
928a551c94aSIdo Barnea	/* Convert from length in u16 values to u8 chars, add 1 for NULL,
929a551c94aSIdo Barnea	 * and subtract 2 because length field is included in length.
930a551c94aSIdo Barnea	 */
931a551c94aSIdo Barnea	*pba_num_size = ((u32)length * 2) - 1;
932a551c94aSIdo Barnea
933a551c94aSIdo Barnea	return E1000_SUCCESS;
934a551c94aSIdo Barnea}
935a551c94aSIdo Barnea
936a551c94aSIdo Barnea/**
937a551c94aSIdo Barnea *  e1000_read_pba_num_generic - Read device part number
938a551c94aSIdo Barnea *  @hw: pointer to the HW structure
939a551c94aSIdo Barnea *  @pba_num: pointer to device part number
940a551c94aSIdo Barnea *
941a551c94aSIdo Barnea *  Reads the product board assembly (PBA) number from the EEPROM and stores
942a551c94aSIdo Barnea *  the value in pba_num.
943a551c94aSIdo Barnea **/
944a551c94aSIdo Barneas32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
945a551c94aSIdo Barnea{
946a551c94aSIdo Barnea	s32 ret_val;
947a551c94aSIdo Barnea	u16 nvm_data;
948a551c94aSIdo Barnea
949a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_pba_num_generic");
950a551c94aSIdo Barnea
951a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
952a551c94aSIdo Barnea	if (ret_val) {
953a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
954a551c94aSIdo Barnea		return ret_val;
955a551c94aSIdo Barnea	} else if (nvm_data == NVM_PBA_PTR_GUARD) {
956a551c94aSIdo Barnea		DEBUGOUT("NVM Not Supported\n");
957a551c94aSIdo Barnea		return -E1000_NOT_IMPLEMENTED;
958a551c94aSIdo Barnea	}
959a551c94aSIdo Barnea	*pba_num = (u32)(nvm_data << 16);
960a551c94aSIdo Barnea
961a551c94aSIdo Barnea	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
962a551c94aSIdo Barnea	if (ret_val) {
963a551c94aSIdo Barnea		DEBUGOUT("NVM Read Error\n");
964a551c94aSIdo Barnea		return ret_val;
965a551c94aSIdo Barnea	}
966a551c94aSIdo Barnea	*pba_num |= nvm_data;
967a551c94aSIdo Barnea
968a551c94aSIdo Barnea	return E1000_SUCCESS;
969a551c94aSIdo Barnea}
970a551c94aSIdo Barnea
971a551c94aSIdo Barnea
972a551c94aSIdo Barnea/**
973a551c94aSIdo Barnea *  e1000_read_pba_raw
974a551c94aSIdo Barnea *  @hw: pointer to the HW structure
975a551c94aSIdo Barnea *  @eeprom_buf: optional pointer to EEPROM image
976a551c94aSIdo Barnea *  @eeprom_buf_size: size of EEPROM image in words
977a551c94aSIdo Barnea *  @max_pba_block_size: PBA block size limit
978a551c94aSIdo Barnea *  @pba: pointer to output PBA structure
979a551c94aSIdo Barnea *
980a551c94aSIdo Barnea *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
981a551c94aSIdo Barnea *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
982a551c94aSIdo Barnea *
983a551c94aSIdo Barnea **/
984a551c94aSIdo Barneas32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
985a551c94aSIdo Barnea		       u32 eeprom_buf_size, u16 max_pba_block_size,
986a551c94aSIdo Barnea		       struct e1000_pba *pba)
987a551c94aSIdo Barnea{
988a551c94aSIdo Barnea	s32 ret_val;
989a551c94aSIdo Barnea	u16 pba_block_size;
990a551c94aSIdo Barnea
991a551c94aSIdo Barnea	if (pba == NULL)
992a551c94aSIdo Barnea		return -E1000_ERR_PARAM;
993a551c94aSIdo Barnea
994a551c94aSIdo Barnea	if (eeprom_buf == NULL) {
995a551c94aSIdo Barnea		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
996a551c94aSIdo Barnea					 &pba->word[0]);
997a551c94aSIdo Barnea		if (ret_val)
998a551c94aSIdo Barnea			return ret_val;
999a551c94aSIdo Barnea	} else {
1000a551c94aSIdo Barnea		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1001a551c94aSIdo Barnea			pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1002a551c94aSIdo Barnea			pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1003a551c94aSIdo Barnea		} else {
1004a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1005a551c94aSIdo Barnea		}
1006a551c94aSIdo Barnea	}
1007a551c94aSIdo Barnea
1008a551c94aSIdo Barnea	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1009a551c94aSIdo Barnea		if (pba->pba_block == NULL)
1010a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1011a551c94aSIdo Barnea
1012a551c94aSIdo Barnea		ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1013a551c94aSIdo Barnea						   eeprom_buf_size,
1014a551c94aSIdo Barnea						   &pba_block_size);
1015a551c94aSIdo Barnea		if (ret_val)
1016a551c94aSIdo Barnea			return ret_val;
1017a551c94aSIdo Barnea
1018a551c94aSIdo Barnea		if (pba_block_size > max_pba_block_size)
1019a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1020a551c94aSIdo Barnea
1021a551c94aSIdo Barnea		if (eeprom_buf == NULL) {
1022a551c94aSIdo Barnea			ret_val = e1000_read_nvm(hw, pba->word[1],
1023a551c94aSIdo Barnea						 pba_block_size,
1024a551c94aSIdo Barnea						 pba->pba_block);
1025a551c94aSIdo Barnea			if (ret_val)
1026a551c94aSIdo Barnea				return ret_val;
1027a551c94aSIdo Barnea		} else {
1028a551c94aSIdo Barnea			if (eeprom_buf_size > (u32)(pba->word[1] +
1029a551c94aSIdo Barnea					      pba_block_size)) {
1030a551c94aSIdo Barnea				memcpy(pba->pba_block,
1031a551c94aSIdo Barnea				       &eeprom_buf[pba->word[1]],
1032a551c94aSIdo Barnea				       pba_block_size * sizeof(u16));
1033a551c94aSIdo Barnea			} else {
1034a551c94aSIdo Barnea				return -E1000_ERR_PARAM;
1035a551c94aSIdo Barnea			}
1036a551c94aSIdo Barnea		}
1037a551c94aSIdo Barnea	}
1038a551c94aSIdo Barnea
1039a551c94aSIdo Barnea	return E1000_SUCCESS;
1040a551c94aSIdo Barnea}
1041a551c94aSIdo Barnea
1042a551c94aSIdo Barnea/**
1043a551c94aSIdo Barnea *  e1000_write_pba_raw
1044a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1045a551c94aSIdo Barnea *  @eeprom_buf: optional pointer to EEPROM image
1046a551c94aSIdo Barnea *  @eeprom_buf_size: size of EEPROM image in words
1047a551c94aSIdo Barnea *  @pba: pointer to PBA structure
1048a551c94aSIdo Barnea *
1049a551c94aSIdo Barnea *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1050a551c94aSIdo Barnea *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1051a551c94aSIdo Barnea *
1052a551c94aSIdo Barnea **/
1053a551c94aSIdo Barneas32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1054a551c94aSIdo Barnea			u32 eeprom_buf_size, struct e1000_pba *pba)
1055a551c94aSIdo Barnea{
1056a551c94aSIdo Barnea	s32 ret_val;
1057a551c94aSIdo Barnea
1058a551c94aSIdo Barnea	if (pba == NULL)
1059a551c94aSIdo Barnea		return -E1000_ERR_PARAM;
1060a551c94aSIdo Barnea
1061a551c94aSIdo Barnea	if (eeprom_buf == NULL) {
1062a551c94aSIdo Barnea		ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1063a551c94aSIdo Barnea					  &pba->word[0]);
1064a551c94aSIdo Barnea		if (ret_val)
1065a551c94aSIdo Barnea			return ret_val;
1066a551c94aSIdo Barnea	} else {
1067a551c94aSIdo Barnea		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1068a551c94aSIdo Barnea			eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1069a551c94aSIdo Barnea			eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1070a551c94aSIdo Barnea		} else {
1071a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1072a551c94aSIdo Barnea		}
1073a551c94aSIdo Barnea	}
1074a551c94aSIdo Barnea
1075a551c94aSIdo Barnea	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1076a551c94aSIdo Barnea		if (pba->pba_block == NULL)
1077a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1078a551c94aSIdo Barnea
1079a551c94aSIdo Barnea		if (eeprom_buf == NULL) {
1080a551c94aSIdo Barnea			ret_val = e1000_write_nvm(hw, pba->word[1],
1081a551c94aSIdo Barnea						  pba->pba_block[0],
1082a551c94aSIdo Barnea						  pba->pba_block);
1083a551c94aSIdo Barnea			if (ret_val)
1084a551c94aSIdo Barnea				return ret_val;
1085a551c94aSIdo Barnea		} else {
1086a551c94aSIdo Barnea			if (eeprom_buf_size > (u32)(pba->word[1] +
1087a551c94aSIdo Barnea					      pba->pba_block[0])) {
1088a551c94aSIdo Barnea				memcpy(&eeprom_buf[pba->word[1]],
1089a551c94aSIdo Barnea				       pba->pba_block,
1090a551c94aSIdo Barnea				       pba->pba_block[0] * sizeof(u16));
1091a551c94aSIdo Barnea			} else {
1092a551c94aSIdo Barnea				return -E1000_ERR_PARAM;
1093a551c94aSIdo Barnea			}
1094a551c94aSIdo Barnea		}
1095a551c94aSIdo Barnea	}
1096a551c94aSIdo Barnea
1097a551c94aSIdo Barnea	return E1000_SUCCESS;
1098a551c94aSIdo Barnea}
1099a551c94aSIdo Barnea
1100a551c94aSIdo Barnea/**
1101a551c94aSIdo Barnea *  e1000_get_pba_block_size
1102a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1103a551c94aSIdo Barnea *  @eeprom_buf: optional pointer to EEPROM image
1104a551c94aSIdo Barnea *  @eeprom_buf_size: size of EEPROM image in words
1105a551c94aSIdo Barnea *  @pba_data_size: pointer to output variable
1106a551c94aSIdo Barnea *
1107a551c94aSIdo Barnea *  Returns the size of the PBA block in words. Function operates on EEPROM
1108a551c94aSIdo Barnea *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1109a551c94aSIdo Barnea *  EEPROM device.
1110a551c94aSIdo Barnea *
1111a551c94aSIdo Barnea **/
1112a551c94aSIdo Barneas32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1113a551c94aSIdo Barnea			     u32 eeprom_buf_size, u16 *pba_block_size)
1114a551c94aSIdo Barnea{
1115a551c94aSIdo Barnea	s32 ret_val;
1116a551c94aSIdo Barnea	u16 pba_word[2];
1117a551c94aSIdo Barnea	u16 length;
1118a551c94aSIdo Barnea
1119a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_pba_block_size");
1120a551c94aSIdo Barnea
1121a551c94aSIdo Barnea	if (eeprom_buf == NULL) {
1122a551c94aSIdo Barnea		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1123a551c94aSIdo Barnea		if (ret_val)
1124a551c94aSIdo Barnea			return ret_val;
1125a551c94aSIdo Barnea	} else {
1126a551c94aSIdo Barnea		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1127a551c94aSIdo Barnea			pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1128a551c94aSIdo Barnea			pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1129a551c94aSIdo Barnea		} else {
1130a551c94aSIdo Barnea			return -E1000_ERR_PARAM;
1131a551c94aSIdo Barnea		}
1132a551c94aSIdo Barnea	}
1133a551c94aSIdo Barnea
1134a551c94aSIdo Barnea	if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1135a551c94aSIdo Barnea		if (eeprom_buf == NULL) {
1136a551c94aSIdo Barnea			ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1137a551c94aSIdo Barnea						 &length);
1138a551c94aSIdo Barnea			if (ret_val)
1139a551c94aSIdo Barnea				return ret_val;
1140a551c94aSIdo Barnea		} else {
1141a551c94aSIdo Barnea			if (eeprom_buf_size > pba_word[1])
1142a551c94aSIdo Barnea				length = eeprom_buf[pba_word[1] + 0];
1143a551c94aSIdo Barnea			else
1144a551c94aSIdo Barnea				return -E1000_ERR_PARAM;
1145a551c94aSIdo Barnea		}
1146a551c94aSIdo Barnea
1147a551c94aSIdo Barnea		if (length == 0xFFFF || length == 0)
1148a551c94aSIdo Barnea			return -E1000_ERR_NVM_PBA_SECTION;
1149a551c94aSIdo Barnea	} else {
1150a551c94aSIdo Barnea		/* PBA number in legacy format, there is no PBA Block. */
1151a551c94aSIdo Barnea		length = 0;
1152a551c94aSIdo Barnea	}
1153a551c94aSIdo Barnea
1154a551c94aSIdo Barnea	if (pba_block_size != NULL)
1155a551c94aSIdo Barnea		*pba_block_size = length;
1156a551c94aSIdo Barnea
1157a551c94aSIdo Barnea	return E1000_SUCCESS;
1158a551c94aSIdo Barnea}
1159a551c94aSIdo Barnea
1160a551c94aSIdo Barnea/**
1161a551c94aSIdo Barnea *  e1000_read_mac_addr_generic - Read device MAC address
1162a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1163a551c94aSIdo Barnea *
1164a551c94aSIdo Barnea *  Reads the device MAC address from the EEPROM and stores the value.
1165a551c94aSIdo Barnea *  Since devices with two ports use the same EEPROM, we increment the
1166a551c94aSIdo Barnea *  last bit in the MAC address for the second port.
1167a551c94aSIdo Barnea **/
1168a551c94aSIdo Barneas32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1169a551c94aSIdo Barnea{
1170a551c94aSIdo Barnea	u32 rar_high;
1171a551c94aSIdo Barnea	u32 rar_low;
1172a551c94aSIdo Barnea	u16 i;
1173a551c94aSIdo Barnea
1174a551c94aSIdo Barnea	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1175a551c94aSIdo Barnea	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1176a551c94aSIdo Barnea
1177a551c94aSIdo Barnea	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1178a551c94aSIdo Barnea		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1179a551c94aSIdo Barnea
1180a551c94aSIdo Barnea	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1181a551c94aSIdo Barnea		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1182a551c94aSIdo Barnea
1183a551c94aSIdo Barnea	for (i = 0; i < ETH_ADDR_LEN; i++)
1184a551c94aSIdo Barnea		hw->mac.addr[i] = hw->mac.perm_addr[i];
1185a551c94aSIdo Barnea
1186a551c94aSIdo Barnea	return E1000_SUCCESS;
1187a551c94aSIdo Barnea}
1188a551c94aSIdo Barnea
1189a551c94aSIdo Barnea/**
1190a551c94aSIdo Barnea *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1191a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1192a551c94aSIdo Barnea *
1193a551c94aSIdo Barnea *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1194a551c94aSIdo Barnea *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1195a551c94aSIdo Barnea **/
1196a551c94aSIdo Barneas32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1197a551c94aSIdo Barnea{
1198a551c94aSIdo Barnea	s32 ret_val;
1199a551c94aSIdo Barnea	u16 checksum = 0;
1200a551c94aSIdo Barnea	u16 i, nvm_data;
1201a551c94aSIdo Barnea
1202a551c94aSIdo Barnea	DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1203a551c94aSIdo Barnea
1204a551c94aSIdo Barnea	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1205a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1206a551c94aSIdo Barnea		if (ret_val) {
1207a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error\n");
1208a551c94aSIdo Barnea			return ret_val;
1209a551c94aSIdo Barnea		}
1210a551c94aSIdo Barnea		checksum += nvm_data;
1211a551c94aSIdo Barnea	}
1212a551c94aSIdo Barnea
1213a551c94aSIdo Barnea	if (checksum != (u16) NVM_SUM) {
1214a551c94aSIdo Barnea		DEBUGOUT("NVM Checksum Invalid\n");
1215a551c94aSIdo Barnea		return -E1000_ERR_NVM;
1216a551c94aSIdo Barnea	}
1217a551c94aSIdo Barnea
1218a551c94aSIdo Barnea	return E1000_SUCCESS;
1219a551c94aSIdo Barnea}
1220a551c94aSIdo Barnea
1221a551c94aSIdo Barnea/**
1222a551c94aSIdo Barnea *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1223a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1224a551c94aSIdo Barnea *
1225a551c94aSIdo Barnea *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1226a551c94aSIdo Barnea *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1227a551c94aSIdo Barnea *  value to the EEPROM.
1228a551c94aSIdo Barnea **/
1229a551c94aSIdo Barneas32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1230a551c94aSIdo Barnea{
1231a551c94aSIdo Barnea	s32 ret_val;
1232a551c94aSIdo Barnea	u16 checksum = 0;
1233a551c94aSIdo Barnea	u16 i, nvm_data;
1234a551c94aSIdo Barnea
1235a551c94aSIdo Barnea	DEBUGFUNC("e1000_update_nvm_checksum");
1236a551c94aSIdo Barnea
1237a551c94aSIdo Barnea	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1238a551c94aSIdo Barnea		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1239a551c94aSIdo Barnea		if (ret_val) {
1240a551c94aSIdo Barnea			DEBUGOUT("NVM Read Error while updating checksum.\n");
1241a551c94aSIdo Barnea			return ret_val;
1242a551c94aSIdo Barnea		}
1243a551c94aSIdo Barnea		checksum += nvm_data;
1244a551c94aSIdo Barnea	}
1245a551c94aSIdo Barnea	checksum = (u16) NVM_SUM - checksum;
1246a551c94aSIdo Barnea	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1247a551c94aSIdo Barnea	if (ret_val)
1248a551c94aSIdo Barnea		DEBUGOUT("NVM Write Error while updating checksum.\n");
1249a551c94aSIdo Barnea
1250a551c94aSIdo Barnea	return ret_val;
1251a551c94aSIdo Barnea}
1252a551c94aSIdo Barnea
1253a551c94aSIdo Barnea/**
1254a551c94aSIdo Barnea *  e1000_reload_nvm_generic - Reloads EEPROM
1255a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1256a551c94aSIdo Barnea *
1257a551c94aSIdo Barnea *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1258a551c94aSIdo Barnea *  extended control register.
1259a551c94aSIdo Barnea **/
1260a551c94aSIdo BarneaSTATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1261a551c94aSIdo Barnea{
1262a551c94aSIdo Barnea	u32 ctrl_ext;
1263a551c94aSIdo Barnea
1264a551c94aSIdo Barnea	DEBUGFUNC("e1000_reload_nvm_generic");
1265a551c94aSIdo Barnea
1266a551c94aSIdo Barnea	usec_delay(10);
1267a551c94aSIdo Barnea	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268a551c94aSIdo Barnea	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1269a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1270a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
1271a551c94aSIdo Barnea}
1272a551c94aSIdo Barnea
1273a551c94aSIdo Barnea/**
1274a551c94aSIdo Barnea *  e1000_get_fw_version - Get firmware version information
1275a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1276a551c94aSIdo Barnea *  @fw_vers: pointer to output version structure
1277a551c94aSIdo Barnea *
1278a551c94aSIdo Barnea *  unsupported/not present features return 0 in version structure
1279a551c94aSIdo Barnea **/
1280a551c94aSIdo Barneavoid e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1281a551c94aSIdo Barnea{
1282a551c94aSIdo Barnea	u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1283a551c94aSIdo Barnea	u8 q, hval, rem, result;
1284a551c94aSIdo Barnea	u16 comb_verh, comb_verl, comb_offset;
1285a551c94aSIdo Barnea
1286a551c94aSIdo Barnea	memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1287a551c94aSIdo Barnea
1288a551c94aSIdo Barnea	/* basic eeprom version numbers, bits used vary by part and by tool
1289a551c94aSIdo Barnea	 * used to create the nvm images */
1290a551c94aSIdo Barnea	/* Check which data format we have */
1291a551c94aSIdo Barnea	switch (hw->mac.type) {
1292a551c94aSIdo Barnea	case e1000_i211:
1293a551c94aSIdo Barnea		e1000_read_invm_version(hw, fw_vers);
1294a551c94aSIdo Barnea		return;
1295a551c94aSIdo Barnea	case e1000_82575:
1296a551c94aSIdo Barnea	case e1000_82576:
1297a551c94aSIdo Barnea	case e1000_82580:
12989ca4a157SIdo Barnea	case e1000_i354:
1299a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1300a551c94aSIdo Barnea		/* Use this format, unless EETRACK ID exists,
1301a551c94aSIdo Barnea		 * then use alternate format
1302a551c94aSIdo Barnea		 */
1303a551c94aSIdo Barnea		if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1304a551c94aSIdo Barnea			hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1305a551c94aSIdo Barnea			fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1306a551c94aSIdo Barnea					      >> NVM_MAJOR_SHIFT;
1307a551c94aSIdo Barnea			fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1308a551c94aSIdo Barnea					      >> NVM_MINOR_SHIFT;
1309a551c94aSIdo Barnea			fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1310a551c94aSIdo Barnea			goto etrack_id;
1311a551c94aSIdo Barnea		}
1312a551c94aSIdo Barnea		break;
1313a551c94aSIdo Barnea	case e1000_i210:
1314a551c94aSIdo Barnea		if (!(e1000_get_flash_presence_i210(hw))) {
1315a551c94aSIdo Barnea			e1000_read_invm_version(hw, fw_vers);
1316a551c94aSIdo Barnea			return;
1317a551c94aSIdo Barnea		}
1318a551c94aSIdo Barnea		/* fall through */
1319a551c94aSIdo Barnea	case e1000_i350:
1320a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1321a551c94aSIdo Barnea		/* find combo image version */
1322a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1323a551c94aSIdo Barnea		if ((comb_offset != 0x0) &&
1324a551c94aSIdo Barnea		    (comb_offset != NVM_VER_INVALID)) {
1325a551c94aSIdo Barnea
1326a551c94aSIdo Barnea			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1327a551c94aSIdo Barnea					 + 1), 1, &comb_verh);
1328a551c94aSIdo Barnea			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1329a551c94aSIdo Barnea					 1, &comb_verl);
1330a551c94aSIdo Barnea
1331a551c94aSIdo Barnea			/* get Option Rom version if it exists and is valid */
1332a551c94aSIdo Barnea			if ((comb_verh && comb_verl) &&
1333a551c94aSIdo Barnea			    ((comb_verh != NVM_VER_INVALID) &&
1334a551c94aSIdo Barnea			     (comb_verl != NVM_VER_INVALID))) {
1335a551c94aSIdo Barnea
1336a551c94aSIdo Barnea				fw_vers->or_valid = true;
1337a551c94aSIdo Barnea				fw_vers->or_major =
1338a551c94aSIdo Barnea					comb_verl >> NVM_COMB_VER_SHFT;
1339a551c94aSIdo Barnea				fw_vers->or_build =
1340a551c94aSIdo Barnea					(comb_verl << NVM_COMB_VER_SHFT)
1341a551c94aSIdo Barnea					| (comb_verh >> NVM_COMB_VER_SHFT);
1342a551c94aSIdo Barnea				fw_vers->or_patch =
1343a551c94aSIdo Barnea					comb_verh & NVM_COMB_VER_MASK;
1344a551c94aSIdo Barnea			}
1345a551c94aSIdo Barnea		}
1346a551c94aSIdo Barnea		break;
1347a551c94aSIdo Barnea	default:
1348a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1349a551c94aSIdo Barnea		return;
1350a551c94aSIdo Barnea	}
1351a551c94aSIdo Barnea	hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1352a551c94aSIdo Barnea	fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1353a551c94aSIdo Barnea			      >> NVM_MAJOR_SHIFT;
1354a551c94aSIdo Barnea
1355a551c94aSIdo Barnea	/* check for old style version format in newer images*/
1356a551c94aSIdo Barnea	if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1357a551c94aSIdo Barnea		eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1358a551c94aSIdo Barnea	} else {
1359a551c94aSIdo Barnea		eeprom_verl = (fw_version & NVM_MINOR_MASK)
1360a551c94aSIdo Barnea				>> NVM_MINOR_SHIFT;
1361a551c94aSIdo Barnea	}
1362a551c94aSIdo Barnea	/* Convert minor value to hex before assigning to output struct
1363a551c94aSIdo Barnea	 * Val to be converted will not be higher than 99, per tool output
1364a551c94aSIdo Barnea	 */
1365a551c94aSIdo Barnea	q = eeprom_verl / NVM_HEX_CONV;
1366a551c94aSIdo Barnea	hval = q * NVM_HEX_TENS;
1367a551c94aSIdo Barnea	rem = eeprom_verl % NVM_HEX_CONV;
1368a551c94aSIdo Barnea	result = hval + rem;
1369a551c94aSIdo Barnea	fw_vers->eep_minor = result;
1370a551c94aSIdo Barnea
1371a551c94aSIdo Barneaetrack_id:
1372a551c94aSIdo Barnea	if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1373a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1374a551c94aSIdo Barnea		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1375a551c94aSIdo Barnea		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1376a551c94aSIdo Barnea			| eeprom_verl;
1377a551c94aSIdo Barnea	} else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1378a551c94aSIdo Barnea		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1379a551c94aSIdo Barnea		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1380a551c94aSIdo Barnea		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
1381a551c94aSIdo Barnea				     eeprom_verl;
1382a551c94aSIdo Barnea	}
1383a551c94aSIdo Barnea}
1384a551c94aSIdo Barnea
1385a551c94aSIdo Barnea
1386