1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo BarneaCopyright (c) 2001-2015, Intel Corporation
4a551c94aSIdo BarneaAll rights reserved.
5a551c94aSIdo Barnea
6a551c94aSIdo BarneaRedistribution and use in source and binary forms, with or without
7a551c94aSIdo Barneamodification, are permitted provided that the following conditions are met:
8a551c94aSIdo Barnea
9a551c94aSIdo Barnea 1. Redistributions of source code must retain the above copyright notice,
10a551c94aSIdo Barnea    this list of conditions and the following disclaimer.
11a551c94aSIdo Barnea
12a551c94aSIdo Barnea 2. Redistributions in binary form must reproduce the above copyright
13a551c94aSIdo Barnea    notice, this list of conditions and the following disclaimer in the
14a551c94aSIdo Barnea    documentation and/or other materials provided with the distribution.
15a551c94aSIdo Barnea
16a551c94aSIdo Barnea 3. Neither the name of the Intel Corporation nor the names of its
17a551c94aSIdo Barnea    contributors may be used to endorse or promote products derived from
18a551c94aSIdo Barnea    this software without specific prior written permission.
19a551c94aSIdo Barnea
20a551c94aSIdo BarneaTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21a551c94aSIdo BarneaAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a551c94aSIdo BarneaIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a551c94aSIdo BarneaARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24a551c94aSIdo BarneaLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a551c94aSIdo BarneaCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a551c94aSIdo BarneaSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a551c94aSIdo BarneaINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a551c94aSIdo BarneaCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a551c94aSIdo BarneaARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30a551c94aSIdo BarneaPOSSIBILITY OF SUCH DAMAGE.
31a551c94aSIdo Barnea
32a551c94aSIdo Barnea***************************************************************************/
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#include "e1000_api.h"
35a551c94aSIdo Barnea
36a551c94aSIdo BarneaSTATIC s32 e1000_wait_autoneg(struct e1000_hw *hw);
37a551c94aSIdo BarneaSTATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
38a551c94aSIdo Barnea					  u16 *data, bool read, bool page_set);
39a551c94aSIdo BarneaSTATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
40a551c94aSIdo BarneaSTATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
41a551c94aSIdo Barnea					  u16 *data, bool read);
42a551c94aSIdo Barnea
43a551c94aSIdo Barnea/* Cable length tables */
44a551c94aSIdo BarneaSTATIC const u16 e1000_m88_cable_length_table[] = {
45a551c94aSIdo Barnea	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46a551c94aSIdo Barnea#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47a551c94aSIdo Barnea		(sizeof(e1000_m88_cable_length_table) / \
48a551c94aSIdo Barnea		 sizeof(e1000_m88_cable_length_table[0]))
49a551c94aSIdo Barnea
50a551c94aSIdo BarneaSTATIC const u16 e1000_igp_2_cable_length_table[] = {
51a551c94aSIdo Barnea	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52a551c94aSIdo Barnea	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53a551c94aSIdo Barnea	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54a551c94aSIdo Barnea	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55a551c94aSIdo Barnea	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56a551c94aSIdo Barnea	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57a551c94aSIdo Barnea	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58a551c94aSIdo Barnea	124};
59a551c94aSIdo Barnea#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60a551c94aSIdo Barnea		(sizeof(e1000_igp_2_cable_length_table) / \
61a551c94aSIdo Barnea		 sizeof(e1000_igp_2_cable_length_table[0]))
62a551c94aSIdo Barnea
63a551c94aSIdo Barnea/**
64a551c94aSIdo Barnea *  e1000_init_phy_ops_generic - Initialize PHY function pointers
65a551c94aSIdo Barnea *  @hw: pointer to the HW structure
66a551c94aSIdo Barnea *
67a551c94aSIdo Barnea *  Setups up the function pointers to no-op functions
68a551c94aSIdo Barnea **/
69a551c94aSIdo Barneavoid e1000_init_phy_ops_generic(struct e1000_hw *hw)
70a551c94aSIdo Barnea{
71a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
72a551c94aSIdo Barnea	DEBUGFUNC("e1000_init_phy_ops_generic");
73a551c94aSIdo Barnea
74a551c94aSIdo Barnea	/* Initialize function pointers */
75a551c94aSIdo Barnea	phy->ops.init_params = e1000_null_ops_generic;
76a551c94aSIdo Barnea	phy->ops.acquire = e1000_null_ops_generic;
77a551c94aSIdo Barnea	phy->ops.check_polarity = e1000_null_ops_generic;
78a551c94aSIdo Barnea	phy->ops.check_reset_block = e1000_null_ops_generic;
79a551c94aSIdo Barnea	phy->ops.commit = e1000_null_ops_generic;
80a551c94aSIdo Barnea	phy->ops.force_speed_duplex = e1000_null_ops_generic;
81a551c94aSIdo Barnea	phy->ops.get_cfg_done = e1000_null_ops_generic;
82a551c94aSIdo Barnea	phy->ops.get_cable_length = e1000_null_ops_generic;
83a551c94aSIdo Barnea	phy->ops.get_info = e1000_null_ops_generic;
84a551c94aSIdo Barnea	phy->ops.set_page = e1000_null_set_page;
85a551c94aSIdo Barnea	phy->ops.read_reg = e1000_null_read_reg;
86a551c94aSIdo Barnea	phy->ops.read_reg_locked = e1000_null_read_reg;
87a551c94aSIdo Barnea	phy->ops.read_reg_page = e1000_null_read_reg;
88a551c94aSIdo Barnea	phy->ops.release = e1000_null_phy_generic;
89a551c94aSIdo Barnea	phy->ops.reset = e1000_null_ops_generic;
90a551c94aSIdo Barnea	phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
91a551c94aSIdo Barnea	phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
92a551c94aSIdo Barnea	phy->ops.write_reg = e1000_null_write_reg;
93a551c94aSIdo Barnea	phy->ops.write_reg_locked = e1000_null_write_reg;
94a551c94aSIdo Barnea	phy->ops.write_reg_page = e1000_null_write_reg;
95a551c94aSIdo Barnea	phy->ops.power_up = e1000_null_phy_generic;
96a551c94aSIdo Barnea	phy->ops.power_down = e1000_null_phy_generic;
97a551c94aSIdo Barnea	phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
98a551c94aSIdo Barnea	phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
99a551c94aSIdo Barnea	phy->ops.cfg_on_link_up = e1000_null_ops_generic;
100a551c94aSIdo Barnea}
101a551c94aSIdo Barnea
102a551c94aSIdo Barnea/**
103a551c94aSIdo Barnea *  e1000_null_set_page - No-op function, return 0
104a551c94aSIdo Barnea *  @hw: pointer to the HW structure
105a551c94aSIdo Barnea **/
106a551c94aSIdo Barneas32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
107a551c94aSIdo Barnea			u16 E1000_UNUSEDARG data)
108a551c94aSIdo Barnea{
109a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_set_page");
110a551c94aSIdo Barnea	UNREFERENCED_2PARAMETER(hw, data);
111a551c94aSIdo Barnea	return E1000_SUCCESS;
112a551c94aSIdo Barnea}
113a551c94aSIdo Barnea
114a551c94aSIdo Barnea/**
115a551c94aSIdo Barnea *  e1000_null_read_reg - No-op function, return 0
116a551c94aSIdo Barnea *  @hw: pointer to the HW structure
117a551c94aSIdo Barnea **/
118a551c94aSIdo Barneas32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
119a551c94aSIdo Barnea			u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
120a551c94aSIdo Barnea{
121a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_read_reg");
122a551c94aSIdo Barnea	UNREFERENCED_3PARAMETER(hw, offset, data);
123a551c94aSIdo Barnea	return E1000_SUCCESS;
124a551c94aSIdo Barnea}
125a551c94aSIdo Barnea
126a551c94aSIdo Barnea/**
127a551c94aSIdo Barnea *  e1000_null_phy_generic - No-op function, return void
128a551c94aSIdo Barnea *  @hw: pointer to the HW structure
129a551c94aSIdo Barnea **/
130a551c94aSIdo Barneavoid e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
131a551c94aSIdo Barnea{
132a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_phy_generic");
133a551c94aSIdo Barnea	UNREFERENCED_1PARAMETER(hw);
134a551c94aSIdo Barnea	return;
135a551c94aSIdo Barnea}
136a551c94aSIdo Barnea
137a551c94aSIdo Barnea/**
138a551c94aSIdo Barnea *  e1000_null_lplu_state - No-op function, return 0
139a551c94aSIdo Barnea *  @hw: pointer to the HW structure
140a551c94aSIdo Barnea **/
141a551c94aSIdo Barneas32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
142a551c94aSIdo Barnea			  bool E1000_UNUSEDARG active)
143a551c94aSIdo Barnea{
144a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_lplu_state");
145a551c94aSIdo Barnea	UNREFERENCED_2PARAMETER(hw, active);
146a551c94aSIdo Barnea	return E1000_SUCCESS;
147a551c94aSIdo Barnea}
148a551c94aSIdo Barnea
149a551c94aSIdo Barnea/**
150a551c94aSIdo Barnea *  e1000_null_write_reg - No-op function, return 0
151a551c94aSIdo Barnea *  @hw: pointer to the HW structure
152a551c94aSIdo Barnea **/
153a551c94aSIdo Barneas32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
154a551c94aSIdo Barnea			 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
155a551c94aSIdo Barnea{
156a551c94aSIdo Barnea	DEBUGFUNC("e1000_null_write_reg");
157a551c94aSIdo Barnea	UNREFERENCED_3PARAMETER(hw, offset, data);
158a551c94aSIdo Barnea	return E1000_SUCCESS;
159a551c94aSIdo Barnea}
160a551c94aSIdo Barnea
161a551c94aSIdo Barnea/**
162a551c94aSIdo Barnea *  e1000_read_i2c_byte_null - No-op function, return 0
163a551c94aSIdo Barnea *  @hw: pointer to hardware structure
164a551c94aSIdo Barnea *  @byte_offset: byte offset to write
165a551c94aSIdo Barnea *  @dev_addr: device address
166a551c94aSIdo Barnea *  @data: data value read
167a551c94aSIdo Barnea *
168a551c94aSIdo Barnea **/
169a551c94aSIdo Barneas32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
170a551c94aSIdo Barnea			     u8 E1000_UNUSEDARG byte_offset,
171a551c94aSIdo Barnea			     u8 E1000_UNUSEDARG dev_addr,
172a551c94aSIdo Barnea			     u8 E1000_UNUSEDARG *data)
173a551c94aSIdo Barnea{
174a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_i2c_byte_null");
175a551c94aSIdo Barnea	UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
176a551c94aSIdo Barnea	return E1000_SUCCESS;
177a551c94aSIdo Barnea}
178a551c94aSIdo Barnea
179a551c94aSIdo Barnea/**
180a551c94aSIdo Barnea *  e1000_write_i2c_byte_null - No-op function, return 0
181a551c94aSIdo Barnea *  @hw: pointer to hardware structure
182a551c94aSIdo Barnea *  @byte_offset: byte offset to write
183a551c94aSIdo Barnea *  @dev_addr: device address
184a551c94aSIdo Barnea *  @data: data value to write
185a551c94aSIdo Barnea *
186a551c94aSIdo Barnea **/
187a551c94aSIdo Barneas32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
188a551c94aSIdo Barnea			      u8 E1000_UNUSEDARG byte_offset,
189a551c94aSIdo Barnea			      u8 E1000_UNUSEDARG dev_addr,
190a551c94aSIdo Barnea			      u8 E1000_UNUSEDARG data)
191a551c94aSIdo Barnea{
192a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_i2c_byte_null");
193a551c94aSIdo Barnea	UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
194a551c94aSIdo Barnea	return E1000_SUCCESS;
195a551c94aSIdo Barnea}
196a551c94aSIdo Barnea
197a551c94aSIdo Barnea/**
198a551c94aSIdo Barnea *  e1000_check_reset_block_generic - Check if PHY reset is blocked
199a551c94aSIdo Barnea *  @hw: pointer to the HW structure
200a551c94aSIdo Barnea *
201a551c94aSIdo Barnea *  Read the PHY management control register and check whether a PHY reset
202a551c94aSIdo Barnea *  is blocked.  If a reset is not blocked return E1000_SUCCESS, otherwise
203a551c94aSIdo Barnea *  return E1000_BLK_PHY_RESET (12).
204a551c94aSIdo Barnea **/
205a551c94aSIdo Barneas32 e1000_check_reset_block_generic(struct e1000_hw *hw)
206a551c94aSIdo Barnea{
207a551c94aSIdo Barnea	u32 manc;
208a551c94aSIdo Barnea
209a551c94aSIdo Barnea	DEBUGFUNC("e1000_check_reset_block");
210a551c94aSIdo Barnea
211a551c94aSIdo Barnea	manc = E1000_READ_REG(hw, E1000_MANC);
212a551c94aSIdo Barnea
213a551c94aSIdo Barnea	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
214a551c94aSIdo Barnea	       E1000_BLK_PHY_RESET : E1000_SUCCESS;
215a551c94aSIdo Barnea}
216a551c94aSIdo Barnea
217a551c94aSIdo Barnea/**
218a551c94aSIdo Barnea *  e1000_get_phy_id - Retrieve the PHY ID and revision
219a551c94aSIdo Barnea *  @hw: pointer to the HW structure
220a551c94aSIdo Barnea *
221a551c94aSIdo Barnea *  Reads the PHY registers and stores the PHY ID and possibly the PHY
222a551c94aSIdo Barnea *  revision in the hardware structure.
223a551c94aSIdo Barnea **/
224a551c94aSIdo Barneas32 e1000_get_phy_id(struct e1000_hw *hw)
225a551c94aSIdo Barnea{
226a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
227a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
228a551c94aSIdo Barnea	u16 phy_id;
229a551c94aSIdo Barnea	u16 retry_count = 0;
230a551c94aSIdo Barnea
231a551c94aSIdo Barnea	DEBUGFUNC("e1000_get_phy_id");
232a551c94aSIdo Barnea
233a551c94aSIdo Barnea	if (!phy->ops.read_reg)
234a551c94aSIdo Barnea		return E1000_SUCCESS;
235a551c94aSIdo Barnea
236a551c94aSIdo Barnea	while (retry_count < 2) {
237a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
238a551c94aSIdo Barnea		if (ret_val)
239a551c94aSIdo Barnea			return ret_val;
240a551c94aSIdo Barnea
241a551c94aSIdo Barnea		phy->id = (u32)(phy_id << 16);
242a551c94aSIdo Barnea		usec_delay(20);
243a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
244a551c94aSIdo Barnea		if (ret_val)
245a551c94aSIdo Barnea			return ret_val;
246a551c94aSIdo Barnea
247a551c94aSIdo Barnea		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248a551c94aSIdo Barnea		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
249a551c94aSIdo Barnea
250a551c94aSIdo Barnea		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
251a551c94aSIdo Barnea			return E1000_SUCCESS;
252a551c94aSIdo Barnea
253a551c94aSIdo Barnea		retry_count++;
254a551c94aSIdo Barnea	}
255a551c94aSIdo Barnea
256a551c94aSIdo Barnea	return E1000_SUCCESS;
257a551c94aSIdo Barnea}
258a551c94aSIdo Barnea
259a551c94aSIdo Barnea/**
260a551c94aSIdo Barnea *  e1000_phy_reset_dsp_generic - Reset PHY DSP
261a551c94aSIdo Barnea *  @hw: pointer to the HW structure
262a551c94aSIdo Barnea *
263a551c94aSIdo Barnea *  Reset the digital signal processor.
264a551c94aSIdo Barnea **/
265a551c94aSIdo Barneas32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
266a551c94aSIdo Barnea{
267a551c94aSIdo Barnea	s32 ret_val;
268a551c94aSIdo Barnea
269a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_reset_dsp_generic");
270a551c94aSIdo Barnea
271a551c94aSIdo Barnea	if (!hw->phy.ops.write_reg)
272a551c94aSIdo Barnea		return E1000_SUCCESS;
273a551c94aSIdo Barnea
274a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
275a551c94aSIdo Barnea	if (ret_val)
276a551c94aSIdo Barnea		return ret_val;
277a551c94aSIdo Barnea
278a551c94aSIdo Barnea	return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
279a551c94aSIdo Barnea}
280a551c94aSIdo Barnea
281a551c94aSIdo Barnea/**
282a551c94aSIdo Barnea *  e1000_read_phy_reg_mdic - Read MDI control register
283a551c94aSIdo Barnea *  @hw: pointer to the HW structure
284a551c94aSIdo Barnea *  @offset: register offset to be read
285a551c94aSIdo Barnea *  @data: pointer to the read data
286a551c94aSIdo Barnea *
287a551c94aSIdo Barnea *  Reads the MDI control register in the PHY at offset and stores the
288a551c94aSIdo Barnea *  information read to data.
289a551c94aSIdo Barnea **/
290a551c94aSIdo Barneas32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
291a551c94aSIdo Barnea{
292a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
293a551c94aSIdo Barnea	u32 i, mdic = 0;
294a551c94aSIdo Barnea
295a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_mdic");
296a551c94aSIdo Barnea
297a551c94aSIdo Barnea	if (offset > MAX_PHY_REG_ADDRESS) {
298a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %d is out of range\n", offset);
299a551c94aSIdo Barnea		return -E1000_ERR_PARAM;
300a551c94aSIdo Barnea	}
301a551c94aSIdo Barnea
302a551c94aSIdo Barnea	/* Set up Op-code, Phy Address, and register offset in the MDI
303a551c94aSIdo Barnea	 * Control register.  The MAC will take care of interfacing with the
304a551c94aSIdo Barnea	 * PHY to retrieve the desired data.
305a551c94aSIdo Barnea	 */
306a551c94aSIdo Barnea	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
307a551c94aSIdo Barnea		(phy->addr << E1000_MDIC_PHY_SHIFT) |
308a551c94aSIdo Barnea		(E1000_MDIC_OP_READ));
309a551c94aSIdo Barnea
310a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
311a551c94aSIdo Barnea
312a551c94aSIdo Barnea	/* Poll the ready bit to see if the MDI read completed
313a551c94aSIdo Barnea	 * Increasing the time out as testing showed failures with
314a551c94aSIdo Barnea	 * the lower time out
315a551c94aSIdo Barnea	 */
316a551c94aSIdo Barnea	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
317a551c94aSIdo Barnea		usec_delay_irq(50);
318a551c94aSIdo Barnea		mdic = E1000_READ_REG(hw, E1000_MDIC);
319a551c94aSIdo Barnea		if (mdic & E1000_MDIC_READY)
320a551c94aSIdo Barnea			break;
321a551c94aSIdo Barnea	}
322a551c94aSIdo Barnea	if (!(mdic & E1000_MDIC_READY)) {
323a551c94aSIdo Barnea		DEBUGOUT("MDI Read did not complete\n");
324a551c94aSIdo Barnea		return -E1000_ERR_PHY;
325a551c94aSIdo Barnea	}
326a551c94aSIdo Barnea	if (mdic & E1000_MDIC_ERROR) {
327a551c94aSIdo Barnea		DEBUGOUT("MDI Error\n");
328a551c94aSIdo Barnea		return -E1000_ERR_PHY;
329a551c94aSIdo Barnea	}
330a551c94aSIdo Barnea	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
331a551c94aSIdo Barnea		DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
332a551c94aSIdo Barnea			  offset,
333a551c94aSIdo Barnea			  (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
334a551c94aSIdo Barnea		return -E1000_ERR_PHY;
335a551c94aSIdo Barnea	}
336a551c94aSIdo Barnea	*data = (u16) mdic;
337a551c94aSIdo Barnea
338a551c94aSIdo Barnea	/* Allow some time after each MDIC transaction to avoid
339a551c94aSIdo Barnea	 * reading duplicate data in the next MDIC transaction.
340a551c94aSIdo Barnea	 */
341a551c94aSIdo Barnea	if (hw->mac.type == e1000_pch2lan)
342a551c94aSIdo Barnea		usec_delay_irq(100);
343a551c94aSIdo Barnea
344a551c94aSIdo Barnea	return E1000_SUCCESS;
345a551c94aSIdo Barnea}
346a551c94aSIdo Barnea
347a551c94aSIdo Barnea/**
348a551c94aSIdo Barnea *  e1000_write_phy_reg_mdic - Write MDI control register
349a551c94aSIdo Barnea *  @hw: pointer to the HW structure
350a551c94aSIdo Barnea *  @offset: register offset to write to
351a551c94aSIdo Barnea *  @data: data to write to register at offset
352a551c94aSIdo Barnea *
353a551c94aSIdo Barnea *  Writes data to MDI control register in the PHY at offset.
354a551c94aSIdo Barnea **/
355a551c94aSIdo Barneas32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
356a551c94aSIdo Barnea{
357a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
358a551c94aSIdo Barnea	u32 i, mdic = 0;
359a551c94aSIdo Barnea
360a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_mdic");
361a551c94aSIdo Barnea
362a551c94aSIdo Barnea	if (offset > MAX_PHY_REG_ADDRESS) {
363a551c94aSIdo Barnea		DEBUGOUT1("PHY Address %d is out of range\n", offset);
364a551c94aSIdo Barnea		return -E1000_ERR_PARAM;
365a551c94aSIdo Barnea	}
366a551c94aSIdo Barnea
367a551c94aSIdo Barnea	/* Set up Op-code, Phy Address, and register offset in the MDI
368a551c94aSIdo Barnea	 * Control register.  The MAC will take care of interfacing with the
369a551c94aSIdo Barnea	 * PHY to retrieve the desired data.
370a551c94aSIdo Barnea	 */
371a551c94aSIdo Barnea	mdic = (((u32)data) |
372a551c94aSIdo Barnea		(offset << E1000_MDIC_REG_SHIFT) |
373a551c94aSIdo Barnea		(phy->addr << E1000_MDIC_PHY_SHIFT) |
374a551c94aSIdo Barnea		(E1000_MDIC_OP_WRITE));
375a551c94aSIdo Barnea
376a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
377a551c94aSIdo Barnea
378a551c94aSIdo Barnea	/* Poll the ready bit to see if the MDI read completed
379a551c94aSIdo Barnea	 * Increasing the time out as testing showed failures with
380a551c94aSIdo Barnea	 * the lower time out
381a551c94aSIdo Barnea	 */
382a551c94aSIdo Barnea	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
383a551c94aSIdo Barnea		usec_delay_irq(50);
384a551c94aSIdo Barnea		mdic = E1000_READ_REG(hw, E1000_MDIC);
385a551c94aSIdo Barnea		if (mdic & E1000_MDIC_READY)
386a551c94aSIdo Barnea			break;
387a551c94aSIdo Barnea	}
388a551c94aSIdo Barnea	if (!(mdic & E1000_MDIC_READY)) {
389a551c94aSIdo Barnea		DEBUGOUT("MDI Write did not complete\n");
390a551c94aSIdo Barnea		return -E1000_ERR_PHY;
391a551c94aSIdo Barnea	}
392a551c94aSIdo Barnea	if (mdic & E1000_MDIC_ERROR) {
393a551c94aSIdo Barnea		DEBUGOUT("MDI Error\n");
394a551c94aSIdo Barnea		return -E1000_ERR_PHY;
395a551c94aSIdo Barnea	}
396a551c94aSIdo Barnea	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
397a551c94aSIdo Barnea		DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
398a551c94aSIdo Barnea			  offset,
399a551c94aSIdo Barnea			  (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
400a551c94aSIdo Barnea		return -E1000_ERR_PHY;
401a551c94aSIdo Barnea	}
402a551c94aSIdo Barnea
403a551c94aSIdo Barnea	/* Allow some time after each MDIC transaction to avoid
404a551c94aSIdo Barnea	 * reading duplicate data in the next MDIC transaction.
405a551c94aSIdo Barnea	 */
406a551c94aSIdo Barnea	if (hw->mac.type == e1000_pch2lan)
407a551c94aSIdo Barnea		usec_delay_irq(100);
408a551c94aSIdo Barnea
409a551c94aSIdo Barnea	return E1000_SUCCESS;
410a551c94aSIdo Barnea}
411a551c94aSIdo Barnea
412a551c94aSIdo Barnea/**
413a551c94aSIdo Barnea *  e1000_read_phy_reg_i2c - Read PHY register using i2c
414a551c94aSIdo Barnea *  @hw: pointer to the HW structure
415a551c94aSIdo Barnea *  @offset: register offset to be read
416a551c94aSIdo Barnea *  @data: pointer to the read data
417a551c94aSIdo Barnea *
418a551c94aSIdo Barnea *  Reads the PHY register at offset using the i2c interface and stores the
419a551c94aSIdo Barnea *  retrieved information in data.
420a551c94aSIdo Barnea **/
421a551c94aSIdo Barneas32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
422a551c94aSIdo Barnea{
423a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
424a551c94aSIdo Barnea	u32 i, i2ccmd = 0;
425a551c94aSIdo Barnea
426a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_i2c");
427a551c94aSIdo Barnea
428a551c94aSIdo Barnea	/* Set up Op-code, Phy Address, and register address in the I2CCMD
429a551c94aSIdo Barnea	 * register.  The MAC will take care of interfacing with the
430a551c94aSIdo Barnea	 * PHY to retrieve the desired data.
431a551c94aSIdo Barnea	 */
432a551c94aSIdo Barnea	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
433a551c94aSIdo Barnea		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
434a551c94aSIdo Barnea		  (E1000_I2CCMD_OPCODE_READ));
435a551c94aSIdo Barnea
436a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
437a551c94aSIdo Barnea
438a551c94aSIdo Barnea	/* Poll the ready bit to see if the I2C read completed */
439a551c94aSIdo Barnea	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
440a551c94aSIdo Barnea		usec_delay(50);
441a551c94aSIdo Barnea		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
442a551c94aSIdo Barnea		if (i2ccmd & E1000_I2CCMD_READY)
443a551c94aSIdo Barnea			break;
444a551c94aSIdo Barnea	}
445a551c94aSIdo Barnea	if (!(i2ccmd & E1000_I2CCMD_READY)) {
446a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Read did not complete\n");
447a551c94aSIdo Barnea		return -E1000_ERR_PHY;
448a551c94aSIdo Barnea	}
449a551c94aSIdo Barnea	if (i2ccmd & E1000_I2CCMD_ERROR) {
450a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Error bit set\n");
451a551c94aSIdo Barnea		return -E1000_ERR_PHY;
452a551c94aSIdo Barnea	}
453a551c94aSIdo Barnea
454a551c94aSIdo Barnea	/* Need to byte-swap the 16-bit value. */
455a551c94aSIdo Barnea	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
456a551c94aSIdo Barnea
457a551c94aSIdo Barnea	return E1000_SUCCESS;
458a551c94aSIdo Barnea}
459a551c94aSIdo Barnea
460a551c94aSIdo Barnea/**
461a551c94aSIdo Barnea *  e1000_write_phy_reg_i2c - Write PHY register using i2c
462a551c94aSIdo Barnea *  @hw: pointer to the HW structure
463a551c94aSIdo Barnea *  @offset: register offset to write to
464a551c94aSIdo Barnea *  @data: data to write at register offset
465a551c94aSIdo Barnea *
466a551c94aSIdo Barnea *  Writes the data to PHY register at the offset using the i2c interface.
467a551c94aSIdo Barnea **/
468a551c94aSIdo Barneas32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
469a551c94aSIdo Barnea{
470a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
471a551c94aSIdo Barnea	u32 i, i2ccmd = 0;
472a551c94aSIdo Barnea	u16 phy_data_swapped;
473a551c94aSIdo Barnea
474a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_i2c");
475a551c94aSIdo Barnea
476a551c94aSIdo Barnea	/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
477a551c94aSIdo Barnea	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
478a551c94aSIdo Barnea		DEBUGOUT1("PHY I2C Address %d is out of range.\n",
479a551c94aSIdo Barnea			  hw->phy.addr);
480a551c94aSIdo Barnea		return -E1000_ERR_CONFIG;
481a551c94aSIdo Barnea	}
482a551c94aSIdo Barnea
483a551c94aSIdo Barnea	/* Swap the data bytes for the I2C interface */
484a551c94aSIdo Barnea	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
485a551c94aSIdo Barnea
486a551c94aSIdo Barnea	/* Set up Op-code, Phy Address, and register address in the I2CCMD
487a551c94aSIdo Barnea	 * register.  The MAC will take care of interfacing with the
488a551c94aSIdo Barnea	 * PHY to retrieve the desired data.
489a551c94aSIdo Barnea	 */
490a551c94aSIdo Barnea	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
491a551c94aSIdo Barnea		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
492a551c94aSIdo Barnea		  E1000_I2CCMD_OPCODE_WRITE |
493a551c94aSIdo Barnea		  phy_data_swapped);
494a551c94aSIdo Barnea
495a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
496a551c94aSIdo Barnea
497a551c94aSIdo Barnea	/* Poll the ready bit to see if the I2C read completed */
498a551c94aSIdo Barnea	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
499a551c94aSIdo Barnea		usec_delay(50);
500a551c94aSIdo Barnea		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
501a551c94aSIdo Barnea		if (i2ccmd & E1000_I2CCMD_READY)
502a551c94aSIdo Barnea			break;
503a551c94aSIdo Barnea	}
504a551c94aSIdo Barnea	if (!(i2ccmd & E1000_I2CCMD_READY)) {
505a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Write did not complete\n");
506a551c94aSIdo Barnea		return -E1000_ERR_PHY;
507a551c94aSIdo Barnea	}
508a551c94aSIdo Barnea	if (i2ccmd & E1000_I2CCMD_ERROR) {
509a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Error bit set\n");
510a551c94aSIdo Barnea		return -E1000_ERR_PHY;
511a551c94aSIdo Barnea	}
512a551c94aSIdo Barnea
513a551c94aSIdo Barnea	return E1000_SUCCESS;
514a551c94aSIdo Barnea}
515a551c94aSIdo Barnea
516a551c94aSIdo Barnea/**
517a551c94aSIdo Barnea *  e1000_read_sfp_data_byte - Reads SFP module data.
518a551c94aSIdo Barnea *  @hw: pointer to the HW structure
519a551c94aSIdo Barnea *  @offset: byte location offset to be read
520a551c94aSIdo Barnea *  @data: read data buffer pointer
521a551c94aSIdo Barnea *
522a551c94aSIdo Barnea *  Reads one byte from SFP module data stored
523a551c94aSIdo Barnea *  in SFP resided EEPROM memory or SFP diagnostic area.
524a551c94aSIdo Barnea *  Function should be called with
525a551c94aSIdo Barnea *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
526a551c94aSIdo Barnea *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
527a551c94aSIdo Barnea *  access
528a551c94aSIdo Barnea **/
529a551c94aSIdo Barneas32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
530a551c94aSIdo Barnea{
531a551c94aSIdo Barnea	u32 i = 0;
532a551c94aSIdo Barnea	u32 i2ccmd = 0;
533a551c94aSIdo Barnea	u32 data_local = 0;
534a551c94aSIdo Barnea
535a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_sfp_data_byte");
536a551c94aSIdo Barnea
537a551c94aSIdo Barnea	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
538a551c94aSIdo Barnea		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
539a551c94aSIdo Barnea		return -E1000_ERR_PHY;
540a551c94aSIdo Barnea	}
541a551c94aSIdo Barnea
542a551c94aSIdo Barnea	/* Set up Op-code, EEPROM Address,in the I2CCMD
543a551c94aSIdo Barnea	 * register. The MAC will take care of interfacing with the
544a551c94aSIdo Barnea	 * EEPROM to retrieve the desired data.
545a551c94aSIdo Barnea	 */
546a551c94aSIdo Barnea	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
547a551c94aSIdo Barnea		  E1000_I2CCMD_OPCODE_READ);
548a551c94aSIdo Barnea
549a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
550a551c94aSIdo Barnea
551a551c94aSIdo Barnea	/* Poll the ready bit to see if the I2C read completed */
552a551c94aSIdo Barnea	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
553a551c94aSIdo Barnea		usec_delay(50);
554a551c94aSIdo Barnea		data_local = E1000_READ_REG(hw, E1000_I2CCMD);
555a551c94aSIdo Barnea		if (data_local & E1000_I2CCMD_READY)
556a551c94aSIdo Barnea			break;
557a551c94aSIdo Barnea	}
558a551c94aSIdo Barnea	if (!(data_local & E1000_I2CCMD_READY)) {
559a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Read did not complete\n");
560a551c94aSIdo Barnea		return -E1000_ERR_PHY;
561a551c94aSIdo Barnea	}
562a551c94aSIdo Barnea	if (data_local & E1000_I2CCMD_ERROR) {
563a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Error bit set\n");
564a551c94aSIdo Barnea		return -E1000_ERR_PHY;
565a551c94aSIdo Barnea	}
566a551c94aSIdo Barnea	*data = (u8) data_local & 0xFF;
567a551c94aSIdo Barnea
568a551c94aSIdo Barnea	return E1000_SUCCESS;
569a551c94aSIdo Barnea}
570a551c94aSIdo Barnea
571a551c94aSIdo Barnea/**
572a551c94aSIdo Barnea *  e1000_write_sfp_data_byte - Writes SFP module data.
573a551c94aSIdo Barnea *  @hw: pointer to the HW structure
574a551c94aSIdo Barnea *  @offset: byte location offset to write to
575a551c94aSIdo Barnea *  @data: data to write
576a551c94aSIdo Barnea *
577a551c94aSIdo Barnea *  Writes one byte to SFP module data stored
578a551c94aSIdo Barnea *  in SFP resided EEPROM memory or SFP diagnostic area.
579a551c94aSIdo Barnea *  Function should be called with
580a551c94aSIdo Barnea *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
581a551c94aSIdo Barnea *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
582a551c94aSIdo Barnea *  access
583a551c94aSIdo Barnea **/
584a551c94aSIdo Barneas32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
585a551c94aSIdo Barnea{
586a551c94aSIdo Barnea	u32 i = 0;
587a551c94aSIdo Barnea	u32 i2ccmd = 0;
588a551c94aSIdo Barnea	u32 data_local = 0;
589a551c94aSIdo Barnea
590a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_sfp_data_byte");
591a551c94aSIdo Barnea
592a551c94aSIdo Barnea	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
593a551c94aSIdo Barnea		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
594a551c94aSIdo Barnea		return -E1000_ERR_PHY;
595a551c94aSIdo Barnea	}
596a551c94aSIdo Barnea	/* The programming interface is 16 bits wide
597a551c94aSIdo Barnea	 * so we need to read the whole word first
598a551c94aSIdo Barnea	 * then update appropriate byte lane and write
599a551c94aSIdo Barnea	 * the updated word back.
600a551c94aSIdo Barnea	 */
601a551c94aSIdo Barnea	/* Set up Op-code, EEPROM Address,in the I2CCMD
602a551c94aSIdo Barnea	 * register. The MAC will take care of interfacing
603a551c94aSIdo Barnea	 * with an EEPROM to write the data given.
604a551c94aSIdo Barnea	 */
605a551c94aSIdo Barnea	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
606a551c94aSIdo Barnea		  E1000_I2CCMD_OPCODE_READ);
607a551c94aSIdo Barnea	/* Set a command to read single word */
608a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
609a551c94aSIdo Barnea	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
610a551c94aSIdo Barnea		usec_delay(50);
611a551c94aSIdo Barnea		/* Poll the ready bit to see if lastly
612a551c94aSIdo Barnea		 * launched I2C operation completed
613a551c94aSIdo Barnea		 */
614a551c94aSIdo Barnea		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
615a551c94aSIdo Barnea		if (i2ccmd & E1000_I2CCMD_READY) {
616a551c94aSIdo Barnea			/* Check if this is READ or WRITE phase */
617a551c94aSIdo Barnea			if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
618a551c94aSIdo Barnea			    E1000_I2CCMD_OPCODE_READ) {
619a551c94aSIdo Barnea				/* Write the selected byte
620a551c94aSIdo Barnea				 * lane and update whole word
621a551c94aSIdo Barnea				 */
622a551c94aSIdo Barnea				data_local = i2ccmd & 0xFF00;
623a551c94aSIdo Barnea				data_local |= data;
624a551c94aSIdo Barnea				i2ccmd = ((offset <<
625a551c94aSIdo Barnea					E1000_I2CCMD_REG_ADDR_SHIFT) |
626a551c94aSIdo Barnea					E1000_I2CCMD_OPCODE_WRITE | data_local);
627a551c94aSIdo Barnea				E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
628a551c94aSIdo Barnea			} else {
629a551c94aSIdo Barnea				break;
630a551c94aSIdo Barnea			}
631a551c94aSIdo Barnea		}
632a551c94aSIdo Barnea	}
633a551c94aSIdo Barnea	if (!(i2ccmd & E1000_I2CCMD_READY)) {
634a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Write did not complete\n");
635a551c94aSIdo Barnea		return -E1000_ERR_PHY;
636a551c94aSIdo Barnea	}
637a551c94aSIdo Barnea	if (i2ccmd & E1000_I2CCMD_ERROR) {
638a551c94aSIdo Barnea		DEBUGOUT("I2CCMD Error bit set\n");
639a551c94aSIdo Barnea		return -E1000_ERR_PHY;
640a551c94aSIdo Barnea	}
641a551c94aSIdo Barnea	return E1000_SUCCESS;
642a551c94aSIdo Barnea}
643a551c94aSIdo Barnea
644a551c94aSIdo Barnea/**
645a551c94aSIdo Barnea *  e1000_read_phy_reg_m88 - Read m88 PHY register
646a551c94aSIdo Barnea *  @hw: pointer to the HW structure
647a551c94aSIdo Barnea *  @offset: register offset to be read
648a551c94aSIdo Barnea *  @data: pointer to the read data
649a551c94aSIdo Barnea *
650a551c94aSIdo Barnea *  Acquires semaphore, if necessary, then reads the PHY register at offset
651a551c94aSIdo Barnea *  and storing the retrieved information in data.  Release any acquired
652a551c94aSIdo Barnea *  semaphores before exiting.
653a551c94aSIdo Barnea **/
654a551c94aSIdo Barneas32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
655a551c94aSIdo Barnea{
656a551c94aSIdo Barnea	s32 ret_val;
657a551c94aSIdo Barnea
658a551c94aSIdo Barnea	DEBUGFUNC("e1000_read_phy_reg_m88");
659a551c94aSIdo Barnea
660a551c94aSIdo Barnea	if (!hw->phy.ops.acquire)
661a551c94aSIdo Barnea		return E1000_SUCCESS;
662a551c94aSIdo Barnea
663a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
664a551c94aSIdo Barnea	if (ret_val)
665a551c94aSIdo Barnea		return ret_val;
666a551c94aSIdo Barnea
667a551c94aSIdo Barnea	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
668a551c94aSIdo Barnea					  data);
669a551c94aSIdo Barnea
670a551c94aSIdo Barnea	hw->phy.ops.release(hw);
671a551c94aSIdo Barnea
672a551c94aSIdo Barnea	return ret_val;
673a551c94aSIdo Barnea}
674a551c94aSIdo Barnea
675a551c94aSIdo Barnea/**
676a551c94aSIdo Barnea *  e1000_write_phy_reg_m88 - Write m88 PHY register
677a551c94aSIdo Barnea *  @hw: pointer to the HW structure
678a551c94aSIdo Barnea *  @offset: register offset to write to
679a551c94aSIdo Barnea *  @data: data to write at register offset
680a551c94aSIdo Barnea *
681a551c94aSIdo Barnea *  Acquires semaphore, if necessary, then writes the data to PHY register
682a551c94aSIdo Barnea *  at the offset.  Release any acquired semaphores before exiting.
683a551c94aSIdo Barnea **/
684a551c94aSIdo Barneas32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
685a551c94aSIdo Barnea{
686a551c94aSIdo Barnea	s32 ret_val;
687a551c94aSIdo Barnea
688a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_m88");
689a551c94aSIdo Barnea
690a551c94aSIdo Barnea	if (!hw->phy.ops.acquire)
691a551c94aSIdo Barnea		return E1000_SUCCESS;
692a551c94aSIdo Barnea
693a551c94aSIdo Barnea	ret_val = hw->phy.ops.acquire(hw);
694a551c94aSIdo Barnea	if (ret_val)
695a551c94aSIdo Barnea		return ret_val;
696a551c94aSIdo Barnea
697a551c94aSIdo Barnea	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
698a551c94aSIdo Barnea					   data);
699a551c94aSIdo Barnea
700a551c94aSIdo Barnea	hw->phy.ops.release(hw);
701a551c94aSIdo Barnea
702a551c94aSIdo Barnea	return ret_val;
703a551c94aSIdo Barnea}
704a551c94aSIdo Barnea
705a551c94aSIdo Barnea/**
706a551c94aSIdo Barnea *  e1000_set_page_igp - Set page as on IGP-like PHY(s)
707a551c94aSIdo Barnea *  @hw: pointer to the HW structure
708a551c94aSIdo Barnea *  @page: page to set (shifted left when necessary)
709a551c94aSIdo Barnea *
710a551c94aSIdo Barnea *  Sets PHY page required for PHY register access.  Assumes semaphore is
711a551c94aSIdo Barnea *  already acquired.  Note, this function sets phy.addr to 1 so the caller
712a551c94aSIdo Barnea *  must set it appropriately (if necessary) after this function returns.
713a551c94aSIdo Barnea **/
714a551c94aSIdo Barneas32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
715a551c94aSIdo Barnea{
716a551c94aSIdo Barnea	DEBUGFUNC("e1000_set_page_igp");
717a551c94aSIdo Barnea
718a551c94aSIdo Barnea	DEBUGOUT1("Setting page 0x%x\n", page);
719a551c94aSIdo Barnea
720a551c94aSIdo Barnea	hw->phy.addr = 1;
721a551c94aSIdo Barnea
722a551c94aSIdo Barnea	return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
723a551c94aSIdo Barnea}
724a551c94aSIdo Barnea
725a551c94aSIdo Barnea/**
726a551c94aSIdo Barnea *  __e1000_read_phy_reg_igp - Read igp PHY register
727a551c94aSIdo Barnea *  @hw: pointer to the HW structure
728a551c94aSIdo Barnea *  @offset: register offset to be read
729a551c94aSIdo Barnea *  @data: pointer to the read data
730a551c94aSIdo Barnea *  @locked: semaphore has already been acquired or not
731a551c94aSIdo Barnea *
732a551c94aSIdo Barnea *  Acquires semaphore, if necessary, then reads the PHY register at offset
733a551c94aSIdo Barnea *  and stores the retrieved information in data.  Release any acquired
734a551c94aSIdo Barnea *  semaphores before exiting.
735a551c94aSIdo Barnea **/
736a551c94aSIdo BarneaSTATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
737a551c94aSIdo Barnea				    bool locked)
738a551c94aSIdo Barnea{
739a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
740a551c94aSIdo Barnea
741a551c94aSIdo Barnea	DEBUGFUNC("__e1000_read_phy_reg_igp");
742a551c94aSIdo Barnea
743a551c94aSIdo Barnea	if (!locked) {
744a551c94aSIdo Barnea		if (!hw->phy.ops.acquire)
745a551c94aSIdo Barnea			return E1000_SUCCESS;
746a551c94aSIdo Barnea
747a551c94aSIdo Barnea		ret_val = hw->phy.ops.acquire(hw);
748a551c94aSIdo Barnea		if (ret_val)
749a551c94aSIdo Barnea			return ret_val;
750a551c94aSIdo Barnea	}
751a551c94aSIdo Barnea
752a551c94aSIdo Barnea	if (offset > MAX_PHY_MULTI_PAGE_REG)
753a551c94aSIdo Barnea		ret_val = e1000_write_phy_reg_mdic(hw,
754a551c94aSIdo Barnea						   IGP01E1000_PHY_PAGE_SELECT,
755a551c94aSIdo Barnea						   (u16)offset);
756a551c94aSIdo Barnea	if (!ret_val)
757a551c94aSIdo Barnea		ret_val = e1000_read_phy_reg_mdic(hw,
758a551c94aSIdo Barnea						  MAX_PHY_REG_ADDRESS & offset,
759a551c94aSIdo Barnea						  data);
760a551c94aSIdo Barnea	if (!locked)
761a551c94aSIdo Barnea		hw->phy.ops.release(hw);
762a551c94aSIdo Barnea
763a551c94aSIdo Barnea	return ret_val;
764a551c94aSIdo Barnea}
765a551c94aSIdo Barnea
766a551c94aSIdo Barnea/**
767a551c94aSIdo Barnea *  e1000_read_phy_reg_igp - Read igp PHY register
768a551c94aSIdo Barnea *  @hw: pointer to the HW structure
769a551c94aSIdo Barnea *  @offset: register offset to be read
770a551c94aSIdo Barnea *  @data: pointer to the read data
771a551c94aSIdo Barnea *
772a551c94aSIdo Barnea *  Acquires semaphore then reads the PHY register at offset and stores the
773a551c94aSIdo Barnea *  retrieved information in data.
774a551c94aSIdo Barnea *  Release the acquired semaphore before exiting.
775a551c94aSIdo Barnea **/
776a551c94aSIdo Barneas32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
777a551c94aSIdo Barnea{
778a551c94aSIdo Barnea	return __e1000_read_phy_reg_igp(hw, offset, data, false);
779a551c94aSIdo Barnea}
780a551c94aSIdo Barnea
781a551c94aSIdo Barnea/**
782a551c94aSIdo Barnea *  e1000_read_phy_reg_igp_locked - Read igp PHY register
783a551c94aSIdo Barnea *  @hw: pointer to the HW structure
784a551c94aSIdo Barnea *  @offset: register offset to be read
785a551c94aSIdo Barnea *  @data: pointer to the read data
786a551c94aSIdo Barnea *
787a551c94aSIdo Barnea *  Reads the PHY register at offset and stores the retrieved information
788a551c94aSIdo Barnea *  in data.  Assumes semaphore already acquired.
789a551c94aSIdo Barnea **/
790a551c94aSIdo Barneas32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
791a551c94aSIdo Barnea{
792a551c94aSIdo Barnea	return __e1000_read_phy_reg_igp(hw, offset, data, true);
793a551c94aSIdo Barnea}
794a551c94aSIdo Barnea
795a551c94aSIdo Barnea/**
796a551c94aSIdo Barnea *  e1000_write_phy_reg_igp - Write igp PHY register
797a551c94aSIdo Barnea *  @hw: pointer to the HW structure
798a551c94aSIdo Barnea *  @offset: register offset to write to
799a551c94aSIdo Barnea *  @data: data to write at register offset
800a551c94aSIdo Barnea *  @locked: semaphore has already been acquired or not
801a551c94aSIdo Barnea *
802a551c94aSIdo Barnea *  Acquires semaphore, if necessary, then writes the data to PHY register
803a551c94aSIdo Barnea *  at the offset.  Release any acquired semaphores before exiting.
804a551c94aSIdo Barnea **/
805a551c94aSIdo BarneaSTATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
806a551c94aSIdo Barnea				     bool locked)
807a551c94aSIdo Barnea{
808a551c94aSIdo Barnea	s32 ret_val = E1000_SUCCESS;
809a551c94aSIdo Barnea
810a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_phy_reg_igp");
811a551c94aSIdo Barnea
812a551c94aSIdo Barnea	if (!locked) {
813a551c94aSIdo Barnea		if (!hw->phy.ops.acquire)
814a551c94aSIdo Barnea			return E1000_SUCCESS;
815a551c94aSIdo Barnea
816a551c94aSIdo Barnea		ret_val = hw->phy.ops.acquire(hw);
817a551c94aSIdo Barnea		if (ret_val)
818a551c94aSIdo Barnea			return ret_val;
819a551c94aSIdo Barnea	}
820a551c94aSIdo Barnea
821a551c94aSIdo Barnea	if (offset > MAX_PHY_MULTI_PAGE_REG)
822a551c94aSIdo Barnea		ret_val = e1000_write_phy_reg_mdic(hw,
823a551c94aSIdo Barnea						   IGP01E1000_PHY_PAGE_SELECT,
824a551c94aSIdo Barnea						   (u16)offset);
825a551c94aSIdo Barnea	if (!ret_val)
826a551c94aSIdo Barnea		ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
827a551c94aSIdo Barnea						       offset,
828a551c94aSIdo Barnea						   data);
829a551c94aSIdo Barnea	if (!locked)
830a551c94aSIdo Barnea		hw->phy.ops.release(hw);
831a551c94aSIdo Barnea
832a551c94aSIdo Barnea	return ret_val;
833a551c94aSIdo Barnea}
834a551c94aSIdo Barnea
835a551c94aSIdo Barnea/**
836a551c94aSIdo Barnea *  e1000_write_phy_reg_igp - Write igp PHY register
837a551c94aSIdo Barnea *  @hw: pointer to the HW structure
838a551c94aSIdo Barnea *  @offset: register offset to write to
839a551c94aSIdo Barnea *  @data: data to write at register offset
840a551c94aSIdo Barnea *
841a551c94aSIdo Barnea *  Acquires semaphore then writes the data to PHY register
842a551c94aSIdo Barnea *  at the offset.  Release any acquired semaphores before exiting.
843a551c94aSIdo Barnea **/
844a551c94aSIdo Barneas32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
845a551c94aSIdo Barnea{
846a551c94aSIdo Barnea	return __e1000_write_phy_reg_igp(hw, offset, data, false);
847a551c94aSIdo Barnea}
848a551c94aSIdo Barnea
849a551c94aSIdo Barnea/**
850a551c94aSIdo Barnea *  e1000_write_phy_reg_igp_locked - Write igp PHY register
851a551c94aSIdo Barnea *  @hw: pointer to the HW structure
852a551c94aSIdo Barnea *  @offset: register offset to write to
853a551c94aSIdo Barnea *  @data: data to write at register offset
854a551c94aSIdo Barnea *
855a551c94aSIdo Barnea *  Writes the data to PHY register at the offset.
856a551c94aSIdo Barnea *  Assumes semaphore already acquired.
857a551c94aSIdo Barnea **/
858a551c94aSIdo Barneas32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
859a551c94aSIdo Barnea{
860a551c94aSIdo Barnea	return __e1000_write_phy_reg_igp(hw, offset, data, true);
861a551c94aSIdo Barnea}
862a551c94aSIdo Barnea
863a551c94aSIdo Barnea/**
864a551c94aSIdo Barnea *  __e1000_read_kmrn_reg - Read kumeran register
865a551c94aSIdo Barnea *  @hw: pointer to the HW structure
866a551c94aSIdo Barnea *  @offset: register offset to be read
867a551c94aSIdo Barnea *  @data: pointer to the read data
868a551c94aSIdo Barnea *  @locked: semaphore has already been acquired or not
869a551c94aSIdo Barnea *
870a551c94aSIdo Barnea *  Acquires semaphore, if necessary.  Then reads the PHY register at offset
871a551c94aSIdo Barnea *  using the kumeran interface.  The information retrieved is stored in data.
872a551c94aSIdo Barnea *  Release any acquired semaphores before exiting.
873a551c94aSIdo Barnea **/
874a551c94aSIdo BarneaSTATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
875a551c94aSIdo Barnea				 bool locked)
876a551c94aSIdo Barnea{
877a551c94aSIdo Barnea	u32 kmrnctrlsta;
878a551c94aSIdo Barnea
879a551c94aSIdo Barnea	DEBUGFUNC("__e1000_read_kmrn_reg");
880a551c94aSIdo Barnea
881a551c94aSIdo Barnea	if (!locked) {
882a551c94aSIdo Barnea		s32 ret_val = E1000_SUCCESS;
883a551c94aSIdo Barnea
884a551c94aSIdo Barnea		if (!hw->phy.ops.acquire)
885a551c94aSIdo Barnea			return E1000_SUCCESS;
886a551c94aSIdo Barnea
887a551c94aSIdo Barnea		ret_val = hw->phy.ops.acquire(hw);
888a551c94aSIdo Barnea		if (ret_val)
889a551c94aSIdo Barnea			return ret_val;
890a551c94aSIdo Barnea	}
891a551c94aSIdo Barnea
892a551c94aSIdo Barnea	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
893a551c94aSIdo Barnea		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
894a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
895a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
896a551c94aSIdo Barnea
897a551c94aSIdo Barnea	usec_delay(2);
898a551c94aSIdo Barnea
899a551c94aSIdo Barnea	kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
900a551c94aSIdo Barnea	*data = (u16)kmrnctrlsta;
901a551c94aSIdo Barnea
902a551c94aSIdo Barnea	if (!locked)
903a551c94aSIdo Barnea		hw->phy.ops.release(hw);
904a551c94aSIdo Barnea
905a551c94aSIdo Barnea	return E1000_SUCCESS;
906a551c94aSIdo Barnea}
907a551c94aSIdo Barnea
908a551c94aSIdo Barnea/**
909a551c94aSIdo Barnea *  e1000_read_kmrn_reg_generic -  Read kumeran register
910a551c94aSIdo Barnea *  @hw: pointer to the HW structure
911a551c94aSIdo Barnea *  @offset: register offset to be read
912a551c94aSIdo Barnea *  @data: pointer to the read data
913a551c94aSIdo Barnea *
914a551c94aSIdo Barnea *  Acquires semaphore then reads the PHY register at offset using the
915a551c94aSIdo Barnea *  kumeran interface.  The information retrieved is stored in data.
916a551c94aSIdo Barnea *  Release the acquired semaphore before exiting.
917a551c94aSIdo Barnea **/
918a551c94aSIdo Barneas32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
919a551c94aSIdo Barnea{
920a551c94aSIdo Barnea	return __e1000_read_kmrn_reg(hw, offset, data, false);
921a551c94aSIdo Barnea}
922a551c94aSIdo Barnea
923a551c94aSIdo Barnea/**
924a551c94aSIdo Barnea *  e1000_read_kmrn_reg_locked -  Read kumeran register
925a551c94aSIdo Barnea *  @hw: pointer to the HW structure
926a551c94aSIdo Barnea *  @offset: register offset to be read
927a551c94aSIdo Barnea *  @data: pointer to the read data
928a551c94aSIdo Barnea *
929a551c94aSIdo Barnea *  Reads the PHY register at offset using the kumeran interface.  The
930a551c94aSIdo Barnea *  information retrieved is stored in data.
931a551c94aSIdo Barnea *  Assumes semaphore already acquired.
932a551c94aSIdo Barnea **/
933a551c94aSIdo Barneas32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
934a551c94aSIdo Barnea{
935a551c94aSIdo Barnea	return __e1000_read_kmrn_reg(hw, offset, data, true);
936a551c94aSIdo Barnea}
937a551c94aSIdo Barnea
938a551c94aSIdo Barnea/**
939a551c94aSIdo Barnea *  __e1000_write_kmrn_reg - Write kumeran register
940a551c94aSIdo Barnea *  @hw: pointer to the HW structure
941a551c94aSIdo Barnea *  @offset: register offset to write to
942a551c94aSIdo Barnea *  @data: data to write at register offset
943a551c94aSIdo Barnea *  @locked: semaphore has already been acquired or not
944a551c94aSIdo Barnea *
945a551c94aSIdo Barnea *  Acquires semaphore, if necessary.  Then write the data to PHY register
946a551c94aSIdo Barnea *  at the offset using the kumeran interface.  Release any acquired semaphores
947a551c94aSIdo Barnea *  before exiting.
948a551c94aSIdo Barnea **/
949a551c94aSIdo BarneaSTATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
950a551c94aSIdo Barnea				  bool locked)
951a551c94aSIdo Barnea{
952a551c94aSIdo Barnea	u32 kmrnctrlsta;
953a551c94aSIdo Barnea
954a551c94aSIdo Barnea	DEBUGFUNC("e1000_write_kmrn_reg_generic");
955a551c94aSIdo Barnea
956a551c94aSIdo Barnea	if (!locked) {
957a551c94aSIdo Barnea		s32 ret_val = E1000_SUCCESS;
958a551c94aSIdo Barnea
959a551c94aSIdo Barnea		if (!hw->phy.ops.acquire)
960a551c94aSIdo Barnea			return E1000_SUCCESS;
961a551c94aSIdo Barnea
962a551c94aSIdo Barnea		ret_val = hw->phy.ops.acquire(hw);
963a551c94aSIdo Barnea		if (ret_val)
964a551c94aSIdo Barnea			return ret_val;
965a551c94aSIdo Barnea	}
966a551c94aSIdo Barnea
967a551c94aSIdo Barnea	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
968a551c94aSIdo Barnea		       E1000_KMRNCTRLSTA_OFFSET) | data;
969a551c94aSIdo Barnea	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
970a551c94aSIdo Barnea	E1000_WRITE_FLUSH(hw);
971a551c94aSIdo Barnea
972a551c94aSIdo Barnea	usec_delay(2);
973a551c94aSIdo Barnea
974a551c94aSIdo Barnea	if (!locked)
975a551c94aSIdo Barnea		hw->phy.ops.release(hw);
976a551c94aSIdo Barnea
977a551c94aSIdo Barnea	return E1000_SUCCESS;
978a551c94aSIdo Barnea}
979a551c94aSIdo Barnea
980a551c94aSIdo Barnea/**
981a551c94aSIdo Barnea *  e1000_write_kmrn_reg_generic -  Write kumeran register
982a551c94aSIdo Barnea *  @hw: pointer to the HW structure
983a551c94aSIdo Barnea *  @offset: register offset to write to
984a551c94aSIdo Barnea *  @data: data to write at register offset
985a551c94aSIdo Barnea *
986a551c94aSIdo Barnea *  Acquires semaphore then writes the data to the PHY register at the offset
987a551c94aSIdo Barnea *  using the kumeran interface.  Release the acquired semaphore before exiting.
988a551c94aSIdo Barnea **/
989a551c94aSIdo Barneas32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
990a551c94aSIdo Barnea{
991a551c94aSIdo Barnea	return __e1000_write_kmrn_reg(hw, offset, data, false);
992a551c94aSIdo Barnea}
993a551c94aSIdo Barnea
994a551c94aSIdo Barnea/**
995a551c94aSIdo Barnea *  e1000_write_kmrn_reg_locked -  Write kumeran register
996a551c94aSIdo Barnea *  @hw: pointer to the HW structure
997a551c94aSIdo Barnea *  @offset: register offset to write to
998a551c94aSIdo Barnea *  @data: data to write at register offset
999a551c94aSIdo Barnea *
1000a551c94aSIdo Barnea *  Write the data to PHY register at the offset using the kumeran interface.
1001a551c94aSIdo Barnea *  Assumes semaphore already acquired.
1002a551c94aSIdo Barnea **/
1003a551c94aSIdo Barneas32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1004a551c94aSIdo Barnea{
1005a551c94aSIdo Barnea	return __e1000_write_kmrn_reg(hw, offset, data, true);
1006a551c94aSIdo Barnea}
1007a551c94aSIdo Barnea
1008a551c94aSIdo Barnea/**
1009a551c94aSIdo Barnea *  e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1010a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1011a551c94aSIdo Barnea *
1012a551c94aSIdo Barnea *  Sets up Master/slave mode
1013a551c94aSIdo Barnea **/
1014a551c94aSIdo BarneaSTATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1015a551c94aSIdo Barnea{
1016a551c94aSIdo Barnea	s32 ret_val;
1017a551c94aSIdo Barnea	u16 phy_data;
1018a551c94aSIdo Barnea
1019a551c94aSIdo Barnea	/* Resolve Master/Slave mode */
1020a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1021a551c94aSIdo Barnea	if (ret_val)
1022a551c94aSIdo Barnea		return ret_val;
1023a551c94aSIdo Barnea
1024a551c94aSIdo Barnea	/* load defaults for future use */
1025a551c94aSIdo Barnea	hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1026a551c94aSIdo Barnea				   ((phy_data & CR_1000T_MS_VALUE) ?
1027a551c94aSIdo Barnea				    e1000_ms_force_master :
1028a551c94aSIdo Barnea				    e1000_ms_force_slave) : e1000_ms_auto;
1029a551c94aSIdo Barnea
1030a551c94aSIdo Barnea	switch (hw->phy.ms_type) {
1031a551c94aSIdo Barnea	case e1000_ms_force_master:
1032a551c94aSIdo Barnea		phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1033a551c94aSIdo Barnea		break;
1034a551c94aSIdo Barnea	case e1000_ms_force_slave:
1035a551c94aSIdo Barnea		phy_data |= CR_1000T_MS_ENABLE;
1036a551c94aSIdo Barnea		phy_data &= ~(CR_1000T_MS_VALUE);
1037a551c94aSIdo Barnea		break;
1038a551c94aSIdo Barnea	case e1000_ms_auto:
1039a551c94aSIdo Barnea		phy_data &= ~CR_1000T_MS_ENABLE;
1040a551c94aSIdo Barnea		/* fall-through */
1041a551c94aSIdo Barnea	default:
1042a551c94aSIdo Barnea		break;
1043a551c94aSIdo Barnea	}
1044a551c94aSIdo Barnea
1045a551c94aSIdo Barnea	return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1046a551c94aSIdo Barnea}
1047a551c94aSIdo Barnea
1048a551c94aSIdo Barnea/**
1049a551c94aSIdo Barnea *  e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1050a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1051a551c94aSIdo Barnea *
1052a551c94aSIdo Barnea *  Sets up Carrier-sense on Transmit and downshift values.
1053a551c94aSIdo Barnea **/
1054a551c94aSIdo Barneas32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1055a551c94aSIdo Barnea{
1056a551c94aSIdo Barnea	s32 ret_val;
1057a551c94aSIdo Barnea	u16 phy_data;
1058a551c94aSIdo Barnea
1059a551c94aSIdo Barnea	DEBUGFUNC("e1000_copper_link_setup_82577");
1060a551c94aSIdo Barnea
1061a551c94aSIdo Barnea	if (hw->phy.type == e1000_phy_82580) {
1062a551c94aSIdo Barnea		ret_val = hw->phy.ops.reset(hw);
1063a551c94aSIdo Barnea		if (ret_val) {
1064a551c94aSIdo Barnea			DEBUGOUT("Error resetting the PHY.\n");
1065a551c94aSIdo Barnea			return ret_val;
1066a551c94aSIdo Barnea		}
1067a551c94aSIdo Barnea	}
1068a551c94aSIdo Barnea
1069a551c94aSIdo Barnea	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1070a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1071a551c94aSIdo Barnea	if (ret_val)
1072a551c94aSIdo Barnea		return ret_val;
1073a551c94aSIdo Barnea
1074a551c94aSIdo Barnea	phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1075a551c94aSIdo Barnea
1076a551c94aSIdo Barnea	/* Enable downshift */
1077a551c94aSIdo Barnea	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1078a551c94aSIdo Barnea
1079a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1080a551c94aSIdo Barnea	if (ret_val)
1081a551c94aSIdo Barnea		return ret_val;
1082a551c94aSIdo Barnea
1083a551c94aSIdo Barnea	/* Set MDI/MDIX mode */
1084a551c94aSIdo Barnea	ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1085a551c94aSIdo Barnea	if (ret_val)
1086a551c94aSIdo Barnea		return ret_val;
1087a551c94aSIdo Barnea	phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1088a551c94aSIdo Barnea	/* Options:
1089a551c94aSIdo Barnea	 *   0 - Auto (default)
1090a551c94aSIdo Barnea	 *   1 - MDI mode
1091a551c94aSIdo Barnea	 *   2 - MDI-X mode
1092a551c94aSIdo Barnea	 */
1093a551c94aSIdo Barnea	switch (hw->phy.mdix) {
1094a551c94aSIdo Barnea	case 1:
1095a551c94aSIdo Barnea		break;
1096a551c94aSIdo Barnea	case 2:
1097a551c94aSIdo Barnea		phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1098a551c94aSIdo Barnea		break;
1099a551c94aSIdo Barnea	case 0:
1100a551c94aSIdo Barnea	default:
1101a551c94aSIdo Barnea		phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1102a551c94aSIdo Barnea		break;
1103a551c94aSIdo Barnea	}
1104a551c94aSIdo Barnea	ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1105a551c94aSIdo Barnea	if (ret_val)
1106a551c94aSIdo Barnea		return ret_val;
1107a551c94aSIdo Barnea
1108a551c94aSIdo Barnea	return e1000_set_master_slave_mode(hw);
1109a551c94aSIdo Barnea}
1110a551c94aSIdo Barnea
1111a551c94aSIdo Barnea/**
1112a551c94aSIdo Barnea *  e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1113a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1114a551c94aSIdo Barnea *
1115a551c94aSIdo Barnea *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
1116a551c94aSIdo Barnea *  and downshift values are set also.
1117a551c94aSIdo Barnea **/
1118a551c94aSIdo Barneas32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1119a551c94aSIdo Barnea{
1120a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1121a551c94aSIdo Barnea	s32 ret_val;
1122a551c94aSIdo Barnea	u16 phy_data;
1123a551c94aSIdo Barnea
1124a551c94aSIdo Barnea	DEBUGFUNC("e1000_copper_link_setup_m88");
1125a551c94aSIdo Barnea
1126a551c94aSIdo Barnea
1127a551c94aSIdo Barnea	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1128a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1129a551c94aSIdo Barnea	if (ret_val)
1130a551c94aSIdo Barnea		return ret_val;
1131a551c94aSIdo Barnea
1132a551c94aSIdo Barnea	/* For BM PHY this bit is downshift enable */
1133a551c94aSIdo Barnea	if (phy->type != e1000_phy_bm)
1134a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1135a551c94aSIdo Barnea
1136a551c94aSIdo Barnea	/* Options:
1137a551c94aSIdo Barnea	 *   MDI/MDI-X = 0 (default)
1138a551c94aSIdo Barnea	 *   0 - Auto for all speeds
1139a551c94aSIdo Barnea	 *   1 - MDI mode
1140a551c94aSIdo Barnea	 *   2 - MDI-X mode
1141a551c94aSIdo Barnea	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1142a551c94aSIdo Barnea	 */
1143a551c94aSIdo Barnea	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1144a551c94aSIdo Barnea
1145a551c94aSIdo Barnea	switch (phy->mdix) {
1146a551c94aSIdo Barnea	case 1:
1147a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1148a551c94aSIdo Barnea		break;
1149a551c94aSIdo Barnea	case 2:
1150a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1151a551c94aSIdo Barnea		break;
1152a551c94aSIdo Barnea	case 3:
1153a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1154a551c94aSIdo Barnea		break;
1155a551c94aSIdo Barnea	case 0:
1156a551c94aSIdo Barnea	default:
1157a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1158a551c94aSIdo Barnea		break;
1159a551c94aSIdo Barnea	}
1160a551c94aSIdo Barnea
1161a551c94aSIdo Barnea	/* Options:
1162a551c94aSIdo Barnea	 *   disable_polarity_correction = 0 (default)
1163a551c94aSIdo Barnea	 *       Automatic Correction for Reversed Cable Polarity
1164a551c94aSIdo Barnea	 *   0 - Disabled
1165a551c94aSIdo Barnea	 *   1 - Enabled
1166a551c94aSIdo Barnea	 */
1167a551c94aSIdo Barnea	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1168a551c94aSIdo Barnea	if (phy->disable_polarity_correction)
1169a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1170a551c94aSIdo Barnea
1171a551c94aSIdo Barnea	/* Enable downshift on BM (disabled by default) */
1172a551c94aSIdo Barnea	if (phy->type == e1000_phy_bm) {
1173a551c94aSIdo Barnea		/* For 82574/82583, first disable then enable downshift */
1174a551c94aSIdo Barnea		if (phy->id == BME1000_E_PHY_ID_R2) {
1175a551c94aSIdo Barnea			phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1176a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1177a551c94aSIdo Barnea						     phy_data);
1178a551c94aSIdo Barnea			if (ret_val)
1179a551c94aSIdo Barnea				return ret_val;
1180a551c94aSIdo Barnea			/* Commit the changes. */
1181a551c94aSIdo Barnea			ret_val = phy->ops.commit(hw);
1182a551c94aSIdo Barnea			if (ret_val) {
1183a551c94aSIdo Barnea				DEBUGOUT("Error committing the PHY changes\n");
1184a551c94aSIdo Barnea				return ret_val;
1185a551c94aSIdo Barnea			}
1186a551c94aSIdo Barnea		}
1187a551c94aSIdo Barnea
1188a551c94aSIdo Barnea		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1189a551c94aSIdo Barnea	}
1190a551c94aSIdo Barnea
1191a551c94aSIdo Barnea	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1192a551c94aSIdo Barnea	if (ret_val)
1193a551c94aSIdo Barnea		return ret_val;
1194a551c94aSIdo Barnea
1195a551c94aSIdo Barnea	if ((phy->type == e1000_phy_m88) &&
1196a551c94aSIdo Barnea	    (phy->revision < E1000_REVISION_4) &&
1197a551c94aSIdo Barnea	    (phy->id != BME1000_E_PHY_ID_R2)) {
1198a551c94aSIdo Barnea		/* Force TX_CLK in the Extended PHY Specific Control Register
1199a551c94aSIdo Barnea		 * to 25MHz clock.
1200a551c94aSIdo Barnea		 */
1201a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1202a551c94aSIdo Barnea					    &phy_data);
1203a551c94aSIdo Barnea		if (ret_val)
1204a551c94aSIdo Barnea			return ret_val;
1205a551c94aSIdo Barnea
1206a551c94aSIdo Barnea		phy_data |= M88E1000_EPSCR_TX_CLK_25;
1207a551c94aSIdo Barnea
1208a551c94aSIdo Barnea		if ((phy->revision == E1000_REVISION_2) &&
1209a551c94aSIdo Barnea		    (phy->id == M88E1111_I_PHY_ID)) {
1210a551c94aSIdo Barnea			/* 82573L PHY - set the downshift counter to 5x. */
1211a551c94aSIdo Barnea			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1212a551c94aSIdo Barnea			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1213a551c94aSIdo Barnea		} else {
1214a551c94aSIdo Barnea			/* Configure Master and Slave downshift values */
1215a551c94aSIdo Barnea			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1216a551c94aSIdo Barnea				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1217a551c94aSIdo Barnea			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1218a551c94aSIdo Barnea				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1219a551c94aSIdo Barnea		}
1220a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1221a551c94aSIdo Barnea					     phy_data);
1222a551c94aSIdo Barnea		if (ret_val)
1223a551c94aSIdo Barnea			return ret_val;
1224a551c94aSIdo Barnea	}
1225a551c94aSIdo Barnea
1226a551c94aSIdo Barnea	if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1227a551c94aSIdo Barnea		/* Set PHY page 0, register 29 to 0x0003 */
1228a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1229a551c94aSIdo Barnea		if (ret_val)
1230a551c94aSIdo Barnea			return ret_val;
1231a551c94aSIdo Barnea
1232a551c94aSIdo Barnea		/* Set PHY page 0, register 30 to 0x0000 */
1233a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1234a551c94aSIdo Barnea		if (ret_val)
1235a551c94aSIdo Barnea			return ret_val;
1236a551c94aSIdo Barnea	}
1237a551c94aSIdo Barnea
1238a551c94aSIdo Barnea	/* Commit the changes. */
1239a551c94aSIdo Barnea	ret_val = phy->ops.commit(hw);
1240a551c94aSIdo Barnea	if (ret_val) {
1241a551c94aSIdo Barnea		DEBUGOUT("Error committing the PHY changes\n");
1242a551c94aSIdo Barnea		return ret_val;
1243a551c94aSIdo Barnea	}
1244a551c94aSIdo Barnea
1245a551c94aSIdo Barnea	if (phy->type == e1000_phy_82578) {
1246a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1247a551c94aSIdo Barnea					    &phy_data);
1248a551c94aSIdo Barnea		if (ret_val)
1249a551c94aSIdo Barnea			return ret_val;
1250a551c94aSIdo Barnea
1251a551c94aSIdo Barnea		/* 82578 PHY - set the downshift count to 1x. */
1252a551c94aSIdo Barnea		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1253a551c94aSIdo Barnea		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1254a551c94aSIdo Barnea		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1255a551c94aSIdo Barnea					     phy_data);
1256a551c94aSIdo Barnea		if (ret_val)
1257a551c94aSIdo Barnea			return ret_val;
1258a551c94aSIdo Barnea	}
1259a551c94aSIdo Barnea
1260a551c94aSIdo Barnea	return E1000_SUCCESS;
1261a551c94aSIdo Barnea}
1262a551c94aSIdo Barnea
1263a551c94aSIdo Barnea/**
1264a551c94aSIdo Barnea *  e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1265a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1266a551c94aSIdo Barnea *
1267a551c94aSIdo Barnea *  Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1268a551c94aSIdo Barnea *  Also enables and sets the downshift parameters.
1269a551c94aSIdo Barnea **/
1270a551c94aSIdo Barneas32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1271a551c94aSIdo Barnea{
1272a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1273a551c94aSIdo Barnea	s32 ret_val;
1274a551c94aSIdo Barnea	u16 phy_data;
1275a551c94aSIdo Barnea
1276a551c94aSIdo Barnea	DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1277a551c94aSIdo Barnea
1278a551c94aSIdo Barnea
1279a551c94aSIdo Barnea	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1280a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1281a551c94aSIdo Barnea	if (ret_val)
1282a551c94aSIdo Barnea		return ret_val;
1283a551c94aSIdo Barnea
1284a551c94aSIdo Barnea	/* Options:
1285a551c94aSIdo Barnea	 *   MDI/MDI-X = 0 (default)
1286a551c94aSIdo Barnea	 *   0 - Auto for all speeds
1287a551c94aSIdo Barnea	 *   1 - MDI mode
1288a551c94aSIdo Barnea	 *   2 - MDI-X mode
1289a551c94aSIdo Barnea	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1290a551c94aSIdo Barnea	 */
1291a551c94aSIdo Barnea	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1292a551c94aSIdo Barnea
1293a551c94aSIdo Barnea	switch (phy->mdix) {
1294a551c94aSIdo Barnea	case 1:
1295a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1296a551c94aSIdo Barnea		break;
1297a551c94aSIdo Barnea	case 2:
1298a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1299a551c94aSIdo Barnea		break;
1300a551c94aSIdo Barnea	case 3:
1301a551c94aSIdo Barnea		/* M88E1112 does not support this mode) */
1302a551c94aSIdo Barnea		if (phy->id != M88E1112_E_PHY_ID) {
1303a551c94aSIdo Barnea			phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1304a551c94aSIdo Barnea			break;
1305a551c94aSIdo Barnea		}
1306a551c94aSIdo Barnea	case 0:
1307a551c94aSIdo Barnea	default:
1308a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1309a551c94aSIdo Barnea		break;
1310a551c94aSIdo Barnea	}
1311a551c94aSIdo Barnea
1312a551c94aSIdo Barnea	/* Options:
1313a551c94aSIdo Barnea	 *   disable_polarity_correction = 0 (default)
1314a551c94aSIdo Barnea	 *       Automatic Correction for Reversed Cable Polarity
1315a551c94aSIdo Barnea	 *   0 - Disabled
1316a551c94aSIdo Barnea	 *   1 - Enabled
1317a551c94aSIdo Barnea	 */
1318a551c94aSIdo Barnea	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1319a551c94aSIdo Barnea	if (phy->disable_polarity_correction)
1320a551c94aSIdo Barnea		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1321a551c94aSIdo Barnea
1322a551c94aSIdo Barnea	/* Enable downshift and setting it to X6 */
1323a551c94aSIdo Barnea	if (phy->id == M88E1543_E_PHY_ID) {
1324a551c94aSIdo Barnea		phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1325a551c94aSIdo Barnea		ret_val =
1326a551c94aSIdo Barnea		    phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1327a551c94aSIdo Barnea		if (ret_val)
1328a551c94aSIdo Barnea			return ret_val;
1329a551c94aSIdo Barnea
1330a551c94aSIdo Barnea		ret_val = phy->ops.commit(hw);
1331a551c94aSIdo Barnea		if (ret_val) {
1332a551c94aSIdo Barnea			DEBUGOUT("Error committing the PHY changes\n");
1333a551c94aSIdo Barnea			return ret_val;
1334a551c94aSIdo Barnea		}
1335a551c94aSIdo Barnea	}
1336a551c94aSIdo Barnea
1337a551c94aSIdo Barnea	phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1338a551c94aSIdo Barnea	phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1339a551c94aSIdo Barnea	phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1340a551c94aSIdo Barnea
1341a551c94aSIdo Barnea	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1342a551c94aSIdo Barnea	if (ret_val)
1343a551c94aSIdo Barnea		return ret_val;
1344a551c94aSIdo Barnea
1345a551c94aSIdo Barnea	/* Commit the changes. */
1346a551c94aSIdo Barnea	ret_val = phy->ops.commit(hw);
1347a551c94aSIdo Barnea	if (ret_val) {
1348a551c94aSIdo Barnea		DEBUGOUT("Error committing the PHY changes\n");
1349a551c94aSIdo Barnea		return ret_val;
1350a551c94aSIdo Barnea	}
1351a551c94aSIdo Barnea
1352a551c94aSIdo Barnea	ret_val = e1000_set_master_slave_mode(hw);
1353a551c94aSIdo Barnea	if (ret_val)
1354a551c94aSIdo Barnea		return ret_val;
1355a551c94aSIdo Barnea
1356a551c94aSIdo Barnea	return E1000_SUCCESS;
1357a551c94aSIdo Barnea}
1358a551c94aSIdo Barnea
1359a551c94aSIdo Barnea/**
1360a551c94aSIdo Barnea *  e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1361a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1362a551c94aSIdo Barnea *
1363a551c94aSIdo Barnea *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1364a551c94aSIdo Barnea *  igp PHY's.
1365a551c94aSIdo Barnea **/
1366a551c94aSIdo Barneas32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1367a551c94aSIdo Barnea{
1368a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1369a551c94aSIdo Barnea	s32 ret_val;
1370a551c94aSIdo Barnea	u16 data;
1371a551c94aSIdo Barnea
1372a551c94aSIdo Barnea	DEBUGFUNC("e1000_copper_link_setup_igp");
1373a551c94aSIdo Barnea
1374a551c94aSIdo Barnea
1375a551c94aSIdo Barnea	ret_val = hw->phy.ops.reset(hw);
1376a551c94aSIdo Barnea	if (ret_val) {
1377a551c94aSIdo Barnea		DEBUGOUT("Error resetting the PHY.\n");
1378a551c94aSIdo Barnea		return ret_val;
1379a551c94aSIdo Barnea	}
1380a551c94aSIdo Barnea
1381a551c94aSIdo Barnea	/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1382a551c94aSIdo Barnea	 * timeout issues when LFS is enabled.
1383a551c94aSIdo Barnea	 */
1384a551c94aSIdo Barnea	msec_delay(100);
1385a551c94aSIdo Barnea
1386a551c94aSIdo Barnea	/* The NVM settings will configure LPLU in D3 for
1387a551c94aSIdo Barnea	 * non-IGP1 PHYs.
1388a551c94aSIdo Barnea	 */
1389a551c94aSIdo Barnea	if (phy->type == e1000_phy_igp) {
1390a551c94aSIdo Barnea		/* disable lplu d3 during driver init */
1391a551c94aSIdo Barnea		ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1392a551c94aSIdo Barnea		if (ret_val) {
1393a551c94aSIdo Barnea			DEBUGOUT("Error Disabling LPLU D3\n");
1394a551c94aSIdo Barnea			return ret_val;
1395a551c94aSIdo Barnea		}
1396a551c94aSIdo Barnea	}
1397a551c94aSIdo Barnea
1398a551c94aSIdo Barnea	/* disable lplu d0 during driver init */
1399a551c94aSIdo Barnea	if (hw->phy.ops.set_d0_lplu_state) {
1400a551c94aSIdo Barnea		ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1401a551c94aSIdo Barnea		if (ret_val) {
1402a551c94aSIdo Barnea			DEBUGOUT("Error Disabling LPLU D0\n");
1403a551c94aSIdo Barnea			return ret_val;
1404a551c94aSIdo Barnea		}
1405a551c94aSIdo Barnea	}
1406a551c94aSIdo Barnea	/* Configure mdi-mdix settings */
1407a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1408a551c94aSIdo Barnea	if (ret_val)
1409a551c94aSIdo Barnea		return ret_val;
1410a551c94aSIdo Barnea
1411a551c94aSIdo Barnea	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1412a551c94aSIdo Barnea
1413a551c94aSIdo Barnea	switch (phy->mdix) {
1414a551c94aSIdo Barnea	case 1:
1415a551c94aSIdo Barnea		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1416a551c94aSIdo Barnea		break;
1417a551c94aSIdo Barnea	case 2:
1418a551c94aSIdo Barnea		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1419a551c94aSIdo Barnea		break;
1420a551c94aSIdo Barnea	case 0:
1421a551c94aSIdo Barnea	default:
1422a551c94aSIdo Barnea		data |= IGP01E1000_PSCR_AUTO_MDIX;
1423a551c94aSIdo Barnea		break;
1424a551c94aSIdo Barnea	}
1425a551c94aSIdo Barnea	ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1426a551c94aSIdo Barnea	if (ret_val)
1427a551c94aSIdo Barnea		return ret_val;
1428a551c94aSIdo Barnea
1429a551c94aSIdo Barnea	/* set auto-master slave resolution settings */
1430a551c94aSIdo Barnea	if (hw->mac.autoneg) {
1431a551c94aSIdo Barnea		/* when autonegotiation advertisement is only 1000Mbps then we
1432a551c94aSIdo Barnea		 * should disable SmartSpeed and enable Auto MasterSlave
1433a551c94aSIdo Barnea		 * resolution as hardware default.
1434a551c94aSIdo Barnea		 */
1435a551c94aSIdo Barnea		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1436a551c94aSIdo Barnea			/* Disable SmartSpeed */
1437a551c94aSIdo Barnea			ret_val = phy->ops.read_reg(hw,
1438a551c94aSIdo Barnea						    IGP01E1000_PHY_PORT_CONFIG,
1439a551c94aSIdo Barnea						    &data);
1440a551c94aSIdo Barnea			if (ret_val)
1441a551c94aSIdo Barnea				return ret_val;
1442a551c94aSIdo Barnea
1443a551c94aSIdo Barnea			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1444a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw,
1445a551c94aSIdo Barnea						     IGP01E1000_PHY_PORT_CONFIG,
1446a551c94aSIdo Barnea						     data);
1447a551c94aSIdo Barnea			if (ret_val)
1448a551c94aSIdo Barnea				return ret_val;
1449a551c94aSIdo Barnea
1450a551c94aSIdo Barnea			/* Set auto Master/Slave resolution process */
1451a551c94aSIdo Barnea			ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1452a551c94aSIdo Barnea			if (ret_val)
1453a551c94aSIdo Barnea				return ret_val;
1454a551c94aSIdo Barnea
1455a551c94aSIdo Barnea			data &= ~CR_1000T_MS_ENABLE;
1456a551c94aSIdo Barnea			ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1457a551c94aSIdo Barnea			if (ret_val)
1458a551c94aSIdo Barnea				return ret_val;
1459a551c94aSIdo Barnea		}
1460a551c94aSIdo Barnea
1461a551c94aSIdo Barnea		ret_val = e1000_set_master_slave_mode(hw);
1462a551c94aSIdo Barnea	}
1463a551c94aSIdo Barnea
1464a551c94aSIdo Barnea	return ret_val;
1465a551c94aSIdo Barnea}
1466a551c94aSIdo Barnea
1467a551c94aSIdo Barnea/**
1468a551c94aSIdo Barnea *  e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1469a551c94aSIdo Barnea *  @hw: pointer to the HW structure
1470a551c94aSIdo Barnea *
1471a551c94aSIdo Barnea *  Reads the MII auto-neg advertisement register and/or the 1000T control
1472a551c94aSIdo Barnea *  register and if the PHY is already setup for auto-negotiation, then
1473a551c94aSIdo Barnea *  return successful.  Otherwise, setup advertisement and flow control to
1474a551c94aSIdo Barnea *  the appropriate values for the wanted auto-negotiation.
1475a551c94aSIdo Barnea **/
1476a551c94aSIdo Barneas32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1477a551c94aSIdo Barnea{
1478a551c94aSIdo Barnea	struct e1000_phy_info *phy = &hw->phy;
1479a551c94aSIdo Barnea	s32 ret_val;
1480a551c94aSIdo Barnea	u16 mii_autoneg_adv_reg;
1481a551c94aSIdo Barnea	u16 mii_1000t_ctrl_reg = 0;
1482a551c94aSIdo Barnea
1483a551c94aSIdo Barnea	DEBUGFUNC("e1000_phy_setup_autoneg");
1484a551c94aSIdo Barnea
1485a551c94aSIdo Barnea	phy->autoneg_advertised &= phy->autoneg_mask;
1486a551c94aSIdo Barnea
1487a551c94aSIdo Barnea	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
1488a551c94aSIdo Barnea	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1489a551c94aSIdo Barnea	if (ret_val)
1490a551c94aSIdo Barnea		return ret_val;
1491a551c94aSIdo Barnea
1492a551c94aSIdo Barnea	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1493a551c94aSIdo Barnea		/* Read the MII 1000Base-T Control Register (Address 9). */
1494a551c94aSIdo Barnea		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1495a551c94aSIdo Barnea					    &mii_1000t_ctrl_reg);
1496a551c94aSIdo Barnea		if (ret_val)
1497a551c94aSIdo Barnea			return ret_val;
1498a551c94aSIdo Barnea	}
1499a551c94aSIdo Barnea
1500a551c94aSIdo Barnea	/* Need to parse both autoneg_advertised and fc and set up
1501a551c94aSIdo Barnea	 * the appropriate PHY registers.  First we will parse for
1502a551c94aSIdo Barnea	 * autoneg_advertised software override.  Since we can advertise
1503a551c94aSIdo Barnea	 * a plethora of combinations, we need to check each bit
1504a551c94aSIdo Barnea	 * individually.
1505a551c94aSIdo Barnea	 */
1506a551c94aSIdo Barnea
1507a551c94aSIdo Barnea	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
1508a551c94aSIdo Barnea	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1509a551c94aSIdo Barnea	 * the  1000Base-T Control Register (Address 9).
1510a551c94aSIdo Barnea	 */
1511a551c94aSIdo Barnea	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1512a551c94aSIdo Barnea				 NWAY_AR_100TX_HD_CAPS |
1513a551c94aSIdo Barnea				 NWAY_AR_10T_FD_CAPS   |
1514a551c94aSIdo Barnea				 NWAY_AR_10T_HD_CAPS);
1515a551c94aSIdo Barnea	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1516a551c94aSIdo Barnea
1517a551c94aSIdo Barnea	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1518a551c94aSIdo Barnea
1519a551c94aSIdo Barnea	/* Do we want to advertise 10 Mb Half Duplex? */
1520a551c94aSIdo Barnea	if (