1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
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18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34#ifndef _E1000_VF_H_
35#define _E1000_VF_H_
36
37#include "e1000_osdep.h"
38#include "e1000_regs.h"
39#include "e1000_defines.h"
40
41struct e1000_hw;
42
43#define E1000_DEV_ID_82576_VF		0x10CA
44#define E1000_DEV_ID_I350_VF		0x1520
45
46#define E1000_VF_INIT_TIMEOUT		200 /* Num of retries to clear RSTI */
47
48/* Additional Descriptor Control definitions */
49#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
50#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
51
52/* SRRCTL bit definitions */
53#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
54				 (0x0C00C + ((_n) * 0x40)))
55#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
56#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
57#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
58#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
59#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
60#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
61#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
62#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
63#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
64#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
65#define E1000_SRRCTL_DROP_EN			0x80000000
66
67#define E1000_SRRCTL_BSIZEPKT_MASK	0x0000007F
68#define E1000_SRRCTL_BSIZEHDR_MASK	0x00003F00
69
70/* Interrupt Defines */
71#define E1000_EICR		0x01580 /* Ext. Interrupt Cause Read - R/clr */
72#define E1000_EITR(_n)		(0x01680 + ((_n) << 2))
73#define E1000_EICS		0x01520 /* Ext. Intr Cause Set -W0 */
74#define E1000_EIMS		0x01524 /* Ext. Intr Mask Set/Read -RW */
75#define E1000_EIMC		0x01528 /* Ext. Intr Mask Clear -WO */
76#define E1000_EIAC		0x0152C /* Ext. Intr Auto Clear -RW */
77#define E1000_EIAM		0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */
78#define E1000_IVAR0		0x01700 /* Intr Vector Alloc (array) -RW */
79#define E1000_IVAR_MISC		0x01740 /* IVAR for "other" causes -RW */
80#define E1000_IVAR_VALID	0x80
81
82/* Receive Descriptor - Advanced */
83union e1000_adv_rx_desc {
84	struct {
85		u64 pkt_addr; /* Packet buffer address */
86		u64 hdr_addr; /* Header buffer address */
87	} read;
88	struct {
89		struct {
90			union {
91				u32 data;
92				struct {
93					/* RSS type, Packet type */
94					u16 pkt_info;
95					/* Split Header, header buffer len */
96					u16 hdr_info;
97				} hs_rss;
98			} lo_dword;
99			union {
100				u32 rss; /* RSS Hash */
101				struct {
102					u16 ip_id; /* IP id */
103					u16 csum; /* Packet Checksum */
104				} csum_ip;
105			} hi_dword;
106		} lower;
107		struct {
108			u32 status_error; /* ext status/error */
109			u16 length; /* Packet length */
110			u16 vlan; /* VLAN tag */
111		} upper;
112	} wb;  /* writeback */
113};
114
115#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
116#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
117
118/* Transmit Descriptor - Advanced */
119union e1000_adv_tx_desc {
120	struct {
121		u64 buffer_addr;    /* Address of descriptor's data buf */
122		u32 cmd_type_len;
123		u32 olinfo_status;
124	} read;
125	struct {
126		u64 rsvd;       /* Reserved */
127		u32 nxtseq_seed;
128		u32 status;
129	} wb;
130};
131
132/* Adv Transmit Descriptor Config Masks */
133#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
134#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
135#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
136#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
137#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
138#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
139#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
140#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
141#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
142
143/* Context descriptors */
144struct e1000_adv_tx_context_desc {
145	u32 vlan_macip_lens;
146	u32 seqnum_seed;
147	u32 type_tucmd_mlhl;
148	u32 mss_l4len_idx;
149};
150
151#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
152#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
153#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
154#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
155#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
156
157enum e1000_mac_type {
158	e1000_undefined = 0,
159	e1000_vfadapt,
160	e1000_vfadapt_i350,
161	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
162};
163
164struct e1000_vf_stats {
165	u64 base_gprc;
166	u64 base_gptc;
167	u64 base_gorc;
168	u64 base_gotc;
169	u64 base_mprc;
170	u64 base_gotlbc;
171	u64 base_gptlbc;
172	u64 base_gorlbc;
173	u64 base_gprlbc;
174
175	u32 last_gprc;
176	u32 last_gptc;
177	u32 last_gorc;
178	u32 last_gotc;
179	u32 last_mprc;
180	u32 last_gotlbc;
181	u32 last_gptlbc;
182	u32 last_gorlbc;
183	u32 last_gprlbc;
184
185	u64 gprc;
186	u64 gptc;
187	u64 gorc;
188	u64 gotc;
189	u64 mprc;
190	u64 gotlbc;
191	u64 gptlbc;
192	u64 gorlbc;
193	u64 gprlbc;
194};
195
196#include "e1000_mbx.h"
197
198struct e1000_mac_operations {
199	/* Function pointers for the MAC. */
200	s32  (*init_params)(struct e1000_hw *);
201	s32  (*check_for_link)(struct e1000_hw *);
202	void (*clear_vfta)(struct e1000_hw *);
203	s32  (*get_bus_info)(struct e1000_hw *);
204	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
205	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
206	s32  (*reset_hw)(struct e1000_hw *);
207	s32  (*init_hw)(struct e1000_hw *);
208	s32  (*setup_link)(struct e1000_hw *);
209	void (*write_vfta)(struct e1000_hw *, u32, u32);
210	int  (*rar_set)(struct e1000_hw *, u8*, u32);
211	s32  (*read_mac_addr)(struct e1000_hw *);
212};
213
214struct e1000_mac_info {
215	struct e1000_mac_operations ops;
216	u8 addr[6];
217	u8 perm_addr[6];
218
219	enum e1000_mac_type type;
220
221	u16 mta_reg_count;
222	u16 rar_entry_count;
223
224	bool get_link_status;
225};
226
227struct e1000_mbx_operations {
228	s32 (*init_params)(struct e1000_hw *hw);
229	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
230	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
231	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
232	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
233	s32 (*check_for_msg)(struct e1000_hw *, u16);
234	s32 (*check_for_ack)(struct e1000_hw *, u16);
235	s32 (*check_for_rst)(struct e1000_hw *, u16);
236};
237
238struct e1000_mbx_stats {
239	u32 msgs_tx;
240	u32 msgs_rx;
241
242	u32 acks;
243	u32 reqs;
244	u32 rsts;
245};
246
247struct e1000_mbx_info {
248	struct e1000_mbx_operations ops;
249	struct e1000_mbx_stats stats;
250	u32 timeout;
251	u32 usec_delay;
252	u16 size;
253};
254
255struct e1000_dev_spec_vf {
256	u32 vf_number;
257	u32 v2p_mailbox;
258};
259
260struct e1000_hw {
261	void *back;
262
263	u8 *hw_addr;
264	u8 *flash_address;
265	unsigned long io_base;
266
267	struct e1000_mac_info  mac;
268	struct e1000_mbx_info mbx;
269
270	union {
271		struct e1000_dev_spec_vf vf;
272	} dev_spec;
273
274	u16 device_id;
275	u16 subsystem_vendor_id;
276	u16 subsystem_device_id;
277	u16 vendor_id;
278
279	u8  revision_id;
280};
281
282enum e1000_promisc_type {
283	e1000_promisc_disabled = 0,   /* all promisc modes disabled */
284	e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
285	e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
286	e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
287	e1000_num_promisc_types
288};
289
290/* These functions must be implemented by drivers */
291s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
292void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
293void e1000_rlpml_set_vf(struct e1000_hw *, u16);
294s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
295#endif /* _E1000_VF_H_ */
296