1/*******************************************************************************
2
3Copyright (c) 2013 - 2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34#include "i40e_diag.h"
35#include "i40e_prototype.h"
36
37/**
38 * i40e_diag_set_loopback
39 * @hw: pointer to the hw struct
40 * @mode: loopback mode
41 *
42 * Set chosen loopback mode
43 **/
44enum i40e_status_code i40e_diag_set_loopback(struct i40e_hw *hw,
45					     enum i40e_lb_mode mode)
46{
47	enum i40e_status_code ret_code = I40E_SUCCESS;
48
49	if (i40e_aq_set_lb_modes(hw, mode, NULL))
50		ret_code = I40E_ERR_DIAG_TEST_FAILED;
51
52	return ret_code;
53}
54
55/**
56 * i40e_diag_reg_pattern_test
57 * @hw: pointer to the hw struct
58 * @reg: reg to be tested
59 * @mask: bits to be touched
60 **/
61static enum i40e_status_code i40e_diag_reg_pattern_test(struct i40e_hw *hw,
62							u32 reg, u32 mask)
63{
64	const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
65	u32 pat, val, orig_val;
66	int i;
67
68	orig_val = rd32(hw, reg);
69	for (i = 0; i < ARRAY_SIZE(patterns); i++) {
70		pat = patterns[i];
71		wr32(hw, reg, (pat & mask));
72		val = rd32(hw, reg);
73		if ((val & mask) != (pat & mask)) {
74			return I40E_ERR_DIAG_TEST_FAILED;
75		}
76	}
77
78	wr32(hw, reg, orig_val);
79	val = rd32(hw, reg);
80	if (val != orig_val) {
81		return I40E_ERR_DIAG_TEST_FAILED;
82	}
83
84	return I40E_SUCCESS;
85}
86
87struct i40e_diag_reg_test_info i40e_reg_list[] = {
88	/* offset               mask         elements   stride */
89	{I40E_QTX_CTL(0),       0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
90	{I40E_PFINT_ITR0(0),    0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
91	{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
92	{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
93	{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
94	{I40E_PFINT_STAT_CTL0,  0x0000000C, 1, 0},
95	{I40E_PFINT_LNKLST0,    0x00001FFF, 1, 0},
96	{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
97	{I40E_QINT_TQCTL(0),    0x000000FF, 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
98	{I40E_QINT_RQCTL(0),    0x000000FF, 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
99	{I40E_PFINT_ICR0_ENA,   0xF7F20000, 1, 0},
100	{ 0 }
101};
102
103/**
104 * i40e_diag_reg_test
105 * @hw: pointer to the hw struct
106 *
107 * Perform registers diagnostic test
108 **/
109enum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw)
110{
111	enum i40e_status_code ret_code = I40E_SUCCESS;
112	u32 reg, mask;
113	u32 i, j;
114
115	for (i = 0; i40e_reg_list[i].offset != 0 &&
116					     ret_code == I40E_SUCCESS; i++) {
117
118		/* set actual reg range for dynamically allocated resources */
119		if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
120		    hw->func_caps.num_tx_qp != 0)
121			i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
122		if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
123		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
124		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
125		     i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
126		     i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
127		    hw->func_caps.num_msix_vectors != 0)
128			i40e_reg_list[i].elements =
129				hw->func_caps.num_msix_vectors - 1;
130
131		/* test register access */
132		mask = i40e_reg_list[i].mask;
133		for (j = 0; j < i40e_reg_list[i].elements &&
134			    ret_code == I40E_SUCCESS; j++) {
135			reg = i40e_reg_list[i].offset
136				+ (j * i40e_reg_list[i].stride);
137			ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
138		}
139	}
140
141	return ret_code;
142}
143
144/**
145 * i40e_diag_eeprom_test
146 * @hw: pointer to the hw struct
147 *
148 * Perform EEPROM diagnostic test
149 **/
150enum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw)
151{
152	enum i40e_status_code ret_code;
153	u16 reg_val;
154
155	/* read NVM control word and if NVM valid, validate EEPROM checksum*/
156	ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
157	if ((ret_code == I40E_SUCCESS) &&
158	    ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
159	     BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))
160		return i40e_validate_nvm_checksum(hw, NULL);
161	else
162		return I40E_ERR_DIAG_TEST_FAILED;
163}
164
165/**
166 * i40e_diag_fw_alive_test
167 * @hw: pointer to the hw struct
168 *
169 * Perform FW alive diagnostic test
170 **/
171enum i40e_status_code i40e_diag_fw_alive_test(struct i40e_hw *hw)
172{
173	UNREFERENCED_1PARAMETER(hw);
174	return I40E_SUCCESS;
175}
176