i40e_rxtx_vec_sse.c revision 9ca4a157
1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <stdint.h>
35#include <rte_ethdev.h>
36#include <rte_malloc.h>
37
38#include "base/i40e_prototype.h"
39#include "base/i40e_type.h"
40#include "i40e_ethdev.h"
41#include "i40e_rxtx.h"
42#include "i40e_rxtx_vec_common.h"
43
44#include <tmmintrin.h>
45
46#ifndef __INTEL_COMPILER
47#pragma GCC diagnostic ignored "-Wcast-qual"
48#endif
49
50static inline void
51i40e_rxq_rearm(struct i40e_rx_queue *rxq)
52{
53	int i;
54	uint16_t rx_id;
55	volatile union i40e_rx_desc *rxdp;
56	struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
57	struct rte_mbuf *mb0, *mb1;
58	__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
59			RTE_PKTMBUF_HEADROOM);
60	__m128i dma_addr0, dma_addr1;
61
62	rxdp = rxq->rx_ring + rxq->rxrearm_start;
63
64	/* Pull 'n' more MBUFs into the software ring */
65	if (rte_mempool_get_bulk(rxq->mp,
66				 (void *)rxep,
67				 RTE_I40E_RXQ_REARM_THRESH) < 0) {
68		if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
69		    rxq->nb_rx_desc) {
70			dma_addr0 = _mm_setzero_si128();
71			for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
72				rxep[i].mbuf = &rxq->fake_mbuf;
73				_mm_store_si128((__m128i *)&rxdp[i].read,
74						dma_addr0);
75			}
76		}
77		rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78			RTE_I40E_RXQ_REARM_THRESH;
79		return;
80	}
81
82	/* Initialize the mbufs in vector, process 2 mbufs in one loop */
83	for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84		__m128i vaddr0, vaddr1;
85		uintptr_t p0, p1;
86
87		mb0 = rxep[0].mbuf;
88		mb1 = rxep[1].mbuf;
89
90		 /* Flush mbuf with pkt template.
91		 * Data to be rearmed is 6 bytes long.
92		 * Though, RX will overwrite ol_flags that are coming next
93		 * anyway. So overwrite whole 8 bytes with one load:
94		 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
95		 */
96		p0 = (uintptr_t)&mb0->rearm_data;
97		*(uint64_t *)p0 = rxq->mbuf_initializer;
98		p1 = (uintptr_t)&mb1->rearm_data;
99		*(uint64_t *)p1 = rxq->mbuf_initializer;
100
101		/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
102		vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
103		vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
104
105		/* convert pa to dma_addr hdr/data */
106		dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
107		dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
108
109		/* add headroom to pa values */
110		dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
111		dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
112
113		/* flush desc with pa dma_addr */
114		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
115		_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
116	}
117
118	rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
119	if (rxq->rxrearm_start >= rxq->nb_rx_desc)
120		rxq->rxrearm_start = 0;
121
122	rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
123
124	rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
125			     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
126
127	/* Update the tail pointer on the NIC */
128	I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
129}
130
131/* Handling the offload flags (olflags) field takes computation
132 * time when receiving packets. Therefore we provide a flag to disable
133 * the processing of the olflags field when they are not needed. This
134 * gives improved performance, at the cost of losing the offload info
135 * in the received packet
136 */
137#ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
138
139static inline void
140desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
141{
142	__m128i vlan0, vlan1, rss, l3_l4e;
143
144	/* mask everything except RSS, flow director and VLAN flags
145	 * bit2 is for VLAN tag, bit11 for flow director indication
146	 * bit13:12 for RSS indication.
147	 */
148	const __m128i rss_vlan_msk = _mm_set_epi32(
149			0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
150
151	const __m128i cksum_mask = _mm_set_epi32(
152			PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
153			PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
154			PKT_RX_EIP_CKSUM_BAD,
155			PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
156			PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
157			PKT_RX_EIP_CKSUM_BAD,
158			PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
159			PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
160			PKT_RX_EIP_CKSUM_BAD,
161			PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
162			PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
163			PKT_RX_EIP_CKSUM_BAD);
164
165	/* map rss and vlan type to rss hash and vlan flag */
166	const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
167			0, 0, 0, 0,
168			0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
169			0, 0, 0, 0);
170
171	const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
172			0, 0, 0, 0,
173			PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
174			0, 0, PKT_RX_FDIR, 0);
175
176	const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
177			/* shift right 1 bit to make sure it not exceed 255 */
178			(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
179			 PKT_RX_IP_CKSUM_BAD) >> 1,
180			(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
181			 PKT_RX_L4_CKSUM_BAD) >> 1,
182			(PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
183			(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
184			(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
185			(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
186			PKT_RX_IP_CKSUM_BAD >> 1,
187			(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
188
189	vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
190	vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
191	vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
192
193	vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
194	vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
195
196	rss = _mm_srli_epi32(vlan1, 11);
197	rss = _mm_shuffle_epi8(rss_flags, rss);
198
199	l3_l4e = _mm_srli_epi32(vlan1, 22);
200	l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
201	/* then we shift left 1 bit */
202	l3_l4e = _mm_slli_epi32(l3_l4e, 1);
203	/* we need to mask out the reduntant bits */
204	l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
205
206	vlan0 = _mm_or_si128(vlan0, rss);
207	vlan0 = _mm_or_si128(vlan0, l3_l4e);
208
209	rx_pkts[0]->ol_flags = _mm_extract_epi16(vlan0, 0);
210	rx_pkts[1]->ol_flags = _mm_extract_epi16(vlan0, 2);
211	rx_pkts[2]->ol_flags = _mm_extract_epi16(vlan0, 4);
212	rx_pkts[3]->ol_flags = _mm_extract_epi16(vlan0, 6);
213}
214#else
215#define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
216#endif
217
218#define PKTLEN_SHIFT     10
219
220static inline void
221desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
222{
223	__m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
224	__m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
225
226	ptype0 = _mm_srli_epi64(ptype0, 30);
227	ptype1 = _mm_srli_epi64(ptype1, 30);
228
229	rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 0));
230	rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 8));
231	rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 0));
232	rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 8));
233}
234
235 /*
236 * Notice:
237 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
238 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
239 *   numbers of DD bits
240 */
241static inline uint16_t
242_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
243		   uint16_t nb_pkts, uint8_t *split_packet)
244{
245	volatile union i40e_rx_desc *rxdp;
246	struct i40e_rx_entry *sw_ring;
247	uint16_t nb_pkts_recd;
248	int pos;
249	uint64_t var;
250	__m128i shuf_msk;
251
252	__m128i crc_adjust = _mm_set_epi16(
253				0, 0, 0,    /* ignore non-length fields */
254				-rxq->crc_len, /* sub crc on data_len */
255				0,          /* ignore high-16bits of pkt_len */
256				-rxq->crc_len, /* sub crc on pkt_len */
257				0, 0            /* ignore pkt_type field */
258			);
259	__m128i dd_check, eop_check;
260
261	/* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
262	nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
263
264	/* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
265	nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
266
267	/* Just the act of getting into the function from the application is
268	 * going to cost about 7 cycles
269	 */
270	rxdp = rxq->rx_ring + rxq->rx_tail;
271
272	rte_prefetch0(rxdp);
273
274	/* See if we need to rearm the RX queue - gives the prefetch a bit
275	 * of time to act
276	 */
277	if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
278		i40e_rxq_rearm(rxq);
279
280	/* Before we start moving massive data around, check to see if
281	 * there is actually a packet available
282	 */
283	if (!(rxdp->wb.qword1.status_error_len &
284			rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
285		return 0;
286
287	/* 4 packets DD mask */
288	dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
289
290	/* 4 packets EOP mask */
291	eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
292
293	/* mask to shuffle from desc. to mbuf */
294	shuf_msk = _mm_set_epi8(
295		7, 6, 5, 4,  /* octet 4~7, 32bits rss */
296		3, 2,        /* octet 2~3, low 16 bits vlan_macip */
297		15, 14,      /* octet 15~14, 16 bits data_len */
298		0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
299		15, 14,      /* octet 15~14, low 16 bits pkt_len */
300		0xFF, 0xFF,  /* pkt_type set as unknown */
301		0xFF, 0xFF  /*pkt_type set as unknown */
302		);
303
304	/* Cache is empty -> need to scan the buffer rings, but first move
305	 * the next 'n' mbufs into the cache
306	 */
307	sw_ring = &rxq->sw_ring[rxq->rx_tail];
308
309	/* A. load 4 packet in one loop
310	 * [A*. mask out 4 unused dirty field in desc]
311	 * B. copy 4 mbuf point from swring to rx_pkts
312	 * C. calc the number of DD bits among the 4 packets
313	 * [C*. extract the end-of-packet bit, if requested]
314	 * D. fill info. from desc to mbuf
315	 */
316
317	for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
318			pos += RTE_I40E_DESCS_PER_LOOP,
319			rxdp += RTE_I40E_DESCS_PER_LOOP) {
320		__m128i descs[RTE_I40E_DESCS_PER_LOOP];
321		__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
322		__m128i zero, staterr, sterr_tmp1, sterr_tmp2;
323		__m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
324
325		/* B.1 load 1 mbuf point */
326		mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
327		/* Read desc statuses backwards to avoid race condition */
328		/* A.1 load 4 pkts desc */
329		descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
330		rte_compiler_barrier();
331
332		/* B.2 copy 2 mbuf point into rx_pkts  */
333		_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
334
335		/* B.1 load 1 mbuf point */
336		mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
337
338		descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
339		rte_compiler_barrier();
340		/* B.1 load 2 mbuf point */
341		descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
342		rte_compiler_barrier();
343		descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
344
345		/* B.2 copy 2 mbuf point into rx_pkts  */
346		_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
347
348		if (split_packet) {
349			rte_mbuf_prefetch_part2(rx_pkts[pos]);
350			rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
351			rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
352			rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
353		}
354
355		/* avoid compiler reorder optimization */
356		rte_compiler_barrier();
357
358		/* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
359		const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
360		const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
361
362		/* merge the now-aligned packet length fields back in */
363		descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
364		descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
365
366		/* D.1 pkt 3,4 convert format from desc to pktmbuf */
367		pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
368		pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
369
370		/* C.1 4=>2 filter staterr info only */
371		sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
372		/* C.1 4=>2 filter staterr info only */
373		sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
374
375		desc_to_olflags_v(descs, &rx_pkts[pos]);
376
377		/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
378		pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
379		pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
380
381		/* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
382		const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
383		const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
384
385		/* merge the now-aligned packet length fields back in */
386		descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
387		descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
388
389		/* D.1 pkt 1,2 convert format from desc to pktmbuf */
390		pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
391		pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
392
393		/* C.2 get 4 pkts staterr value  */
394		zero = _mm_xor_si128(dd_check, dd_check);
395		staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
396
397		/* D.3 copy final 3,4 data to rx_pkts */
398		_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
399				 pkt_mb4);
400		_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
401				 pkt_mb3);
402
403		/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
404		pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
405		pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
406
407		/* C* extract and record EOP bit */
408		if (split_packet) {
409			__m128i eop_shuf_mask = _mm_set_epi8(
410					0xFF, 0xFF, 0xFF, 0xFF,
411					0xFF, 0xFF, 0xFF, 0xFF,
412					0xFF, 0xFF, 0xFF, 0xFF,
413					0x04, 0x0C, 0x00, 0x08
414					);
415
416			/* and with mask to extract bits, flipping 1-0 */
417			__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
418			/* the staterr values are not in order, as the count
419			 * count of dd bits doesn't care. However, for end of
420			 * packet tracking, we do care, so shuffle. This also
421			 * compresses the 32-bit values to 8-bit
422			 */
423			eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
424			/* store the resulting 32-bit value */
425			*(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
426			split_packet += RTE_I40E_DESCS_PER_LOOP;
427
428			/* zero-out next pointers */
429			rx_pkts[pos]->next = NULL;
430			rx_pkts[pos + 1]->next = NULL;
431			rx_pkts[pos + 2]->next = NULL;
432			rx_pkts[pos + 3]->next = NULL;
433		}
434
435		/* C.3 calc available number of desc */
436		staterr = _mm_and_si128(staterr, dd_check);
437		staterr = _mm_packs_epi32(staterr, zero);
438
439		/* D.3 copy final 1,2 data to rx_pkts */
440		_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
441				 pkt_mb2);
442		_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
443				 pkt_mb1);
444		desc_to_ptype_v(descs, &rx_pkts[pos]);
445		/* C.4 calc avaialbe number of desc */
446		var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
447		nb_pkts_recd += var;
448		if (likely(var != RTE_I40E_DESCS_PER_LOOP))
449			break;
450	}
451
452	/* Update our internal tail pointer */
453	rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
454	rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
455	rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
456
457	return nb_pkts_recd;
458}
459
460 /*
461 * Notice:
462 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
463 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
464 *   numbers of DD bits
465 */
466uint16_t
467i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
468		   uint16_t nb_pkts)
469{
470	return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
471}
472
473 /* vPMD receive routine that reassembles scattered packets
474 * Notice:
475 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
476 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
477 *   numbers of DD bits
478 */
479uint16_t
480i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
481			     uint16_t nb_pkts)
482{
483
484	struct i40e_rx_queue *rxq = rx_queue;
485	uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
486
487	/* get some new buffers */
488	uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
489			split_flags);
490	if (nb_bufs == 0)
491		return 0;
492
493	/* happy day case, full burst + no packets to be joined */
494	const uint64_t *split_fl64 = (uint64_t *)split_flags;
495
496	if (rxq->pkt_first_seg == NULL &&
497			split_fl64[0] == 0 && split_fl64[1] == 0 &&
498			split_fl64[2] == 0 && split_fl64[3] == 0)
499		return nb_bufs;
500
501	/* reassemble any packets that need reassembly*/
502	unsigned i = 0;
503
504	if (rxq->pkt_first_seg == NULL) {
505		/* find the first split flag, and only reassemble then*/
506		while (i < nb_bufs && !split_flags[i])
507			i++;
508		if (i == nb_bufs)
509			return nb_bufs;
510	}
511	return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
512		&split_flags[i]);
513}
514
515static inline void
516vtx1(volatile struct i40e_tx_desc *txdp,
517		struct rte_mbuf *pkt, uint64_t flags)
518{
519	uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
520			((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
521			((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
522
523	__m128i descriptor = _mm_set_epi64x(high_qw,
524				pkt->buf_physaddr + pkt->data_off);
525	_mm_store_si128((__m128i *)txdp, descriptor);
526}
527
528static inline void
529vtx(volatile struct i40e_tx_desc *txdp,
530		struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
531{
532	int i;
533
534	for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
535		vtx1(txdp, *pkt, flags);
536}
537
538uint16_t
539i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
540		   uint16_t nb_pkts)
541{
542	struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
543	volatile struct i40e_tx_desc *txdp;
544	struct i40e_tx_entry *txep;
545	uint16_t n, nb_commit, tx_id;
546	uint64_t flags = I40E_TD_CMD;
547	uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
548	int i;
549
550	/* cross rx_thresh boundary is not allowed */
551	nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
552
553	if (txq->nb_tx_free < txq->tx_free_thresh)
554		i40e_tx_free_bufs(txq);
555
556	nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
557	if (unlikely(nb_pkts == 0))
558		return 0;
559
560	tx_id = txq->tx_tail;
561	txdp = &txq->tx_ring[tx_id];
562	txep = &txq->sw_ring[tx_id];
563
564	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
565
566	n = (uint16_t)(txq->nb_tx_desc - tx_id);
567	if (nb_commit >= n) {
568		tx_backlog_entry(txep, tx_pkts, n);
569
570		for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
571			vtx1(txdp, *tx_pkts, flags);
572
573		vtx1(txdp, *tx_pkts++, rs);
574
575		nb_commit = (uint16_t)(nb_commit - n);
576
577		tx_id = 0;
578		txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
579
580		/* avoid reach the end of ring */
581		txdp = &txq->tx_ring[tx_id];
582		txep = &txq->sw_ring[tx_id];
583	}
584
585	tx_backlog_entry(txep, tx_pkts, nb_commit);
586
587	vtx(txdp, tx_pkts, nb_commit, flags);
588
589	tx_id = (uint16_t)(tx_id + nb_commit);
590	if (tx_id > txq->tx_next_rs) {
591		txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
592			rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
593						I40E_TXD_QW1_CMD_SHIFT);
594		txq->tx_next_rs =
595			(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
596	}
597
598	txq->tx_tail = tx_id;
599
600	I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
601
602	return nb_pkts;
603}
604
605void __attribute__((cold))
606i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
607{
608	_i40e_rx_queue_release_mbufs_vec(rxq);
609}
610
611int __attribute__((cold))
612i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
613{
614	return i40e_rxq_vec_setup_default(rxq);
615}
616
617int __attribute__((cold))
618i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
619{
620	return 0;
621}
622
623int __attribute__((cold))
624i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
625{
626#ifndef RTE_LIBRTE_IEEE1588
627	/* need SSE4.1 support */
628	if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
629		return -1;
630#endif
631
632	return i40e_rx_vec_dev_conf_condition_check_default(dev);
633}
634