ixgbe_api.c revision 9ca4a157
1/*******************************************************************************
2
3Copyright (c) 2001-2015, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34#include "ixgbe_api.h"
35#include "ixgbe_common.h"
36
37#define IXGBE_EMPTY_PARAM
38
39static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
40	IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
41};
42
43static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
44	IXGBE_MVALS_INIT(_X540)
45};
46
47static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
48	IXGBE_MVALS_INIT(_X550)
49};
50
51static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
52	IXGBE_MVALS_INIT(_X550EM_x)
53};
54
55static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = {
56	IXGBE_MVALS_INIT(_X550EM_a)
57};
58
59/**
60 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
61 * @hw: pointer to hardware structure
62 * @map: pointer to u8 arr for returning map
63 *
64 * Read the rtrup2tc HW register and resolve its content into map
65 **/
66void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
67{
68	if (hw->mac.ops.get_rtrup2tc)
69		hw->mac.ops.get_rtrup2tc(hw, map);
70}
71
72/**
73 *  ixgbe_init_shared_code - Initialize the shared code
74 *  @hw: pointer to hardware structure
75 *
76 *  This will assign function pointers and assign the MAC type and PHY code.
77 *  Does not touch the hardware. This function must be called prior to any
78 *  other function in the shared code. The ixgbe_hw structure should be
79 *  memset to 0 prior to calling this function.  The following fields in
80 *  hw structure should be filled in prior to calling this function:
81 *  hw_addr, back, device_id, vendor_id, subsystem_device_id,
82 *  subsystem_vendor_id, and revision_id
83 **/
84s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
85{
86	s32 status;
87
88	DEBUGFUNC("ixgbe_init_shared_code");
89
90	/*
91	 * Set the mac type
92	 */
93	ixgbe_set_mac_type(hw);
94
95	switch (hw->mac.type) {
96	case ixgbe_mac_82598EB:
97		status = ixgbe_init_ops_82598(hw);
98		break;
99	case ixgbe_mac_82599EB:
100		status = ixgbe_init_ops_82599(hw);
101		break;
102	case ixgbe_mac_X540:
103		status = ixgbe_init_ops_X540(hw);
104		break;
105	case ixgbe_mac_X550:
106		status = ixgbe_init_ops_X550(hw);
107		break;
108	case ixgbe_mac_X550EM_x:
109		status = ixgbe_init_ops_X550EM_x(hw);
110		break;
111	case ixgbe_mac_X550EM_a:
112		status = ixgbe_init_ops_X550EM_a(hw);
113		break;
114	case ixgbe_mac_82599_vf:
115	case ixgbe_mac_X540_vf:
116	case ixgbe_mac_X550_vf:
117	case ixgbe_mac_X550EM_x_vf:
118	case ixgbe_mac_X550EM_a_vf:
119		status = ixgbe_init_ops_vf(hw);
120		break;
121	default:
122		status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
123		break;
124	}
125	hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
126
127	return status;
128}
129
130/**
131 *  ixgbe_set_mac_type - Sets MAC type
132 *  @hw: pointer to the HW structure
133 *
134 *  This function sets the mac type of the adapter based on the
135 *  vendor ID and device ID stored in the hw structure.
136 **/
137s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
138{
139	s32 ret_val = IXGBE_SUCCESS;
140
141	DEBUGFUNC("ixgbe_set_mac_type\n");
142
143	if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {
144		ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
145			     "Unsupported vendor id: %x", hw->vendor_id);
146		return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
147	}
148
149	hw->mvals = ixgbe_mvals_base;
150
151	switch (hw->device_id) {
152	case IXGBE_DEV_ID_82598:
153	case IXGBE_DEV_ID_82598_BX:
154	case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
155	case IXGBE_DEV_ID_82598AF_DUAL_PORT:
156	case IXGBE_DEV_ID_82598AT:
157	case IXGBE_DEV_ID_82598AT2:
158	case IXGBE_DEV_ID_82598EB_CX4:
159	case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
160	case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
161	case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
162	case IXGBE_DEV_ID_82598EB_XF_LR:
163	case IXGBE_DEV_ID_82598EB_SFP_LOM:
164		hw->mac.type = ixgbe_mac_82598EB;
165		break;
166	case IXGBE_DEV_ID_82599_KX4:
167	case IXGBE_DEV_ID_82599_KX4_MEZZ:
168	case IXGBE_DEV_ID_82599_XAUI_LOM:
169	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
170	case IXGBE_DEV_ID_82599_KR:
171	case IXGBE_DEV_ID_82599_SFP:
172	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
173	case IXGBE_DEV_ID_82599_SFP_FCOE:
174	case IXGBE_DEV_ID_82599_SFP_EM:
175	case IXGBE_DEV_ID_82599_SFP_SF2:
176	case IXGBE_DEV_ID_82599_SFP_SF_QP:
177	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
178	case IXGBE_DEV_ID_82599EN_SFP:
179	case IXGBE_DEV_ID_82599_CX4:
180	case IXGBE_DEV_ID_82599_LS:
181	case IXGBE_DEV_ID_82599_T3_LOM:
182		hw->mac.type = ixgbe_mac_82599EB;
183		break;
184	case IXGBE_DEV_ID_82599_VF:
185	case IXGBE_DEV_ID_82599_VF_HV:
186		hw->mac.type = ixgbe_mac_82599_vf;
187		break;
188	case IXGBE_DEV_ID_X540_VF:
189	case IXGBE_DEV_ID_X540_VF_HV:
190		hw->mac.type = ixgbe_mac_X540_vf;
191		hw->mvals = ixgbe_mvals_X540;
192		break;
193	case IXGBE_DEV_ID_X540T:
194	case IXGBE_DEV_ID_X540T1:
195		hw->mac.type = ixgbe_mac_X540;
196		hw->mvals = ixgbe_mvals_X540;
197		break;
198	case IXGBE_DEV_ID_X550T:
199	case IXGBE_DEV_ID_X550T1:
200		hw->mac.type = ixgbe_mac_X550;
201		hw->mvals = ixgbe_mvals_X550;
202		break;
203	case IXGBE_DEV_ID_X550EM_X_KX4:
204	case IXGBE_DEV_ID_X550EM_X_KR:
205	case IXGBE_DEV_ID_X550EM_X_10G_T:
206	case IXGBE_DEV_ID_X550EM_X_1G_T:
207	case IXGBE_DEV_ID_X550EM_X_SFP:
208	case IXGBE_DEV_ID_X550EM_X_XFI:
209		hw->mac.type = ixgbe_mac_X550EM_x;
210		hw->mvals = ixgbe_mvals_X550EM_x;
211		break;
212	case IXGBE_DEV_ID_X550EM_A_KR:
213	case IXGBE_DEV_ID_X550EM_A_KR_L:
214	case IXGBE_DEV_ID_X550EM_A_SFP_N:
215	case IXGBE_DEV_ID_X550EM_A_SGMII:
216	case IXGBE_DEV_ID_X550EM_A_SGMII_L:
217	case IXGBE_DEV_ID_X550EM_A_1G_T:
218	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
219	case IXGBE_DEV_ID_X550EM_A_10G_T:
220	case IXGBE_DEV_ID_X550EM_A_QSFP:
221	case IXGBE_DEV_ID_X550EM_A_QSFP_N:
222	case IXGBE_DEV_ID_X550EM_A_SFP:
223		hw->mac.type = ixgbe_mac_X550EM_a;
224		hw->mvals = ixgbe_mvals_X550EM_a;
225		break;
226	case IXGBE_DEV_ID_X550_VF:
227	case IXGBE_DEV_ID_X550_VF_HV:
228		hw->mac.type = ixgbe_mac_X550_vf;
229		hw->mvals = ixgbe_mvals_X550;
230		break;
231	case IXGBE_DEV_ID_X550EM_X_VF:
232	case IXGBE_DEV_ID_X550EM_X_VF_HV:
233		hw->mac.type = ixgbe_mac_X550EM_x_vf;
234		hw->mvals = ixgbe_mvals_X550EM_x;
235		break;
236	case IXGBE_DEV_ID_X550EM_A_VF:
237	case IXGBE_DEV_ID_X550EM_A_VF_HV:
238		hw->mac.type = ixgbe_mac_X550EM_a_vf;
239		hw->mvals = ixgbe_mvals_X550EM_a;
240		break;
241	default:
242		ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
243		ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
244			     "Unsupported device id: %x",
245			     hw->device_id);
246		break;
247	}
248
249	DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
250		  hw->mac.type, ret_val);
251	return ret_val;
252}
253
254/**
255 *  ixgbe_init_hw - Initialize the hardware
256 *  @hw: pointer to hardware structure
257 *
258 *  Initialize the hardware by resetting and then starting the hardware
259 **/
260s32 ixgbe_init_hw(struct ixgbe_hw *hw)
261{
262	return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
263			       IXGBE_NOT_IMPLEMENTED);
264}
265
266/**
267 *  ixgbe_reset_hw - Performs a hardware reset
268 *  @hw: pointer to hardware structure
269 *
270 *  Resets the hardware by resetting the transmit and receive units, masks and
271 *  clears all interrupts, performs a PHY reset, and performs a MAC reset
272 **/
273s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
274{
275	return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
276			       IXGBE_NOT_IMPLEMENTED);
277}
278
279/**
280 *  ixgbe_start_hw - Prepares hardware for Rx/Tx
281 *  @hw: pointer to hardware structure
282 *
283 *  Starts the hardware by filling the bus info structure and media type,
284 *  clears all on chip counters, initializes receive address registers,
285 *  multicast table, VLAN filter table, calls routine to setup link and
286 *  flow control settings, and leaves transmit and receive units disabled
287 *  and uninitialized.
288 **/
289s32 ixgbe_start_hw(struct ixgbe_hw *hw)
290{
291	return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
292			       IXGBE_NOT_IMPLEMENTED);
293}
294
295/**
296 *  ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
297 *  which is disabled by default in ixgbe_start_hw();
298 *
299 *  @hw: pointer to hardware structure
300 *
301 *   Enable relaxed ordering;
302 **/
303void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
304{
305	if (hw->mac.ops.enable_relaxed_ordering)
306		hw->mac.ops.enable_relaxed_ordering(hw);
307}
308
309/**
310 *  ixgbe_clear_hw_cntrs - Clear hardware counters
311 *  @hw: pointer to hardware structure
312 *
313 *  Clears all hardware statistics counters by reading them from the hardware
314 *  Statistics counters are clear on read.
315 **/
316s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
317{
318	return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
319			       IXGBE_NOT_IMPLEMENTED);
320}
321
322/**
323 *  ixgbe_get_media_type - Get media type
324 *  @hw: pointer to hardware structure
325 *
326 *  Returns the media type (fiber, copper, backplane)
327 **/
328enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
329{
330	return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
331			       ixgbe_media_type_unknown);
332}
333
334/**
335 *  ixgbe_get_mac_addr - Get MAC address
336 *  @hw: pointer to hardware structure
337 *  @mac_addr: Adapter MAC address
338 *
339 *  Reads the adapter's MAC address from the first Receive Address Register
340 *  (RAR0) A reset of the adapter must have been performed prior to calling
341 *  this function in order for the MAC address to have been loaded from the
342 *  EEPROM into RAR0
343 **/
344s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
345{
346	return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
347			       (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
348}
349
350/**
351 *  ixgbe_get_san_mac_addr - Get SAN MAC address
352 *  @hw: pointer to hardware structure
353 *  @san_mac_addr: SAN MAC address
354 *
355 *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
356 *  per-port, so set_lan_id() must be called before reading the addresses.
357 **/
358s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
359{
360	return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
361			       (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
362}
363
364/**
365 *  ixgbe_set_san_mac_addr - Write a SAN MAC address
366 *  @hw: pointer to hardware structure
367 *  @san_mac_addr: SAN MAC address
368 *
369 *  Writes A SAN MAC address to the EEPROM.
370 **/
371s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
372{
373	return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
374			       (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
375}
376
377/**
378 *  ixgbe_get_device_caps - Get additional device capabilities
379 *  @hw: pointer to hardware structure
380 *  @device_caps: the EEPROM word for device capabilities
381 *
382 *  Reads the extra device capabilities from the EEPROM
383 **/
384s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
385{
386	return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
387			       (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
388}
389
390/**
391 *  ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
392 *  @hw: pointer to hardware structure
393 *  @wwnn_prefix: the alternative WWNN prefix
394 *  @wwpn_prefix: the alternative WWPN prefix
395 *
396 *  This function will read the EEPROM from the alternative SAN MAC address
397 *  block to check the support for the alternative WWNN/WWPN prefix support.
398 **/
399s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
400			 u16 *wwpn_prefix)
401{
402	return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
403			       (hw, wwnn_prefix, wwpn_prefix),
404			       IXGBE_NOT_IMPLEMENTED);
405}
406
407/**
408 *  ixgbe_get_fcoe_boot_status -  Get FCOE boot status from EEPROM
409 *  @hw: pointer to hardware structure
410 *  @bs: the fcoe boot status
411 *
412 *  This function will read the FCOE boot status from the iSCSI FCOE block
413 **/
414s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
415{
416	return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
417			       (hw, bs),
418			       IXGBE_NOT_IMPLEMENTED);
419}
420
421/**
422 *  ixgbe_get_bus_info - Set PCI bus info
423 *  @hw: pointer to hardware structure
424 *
425 *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
426 **/
427s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
428{
429	return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
430			       IXGBE_NOT_IMPLEMENTED);
431}
432
433/**
434 *  ixgbe_get_num_of_tx_queues - Get Tx queues
435 *  @hw: pointer to hardware structure
436 *
437 *  Returns the number of transmit queues for the given adapter.
438 **/
439u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
440{
441	return hw->mac.max_tx_queues;
442}
443
444/**
445 *  ixgbe_get_num_of_rx_queues - Get Rx queues
446 *  @hw: pointer to hardware structure
447 *
448 *  Returns the number of receive queues for the given adapter.
449 **/
450u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
451{
452	return hw->mac.max_rx_queues;
453}
454
455/**
456 *  ixgbe_stop_adapter - Disable Rx/Tx units
457 *  @hw: pointer to hardware structure
458 *
459 *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
460 *  disables transmit and receive units. The adapter_stopped flag is used by
461 *  the shared code and drivers to determine if the adapter is in a stopped
462 *  state and should not touch the hardware.
463 **/
464s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
465{
466	return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
467			       IXGBE_NOT_IMPLEMENTED);
468}
469
470/**
471 *  ixgbe_read_pba_string - Reads part number string from EEPROM
472 *  @hw: pointer to hardware structure
473 *  @pba_num: stores the part number string from the EEPROM
474 *  @pba_num_size: part number string buffer length
475 *
476 *  Reads the part number string from the EEPROM.
477 **/
478s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
479{
480	return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
481}
482
483/**
484 *  ixgbe_read_pba_num - Reads part number from EEPROM
485 *  @hw: pointer to hardware structure
486 *  @pba_num: stores the part number from the EEPROM
487 *
488 *  Reads the part number from the EEPROM.
489 **/
490s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
491{
492	return ixgbe_read_pba_num_generic(hw, pba_num);
493}
494
495/**
496 *  ixgbe_identify_phy - Get PHY type
497 *  @hw: pointer to hardware structure
498 *
499 *  Determines the physical layer module found on the current adapter.
500 **/
501s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
502{
503	s32 status = IXGBE_SUCCESS;
504
505	if (hw->phy.type == ixgbe_phy_unknown) {
506		status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
507					 IXGBE_NOT_IMPLEMENTED);
508	}
509
510	return status;
511}
512
513/**
514 *  ixgbe_reset_phy - Perform a PHY reset
515 *  @hw: pointer to hardware structure
516 **/
517s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
518{
519	s32 status = IXGBE_SUCCESS;
520
521	if (hw->phy.type == ixgbe_phy_unknown) {
522		if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
523			status = IXGBE_ERR_PHY;
524	}
525
526	if (status == IXGBE_SUCCESS) {
527		status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
528					 IXGBE_NOT_IMPLEMENTED);
529	}
530	return status;
531}
532
533/**
534 *  ixgbe_get_phy_firmware_version -
535 *  @hw: pointer to hardware structure
536 *  @firmware_version: pointer to firmware version
537 **/
538s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
539{
540	s32 status = IXGBE_SUCCESS;
541
542	status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
543				 (hw, firmware_version),
544				 IXGBE_NOT_IMPLEMENTED);
545	return status;
546}
547
548/**
549 *  ixgbe_read_phy_reg - Read PHY register
550 *  @hw: pointer to hardware structure
551 *  @reg_addr: 32 bit address of PHY register to read
552 *  @phy_data: Pointer to read data from PHY register
553 *
554 *  Reads a value from a specified PHY register
555 **/
556s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
557		       u16 *phy_data)
558{
559	if (hw->phy.id == 0)
560		ixgbe_identify_phy(hw);
561
562	return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
563			       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
564}
565
566/**
567 *  ixgbe_write_phy_reg - Write PHY register
568 *  @hw: pointer to hardware structure
569 *  @reg_addr: 32 bit PHY register to write
570 *  @phy_data: Data to write to the PHY register
571 *
572 *  Writes a value to specified PHY register
573 **/
574s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
575			u16 phy_data)
576{
577	if (hw->phy.id == 0)
578		ixgbe_identify_phy(hw);
579
580	return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
581			       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
582}
583
584/**
585 *  ixgbe_setup_phy_link - Restart PHY autoneg
586 *  @hw: pointer to hardware structure
587 *
588 *  Restart autonegotiation and PHY and waits for completion.
589 **/
590s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
591{
592	return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
593			       IXGBE_NOT_IMPLEMENTED);
594}
595
596/**
597 * ixgbe_setup_internal_phy - Configure integrated PHY
598 * @hw: pointer to hardware structure
599 *
600 * Reconfigure the integrated PHY in order to enable talk to the external PHY.
601 * Returns success if not implemented, since nothing needs to be done in this
602 * case.
603 */
604s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
605{
606	return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
607			       IXGBE_SUCCESS);
608}
609
610/**
611 *  ixgbe_check_phy_link - Determine link and speed status
612 *  @hw: pointer to hardware structure
613 *
614 *  Reads a PHY register to determine if link is up and the current speed for
615 *  the PHY.
616 **/
617s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
618			 bool *link_up)
619{
620	return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
621			       link_up), IXGBE_NOT_IMPLEMENTED);
622}
623
624/**
625 *  ixgbe_setup_phy_link_speed - Set auto advertise
626 *  @hw: pointer to hardware structure
627 *  @speed: new link speed
628 *
629 *  Sets the auto advertised capabilities
630 **/
631s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
632			       bool autoneg_wait_to_complete)
633{
634	return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
635			       autoneg_wait_to_complete),
636			       IXGBE_NOT_IMPLEMENTED);
637}
638
639/**
640 * ixgbe_set_phy_power - Control the phy power state
641 * @hw: pointer to hardware structure
642 * @on: true for on, false for off
643 */
644s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
645{
646	return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),
647			       IXGBE_NOT_IMPLEMENTED);
648}
649
650/**
651 *  ixgbe_check_link - Get link and speed status
652 *  @hw: pointer to hardware structure
653 *
654 *  Reads the links register to determine if link is up and the current speed
655 **/
656s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
657		     bool *link_up, bool link_up_wait_to_complete)
658{
659	return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
660			       link_up, link_up_wait_to_complete),
661			       IXGBE_NOT_IMPLEMENTED);
662}
663
664/**
665 *  ixgbe_disable_tx_laser - Disable Tx laser
666 *  @hw: pointer to hardware structure
667 *
668 *  If the driver needs to disable the laser on SFI optics.
669 **/
670void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
671{
672	if (hw->mac.ops.disable_tx_laser)
673		hw->mac.ops.disable_tx_laser(hw);
674}
675
676/**
677 *  ixgbe_enable_tx_laser - Enable Tx laser
678 *  @hw: pointer to hardware structure
679 *
680 *  If the driver needs to enable the laser on SFI optics.
681 **/
682void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
683{
684	if (hw->mac.ops.enable_tx_laser)
685		hw->mac.ops.enable_tx_laser(hw);
686}
687
688/**
689 *  ixgbe_flap_tx_laser - flap Tx laser to start autotry process
690 *  @hw: pointer to hardware structure
691 *
692 *  When the driver changes the link speeds that it can support then
693 *  flap the tx laser to alert the link partner to start autotry
694 *  process on its end.
695 **/
696void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
697{
698	if (hw->mac.ops.flap_tx_laser)
699		hw->mac.ops.flap_tx_laser(hw);
700}
701
702/**
703 *  ixgbe_setup_link - Set link speed
704 *  @hw: pointer to hardware structure
705 *  @speed: new link speed
706 *
707 *  Configures link settings.  Restarts the link.
708 *  Performs autonegotiation if needed.
709 **/
710s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
711		     bool autoneg_wait_to_complete)
712{
713	return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
714			       autoneg_wait_to_complete),
715			       IXGBE_NOT_IMPLEMENTED);
716}
717
718/**
719 *  ixgbe_setup_mac_link - Set link speed
720 *  @hw: pointer to hardware structure
721 *  @speed: new link speed
722 *
723 *  Configures link settings.  Restarts the link.
724 *  Performs autonegotiation if needed.
725 **/
726s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
727			 bool autoneg_wait_to_complete)
728{
729	return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,
730			       autoneg_wait_to_complete),
731			       IXGBE_NOT_IMPLEMENTED);
732}
733
734/**
735 *  ixgbe_get_link_capabilities - Returns link capabilities
736 *  @hw: pointer to hardware structure
737 *
738 *  Determines the link capabilities of the current configuration.
739 **/
740s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
741				bool *autoneg)
742{
743	return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
744			       speed, autoneg), IXGBE_NOT_IMPLEMENTED);
745}
746
747/**
748 *  ixgbe_led_on - Turn on LEDs
749 *  @hw: pointer to hardware structure
750 *  @index: led number to turn on
751 *
752 *  Turns on the software controllable LEDs.
753 **/
754s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
755{
756	return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
757			       IXGBE_NOT_IMPLEMENTED);
758}
759
760/**
761 *  ixgbe_led_off - Turn off LEDs
762 *  @hw: pointer to hardware structure
763 *  @index: led number to turn off
764 *
765 *  Turns off the software controllable LEDs.
766 **/
767s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
768{
769	return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
770			       IXGBE_NOT_IMPLEMENTED);
771}
772
773/**
774 *  ixgbe_blink_led_start - Blink LEDs
775 *  @hw: pointer to hardware structure
776 *  @index: led number to blink
777 *
778 *  Blink LED based on index.
779 **/
780s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
781{
782	return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
783			       IXGBE_NOT_IMPLEMENTED);
784}
785
786/**
787 *  ixgbe_blink_led_stop - Stop blinking LEDs
788 *  @hw: pointer to hardware structure
789 *
790 *  Stop blinking LED based on index.
791 **/
792s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
793{
794	return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
795			       IXGBE_NOT_IMPLEMENTED);
796}
797
798/**
799 *  ixgbe_init_eeprom_params - Initialize EEPROM parameters
800 *  @hw: pointer to hardware structure
801 *
802 *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
803 *  ixgbe_hw struct in order to set up EEPROM access.
804 **/
805s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
806{
807	return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
808			       IXGBE_NOT_IMPLEMENTED);
809}
810
811
812/**
813 *  ixgbe_write_eeprom - Write word to EEPROM
814 *  @hw: pointer to hardware structure
815 *  @offset: offset within the EEPROM to be written to
816 *  @data: 16 bit word to be written to the EEPROM
817 *
818 *  Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
819 *  called after this function, the EEPROM will most likely contain an
820 *  invalid checksum.
821 **/
822s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
823{
824	return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
825			       IXGBE_NOT_IMPLEMENTED);
826}
827
828/**
829 *  ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
830 *  @hw: pointer to hardware structure
831 *  @offset: offset within the EEPROM to be written to
832 *  @data: 16 bit word(s) to be written to the EEPROM
833 *  @words: number of words
834 *
835 *  Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
836 *  called after this function, the EEPROM will most likely contain an
837 *  invalid checksum.
838 **/
839s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
840			      u16 *data)
841{
842	return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
843			       (hw, offset, words, data),
844			       IXGBE_NOT_IMPLEMENTED);
845}
846
847/**
848 *  ixgbe_read_eeprom - Read word from EEPROM
849 *  @hw: pointer to hardware structure
850 *  @offset: offset within the EEPROM to be read
851 *  @data: read 16 bit value from EEPROM
852 *
853 *  Reads 16 bit value from EEPROM
854 **/
855s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
856{
857	return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
858			       IXGBE_NOT_IMPLEMENTED);
859}
860
861/**
862 *  ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
863 *  @hw: pointer to hardware structure
864 *  @offset: offset within the EEPROM to be read
865 *  @data: read 16 bit word(s) from EEPROM
866 *  @words: number of words
867 *
868 *  Reads 16 bit word(s) from EEPROM
869 **/
870s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
871			     u16 words, u16 *data)
872{
873	return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
874			       (hw, offset, words, data),
875			       IXGBE_NOT_IMPLEMENTED);
876}
877
878/**
879 *  ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
880 *  @hw: pointer to hardware structure
881 *  @checksum_val: calculated checksum
882 *
883 *  Performs checksum calculation and validates the EEPROM checksum
884 **/
885s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
886{
887	return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
888			       (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
889}
890
891/**
892 *  ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
893 *  @hw: pointer to hardware structure
894 **/
895s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
896{
897	return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
898			       IXGBE_NOT_IMPLEMENTED);
899}
900
901/**
902 *  ixgbe_insert_mac_addr - Find a RAR for this mac address
903 *  @hw: pointer to hardware structure
904 *  @addr: Address to put into receive address register
905 *  @vmdq: VMDq pool to assign
906 *
907 *  Puts an ethernet address into a receive address register, or
908 *  finds the rar that it is aleady in; adds to the pool list
909 **/
910s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
911{
912	return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
913			       (hw, addr, vmdq),
914			       IXGBE_NOT_IMPLEMENTED);
915}
916
917/**
918 *  ixgbe_set_rar - Set Rx address register
919 *  @hw: pointer to hardware structure
920 *  @index: Receive address register to write
921 *  @addr: Address to put into receive address register
922 *  @vmdq: VMDq "set"
923 *  @enable_addr: set flag that address is active
924 *
925 *  Puts an ethernet address into a receive address register.
926 **/
927s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
928		  u32 enable_addr)
929{
930	return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
931			       enable_addr), IXGBE_NOT_IMPLEMENTED);
932}
933
934/**
935 *  ixgbe_clear_rar - Clear Rx address register
936 *  @hw: pointer to hardware structure
937 *  @index: Receive address register to write
938 *
939 *  Puts an ethernet address into a receive address register.
940 **/
941s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
942{
943	return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
944			       IXGBE_NOT_IMPLEMENTED);
945}
946
947/**
948 *  ixgbe_set_vmdq - Associate a VMDq index with a receive address
949 *  @hw: pointer to hardware structure
950 *  @rar: receive address register index to associate with VMDq index
951 *  @vmdq: VMDq set or pool index
952 **/
953s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
954{
955	return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
956			       IXGBE_NOT_IMPLEMENTED);
957
958}
959
960/**
961 *  ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
962 *  @hw: pointer to hardware structure
963 *  @vmdq: VMDq default pool index
964 **/
965s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
966{
967	return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
968			       (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
969}
970
971/**
972 *  ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
973 *  @hw: pointer to hardware structure
974 *  @rar: receive address register index to disassociate with VMDq index
975 *  @vmdq: VMDq set or pool index
976 **/
977s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
978{
979	return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
980			       IXGBE_NOT_IMPLEMENTED);
981}
982
983/**
984 *  ixgbe_init_rx_addrs - Initializes receive address filters.
985 *  @hw: pointer to hardware structure
986 *
987 *  Places the MAC address in receive address register 0 and clears the rest
988 *  of the receive address registers. Clears the multicast table. Assumes
989 *  the receiver is in reset when the routine is called.
990 **/
991s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
992{
993	return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
994			       IXGBE_NOT_IMPLEMENTED);
995}
996
997/**
998 *  ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
999 *  @hw: pointer to hardware structure
1000 **/
1001u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
1002{
1003	return hw->mac.num_rar_entries;
1004}
1005
1006/**
1007 *  ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
1008 *  @hw: pointer to hardware structure
1009 *  @addr_list: the list of new multicast addresses
1010 *  @addr_count: number of addresses
1011 *  @func: iterator function to walk the multicast address list
1012 *
1013 *  The given list replaces any existing list. Clears the secondary addrs from
1014 *  receive address registers. Uses unused receive address registers for the
1015 *  first secondary addresses, and falls back to promiscuous mode as needed.
1016 **/
1017s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
1018			      u32 addr_count, ixgbe_mc_addr_itr func)
1019{
1020	return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
1021			       addr_list, addr_count, func),
1022			       IXGBE_NOT_IMPLEMENTED);
1023}
1024
1025/**
1026 *  ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
1027 *  @hw: pointer to hardware structure
1028 *  @mc_addr_list: the list of new multicast addresses
1029 *  @mc_addr_count: number of addresses
1030 *  @func: iterator function to walk the multicast address list
1031 *
1032 *  The given list replaces any existing list. Clears the MC addrs from receive
1033 *  address registers and the multicast table. Uses unused receive address
1034 *  registers for the first multicast addresses, and hashes the rest into the
1035 *  multicast table.
1036 **/
1037s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
1038			      u32 mc_addr_count, ixgbe_mc_addr_itr func,
1039			      bool clear)
1040{
1041	return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
1042			       mc_addr_list, mc_addr_count, func, clear),
1043			       IXGBE_NOT_IMPLEMENTED);
1044}
1045
1046/**
1047 *  ixgbe_enable_mc - Enable multicast address in RAR
1048 *  @hw: pointer to hardware structure
1049 *
1050 *  Enables multicast address in RAR and the use of the multicast hash table.
1051 **/
1052s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
1053{
1054	return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
1055			       IXGBE_NOT_IMPLEMENTED);
1056}
1057
1058/**
1059 *  ixgbe_disable_mc - Disable multicast address in RAR
1060 *  @hw: pointer to hardware structure
1061 *
1062 *  Disables multicast address in RAR and the use of the multicast hash table.
1063 **/
1064s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
1065{
1066	return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
1067			       IXGBE_NOT_IMPLEMENTED);
1068}
1069
1070/**
1071 *  ixgbe_clear_vfta - Clear VLAN filter table
1072 *  @hw: pointer to hardware structure
1073 *
1074 *  Clears the VLAN filer table, and the VMDq index associated with the filter
1075 **/
1076s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
1077{
1078	return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
1079			       IXGBE_NOT_IMPLEMENTED);
1080}
1081
1082/**
1083 *  ixgbe_set_vfta - Set VLAN filter table
1084 *  @hw: pointer to hardware structure
1085 *  @vlan: VLAN id to write to VLAN filter
1086 *  @vind: VMDq output index that maps queue to VLAN id in VLVFB
1087 *  @vlan_on: boolean flag to turn on/off VLAN
1088 *  @vlvf_bypass: boolean flag indicating updating the default pool is okay
1089 *
1090 *  Turn on/off specified VLAN in the VLAN filter table.
1091 **/
1092s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1093		   bool vlvf_bypass)
1094{
1095	return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
1096			       vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED);
1097}
1098
1099/**
1100 *  ixgbe_set_vlvf - Set VLAN Pool Filter
1101 *  @hw: pointer to hardware structure
1102 *  @vlan: VLAN id to write to VLAN filter
1103 *  @vind: VMDq output index that maps queue to VLAN id in VLVFB
1104 *  @vlan_on: boolean flag to turn on/off VLAN in VLVF
1105 *  @vfta_delta: pointer to the difference between the current value of VFTA
1106 *		 and the desired value
1107 *  @vfta: the desired value of the VFTA
1108 *  @vlvf_bypass: boolean flag indicating updating the default pool is okay
1109 *
1110 *  Turn on/off specified bit in VLVF table.
1111 **/
1112s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1113		   u32 *vfta_delta, u32 vfta, bool vlvf_bypass)
1114{
1115	return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
1116			       vlan_on, vfta_delta, vfta, vlvf_bypass),
1117			       IXGBE_NOT_IMPLEMENTED);
1118}
1119
1120/**
1121 *  ixgbe_fc_enable - Enable flow control
1122 *  @hw: pointer to hardware structure
1123 *
1124 *  Configures the flow control settings based on SW configuration.
1125 **/
1126s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
1127{
1128	return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
1129			       IXGBE_NOT_IMPLEMENTED);
1130}
1131
1132/**
1133 *  ixgbe_setup_fc - Set up flow control
1134 *  @hw: pointer to hardware structure
1135 *
1136 *  Called at init time to set up flow control.
1137 **/
1138s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
1139{
1140	return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),
1141		IXGBE_NOT_IMPLEMENTED);
1142}
1143
1144/**
1145 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1146 * @hw: pointer to hardware structure
1147 * @maj: driver major number to be sent to firmware
1148 * @min: driver minor number to be sent to firmware
1149 * @build: driver build number to be sent to firmware
1150 * @ver: driver version number to be sent to firmware
1151 * @len: length of driver_ver string
1152 * @driver_ver: driver string
1153 **/
1154s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1155			 u8 ver, u16 len, char *driver_ver)
1156{
1157	return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1158			       build, ver, len, driver_ver),
1159			       IXGBE_NOT_IMPLEMENTED);
1160}
1161
1162
1163/**
1164 *  ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
1165 *  @hw: pointer to hardware structure
1166 *
1167 *  Updates the temperatures in mac.thermal_sensor_data
1168 **/
1169s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)
1170{
1171	return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),
1172				IXGBE_NOT_IMPLEMENTED);
1173}
1174
1175/**
1176 *  ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1177 *  @hw: pointer to hardware structure
1178 *
1179 *  Inits the thermal sensor thresholds according to the NVM map
1180 **/
1181s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)
1182{
1183	return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),
1184				IXGBE_NOT_IMPLEMENTED);
1185}
1186
1187/**
1188 *  ixgbe_dmac_config - Configure DMA Coalescing registers.
1189 *  @hw: pointer to hardware structure
1190 *
1191 *  Configure DMA coalescing. If enabling dmac, dmac is activated.
1192 *  When disabling dmac, dmac enable dmac bit is cleared.
1193 **/
1194s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
1195{
1196	return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
1197				IXGBE_NOT_IMPLEMENTED);
1198}
1199
1200/**
1201 *  ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
1202 *  @hw: pointer to hardware structure
1203 *
1204 *  Disables dmac, updates per TC settings, and then enable dmac.
1205 **/
1206s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
1207{
1208	return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
1209				IXGBE_NOT_IMPLEMENTED);
1210}
1211
1212/**
1213 *  ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
1214 *  @hw: pointer to hardware structure
1215 *
1216 *  Configure DMA coalescing threshold per TC and set high priority bit for
1217 *  FCOE TC. The dmac enable bit must be cleared before configuring.
1218 **/
1219s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
1220{
1221	return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
1222				IXGBE_NOT_IMPLEMENTED);
1223}
1224
1225/**
1226 *  ixgbe_setup_eee - Enable/disable EEE support
1227 *  @hw: pointer to the HW structure
1228 *  @enable_eee: boolean flag to enable EEE
1229 *
1230 *  Enable/disable EEE based on enable_ee flag.
1231 *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1232 *  are modified.
1233 *
1234 **/
1235s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)
1236{
1237	return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),
1238			IXGBE_NOT_IMPLEMENTED);
1239}
1240
1241/**
1242 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning
1243 * @hw: pointer to hardware structure
1244 * @enbale: enable or disable source address pruning
1245 * @pool: Rx pool - Rx pool to toggle source address pruning
1246 **/
1247void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
1248				      unsigned int pool)
1249{
1250	if (hw->mac.ops.set_source_address_pruning)
1251		hw->mac.ops.set_source_address_pruning(hw, enable, pool);
1252}
1253
1254/**
1255 *  ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing
1256 *  @hw: pointer to hardware structure
1257 *  @enable: enable or disable switch for Ethertype anti-spoofing
1258 *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1259 *
1260 **/
1261void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
1262{
1263	if (hw->mac.ops.set_ethertype_anti_spoofing)
1264		hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
1265}
1266
1267/**
1268 *  ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
1269 *  @hw: pointer to hardware structure
1270 *  @reg_addr: 32 bit address of PHY register to read
1271 *  @device_type: type of device you want to communicate with
1272 *  @phy_data: Pointer to read data from PHY register
1273 *
1274 *  Reads a value from a specified PHY register
1275 **/
1276s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1277			   u32 device_type, u32 *phy_data)
1278{
1279	return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
1280			       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1281}
1282
1283/**
1284 *  ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
1285 *  @hw: pointer to hardware structure
1286 *  @reg_addr: 32 bit PHY register to write
1287 *  @device_type: type of device you want to communicate with
1288 *  @phy_data: Data to write to the PHY register
1289 *
1290 *  Writes a value to specified PHY register
1291 **/
1292s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1293			    u32 device_type, u32 phy_data)
1294{
1295	return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
1296			       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1297}
1298
1299/**
1300 *  ixgbe_disable_mdd - Disable malicious driver detection
1301 *  @hw: pointer to hardware structure
1302 *
1303 **/
1304void ixgbe_disable_mdd(struct ixgbe_hw *hw)
1305{
1306	if (hw->mac.ops.disable_mdd)
1307		hw->mac.ops.disable_mdd(hw);
1308}
1309
1310/**
1311 *  ixgbe_enable_mdd - Enable malicious driver detection
1312 *  @hw: pointer to hardware structure
1313 *
1314 **/
1315void ixgbe_enable_mdd(struct ixgbe_hw *hw)
1316{
1317	if (hw->mac.ops.enable_mdd)
1318		hw->mac.ops.enable_mdd(hw);
1319}
1320
1321/**
1322 *  ixgbe_mdd_event - Handle malicious driver detection event
1323 *  @hw: pointer to hardware structure
1324 *  @vf_bitmap: vf bitmap of malicious vfs
1325 *
1326 **/
1327void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)
1328{
1329	if (hw->mac.ops.mdd_event)
1330		hw->mac.ops.mdd_event(hw, vf_bitmap);
1331}
1332
1333/**
1334 *  ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
1335 *  detection event
1336 *  @hw: pointer to hardware structure
1337 *  @vf: vf index
1338 *
1339 **/
1340void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)
1341{
1342	if (hw->mac.ops.restore_mdd_vf)
1343		hw->mac.ops.restore_mdd_vf(hw, vf);
1344}
1345
1346/**
1347 *  ixgbe_enter_lplu - Transition to low power states
1348 *  @hw: pointer to hardware structure
1349 *
1350 * Configures Low Power Link Up on transition to low power states
1351 * (from D0 to non-D0).
1352 **/
1353s32 ixgbe_enter_lplu(struct ixgbe_hw *hw)
1354{
1355	return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),
1356				IXGBE_NOT_IMPLEMENTED);
1357}
1358
1359/**
1360 * ixgbe_handle_lasi - Handle external Base T PHY interrupt
1361 * @hw: pointer to hardware structure
1362 *
1363 * Handle external Base T PHY interrupt. If high temperature
1364 * failure alarm then return error, else if link status change
1365 * then setup internal/external PHY link
1366 *
1367 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1368 * failure alarm, else return PHY access status.
1369 */
1370s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1371{
1372	return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1373				IXGBE_NOT_IMPLEMENTED);
1374}
1375
1376/**
1377 *  ixgbe_read_analog_reg8 - Reads 8 bit analog register
1378 *  @hw: pointer to hardware structure
1379 *  @reg: analog register to read
1380 *  @val: read value
1381 *
1382 *  Performs write operation to analog register specified.
1383 **/
1384s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1385{
1386	return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1387			       val), IXGBE_NOT_IMPLEMENTED);
1388}
1389
1390/**
1391 *  ixgbe_write_analog_reg8 - Writes 8 bit analog register
1392 *  @hw: pointer to hardware structure
1393 *  @reg: analog register to write
1394 *  @val: value to write
1395 *
1396 *  Performs write operation to Atlas analog register specified.
1397 **/
1398s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1399{
1400	return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1401			       val), IXGBE_NOT_IMPLEMENTED);
1402}
1403
1404/**
1405 *  ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1406 *  @hw: pointer to hardware structure
1407 *
1408 *  Initializes the Unicast Table Arrays to zero on device load.  This
1409 *  is part of the Rx init addr execution path.
1410 **/
1411s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1412{
1413	return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1414			       IXGBE_NOT_IMPLEMENTED);
1415}
1416
1417/**
1418 *  ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1419 *  @hw: pointer to hardware structure
1420 *  @byte_offset: byte offset to read
1421 *  @dev_addr: I2C bus address to read from
1422 *  @data: value read
1423 *
1424 *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1425 **/
1426s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1427			u8 *data)
1428{
1429	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1430			       dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1431}
1432
1433/**
1434 *  ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address
1435 *  @hw: pointer to hardware structure
1436 *  @byte_offset: byte offset to read
1437 *  @dev_addr: I2C bus address to read from
1438 *  @data: value read
1439 *
1440 *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1441 **/
1442s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1443				 u8 dev_addr, u8 *data)
1444{
1445	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1446			       (hw, byte_offset, dev_addr, data),
1447			       IXGBE_NOT_IMPLEMENTED);
1448}
1449
1450/**
1451 * ixgbe_read_link - Perform read operation on link device
1452 * @hw: pointer to the hardware structure
1453 * @addr: bus address to read from
1454 * @reg: device register to read from
1455 * @val: pointer to location to receive read value
1456 *
1457 * Returns an error code on error.
1458 */
1459s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1460{
1461	return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr,
1462			       reg, val), IXGBE_NOT_IMPLEMENTED);
1463}
1464
1465/**
1466 * ixgbe_read_link_unlocked - Perform read operation on link device
1467 * @hw: pointer to the hardware structure
1468 * @addr: bus address to read from
1469 * @reg: device register to read from
1470 * @val: pointer to location to receive read value
1471 *
1472 * Returns an error code on error.
1473 **/
1474s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1475{
1476	return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked,
1477			       (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1478}
1479
1480/**
1481 *  ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1482 *  @hw: pointer to hardware structure
1483 *  @byte_offset: byte offset to write
1484 *  @dev_addr: I2C bus address to write to
1485 *  @data: value to write
1486 *
1487 *  Performs byte write operation to SFP module's EEPROM over I2C interface
1488 *  at a specified device address.
1489 **/
1490s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1491			 u8 data)
1492{
1493	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1494			       dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1495}
1496
1497/**
1498 *  ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1499 *  @hw: pointer to hardware structure
1500 *  @byte_offset: byte offset to write
1501 *  @dev_addr: I2C bus address to write to
1502 *  @data: value to write
1503 *
1504 *  Performs byte write operation to SFP module's EEPROM over I2C interface
1505 *  at a specified device address.
1506 **/
1507s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1508				  u8 dev_addr, u8 data)
1509{
1510	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1511			       (hw, byte_offset, dev_addr, data),
1512			       IXGBE_NOT_IMPLEMENTED);
1513}
1514
1515/**
1516 * ixgbe_write_link - Perform write operation on link device
1517 * @hw: pointer to the hardware structure
1518 * @addr: bus address to write to
1519 * @reg: device register to write to
1520 * @val: value to write
1521 *
1522 * Returns an error code on error.
1523 */
1524s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1525{
1526	return ixgbe_call_func(hw, hw->link.ops.write_link,
1527			       (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1528}
1529
1530/**
1531 * ixgbe_write_link_unlocked - Perform write operation on link device
1532 * @hw: pointer to the hardware structure
1533 * @addr: bus address to write to
1534 * @reg: device register to write to
1535 * @val: value to write
1536 *
1537 * Returns an error code on error.
1538 **/
1539s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1540{
1541	return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked,
1542			       (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1543}
1544
1545/**
1546 *  ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1547 *  @hw: pointer to hardware structure
1548 *  @byte_offset: EEPROM byte offset to write
1549 *  @eeprom_data: value to write
1550 *
1551 *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1552 **/
1553s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1554			   u8 byte_offset, u8 eeprom_data)
1555{
1556	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1557			       (hw, byte_offset, eeprom_data),
1558			       IXGBE_NOT_IMPLEMENTED);
1559}
1560
1561/**
1562 *  ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1563 *  @hw: pointer to hardware structure
1564 *  @byte_offset: EEPROM byte offset to read
1565 *  @eeprom_data: value read
1566 *
1567 *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1568 **/
1569s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1570{
1571	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1572			      (hw, byte_offset, eeprom_data),
1573			      IXGBE_NOT_IMPLEMENTED);
1574}
1575
1576/**
1577 *  ixgbe_get_supported_physical_layer - Returns physical layer type
1578 *  @hw: pointer to hardware structure
1579 *
1580 *  Determines physical layer capabilities of the current configuration.
1581 **/
1582u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1583{
1584	return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1585			       (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1586}
1587
1588/**
1589 *  ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1590 *  @hw: pointer to hardware structure
1591 *  @regval: bitfield to write to the Rx DMA register
1592 *
1593 *  Enables the Rx DMA unit of the device.
1594 **/
1595s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1596{
1597	return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1598			       (hw, regval), IXGBE_NOT_IMPLEMENTED);
1599}
1600
1601/**
1602 *  ixgbe_disable_sec_rx_path - Stops the receive data path
1603 *  @hw: pointer to hardware structure
1604 *
1605 *  Stops the receive data path.
1606 **/
1607s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1608{
1609	return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1610				(hw), IXGBE_NOT_IMPLEMENTED);
1611}
1612
1613/**
1614 *  ixgbe_enable_sec_rx_path - Enables the receive data path
1615 *  @hw: pointer to hardware structure
1616 *
1617 *  Enables the receive data path.
1618 **/
1619s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1620{
1621	return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1622				(hw), IXGBE_NOT_IMPLEMENTED);
1623}
1624
1625/**
1626 *  ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1627 *  @hw: pointer to hardware structure
1628 *  @mask: Mask to specify which semaphore to acquire
1629 *
1630 *  Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1631 *  function (CSR, PHY0, PHY1, EEPROM, Flash)
1632 **/
1633s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1634{
1635	return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1636			       (hw, mask), IXGBE_NOT_IMPLEMENTED);
1637}
1638
1639/**
1640 *  ixgbe_release_swfw_semaphore - Release SWFW semaphore
1641 *  @hw: pointer to hardware structure
1642 *  @mask: Mask to specify which semaphore to release
1643 *
1644 *  Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1645 *  function (CSR, PHY0, PHY1, EEPROM, Flash)
1646 **/
1647void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1648{
1649	if (hw->mac.ops.release_swfw_sync)
1650		hw->mac.ops.release_swfw_sync(hw, mask);
1651}
1652
1653/**
1654 *  ixgbe_init_swfw_semaphore - Clean up SWFW semaphore
1655 *  @hw: pointer to hardware structure
1656 *
1657 *  Attempts to acquire the SWFW semaphore through SW_FW_SYNC register.
1658 *  Regardless of whether is succeeds or not it then release the semaphore.
1659 *  This is function is called to recover from catastrophic failures that
1660 *  may have left the semaphore locked.
1661 **/
1662void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw)
1663{
1664	if (hw->mac.ops.init_swfw_sync)
1665		hw->mac.ops.init_swfw_sync(hw);
1666}
1667
1668
1669void ixgbe_disable_rx(struct ixgbe_hw *hw)
1670{
1671	if (hw->mac.ops.disable_rx)
1672		hw->mac.ops.disable_rx(hw);
1673}
1674
1675void ixgbe_enable_rx(struct ixgbe_hw *hw)
1676{
1677	if (hw->mac.ops.enable_rx)
1678		hw->mac.ops.enable_rx(hw);
1679}
1680
1681/**
1682 *  ixgbe_set_rate_select_speed - Set module link speed
1683 *  @hw: pointer to hardware structure
1684 *  @speed: link speed to set
1685 *
1686 *  Set module link speed via the rate select.
1687 */
1688void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
1689{
1690	if (hw->mac.ops.set_rate_select_speed)
1691		hw->mac.ops.set_rate_select_speed(hw, speed);
1692}
1693