1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <stdio.h>
35#include <stdint.h>
36#include <stdarg.h>
37#include <errno.h>
38#include <sys/queue.h>
39
40#include <rte_interrupts.h>
41#include <rte_log.h>
42#include <rte_debug.h>
43#include <rte_pci.h>
44#include <rte_ether.h>
45#include <rte_ethdev.h>
46#include <rte_malloc.h>
47
48#include "ixgbe_logs.h"
49#include "base/ixgbe_api.h"
50#include "base/ixgbe_common.h"
51#include "ixgbe_ethdev.h"
52
53/* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
54#define FDIRCTRL_PBALLOC_MASK           0x03
55
56/* For calculating memory required for FDIR filters */
57#define PBALLOC_SIZE_SHIFT              15
58
59/* Number of bits used to mask bucket hash for different pballoc sizes */
60#define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
61#define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
62#define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
63#define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
64#define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
65#define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
66#define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
67#define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
68#define IXGBE_MAX_FLX_SOURCE_OFF        62
69#define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
70#define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
71
72#define IXGBE_FDIR_FLOW_TYPES ( \
73	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
74	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
75	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
76	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
77	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
78	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
79	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
80	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
81
82#define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
83	uint8_t ipv6_addr[16]; \
84	uint8_t i; \
85	rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
86	(ipv6m) = 0; \
87	for (i = 0; i < sizeof(ipv6_addr); i++) { \
88		if (ipv6_addr[i] == UINT8_MAX) \
89			(ipv6m) |= 1 << i; \
90		else if (ipv6_addr[i] != 0) { \
91			PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
92			return -EINVAL; \
93		} \
94	} \
95} while (0)
96
97#define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
98	uint8_t ipv6_addr[16]; \
99	uint8_t i; \
100	for (i = 0; i < sizeof(ipv6_addr); i++) { \
101		if ((ipv6m) & (1 << i)) \
102			ipv6_addr[i] = UINT8_MAX; \
103		else \
104			ipv6_addr[i] = 0; \
105	} \
106	rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
107} while (0)
108
109#define DEFAULT_VXLAN_PORT 4789
110#define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
111
112static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
113static int fdir_set_input_mask(struct rte_eth_dev *dev,
114			       const struct rte_eth_fdir_masks *input_mask);
115static int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
116static int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
117static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
118		const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
119static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
120static int ixgbe_fdir_filter_to_atr_input(
121		const struct rte_eth_fdir_filter *fdir_filter,
122		union ixgbe_atr_input *input,
123		enum rte_fdir_mode mode);
124static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
125				 uint32_t key);
126static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
127		enum rte_fdir_pballoc_type pballoc);
128static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
129		enum rte_fdir_pballoc_type pballoc);
130static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
131			union ixgbe_atr_input *input, uint8_t queue,
132			uint32_t fdircmd, uint32_t fdirhash,
133			enum rte_fdir_mode mode);
134static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
135		union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
136		uint32_t fdirhash);
137static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
138			      const struct rte_eth_fdir_filter *fdir_filter,
139			      bool del,
140			      bool update);
141static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
142static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
143			struct rte_eth_fdir_info *fdir_info);
144static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
145			struct rte_eth_fdir_stats *fdir_stats);
146
147/**
148 * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
149 * It adds extra configuration of fdirctrl that is common for all filter types.
150 *
151 *  Initialize Flow Director control registers
152 *  @hw: pointer to hardware structure
153 *  @fdirctrl: value to write to flow director control register
154 **/
155static int
156fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
157{
158	int i;
159
160	PMD_INIT_FUNC_TRACE();
161
162	/* Prime the keys for hashing */
163	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
164	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
165
166	/*
167	 * Continue setup of fdirctrl register bits:
168	 *  Set the maximum length per hash bucket to 0xA filters
169	 *  Send interrupt when 64 filters are left
170	 */
171	fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
172		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
173
174	/*
175	 * Poll init-done after we write the register.  Estimated times:
176	 *      10G: PBALLOC = 11b, timing is 60us
177	 *       1G: PBALLOC = 11b, timing is 600us
178	 *     100M: PBALLOC = 11b, timing is 6ms
179	 *
180	 *     Multiple these timings by 4 if under full Rx load
181	 *
182	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
183	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
184	 * this might not finish in our poll time, but we can live with that
185	 * for now.
186	 */
187	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
188	IXGBE_WRITE_FLUSH(hw);
189	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
190		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
191				   IXGBE_FDIRCTRL_INIT_DONE)
192			break;
193		msec_delay(1);
194	}
195
196	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
197		PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
198		return -ETIMEDOUT;
199	}
200	return 0;
201}
202
203/*
204 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
205 * flexbytes matching field, and drop queue (only for perfect matching mode).
206 */
207static inline int
208configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
209{
210	*fdirctrl = 0;
211
212	switch (conf->pballoc) {
213	case RTE_FDIR_PBALLOC_64K:
214		/* 8k - 1 signature filters */
215		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
216		break;
217	case RTE_FDIR_PBALLOC_128K:
218		/* 16k - 1 signature filters */
219		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
220		break;
221	case RTE_FDIR_PBALLOC_256K:
222		/* 32k - 1 signature filters */
223		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
224		break;
225	default:
226		/* bad value */
227		PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
228		return -EINVAL;
229	};
230
231	/* status flags: write hash & swindex in the rx descriptor */
232	switch (conf->status) {
233	case RTE_FDIR_NO_REPORT_STATUS:
234		/* do nothing, default mode */
235		break;
236	case RTE_FDIR_REPORT_STATUS:
237		/* report status when the packet matches a fdir rule */
238		*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
239		break;
240	case RTE_FDIR_REPORT_STATUS_ALWAYS:
241		/* always report status */
242		*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
243		break;
244	default:
245		/* bad value */
246		PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
247		return -EINVAL;
248	};
249
250#define TREX_PATCH
251#ifdef TREX_PATCH
252	*fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
253#else
254	*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
255		     IXGBE_FDIRCTRL_FLEX_SHIFT;
256#endif
257
258	if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
259	    conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
260		*fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
261		*fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
262		if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
263			*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
264					<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
265		else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
266			*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
267					<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
268	}
269
270	return 0;
271}
272
273/**
274 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
275 *
276 *  @hi_dword: Bits 31:16 mask to be bit swapped.
277 *  @lo_dword: Bits 15:0  mask to be bit swapped.
278 *
279 *  Flow director uses several registers to store 2 x 16 bit masks with the
280 *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
281 *  mask affects the MS bit/byte of the target. This function reverses the
282 *  bits in these masks.
283 *  **/
284static inline uint32_t
285reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
286{
287	uint32_t mask = hi_dword << 16;
288
289	mask |= lo_dword;
290	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
291	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
292	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
293	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
294}
295
296/*
297 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
298 * but makes use of the rte_fdir_masks structure to see which bits to set.
299 */
300static int
301fdir_set_input_mask_82599(struct rte_eth_dev *dev)
302{
303	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
304	struct ixgbe_hw_fdir_info *info =
305			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
306	/*
307	 * mask VM pool and DIPv6 since there are currently not supported
308	 * mask FLEX byte, it will be set in flex_conf
309	 */
310	uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
311	uint32_t fdirtcpm;  /* TCP source and destination port masks. */
312	uint32_t fdiripv6m; /* IPv6 source and destination masks. */
313	volatile uint32_t *reg;
314
315	PMD_INIT_FUNC_TRACE();
316
317	/*
318	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
319	 * are zero, then assume a full mask for that field. Also assume that
320	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
321	 * cannot be masked out in this implementation.
322	 */
323	if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
324		/* use the L4 protocol mask for raw IPv4/IPv6 traffic */
325		fdirm |= IXGBE_FDIRM_L4P;
326
327	if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
328		/* mask VLAN Priority */
329		fdirm |= IXGBE_FDIRM_VLANP;
330	else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
331		/* mask VLAN ID */
332		fdirm |= IXGBE_FDIRM_VLANID;
333	else if (info->mask.vlan_tci_mask == 0)
334		/* mask VLAN ID and Priority */
335		fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
336	else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
337		PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
338		return -EINVAL;
339	}
340
341	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
342
343	/* store the TCP/UDP port masks, bit reversed from port layout */
344	fdirtcpm = reverse_fdir_bitmasks(
345			rte_be_to_cpu_16(info->mask.dst_port_mask),
346			rte_be_to_cpu_16(info->mask.src_port_mask));
347
348	/* write all the same so that UDP, TCP and SCTP use the same mask
349	 * (little-endian)
350	 */
351	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
352	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
353	IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
354
355	/* Store source and destination IPv4 masks (big-endian),
356	 * can not use IXGBE_WRITE_REG.
357	 */
358	reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
359	*reg = ~(info->mask.src_ipv4_mask);
360	reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
361	*reg = ~(info->mask.dst_ipv4_mask);
362
363	if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
364		/*
365		 * Store source and destination IPv6 masks (bit reversed)
366		 */
367		fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
368			    info->mask.src_ipv6_mask;
369
370		IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
371	}
372
373	return IXGBE_SUCCESS;
374}
375
376/*
377 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
378 * but makes use of the rte_fdir_masks structure to see which bits to set.
379 */
380static int
381fdir_set_input_mask_x550(struct rte_eth_dev *dev)
382{
383	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
384	struct ixgbe_hw_fdir_info *info =
385			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
386	/* mask VM pool and DIPv6 since there are currently not supported
387	 * mask FLEX byte, it will be set in flex_conf
388	 */
389	uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
390			 IXGBE_FDIRM_FLEX;
391	uint32_t fdiripv6m;
392	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
393	uint16_t mac_mask;
394
395	PMD_INIT_FUNC_TRACE();
396
397	/* set the default UDP port for VxLAN */
398	if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
399		IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
400
401	/* some bits must be set for mac vlan or tunnel mode */
402	fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
403
404	if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
405		/* mask VLAN Priority */
406		fdirm |= IXGBE_FDIRM_VLANP;
407	else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
408		/* mask VLAN ID */
409		fdirm |= IXGBE_FDIRM_VLANID;
410	else if (info->mask.vlan_tci_mask == 0)
411		/* mask VLAN ID and Priority */
412		fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
413	else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
414		PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
415		return -EINVAL;
416	}
417
418	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
419
420	fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
421	fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
422	if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
423		fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
424				IXGBE_FDIRIP6M_TNI_VNI;
425
426	if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
427		mac_mask = info->mask.mac_addr_byte_mask;
428		fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
429				& IXGBE_FDIRIP6M_INNER_MAC;
430
431		switch (info->mask.tunnel_type_mask) {
432		case 0:
433			/* Mask turnnel type */
434			fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
435			break;
436		case 1:
437			break;
438		default:
439			PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
440			return -EINVAL;
441		}
442
443		switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
444		case 0x0:
445			/* Mask vxlan id */
446			fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
447			break;
448		case 0x00FFFFFF:
449			fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
450			break;
451		case 0xFFFFFFFF:
452			break;
453		default:
454			PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
455			return -EINVAL;
456		}
457	}
458
459	IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
460	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
461	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
462	IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
463	IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
464	IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
465
466	return IXGBE_SUCCESS;
467}
468
469static int
470ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
471				  const struct rte_eth_fdir_masks *input_mask)
472{
473	struct ixgbe_hw_fdir_info *info =
474		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
475	uint16_t dst_ipv6m = 0;
476	uint16_t src_ipv6m = 0;
477
478	memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
479	info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
480	info->mask.src_port_mask = input_mask->src_port_mask;
481	info->mask.dst_port_mask = input_mask->dst_port_mask;
482	info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
483	info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
484	IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
485	IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
486	info->mask.src_ipv6_mask = src_ipv6m;
487	info->mask.dst_ipv6_mask = dst_ipv6m;
488
489	return IXGBE_SUCCESS;
490}
491
492static int
493ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
494				 const struct rte_eth_fdir_masks *input_mask)
495{
496	struct ixgbe_hw_fdir_info *info =
497		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
498
499	memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
500	info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
501	info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
502	info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
503	info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
504
505	return IXGBE_SUCCESS;
506}
507
508static int
509ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
510			    const struct rte_eth_fdir_masks *input_mask)
511{
512	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
513
514	if (mode >= RTE_FDIR_MODE_SIGNATURE &&
515	    mode <= RTE_FDIR_MODE_PERFECT)
516		return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
517	else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
518		 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
519		return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
520
521	PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
522	return -ENOTSUP;
523}
524
525int
526ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
527{
528	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
529
530	if (mode >= RTE_FDIR_MODE_SIGNATURE &&
531	    mode <= RTE_FDIR_MODE_PERFECT)
532		return fdir_set_input_mask_82599(dev);
533	else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
534		 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
535		return fdir_set_input_mask_x550(dev);
536
537	PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
538	return -ENOTSUP;
539}
540
541static int
542fdir_set_input_mask(struct rte_eth_dev *dev,
543		    const struct rte_eth_fdir_masks *input_mask)
544{
545	int ret;
546
547	ret = ixgbe_fdir_store_input_mask(dev, input_mask);
548	if (ret)
549		return ret;
550
551	return ixgbe_fdir_set_input_mask(dev);
552}
553
554/*
555 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
556 * arguments are valid
557 */
558static int
559ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
560		const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
561{
562	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
563	struct ixgbe_hw_fdir_info *info =
564			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
565	const struct rte_eth_flex_payload_cfg *flex_cfg;
566	const struct rte_eth_fdir_flex_mask *flex_mask;
567	uint32_t fdirm;
568	uint16_t flexbytes = 0;
569	uint16_t i;
570
571	fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
572#ifndef TREX_PATCH
573	if (conf == NULL) {
574		PMD_DRV_LOG(ERR, "NULL pointer.");
575		return -EINVAL;
576	}
577
578	for (i = 0; i < conf->nb_payloads; i++) {
579		flex_cfg = &conf->flex_set[i];
580		if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
581			PMD_DRV_LOG(ERR, "unsupported payload type.");
582			return -EINVAL;
583		}
584		if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
585		    (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
586		    (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
587			*fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
588			*fdirctrl |=
589				(flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
590					IXGBE_FDIRCTRL_FLEX_SHIFT;
591		} else {
592			PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
593			return -EINVAL;
594		}
595	}
596
597	for (i = 0; i < conf->nb_flexmasks; i++) {
598		flex_mask = &conf->flex_mask[i];
599		if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
600			PMD_DRV_LOG(ERR, "flexmask should be set globally.");
601			return -EINVAL;
602		}
603		flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
604					((flex_mask->mask[1]) & 0xFF));
605		if (flexbytes == UINT16_MAX)
606			fdirm &= ~IXGBE_FDIRM_FLEX;
607		else if (flexbytes != 0) {
608			/* IXGBE_FDIRM_FLEX is set by default when set mask */
609			PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
610			return -EINVAL;
611		}
612	}
613#else
614        fdirm &= ~IXGBE_FDIRM_FLEX;
615        flexbytes = 1;
616        // fdirctrl gets flex_bytes_offset in configure_fdir_flags
617#endif
618	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
619	info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
620	info->flex_bytes_offset = (uint8_t)((*fdirctrl &
621					    IXGBE_FDIRCTRL_FLEX_MASK) >>
622					    IXGBE_FDIRCTRL_FLEX_SHIFT);
623	return 0;
624}
625
626int
627ixgbe_fdir_configure(struct rte_eth_dev *dev)
628{
629	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630	int err;
631	uint32_t fdirctrl, pbsize;
632	int i;
633	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
634
635	PMD_INIT_FUNC_TRACE();
636
637	if (hw->mac.type != ixgbe_mac_82599EB &&
638		hw->mac.type != ixgbe_mac_X540 &&
639		hw->mac.type != ixgbe_mac_X550 &&
640		hw->mac.type != ixgbe_mac_X550EM_x &&
641		hw->mac.type != ixgbe_mac_X550EM_a)
642		return -ENOSYS;
643
644	/* x550 supports mac-vlan and tunnel mode but other NICs not */
645	if (hw->mac.type != ixgbe_mac_X550 &&
646	    hw->mac.type != ixgbe_mac_X550EM_x &&
647	    hw->mac.type != ixgbe_mac_X550EM_a &&
648	    mode != RTE_FDIR_MODE_SIGNATURE &&
649#ifdef TREX_PATCH
650	    mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
651#endif
652	    mode != RTE_FDIR_MODE_PERFECT)
653		return -ENOSYS;
654
655	err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
656	if (err)
657		return err;
658
659	/*
660	 * Before enabling Flow Director, the Rx Packet Buffer size
661	 * must be reduced.  The new value is the current size minus
662	 * flow director memory usage size.
663	 */
664	pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
665	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
666	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
667
668	/*
669	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
670	 * intialized to zero for non DCB mode otherwise actual total RX PB
671	 * would be bigger than programmed and filter space would run into
672	 * the PB 0 region.
673	 */
674	for (i = 1; i < 8; i++)
675		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
676
677	err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
678	if (err < 0) {
679		PMD_INIT_LOG(ERR, " Error on setting FD mask");
680		return err;
681	}
682	err = ixgbe_set_fdir_flex_conf(dev,
683		&dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
684	if (err < 0) {
685		PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
686		return err;
687	}
688
689	err = fdir_enable_82599(hw, fdirctrl);
690	if (err < 0) {
691		PMD_INIT_LOG(ERR, " Error on enabling FD.");
692		return err;
693	}
694	return 0;
695}
696
697/*
698 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
699 * by the IXGBE driver code.
700 */
701static int
702ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
703		union ixgbe_atr_input *input, enum rte_fdir_mode mode)
704{
705	input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
706	input->formatted.flex_bytes = (uint16_t)(
707		(fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
708		(fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
709
710	switch (fdir_filter->input.flow_type) {
711	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
712		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
713		break;
714	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
715		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
716		break;
717	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
718		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
719		break;
720	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
721		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
722		break;
723	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
724		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
725		break;
726	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
727		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
728		break;
729	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
730		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
731		break;
732	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
733		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
734		break;
735	default:
736		break;
737	}
738
739	switch (fdir_filter->input.flow_type) {
740	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
741	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
742		input->formatted.src_port =
743			fdir_filter->input.flow.udp4_flow.src_port;
744		input->formatted.dst_port =
745			fdir_filter->input.flow.udp4_flow.dst_port;
746	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
747	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
748	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
749		input->formatted.src_ip[0] =
750			fdir_filter->input.flow.ip4_flow.src_ip;
751		input->formatted.dst_ip[0] =
752			fdir_filter->input.flow.ip4_flow.dst_ip;
753		break;
754
755	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
756	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
757		input->formatted.src_port =
758			fdir_filter->input.flow.udp6_flow.src_port;
759		input->formatted.dst_port =
760			fdir_filter->input.flow.udp6_flow.dst_port;
761	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
762	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
763	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
764		rte_memcpy(input->formatted.src_ip,
765			   fdir_filter->input.flow.ipv6_flow.src_ip,
766			   sizeof(input->formatted.src_ip));
767		rte_memcpy(input->formatted.dst_ip,
768			   fdir_filter->input.flow.ipv6_flow.dst_ip,
769			   sizeof(input->formatted.dst_ip));
770		break;
771	default:
772		break;
773	}
774
775	if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
776		rte_memcpy(
777			input->formatted.inner_mac,
778			fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
779			sizeof(input->formatted.inner_mac));
780	} else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
781		rte_memcpy(
782			input->formatted.inner_mac,
783			fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
784			sizeof(input->formatted.inner_mac));
785		input->formatted.tunnel_type =
786			fdir_filter->input.flow.tunnel_flow.tunnel_type;
787		input->formatted.tni_vni =
788			fdir_filter->input.flow.tunnel_flow.tunnel_id;
789	}
790
791	return 0;
792}
793
794/*
795 * The below function is taken from the FreeBSD IXGBE drivers release
796 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
797 * before returning, as the signature hash can use 16bits.
798 *
799 * The newer driver has optimised functions for calculating bucket and
800 * signature hashes. However they don't support IPv6 type packets for signature
801 * filters so are not used here.
802 *
803 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
804 * set.
805 *
806 * Compute the hashes for SW ATR
807 *  @stream: input bitstream to compute the hash on
808 *  @key: 32-bit hash key
809 **/
810static uint32_t
811ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
812				 uint32_t key)
813{
814	/*
815	 * The algorithm is as follows:
816	 *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
817	 *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
818	 *    and A[n] x B[n] is bitwise AND between same length strings
819	 *
820	 *    K[n] is 16 bits, defined as:
821	 *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
822	 *       for n modulo 32 < 15, K[n] =
823	 *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
824	 *
825	 *    S[n] is 16 bits, defined as:
826	 *       for n >= 15, S[n] = S[n:n - 15]
827	 *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
828	 *
829	 *    To simplify for programming, the algorithm is implemented
830	 *    in software this way:
831	 *
832	 *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
833	 *
834	 *    for (i = 0; i < 352; i+=32)
835	 *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
836	 *
837	 *    lo_hash_dword[15:0]  ^= Stream[15:0];
838	 *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
839	 *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
840	 *
841	 *    hi_hash_dword[31:0]  ^= Stream[351:320];
842	 *
843	 *    if (key[0])
844	 *        hash[15:0] ^= Stream[15:0];
845	 *
846	 *    for (i = 0; i < 16; i++) {
847	 *        if (key[i])
848	 *            hash[15:0] ^= lo_hash_dword[(i+15):i];
849	 *        if (key[i + 16])
850	 *            hash[15:0] ^= hi_hash_dword[(i+15):i];
851	 *    }
852	 *
853	 */
854	__be32 common_hash_dword = 0;
855	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
856	u32 hash_result = 0;
857	u8 i;
858
859	/* record the flow_vm_vlan bits as they are a key part to the hash */
860	flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
861
862	/* generate common hash dword */
863	for (i = 1; i <= 13; i++)
864		common_hash_dword ^= atr_input->dword_stream[i];
865
866	hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
867
868	/* low dword is word swapped version of common */
869	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
870
871	/* apply flow ID/VM pool/VLAN ID bits to hash words */
872	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
873
874	/* Process bits 0 and 16 */
875	if (key & 0x0001)
876		hash_result ^= lo_hash_dword;
877	if (key & 0x00010000)
878		hash_result ^= hi_hash_dword;
879
880	/*
881	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
882	 * delay this because bit 0 of the stream should not be processed
883	 * so we do not add the vlan until after bit 0 was processed
884	 */
885	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
886
887
888	/* process the remaining 30 bits in the key 2 bits at a time */
889	for (i = 15; i; i--) {
890		if (key & (0x0001 << i))
891			hash_result ^= lo_hash_dword >> i;
892		if (key & (0x00010000 << i))
893			hash_result ^= hi_hash_dword >> i;
894	}
895
896	return hash_result;
897}
898
899static uint32_t
900atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
901		enum rte_fdir_pballoc_type pballoc)
902{
903	if (pballoc == RTE_FDIR_PBALLOC_256K)
904		return ixgbe_atr_compute_hash_82599(input,
905				IXGBE_ATR_BUCKET_HASH_KEY) &
906				PERFECT_BUCKET_256KB_HASH_MASK;
907	else if (pballoc == RTE_FDIR_PBALLOC_128K)
908		return ixgbe_atr_compute_hash_82599(input,
909				IXGBE_ATR_BUCKET_HASH_KEY) &
910				PERFECT_BUCKET_128KB_HASH_MASK;
911	else
912		return ixgbe_atr_compute_hash_82599(input,
913				IXGBE_ATR_BUCKET_HASH_KEY) &
914				PERFECT_BUCKET_64KB_HASH_MASK;
915}
916
917/**
918 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
919 * @hw: pointer to hardware structure
920 */
921static inline int
922ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
923{
924	int i;
925
926	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
927		*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
928		if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
929			return 0;
930		rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
931	}
932
933	return -ETIMEDOUT;
934}
935
936/*
937 * Calculate the hash value needed for signature-match filters. In the FreeBSD
938 * driver, this is done by the optimised function
939 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
940 * doesn't support calculating a hash for an IPv6 filter.
941 */
942static uint32_t
943atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
944		enum rte_fdir_pballoc_type pballoc)
945{
946	uint32_t bucket_hash, sig_hash;
947
948	if (pballoc == RTE_FDIR_PBALLOC_256K)
949		bucket_hash = ixgbe_atr_compute_hash_82599(input,
950				IXGBE_ATR_BUCKET_HASH_KEY) &
951				SIG_BUCKET_256KB_HASH_MASK;
952	else if (pballoc == RTE_FDIR_PBALLOC_128K)
953		bucket_hash = ixgbe_atr_compute_hash_82599(input,
954				IXGBE_ATR_BUCKET_HASH_KEY) &
955				SIG_BUCKET_128KB_HASH_MASK;
956	else
957		bucket_hash = ixgbe_atr_compute_hash_82599(input,
958				IXGBE_ATR_BUCKET_HASH_KEY) &
959				SIG_BUCKET_64KB_HASH_MASK;
960
961	sig_hash = ixgbe_atr_compute_hash_82599(input,
962			IXGBE_ATR_SIGNATURE_HASH_KEY);
963
964	return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
965}
966
967/*
968 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
969 * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
970 * added, and IPv6 support also added. The hash value is also pre-calculated
971 * as the pballoc value is needed to do it.
972 */
973static int
974fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
975			union ixgbe_atr_input *input, uint8_t queue,
976			uint32_t fdircmd, uint32_t fdirhash,
977			enum rte_fdir_mode mode)
978{
979	uint32_t fdirport, fdirvlan;
980	u32 addr_low, addr_high;
981	u32 tunnel_type = 0;
982	int err = 0;
983	volatile uint32_t *reg;
984
985	if (mode == RTE_FDIR_MODE_PERFECT) {
986		/* record the IPv4 address (big-endian)
987		 * can not use IXGBE_WRITE_REG.
988		 */
989		reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
990		*reg = input->formatted.src_ip[0];
991		reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
992		*reg = input->formatted.dst_ip[0];
993
994		/* record source and destination port (little-endian)*/
995		fdirport = IXGBE_NTOHS(input->formatted.dst_port);
996		fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
997		fdirport |= IXGBE_NTOHS(input->formatted.src_port);
998		IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
999	} else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1000		   mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
1001		/* for mac vlan and tunnel modes */
1002		addr_low = ((u32)input->formatted.inner_mac[0] |
1003			    ((u32)input->formatted.inner_mac[1] << 8) |
1004			    ((u32)input->formatted.inner_mac[2] << 16) |
1005			    ((u32)input->formatted.inner_mac[3] << 24));
1006		addr_high = ((u32)input->formatted.inner_mac[4] |
1007			     ((u32)input->formatted.inner_mac[5] << 8));
1008
1009		if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
1010			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1011			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
1012			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1013		} else {
1014			/* tunnel mode */
1015			if (input->formatted.tunnel_type !=
1016				RTE_FDIR_TUNNEL_TYPE_NVGRE)
1017				tunnel_type = 0x80000000;
1018			tunnel_type |= addr_high;
1019			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1020			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1021			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1022					input->formatted.tni_vni);
1023		}
1024	}
1025
1026	/* record vlan (little-endian) and flex_bytes(big-endian) */
1027	fdirvlan = input->formatted.flex_bytes;
1028	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1029	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1030	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1031
1032	/* configure FDIRHASH register */
1033	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1034
1035	/*
1036	 * flush all previous writes to make certain registers are
1037	 * programmed prior to issuing the command
1038	 */
1039	IXGBE_WRITE_FLUSH(hw);
1040
1041	/* configure FDIRCMD register */
1042	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1043		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1044	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1045	fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1046	fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1047
1048	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1049
1050	PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1051
1052	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1053	if (err < 0)
1054		PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1055
1056	return err;
1057}
1058
1059/**
1060 * This function is based on ixgbe_atr_add_signature_filter_82599() in
1061 * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1062 * setting extra fields in the FDIRCMD register, and removes the code that was
1063 * verifying the flow_type field. According to the documentation, a flow type of
1064 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1065 * work ok...
1066 *
1067 *  Adds a signature hash filter
1068 *  @hw: pointer to hardware structure
1069 *  @input: unique input dword
1070 *  @queue: queue index to direct traffic to
1071 *  @fdircmd: any extra flags to set in fdircmd register
1072 *  @fdirhash: pre-calculated hash value for the filter
1073 **/
1074static int
1075fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1076		union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1077		uint32_t fdirhash)
1078{
1079	int err = 0;
1080
1081	PMD_INIT_FUNC_TRACE();
1082
1083	/* configure FDIRCMD register */
1084	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1085		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1086	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1087	fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1088
1089	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1090	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1091
1092	PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1093
1094	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1095	if (err < 0)
1096		PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1097
1098	return err;
1099}
1100
1101/*
1102 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1103 * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1104 * that it can be used for removing signature and perfect filters.
1105 */
1106static int
1107fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1108{
1109	uint32_t fdircmd = 0;
1110	int err = 0;
1111
1112	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1113
1114	/* flush hash to HW */
1115	IXGBE_WRITE_FLUSH(hw);
1116
1117	/* Query if filter is present */
1118	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1119
1120	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1121	if (err < 0) {
1122		PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1123		return err;
1124	}
1125
1126	/* if filter exists in hardware then remove it */
1127	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1128		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1129		IXGBE_WRITE_FLUSH(hw);
1130		IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1131				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1132	}
1133	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1134	if (err < 0)
1135		PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1136	return err;
1137
1138}
1139
1140static inline struct ixgbe_fdir_filter *
1141ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1142			 union ixgbe_atr_input *key)
1143{
1144	int ret;
1145
1146	ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1147	if (ret < 0)
1148		return NULL;
1149
1150	return fdir_info->hash_map[ret];
1151}
1152
1153static inline int
1154ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1155			 struct ixgbe_fdir_filter *fdir_filter)
1156{
1157	int ret;
1158
1159	ret = rte_hash_add_key(fdir_info->hash_handle,
1160			       &fdir_filter->ixgbe_fdir);
1161
1162	if (ret < 0) {
1163		PMD_DRV_LOG(ERR,
1164			    "Failed to insert fdir filter to hash table %d!",
1165			    ret);
1166		return ret;
1167	}
1168
1169	fdir_info->hash_map[ret] = fdir_filter;
1170
1171	TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1172
1173	return 0;
1174}
1175
1176static inline int
1177ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1178			 union ixgbe_atr_input *key)
1179{
1180	int ret;
1181	struct ixgbe_fdir_filter *fdir_filter;
1182
1183	ret = rte_hash_del_key(fdir_info->hash_handle, key);
1184
1185	if (ret < 0) {
1186		PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1187		return ret;
1188	}
1189
1190	fdir_filter = fdir_info->hash_map[ret];
1191	fdir_info->hash_map[ret] = NULL;
1192
1193	TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1194	rte_free(fdir_filter);
1195
1196	return 0;
1197}
1198
1199static int
1200ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
1201			    const struct rte_eth_fdir_filter *fdir_filter,
1202			    struct ixgbe_fdir_rule *rule)
1203{
1204	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1205	int err;
1206
1207	memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
1208
1209	err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
1210					     &rule->ixgbe_fdir,
1211					     fdir_mode);
1212	if (err)
1213		return err;
1214
1215	rule->mode = fdir_mode;
1216	if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
1217		rule->fdirflags = IXGBE_FDIRCMD_DROP;
1218	rule->queue = fdir_filter->action.rx_queue;
1219	rule->soft_id = fdir_filter->soft_id;
1220
1221	return 0;
1222}
1223
1224int
1225ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
1226			  struct ixgbe_fdir_rule *rule,
1227			  bool del,
1228			  bool update)
1229{
1230	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231	uint32_t fdircmd_flags;
1232	uint32_t fdirhash;
1233	uint8_t queue;
1234	bool is_perfect = FALSE;
1235	int err;
1236	struct ixgbe_hw_fdir_info *info =
1237		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1238	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1239	struct ixgbe_fdir_filter *node;
1240	bool add_node = FALSE;
1241
1242	if (fdir_mode == RTE_FDIR_MODE_NONE ||
1243	    fdir_mode != rule->mode)
1244		return -ENOTSUP;
1245
1246	/*
1247	 * Sanity check for x550.
1248	 * When adding a new filter with flow type set to IPv4-other,
1249	 * the flow director mask should be configed before,
1250	 * and the L4 protocol and ports are masked.
1251	 */
1252	if ((!del) &&
1253	    (hw->mac.type == ixgbe_mac_X550 ||
1254	     hw->mac.type == ixgbe_mac_X550EM_x ||
1255	     hw->mac.type == ixgbe_mac_X550EM_a) &&
1256	    (rule->ixgbe_fdir.formatted.flow_type ==
1257	     RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) &&
1258	    (info->mask.src_port_mask != 0 ||
1259	     info->mask.dst_port_mask != 0)) {
1260		PMD_DRV_LOG(ERR, "By this device,"
1261			    " IPv4-other is not supported without"
1262			    " L4 protocol and ports masked!");
1263		return -ENOTSUP;
1264	}
1265
1266	if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1267	    fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1268		is_perfect = TRUE;
1269
1270	if (is_perfect) {
1271#ifndef TREX_PATCH
1272        // No reason not to use IPV6 in perfect filters. It is working.
1273		if (rule->ixgbe_fdir.formatted.flow_type &
1274		    IXGBE_ATR_L4TYPE_IPV6_MASK) {
1275			PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1276				    " perfect mode!");
1277			return -ENOTSUP;
1278		}
1279#endif
1280		fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1281							  dev->data->dev_conf.fdir_conf.pballoc);
1282		fdirhash |= rule->soft_id <<
1283			IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1284	} else
1285		fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1286						      dev->data->dev_conf.fdir_conf.pballoc);
1287
1288	if (del) {
1289		err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1290		if (err < 0)
1291			return err;
1292
1293		err = fdir_erase_filter_82599(hw, fdirhash);
1294		if (err < 0)
1295			PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1296		else
1297			PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1298		return err;
1299	}
1300	/* add or update an fdir filter*/
1301	fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1302	if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1303		if (is_perfect) {
1304			queue = dev->data->dev_conf.fdir_conf.drop_queue;
1305			fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1306		} else {
1307			PMD_DRV_LOG(ERR, "Drop option is not supported in"
1308				    " signature mode.");
1309			return -EINVAL;
1310		}
1311	} else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
1312		queue = (uint8_t)rule->queue;
1313	else
1314		return -EINVAL;
1315
1316	node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
1317	if (node) {
1318		if (update) {
1319			node->fdirflags = fdircmd_flags;
1320			node->fdirhash = fdirhash;
1321			node->queue = queue;
1322		} else {
1323			PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1324			return -EINVAL;
1325		}
1326	} else {
1327		add_node = TRUE;
1328		node = rte_zmalloc("ixgbe_fdir",
1329				   sizeof(struct ixgbe_fdir_filter),
1330				   0);
1331		if (!node)
1332			return -ENOMEM;
1333		(void)rte_memcpy(&node->ixgbe_fdir,
1334				 &rule->ixgbe_fdir,
1335				 sizeof(union ixgbe_atr_input));
1336		node->fdirflags = fdircmd_flags;
1337		node->fdirhash = fdirhash;
1338		node->queue = queue;
1339
1340		err = ixgbe_insert_fdir_filter(info, node);
1341		if (err < 0) {
1342			rte_free(node);
1343			return err;
1344		}
1345	}
1346
1347	if (is_perfect) {
1348		err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
1349						      queue, fdircmd_flags,
1350						      fdirhash, fdir_mode);
1351	} else {
1352		err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
1353						      queue, fdircmd_flags,
1354						      fdirhash);
1355	}
1356	if (err < 0) {
1357		PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1358
1359		if (add_node)
1360			(void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1361	} else {
1362		PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1363	}
1364
1365	return err;
1366}
1367
1368/* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1369 * @dev: pointer to the structure rte_eth_dev
1370 * @fdir_filter: fdir filter entry
1371 * @del: 1 - delete, 0 - add
1372 * @update: 1 - update
1373 */
1374static int
1375ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1376			  const struct rte_eth_fdir_filter *fdir_filter,
1377			  bool del,
1378			  bool update)
1379{
1380	struct ixgbe_fdir_rule rule;
1381	int err;
1382
1383	err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
1384
1385	if (err)
1386		return err;
1387
1388	return ixgbe_fdir_filter_program(dev, &rule, del, update);
1389}
1390
1391static int
1392ixgbe_fdir_flush(struct rte_eth_dev *dev)
1393{
1394	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395	struct ixgbe_hw_fdir_info *info =
1396			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1397	int ret;
1398
1399	ret = ixgbe_reinit_fdir_tables_82599(hw);
1400	if (ret < 0) {
1401		PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1402		return ret;
1403	}
1404
1405	info->f_add = 0;
1406	info->f_remove = 0;
1407	info->add = 0;
1408	info->remove = 0;
1409
1410	return ret;
1411}
1412
1413#define FDIRENTRIES_NUM_SHIFT 10
1414static void
1415ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1416{
1417	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418	struct ixgbe_hw_fdir_info *info =
1419			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1420	uint32_t fdirctrl, max_num;
1421	uint8_t offset;
1422
1423	fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1424	offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1425			IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1426
1427	fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1428	max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1429			(fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1430	if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1431	    fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1432		fdir_info->guarant_spc = max_num;
1433	else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1434		fdir_info->guarant_spc = max_num * 4;
1435
1436	fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1437	fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1438	fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1439	IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1440			fdir_info->mask.ipv6_mask.src_ip);
1441	IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1442			fdir_info->mask.ipv6_mask.dst_ip);
1443	fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1444	fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1445	fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1446	fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1447	fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1448	fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1449
1450	if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1451	    fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1452		fdir_info->flow_types_mask[0] = 0;
1453	else
1454		fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1455
1456	fdir_info->flex_payload_unit = sizeof(uint16_t);
1457	fdir_info->max_flex_payload_segment_num = 1;
1458	fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1459	fdir_info->flex_conf.nb_payloads = 1;
1460	fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1461	fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1462	fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1463	fdir_info->flex_conf.nb_flexmasks = 1;
1464	fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1465	fdir_info->flex_conf.flex_mask[0].mask[0] =
1466			(uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1467	fdir_info->flex_conf.flex_mask[0].mask[1] =
1468			(uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1469}
1470
1471static void
1472ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1473{
1474	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1475	struct ixgbe_hw_fdir_info *info =
1476		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1477	uint32_t reg, max_num;
1478	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1479
1480	/* Get the information from registers */
1481	reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1482	info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1483				     IXGBE_FDIRFREE_COLL_SHIFT);
1484	info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1485				IXGBE_FDIRFREE_FREE_SHIFT);
1486
1487	reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1488	info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1489				   IXGBE_FDIRLEN_MAXHASH_SHIFT);
1490	info->maxlen  = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1491				  IXGBE_FDIRLEN_MAXLEN_SHIFT);
1492
1493	reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1494	info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1495		IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1496	info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1497		IXGBE_FDIRUSTAT_ADD_SHIFT;
1498
1499	reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1500	info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1501		IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1502	info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1503		IXGBE_FDIRFSTAT_FADD_SHIFT;
1504
1505	/*  Copy the new information in the fdir parameter */
1506	fdir_stats->collision = info->collision;
1507	fdir_stats->free = info->free;
1508	fdir_stats->maxhash = info->maxhash;
1509	fdir_stats->maxlen = info->maxlen;
1510	fdir_stats->remove = info->remove;
1511	fdir_stats->add = info->add;
1512	fdir_stats->f_remove = info->f_remove;
1513	fdir_stats->f_add = info->f_add;
1514
1515	reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1516	max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1517			 (reg & FDIRCTRL_PBALLOC_MASK)));
1518	if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1519	    fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1520		fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1521	else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1522		fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1523
1524}
1525
1526/*
1527 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1528 * @dev: pointer to the structure rte_eth_dev
1529 * @filter_op:operation will be taken
1530 * @arg: a pointer to specific structure corresponding to the filter_op
1531 */
1532int
1533ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1534			enum rte_filter_op filter_op, void *arg)
1535{
1536	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537	int ret = 0;
1538
1539	if (hw->mac.type != ixgbe_mac_82599EB &&
1540		hw->mac.type != ixgbe_mac_X540 &&
1541		hw->mac.type != ixgbe_mac_X550 &&
1542		hw->mac.type != ixgbe_mac_X550EM_x &&
1543		hw->mac.type != ixgbe_mac_X550EM_a)
1544		return -ENOTSUP;
1545
1546	if (filter_op == RTE_ETH_FILTER_NOP)
1547		return 0;
1548
1549	if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1550		return -EINVAL;
1551
1552	switch (filter_op) {
1553	case RTE_ETH_FILTER_ADD:
1554		ret = ixgbe_add_del_fdir_filter(dev,
1555			(struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1556		break;
1557	case RTE_ETH_FILTER_UPDATE:
1558		ret = ixgbe_add_del_fdir_filter(dev,
1559			(struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1560		break;
1561	case RTE_ETH_FILTER_DELETE:
1562		ret = ixgbe_add_del_fdir_filter(dev,
1563			(struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1564		break;
1565	case RTE_ETH_FILTER_FLUSH:
1566		ret = ixgbe_fdir_flush(dev);
1567		break;
1568	case RTE_ETH_FILTER_INFO:
1569		ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1570		break;
1571	case RTE_ETH_FILTER_STATS:
1572		ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1573		break;
1574	default:
1575		PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1576		ret = -EINVAL;
1577		break;
1578	}
1579	return ret;
1580}
1581
1582/* restore flow director filter */
1583void
1584ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1585{
1586	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587	struct ixgbe_hw_fdir_info *fdir_info =
1588		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1589	struct ixgbe_fdir_filter *node;
1590	bool is_perfect = FALSE;
1591	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1592
1593	if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1594	    fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1595		is_perfect = TRUE;
1596
1597	if (is_perfect) {
1598		TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1599			(void)fdir_write_perfect_filter_82599(hw,
1600							      &node->ixgbe_fdir,
1601							      node->queue,
1602							      node->fdirflags,
1603							      node->fdirhash,
1604							      fdir_mode);
1605		}
1606	} else {
1607		TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1608			(void)fdir_add_signature_filter_82599(hw,
1609							      &node->ixgbe_fdir,
1610							      node->queue,
1611							      node->fdirflags,
1612							      node->fdirhash);
1613		}
1614	}
1615}
1616
1617/* remove all the flow director filters */
1618int
1619ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1620{
1621	struct ixgbe_hw_fdir_info *fdir_info =
1622		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1623	struct ixgbe_fdir_filter *fdir_filter;
1624	struct ixgbe_fdir_filter *filter_flag;
1625	int ret = 0;
1626
1627	/* flush flow director */
1628	rte_hash_reset(fdir_info->hash_handle);
1629	memset(fdir_info->hash_map, 0,
1630	       sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1631	filter_flag = TAILQ_FIRST(&fdir_info->fdir_list);
1632	while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1633		TAILQ_REMOVE(&fdir_info->fdir_list,
1634			     fdir_filter,
1635			     entries);
1636		rte_free(fdir_filter);
1637	}
1638
1639	if (filter_flag != NULL)
1640		ret = ixgbe_fdir_flush(dev);
1641
1642	return ret;
1643}
1644